Analog-to-digital converter

Abstract

An analog-to-digital converter for converting an analog signal to a digital signal by sampling the analog signal to generate the digital signal, the analog-to-digital converter configured to: acquire a first sample comprising a first plurality of bits representing the digital signal, determine one or more bit positions that are variable within the first plurality of bits, and generate a second sample comprising a second plurality of bits representing the digital signal; determining one or more bit positions that are static within the first plurality of bits, and acquiring a second sample after the first sample has been acquired, the second sample comprising a second plurality of bits representing the digital signal, bit values of at least a portion of the one or more variable bit positions are generated by sampling the analog signal, and the bit value of each of the one or more static bit positions is set to be the same as the bit value of the corresponding bit position in the first sample.

Description

[0001] The present disclosure relates to an analog-to-digital converter. In particular, the present disclosure relates to an analog-to-digital converter for converting an analog signal into a digital signal by sampling the analog signal to generate a digital signal.

[0002] background

[0003] Figure 1 is a schematic diagram of an analog-to-digital converter (ADC) 100. ADC 100 is a successive approximation register (SAR) ADC using oversampling (OVS).

[0004] OVS is a process in which the input signal is repeatedly digitized to obtain data at a sampling frequency higher than the Nyquist rate. OVS can be used to increase the signal-to-noise ratio (SNR) and improve the effective resolution of the sampled data.

[0005] Effective resolution is described by the effective number of bits (ENOB). For example, a system may have 8 bits of resolution, but due to noise, only 6 bits are unaffected by noise, giving an ENOB of 6 bits. Assume that noise is the dominant factor affecting ENOB.

[0006] SAR ADC 100 includes a digital-to-analog converter (DAC) 102 , a sample and hold circuit 104 , a comparator 106 , a SAR logic circuit 108 , and an accumulator 110 .

[0007] The SAR ADC 100 receives an input voltage Vin, ie, an analog signal to be converted. The SAR ADC 100 also receives a reference voltage Vref.

[0008] In operation, the sample and hold circuit 104 receives an input voltage Vin. The input voltage Vin is sampled and held at a fixed value for a period of time. In a subsequent time period, the input voltage Vin is then sampled and held again, and the process is repeated so that the output signal provided by the circuit 104 includes a series of constant voltage values ​​over consecutive time periods, which constant voltage values ​​represent the input voltage Vin.

[0009] In operation, comparator 106 compares input voltage Vin processed by circuit 104 with the output of DAC 102. SAR logic circuit 108 provides a digital code representing input voltage Vin to DAC 102. DAC 102 converts the digital code to an analog value that is provided to comparator 106 using reference voltage Vref.

[0010] The most popular SAR ADC architecture uses a sample and hold block and a DAC block combined into a capacitive DAC block. The DAC uses the charge redistribution principle, while the ADC’s ​​sampling and conversion logic is similar to the Figure 1The circuit is the same as in .

[0011] The successive approximation process allows bits of the digital code representing the input voltage Vin to be generated successively. For example, the most significant bit (MSB) is generated initially, and subsequent processing is used to determine additional bits of decreasing significance, so that as each bit is determined, when generating a digital signal representing the analog signal (input voltage Vin), the signal becomes more accurate.

[0012] The operation of a SAR ADC will be well known to the skilled person.The accumulator 110 stores each sample from the process and then calculates the result.

[0013] Known ADCs using oversampling are described in:

[0014] 1.STMicroelectronics, “STM32L4+Series advanced -based 32-bitMCUs”, RM0432 Reference Manual, 9th edition, June 2021, 670-671. https: / / www.st.com / resource / en / reference_manual / rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf (accessed on January 10, 2023)

[0015] 2. Analog Devices, “4-Channel, 4MSPS, 16-Bit / 14-Bit / 12-Bit, Dual, Simultaneous Sampling SAR ADCs,” AD7386 / AD7387 / AD7388 Data Sheet, Rev. A, 2019, page 37. https: / / www.analog.com / media / en / technical-documentation / data-sheets / ad7386-7387-7388.pdf (accessed on January 10, 2023)

[0016] The disadvantages of these devices are that the time to obtain the oversampled result is increased compared to the typical sampling process, and the resulting power consumption is increased when the oversampled unit is used.

[0017] Overview

[0018] It would be desirable to provide an ADC that improves upon known ADC designs.

[0019] In particular, it would be desirable to provide an ADC that is faster and consumes less power than known systems (eg, an ADC using oversampling).

[0020] According to a first aspect of the present disclosure, an analog-to-digital converter is provided for converting an analog signal into a digital signal by sampling the analog signal to generate a digital signal, the analog-to-digital converter being configured to: acquire a first sample including a first plurality of bits representing the digital signal, determine one or more variable bit positions within the first plurality of bits, determine one or more static bit positions within the first plurality of bits, and acquire a second sample after the first sample has been acquired, the second sample including a second plurality of bits representing the digital signal, wherein in order to acquire the second sample, bit values ​​of at least a portion of the variable one or more bit positions are generated by sampling the analog signal, and the bit value of each of the static one or more bit positions is set to the same bit value as the bit value of the corresponding bit position in the first sample.

[0021] Optionally, sampling the analog signal to generate the digital signal includes oversampling.

[0022] Optionally, the analog-to-digital converter is configured to determine which bit positions of one or more variable bit positions within the first plurality of bits need to be measured, and to generate a bit value for each bit position of the one or more bit positions that need to be measured by sampling the analog signal in order to collect a second sample.

[0023] Optionally, the analog to digital converter is configured to receive the number of noise bits and determine one or more bit positions within the first plurality of bits that are variable using the first sample and the number of noise bits.

[0024] Optionally, the noise bits represent the peak-to-peak noise of the digitized input signal.

[0025] Optionally, the analog to digital converter is configured to determine one or more bit positions within the first plurality of bits that are variable using the first sample and the number of noise bits by determining a noise range for the first sample and evaluating which bit positions of the first sample are variable within the noise range.

[0026] Optionally, the analog-to-digital converter is configured to determine a noise range for the first sample by adding peak-to-peak noise to the first sample to determine an upper noise estimate for the first sample and by subtracting the peak-to-peak noise from the first sample to determine a lower noise estimate for the first sample.

[0027] Optionally, the analog-to-digital converter is configured to determine which bit positions of one or more variable bit positions within the first plurality of bits need to be measured, and to generate a bit value for each bit position of the one or more bit positions that need to be measured by sampling the analog signal in order to collect a second sample.

[0028] Optionally, the number of bit positions that need to be measured is equal to the number of noise bits plus two.

[0029] Optionally, the variable bit positions include a noise bit, a double noise bit, a carry bit, and a full noise bit, and the bit positions to be measured are the noise bit, the double noise bit, and the full noise bit.

[0030] Optionally, the bit positions of the noise bits are the least significant bits.

[0031] Optionally, the bit position of the twice noise bit is one bit position to the left of the noise bit.

[0032] Optionally, the carry bit is the bit to the left of the twice noise bit, having the same bit value as the twice noise bit, and is the bit to the right of the next bit with a different value, which is the full noise bit.

[0033] Optionally, the analog-to-digital converter is configured to: for acquiring a second sample, generate a bit value of each of the noise bit, the double noise bit and the full noise bit by sampling the analog signal, and set the value of the carry bit to the inverted value of the full noise bit.

[0034] Optionally, the analog-to-digital converter is a successive approximation register analog-to-digital converter.

[0035] Optionally, the analog-to-digital converter includes: a sampling and holding circuit configured to receive an input voltage, a digital-to-analog converter configured to receive a reference voltage, a comparator configured to receive a first signal from the digital-to-analog converter and to receive a second signal from the sampling and holding circuit, and a SAR logic circuit configured to receive a comparator output signal from the comparator and provide a SAR output signal to the digital-to-analog converter.

[0036] Optionally, the analog-to-digital converter comprises an accumulator configured to store the first sample and to calculate a result of the oversampling process using the first sample.

[0037] Optionally, the analog-to-digital converter includes a controller configured to: receive a first sample, determine one or more variable bit positions within the first plurality of bits, determine one or more static bit positions within the first plurality of bits, and control the SAR logic circuit so that in order to collect a second sample, bit values ​​of at least a portion of the variable one or more bit positions are generated by sampling the analog signal, and the bit value of each of the static one or more bit positions is set to the same bit value as the bit value of the corresponding bit position in the first sample.

[0038] Optionally, the controller is configured to determine which bit positions of one or more variable bit positions within the first plurality of bits need to be measured, and to control the SAR logic circuit so that in order to collect a second sample, a bit value of each bit position of the one or more bit positions that need to be measured is generated by sampling the analog signal.

[0039] Optionally, the controller is configured to receive a number of noise bits and to use the first sample and the number of noise bits to determine one or more bit positions within the first plurality of bits that are variable.

[0040] Optionally, the noise bits represent the peak-to-peak noise of the digitized input signal.

[0041] Optionally, the controller is configured to determine one or more bit positions within the first plurality of bits that are variable using the first sample and the number of noise bits by determining a noise range for the first sample and evaluating which bit positions of the first sample are variable within the noise range.

[0042] Optionally, the controller is configured to determine the noise range of the first sample by determining an upper noise estimate for the first sample by adding peak-to-peak noise to the first sample and determining a lower noise estimate for the first sample by subtracting the peak-to-peak noise from the first sample.

[0043] Optionally, the analog-to-digital converter comprises an accumulator configured to store the first sample and the second sample and to calculate a result of the oversampling process using the first sample and the second sample.

[0044] Optionally, the analog-to-digital converter is configured to acquire a third sample after the second sample has been acquired, the third sample comprising a third plurality of bits representing the digital signal.

[0045] Optionally, the analog-to-digital converter is configured to acquire a fourth sample after the third sample has been acquired, the fourth sample comprising a fourth plurality of bits representing the digital signal.

[0046] Optionally, the third sample and / or the fourth sample are collected using one or more features described in relation to the second sample of the first aspect.

[0047] According to a second aspect of the present disclosure, there is provided a method for converting an analog signal into a digital signal by sampling the analog signal using an analog-to-digital converter to generate a digital signal, the method comprising: acquiring a first sample comprising a first plurality of bits representing the digital signal, determining one or more variable bit positions within the first plurality of bits, determining one or more static bit positions within the first plurality of bits, and acquiring a second sample after the first sample has been acquired, the second sample comprising a second plurality of bits representing the digital signal, wherein in order to acquire the second sample, bit values ​​of at least a portion of the variable one or more bit positions are generated by sampling the analog signal, and the bit value of each of the static one or more bit positions is set to the same bit value as the bit value of the corresponding bit position in the first sample.

[0048] It will be appreciated that the method of the second aspect may comprise providing and / or using the features set out in the first aspect, and may be combined with other features as described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The present disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which:

[0051] Figure 1 is a schematic diagram of an analog-to-digital converter (ADC) 100;

[0052] FIG. 2( a ) is a schematic diagram of an ADC according to a first embodiment of the present disclosure, and FIG. 2( b ) is a diagram showing an analog signal and a sample 208 forming a digital signal;

[0053] FIG. 3( a ) is a table showing a first sample and an estimate of possible subsequent samples based on noise estimation, and FIG. 3( b ) shows the first sample of FIG. 3( a );

[0054] Figure 4 is a schematic diagram of an ADC according to a second embodiment of the present disclosure;

[0055] Figure 5 Is a description Figure 4 A flowchart of the operation of the ADC;

[0056] FIG. 6( a ) is a graph showing the output of a 2-bit ADC, FIG. 6( b ) is a graph showing the output of a 3-bit ADC, and FIG. 6( c ) is a graph showing four conversions of a signal with noise; and

[0057] Figure 7 is a graph showing example results utilizing an accumulator using a 2-bit ADC with oversampling.

[0058] Detailed Description

[0059] FIG. 2( a ) is a schematic diagram of an ADC 200 for converting an analog signal 202 into a digital signal 204 using a sampling process according to a first embodiment of the present disclosure.

[0060] FIG. 2( b ) is a diagram showing an analog signal 202 varying within an oversampling period 205 and samples 208 forming a digital signal 204 having one bit of noise.

[0061] In operation, ADC 200 acquires a first sample that includes a first plurality of bits representing digital signal 204 .

[0062] Then, before acquiring a second sample, ADC 200 determines which bit positions within the first plurality of bits are variable and which positions are static. The second sample includes a second plurality of bits representing digital signal 204.

[0063] Prior to acquiring the second sample, ADC 200 may determine which bit positions within the first plurality of bits are variable and which positions are static within a sampling period.When sampling analog signal 202 to generate digital signal 204 includes oversampling, the sampling period may be an oversampling period.

[0064] To acquire the second sample, bit values ​​of at least a portion of the variable one or more bit positions are generated by sampling the analog signal 202 .

[0065] It should be understood that the description provided focuses on the acquisition of the second sample. However, other embodiments of the present disclosure may include acquiring at least one subsequent sample using the same method as described with respect to the second sample. All samples may be acquired within a single sampling cycle (e.g., an oversampling cycle). Preferably, the oversampling cycle includes the acquisition of four or more samples.

[0066] During operation, ADC 200 determines static bit positions within the first plurality of bits because these bit positions do not change or are unlikely to change between samples. To collect a second sample, the bit value of each of the static bit positions is set to the same bit value as the bit value of the corresponding bit position in the first sample.

[0067] In a specific embodiment, all variable bit values ​​can be generated by sampling. For example, the first sample can include the following 8 bits 10010101. During operation, ADC 200 will determine which bit positions of these 8 bits will be variable. For example, in the case of the present application, the 2 least significant bits can be evaluated as variable. The remaining bits can be evaluated as static.

[0068] Therefore, when collecting the second sample, only the two least significant bits are sampled. The remaining bits can be equal to the corresponding bits of the first sample. The obtained second sample can be 10010111.

[0069] In an alternative embodiment, only a subset of the variable bit values ​​may be generated by sampling, with the other variable bit values ​​determined by another means.

[0070] For example, the bit value of a variable bit may be derived based on the value of another bit in another bit position. This is possible due to the binary weighted structure of the successive approximation register of the ADC. In this case, the measurement or determination of the other bit may be sufficient to know the value of the variable bit, thereby making the measurement of the variable bit unnecessary.

[0071] For example, the bit values ​​of multiple variable bits may be derived based on the values ​​of multiple other bits in other bit positions. This is possible due to the binary weighted structure of the successive approximation register of the ADC. In this case, the measurement or determination of the other bits may be sufficient to know the value of the variable bit, thereby making the measurement of the variable bit unnecessary.

[0072] This is shown in Figure 2(b) 208, 210. The variable bit 210 is what must be measured, while all other bits can be inferred based on the value of bit 210.

[0073] For example, the first sample may include the following 8 bits 10010101. During operation, the ADC 200 will determine which bit positions of the 8 bits will be variable. For example, in the case of the present application, the 2 least significant bits may be evaluated as variable. The remaining bits may be evaluated as static.

[0074] The variable bits are the two rightmost bits "01". It can be known through analysis or other means that the leftmost variable bit always has the inverted value of the rightmost variable bit. Therefore, only a single bit of the two bits needs to be measured to know the value of the other bit.

[0075] Therefore, when collecting the second sample, only the least significant bit can be sampled. The static bit can be equal to the corresponding bit of the first sample, and the leftmost variable bit can be the inverse value of the rightmost variable bit. The resulting second sample can be 10010110.

[0076] In a specific embodiment, ADC 200 may be configured to determine which variable bits need to be measured. In operation, the second sample may then be acquired using only samples of the bits that need to be measured, while the other variable bits are determined by another means.

[0077] It should be appreciated that in further embodiments, the processes described herein may be applied to the acquisition of one or more subsequent samples after the second sample, with only the variable bits being determined for the acquisition of each new sample.

[0078] Since it is not necessary to sample analog signal 202 to generate all bits of the second sample, the sampling time of ADC 200 is reduced compared to ADC 100 , and power consumption requirements will also be reduced.

[0079] The sampling process may include oversampling and may provide “fast OVS.” The proposed fast OVS method and apparatus allow an ADC operating in an oversampling mode to reduce data acquisition time and power consumption.

[0080] In a particular embodiment, the ADC 200 may receive a number of noise bits 206. The number of noise bits 206 is a number that represents the number of bits that are susceptible to noise. The number of noise bits 206 may be a user-defined value. The noise bits may represent the maximum noise of the ADC 200. For example, the noise bits may represent the expected worst-case full system peak-to-peak noise of, for example, a digitized input signal. The user may analyze the system to determine the expected maximum noise level and then use this information to set the number of noise bits 206.

[0081] The noise may come not only from the ADC 200, but also from other sources (PCB, external components, etc.). The input signal itself may also contain noise.

[0082] ADC 200 may be configured to determine one or more bit positions within the first plurality of bits that are variable by using the first sample and the number of noise bits 206 .

[0083] For (such as Figure 1 The conditions for the conventional OVS (described above) and the fast OVS method (associated with the ADC of the present disclosure) are:

[0084] 1) Noise is included in the conversion result of generating the digital signal 204

[0085] 2) The analog signal 202 is considered constant during the oversampling period

[0086] The oversampling period refers to the time period during which the oversampling process is performed. For example, the first sample and the second sample as described above can both be collected within a single oversampling period.

[0087] Preferably, for ADC 200, the noise amplitude does not exceed a selected noise parameter (number of noise bits) within one oversampling period.

[0088] In order to increase the resolution by one bit with the help of OVS, the OVS ratio K OVSMust be at least four (four samples):

[0089] K OVS =4 N (1)

[0090] where N is the desired number of additional bits of resolution.

[0091] For example, if the resolution of ADC 200 is 10 bits and the desired result resolution is 12 bits, the OVS ratio should be K OVS = 16 samples (using equation (1)). The analog signal 202 should be sampled 16 times to get a 12-bit result.

[0092] 2( b) is a diagram showing an analog signal 202 varying within an oversampling period 205 and a sample 208 forming a digital signal 204 with one bit of noise. The idea of ​​the fast OVS method disclosed in the present invention is as follows: When operating in OVS mode, the difference between samples is a few ADC counts during one oversampling period.

[0093] It is not necessary to measure all bits of each sample result. It is sufficient to measure only the variable bits that form the result. However, the variable bit can be any bit of the result, not just the least significant bit as shown by sample 208. In this example, the 8-bit ADC samples a signal that changes by one count between counts 127 and 128.

[0094] In FIG2( b ), all bits of the result data word are changed, but only one bit (see the number column highlighted by reference numeral 210 ) can be measured to obtain the result. The fast OVS method of the present disclosure provides a method to determine static bits and variable bits, some of which are preferably sampled, to obtain the result.

[0095] Figure 3(a) is a table showing a first sample 300 and an estimate of possible subsequent samples based on the noise estimate. Figure 3(b) shows the first sample 300 of Figure 3(a). This example involves a SAR ADC using oversampling.

[0096] Returning to ADC 200, in a particular embodiment, the variable bit positions may be determined by determining a noise range for a first sample and then evaluating which bit positions are variable within the noise range.

[0097] The noise range can be determined by calculating an upper noise estimate and a lower noise estimate, where the upper noise estimate is determined by adding the peak-to-peak noise to the first sample and the lower estimate is determined by subtracting the peak-to-peak noise from the first sample.As previously mentioned, the maximum noise of the system can be represented by noise bits.

[0098] In this example, the peak-to-peak noise of the acquisition system is 8 counts, which can be represented by 3 bits. Therefore, in the current case, there will be 3 noise bits (meaning the number of noise bits 206 is 3). The acquisition system can be a complete device: for example a PCB with soldered external components, filters, ADC, etc.

[0099] In operation, the ADC 200 may perform a full sampling / conversion process. For example, assuming that the ADC 200 is a 12-bit ADC, the result 1010 0011 1010 may be provided, which is the first sample 300 as shown in FIG3(a) and FIG3(b).

[0100] Since subsequent samples can range from (first sample + maximum noise) to (first sample - maximum noise), it can be assumed that the possible noise range is equal to the peak-to-peak noise multiplied by 2. The possible range of ADC results (including noise) that can be obtained during an OVS period is shown in Figure 3(a).

[0101] In the present example shown in FIG. 3( a ), the seven bits starting from the right are susceptible to variations in the possible noise range. However, only five bits need to be measured (as indicated by numeral 302 ). In the present example, the number of bits to be sampled is equal to the number of noise bits plus 2.

[0102] The description provided herein is based on a conventional method of writing binary numbers comprising a plurality of bits, with the bit positions described in terms of "right" and "left", with the leftmost bit being the most significant bit and the rightmost bit being the least significant bit.

[0103] The variable bit positions include noise bit 305, twice noise bit 304, carry bit 306, and full noise bit 308. The bit positions that need to be measured are noise bit 305, twice noise bit 304, and full noise bit 308. It should be understood that in other embodiments, the categories of bit positions as described may include one or more bits and are not limited to the form described above. For example, the carry bit 306 has been described previously, but in another embodiment, there may be only a single carry bit.

[0104] The bit positions of the noise bits 305 may be the least significant bits. In this example, the noise bits 305 are the three rightmost bit positions.

[0105] The bit position of the double noise bit 304 is one bit position to the left of the noise bit 305 .

[0106] The carry bit 306 is the bit to the left of the double noise bit 304, has the same bit value as the double noise bit 304, and is the bit to the right of the next bit having a different value (ie, the full noise bit 308).

[0107] To acquire the second sample, the bit value of each of the noise bit 305, the double noise bit 304, and the full noise bit 308 is generated by sampling the analog signal 204. The value of the carry bit 306 is set to the inverted value of the full noise bit 308.

[0108] In summary, in this embodiment, the classification of bits forming a binary number can be described as follows:

[0109] Noise bits – generally corresponds to the peak-to-peak noise of the acquisition system, in particular to the ADC noise. This can be a user-defined value and the expected worst-case full system noise.

[0110] Twice the noise bits - after obtaining the first sample, the possible noise range should be multiplied by 2, since the first result obtained may contain both lower and upper noise levels (see Figure 3(a)).

[0111] Total Noise Bit – This bit has the same meaning as the Twice Noise Bit. This bit should be measured due to the SAR structure of the ADC.

[0112] Carry bits - These bits have the inverse value of the full noise bits. These bits can be measured only once during the first sampling / conversion process.

[0113] Skip bits - These are static bits as described previously and are bits that do not change during an oversampling cycle. These bits are measured only once during the first sampling / conversion process.

[0114] In summary, in this embodiment, the variable bits can be divided into the following two types:

[0115] Depends on the bits of the input signal during one OVS cycle. These bits are preferably measured. These are the noise bits, twice the noise bits, the full noise bits

[0116] Bits that can be automatically defined (derived) based on previously measured bits. These bits should preferably not be measured. These are carry bits (the inverted value of the full noise bit).

[0117] Ultimately, there are static bits and variable bits. But preferably, not all variable bits should be measured. Some of them (carry bits) can be automatically defined based on previously measured full-noise bits.

[0118] Variable bits may include bits that depend on the input signal and bits that may be defined based on previously sampled bits.

[0119] The following are examples related to variable bits.

[0120] For example, an ADC samples data, but it is known that the result can only be 151 (b) 1001 0111 or 152 (b) 10011000. No other data is possible. The values ​​151 and 152 differ by 1, but due to the nature of binary numbers, four digits (four bit positions) are changed in the binary representation. Finally, if it is already known that the result can be 151 or 152, it is sufficient to sample only one-third of the bits of the result. In the current example, the bit numbering starts at bit zero and counts from right to left. If the sampled bit is 1, all other bits to the right of the sampled bit are zero. In other cases, if the sampled bit is 0, all other bits to the right of the sampled bit are 1.

[0121] In the case of an integrated circuit, the noise bits can be stored in a memory register. The user can program the number of noise bits or the number of bit positions into the memory register prior to device operation. The ADC will then use the values ​​stored in the memory to analyze the samples during the oversampling period.

[0122] Figure 4 2 is a schematic diagram of an ADC 400 according to a second embodiment of the present disclosure. ADC 200 is an example of a specific embodiment of ADC 200. ADC 400 is a successive approximation register (SAR) ADC.

[0123] ADC 400 includes a sample and hold circuit 402 configured to receive an input voltage Vin. ADC 400 includes a DAC 404 configured to receive a reference voltage Vref. ADC 400 includes a comparator 406 configured to receive a first signal 408 from DAC 404 and a second signal 410 from sample and hold circuit 402. ADC 400 also includes a SAR logic circuit 412 configured to receive a comparator output signal 414 from comparator 406 and provide a SAR output signal 416 to DAC 404.

[0124] The output signal 416 may also be provided to an accumulator and fast OVS logic circuit 420 .

[0125] ADC 400 may include an accumulator 418 for storing the first sample. Accumulator 418 may also be configured to store the second sample. Accumulator 418 may be configured to store all samples of a single oversampling period. Accumulator 418 may be configured to use the stored samples to calculate a result for the oversampling period.

[0126] An example describing how the accumulator 418 works is as follows. These four samples are collected during a fast OVS cycle. The collected data: the first sample is 151, the second sample is 151, the third sample is 152, and the fourth sample is 151. At the beginning of the OVS cycle (before the first sample), the accumulator (acc) is equal to 0. After the first sample is completed, acc = 151. After the second sample is completed, acc = 151 + 151 = 302. After the third sample, acc = 302 + 152 = 454. After the final fourth sample, acc = 454 + 151 = 605. Then, after the fourth sample, the accumulator also needs to calculate the oversampled result, result = acc / 2 = 302.5 or 303 (rounded).

[0127] ADC 400 may include a controller 420 configured to receive the first sample, determine the variable position and the static position, and control SAR logic circuit 412 to acquire a second sample as previously described.

[0128] Controller 420 can be a small state machine (similar to a microcontroller core) that executes a simple program. Such a state machine can be designed using HDL language.

[0129] The controller 420 may also be configured to determine the bit position that needs to be measured and control the SAR logic circuit 412 to generate the bit value that needs to be measured, as described above.

[0130] The operation of ADC 400 may be understood with reference to the description provided previously, particularly with respect to ADC 100 and ADC 200 , which will be clear to the skilled person.

[0131] The controller 420 can be described as being in a conventional SAR ADC structure (eg Figure 1 The fast OVS logic block implemented in the ADC 100 given in FIG.

[0132] In operation, the fast OVS logic block analyzes the first full sample of ADC data and then controls the SAR logic block 412 to measure the bits of each input data word. However, unlike conventional SAR ADCs, only a few bits that affect the result are measured during one oversampling cycle. The input to the fast OVS logic block 420 is the number of noise bits set by the user and the SAR logic block output that provides the first sample of ADC data.

[0133] This method assumes that only a few bits of the output data word change during one oversampling cycle. Other bits can be skipped or restored using the measured bits. In contrast, the traditional oversampling process requires all bits to be measured by the ADC for sampling.

[0134] Figure 5 Is a description Figure 4 The operation of the ADC 400 is shown in flowchart 500 and can be described as follows:

[0135] 1. Set the "noise_bits" value. The allowed range is 1, 2, ... [ADC resolution - 3].

[0136] 2. Perform a sample / convert process to get the ADC result. Store the result in the accumulator. Then analyze the ADC result and define the bit position:

[0137] Find twice the noise bit. This bit is the next bit to the left of the noise bit.

[0138] Find the carry bits. These bits are the next bits to the left of the double noise bit, which have the same value as the double noise bit. There may also be a situation where there is no carry bit and the double noise bit follows the full noise bit.

[0139] Find the full noise bit. This bit is the first bit to the left of the carry bit and is not equal to twice the noise bit.

[0140] Find the skipped bits. These are the bits that are immediately to the left of the full noise bit. These bits do not change during the oversampling process. There may also be cases where there are no skipped bits.

[0141] 3. All subsequent sampling / conversion iterations are performed M times in a loop. Where M = K OVS -1

[0142] Sampling is performed (charging the sampling capacitor).

[0143] Set the internal DAC of the SAR ADC to skip bit values.

[0144] Measure the total noise bit.

[0145] The internal DAC is set to the carry bit value using the following conditions:

[0146] oIf all noise bits are 0, then each carry bit = 1.

[0147] oIn other cases, each carry bit = 0.

[0148] All other bits (twice the noise bit and the noise bit) are measured using conventional SAR principles.

[0149] Store the result in the accumulator (add the current sample to the accumulator data)

[0150] 4. Calculate the results of the OVS process:

[0151]

[0152] Where Acc is the data of the accumulator, K OVS is the oversampling ratio and N is the desired number of additional bits of resolution.

[0153] The efficiency of the fast OVS method can be evaluated using the following equation:

[0154]

[0155] Among them, OVS_TIME is the time required to execute a single regular OVS process, and FAST_OVS_TIME is the time required to execute a single fast OVS process.

[0156] For a 12-bit ADC, the sampling time t 采样 = 1 clock, t 转换 = 12 clocks, peak-to-peak noise is 3 bits (8 counts), and the oversampling ratio is K OVS =16

[0157]

[0158] For the current example, the Fast OVS approach achieves twice the data acquisition speed and cuts the energy consumption by half compared to competing devices.

[0159] The following is a brief description of conventional oversampling.

[0160] In the case of a 2-bit ADC, the four possible output options are:

[0161] (b) 00 = 0 or (1 / 4) Vref,

[0162] (b) 01 = 1 or (2 / 4) Vref,

[0163] (b) 10 = 2 or (3 / 4) Vref,

[0164] (b) 11=3 or (4 / 4)Vref.

[0165] The shift of 1's between the digital code and the Vref value is due to the binary number format. Counting starts at zero.

[0166] It is desirable to increase the ADC resolution by 1 bit to obtain a 3-bit result by oversampling.

[0167] Fig. 6(a) is a diagram showing the output of a 2-bit ADC. Fig. 6(b) is a diagram showing the output of a 3-bit ADC. The signal applied to the input terminals of the 2-bit ADC and the 3-bit ADC is the same signal.

[0168] FIG. 6( c ) is a graph showing four conversions of a noisy signal injected into the input of a 2-bit ADC.

[0169] The output of the 2-bit ADC is: Sample 0 = 3, Sample 1 = 3, Sample 2 = 2, Sample 3 = 3 (decimal). Or Sample 0 = (4 / 4)Vref, Sample 1 = (4 / 4)Vref, Sample 2 = (3 / 4)Vref, Sample 3 = (4 / 4)Vref. To calculate the oversampled result, the sum of the four ADC samples must be divided by four. OVS result = (3+3+2+3) / 2 = 5.5≈6 (rounded because the ADC uses integer arithmetic) or (7 / 8)Vref.

[0170] A description of how the accumulator works is as follows. Figure 7 is a graph showing example results utilizing an accumulator using a 2-bit ADC with oversampling.

[0171] A conventional accumulator is a long register that holds the sum of the input data. In an embodiment of the present disclosure, the accumulator includes functionality to calculate oversampled results.

[0172] The accumulator plays a role regardless of whether the input data is received using regular OVS or fast OVS. The accumulator's task is to sum the data samples and then calculate the OVS result at the end of the OVS cycle. From the accumulator's perspective, the difference between the regular OVS approach and fast OVS is that when operating in fast OVS mode, the second sample of an OVS cycle and all other samples will come into the input of the accumulator faster.

[0173] Various improvements and modifications may be made to the above without departing from the scope of the present disclosure.

Claims

1. An analog-to-digital converter for converting an analog signal into a digital signal by sampling the analog signal to generate a digital signal, the analog-to-digital converter being configured to: acquiring a first sample, the first sample comprising a first plurality of bits representing the digital signal; determining one or more bit positions within the first plurality of bits that are variable; determining one or more bit positions that are static within the first plurality of bits; and acquiring a second sample after the first sample has been acquired, the second sample comprising a second plurality of bits representing the digital signal; wherein: To collect the second sample: i) generating bit values ​​of at least a portion of the variable one or more bit positions by sampling the analog signal; as well as ii) setting the bit value of each of the static one or more bit positions to the same bit value as the bit value of the corresponding bit position in the first sample.

2. The analog-to-digital converter according to claim 1, wherein the analog-to-digital converter is configured to: the number of received noise bits; and One or more bit positions within the first plurality of bits that are variable are determined using the first sample and the number of noise bits.

3. The analog-to-digital converter according to claim 2, wherein the analog-to-digital converter is configured to: determining which bit positions of the variable one or more bit positions within the first plurality of bits need to be measured; and To acquire the second sample, a bit value of each bit position in one or more bit positions that need to be measured is generated by sampling the analog signal.

4. The analog-to-digital converter according to claim 3, wherein: The variable bit positions include a noise bit, a double noise bit, a carry bit and a full noise bit, and the bit positions to be measured are the noise bit, the double noise bit and the full noise bit.

5. The analog-to-digital converter according to claim 4, wherein: The bit position of the noise bit is the least significant bit.

6. The analog-to-digital converter according to claim 5, wherein: The bit position of the twice noise bit is one bit position to the left of the noise bit.

7. The analog-to-digital converter according to claim 6, wherein: The carry bit is the bit to the left of the twice noise bit that has the same bit value as the twice noise bit and is the bit to the right of the next bit with a different value, the next bit with a different value being the full noise bit.

8. The analog-to-digital converter according to claim 7, wherein the analog-to-digital converter is configured to: To acquire the second sample, generating a bit value of each of the noise bit, the twice noise bit, and the full noise bit by sampling the analog signal; and The value of the carry bit is set to the inverse value of the full noise bit.

9. An analog-to-digital converter according to any preceding claim, wherein: Sampling the analog signal to generate the digital signal includes oversampling.

10. The analog-to-digital converter of claim 9, wherein the analog-to-digital converter is a successive approximation register analog-to-digital converter.

11. The analog-to-digital converter according to claim 10, comprising: a sample and hold circuit configured to receive an input voltage; a digital-to-analog converter configured to receive a reference voltage; a comparator configured to receive a first signal from the digital-to-analog converter and a second signal from the sample and hold circuit; as well as A SAR logic circuit is configured to receive a comparator output signal from the comparator and provide a SAR output signal to the digital-to-analog converter.

12. The analog-to-digital converter of claim 11, comprising an accumulator configured to store the first sample and to calculate a result of an oversampling process using the first sample.

13. A method of converting an analog signal into a digital signal using an analog-to-digital converter by sampling the analog signal to generate a digital signal, the method comprising: acquiring a first sample, the first sample comprising a first plurality of bits representing the digital signal; determining one or more bit positions within the first plurality of bits that are variable; determining one or more bit positions that are static within the first plurality of bits; and acquiring a second sample after the first sample has been acquired, the second sample comprising a second plurality of bits representing the digital signal; wherein: To collect the second sample: i) generating bit values ​​of at least a portion of the variable one or more bit positions by sampling the analog signal; as well as ii) setting the bit value of each of the static one or more bit positions to the same bit value as the bit value of the corresponding bit position in the first sample.

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