A delta-sigma modulator

Abstract

The application discloses a kind of Delta-Sigma modulators, including first integral module, second integral module, third integral module, accumulation module and comparator module;The first integral module, second integral module and the third integral module are connected with the comparator module by the accumulation module;The circuit structure of the first noninverting input structure and the first inverting input structure is identical;The first noninverting input structure includes first resistance, first capacitance, second switch, third switch, fourth switch, fifth switch, sixth switch and seventh switch.This method can improve linearity.The application can be widely applied to integrated circuit technical field.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a Delta-Sigma modulator. BACKGROUND

[0002] An analog-to-digital converter (ADC) is an important analog circuit, which converts an analog signal input from the outside into a binary digital code through certain rules. Different types of ADCs have different precision and speed, so their application fields are also different. For designers, how to implement a high-performance ADC has always been a difficult problem.

[0003] Today's single-type ADCs include pipeline, successive approximation register (SAR), flash, Delta-Sigma, and many other types. Among various ADC architectures, discrete-time (DT) Delta-Sigma ADC is the most suitable type for achieving high precision in low-frequency applications described above.

[0004] A Delta-Sigma ADC is composed of a Delta-Sigma modulator and a digital decimation filter. It uses oversampling and noise shaping techniques to modulate a low-speed analog input signal into a high-speed digital code stream, and then performs a down-conversion filtering operation through a digital filter to obtain a high-precision digital output signal. How to make the analog circuit part of the Delta-Sigma modulator in the ADC work in a lower voltage environment while maintaining good performance has become one of the key research issues in academia and industry.

[0005] In related technologies, in order to make the ADC exhibit good performance, the Delta-Sigma modulator in the designed ADC uses complementary switches to improve the linearity of the switches. However, the improvement is limited in magnitude and cannot meet the high-precision requirements of the ADC. The Delta-Sigma modulator can also use clock boosting technology and bootstrap switches, which can effectively enhance the linearity of the switches by generating higher voltage levels, but require additional hardware overhead. Therefore, a new Delta-Sigma modulator is urgently needed. SUMMARY

[0006] The present application aims to at least partially solve one of the technical problems existing in the prior art.

[0007] To this end, an object of an embodiment of the present application is to provide a Delta-Sigma modulator, which can improve linearity.

[0008] In order to achieve the above technical purposes, the technical scheme adopted by the embodiment of the present application comprises: a Delta-Sigma modulator comprising a first integration module, a second integration module, a third integration module, an accumulation module and a comparator module; the first integration module, the second integration module and the third integration module are connected with the accumulation module and the comparator module; wherein the first integration module comprises a first non-inverting input structure, a first inverting input structure, a first switch, an input chopper, a first trans-impedance amplifier, an output chopper, a first feedback capacitor and a second feedback capacitor; the first non-inverting input structure and the first inverting input structure are connected through the first switch; one end of the first feedback capacitor and the first non-inverting input structure are connected with the non-inverting input end of the first trans-impedance amplifier through the input chopper; one end of the second feedback capacitor and the first inverting input structure are connected with the inverting input end of the first trans-impedance amplifier through the input chopper; the other end of the first feedback capacitor is connected with the inverting output end of the first trans-impedance amplifier through the output chopper; the other end of the second feedback capacitor is connected with the non-inverting output end of the first trans-impedance amplifier through the output chopper; the circuit structure of the first non-inverting input structure and the first inverting input structure is the same; the first non-inverting input structure comprises a first resistor, a first capacitor, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch and a seventh switch; one end of the first resistor is connected with a differential input signal, and the other end of the first resistor is connected with the input chopper through the second switch; one end of the first capacitor is connected with a common mode level through the third switch, and the other end of the first capacitor is connected with the common mode level through the fourth switch; the other end of the first capacitor is connected with a first reference voltage through the sixth switch, and the other end of the first capacitor is connected with a second reference voltage through the seventh switch; one end of the first capacitor is connected with the input chopper through the third switch.

[0009] In addition, according to the method for generating an arbitrary orthogonal pulse frequency division output according to any one of the above embodiments of the present application, the following additional technical features can also be provided.

[0010] Further, in the embodiment of the present application, the accumulation module comprises a first accumulation sub-circuit to an eighth accumulation sub-circuit; the first accumulation sub-circuit, the third accumulation sub-circuit, the fifth accumulation sub-circuit and the seventh accumulation sub-circuit are connected in parallel and connected with the comparator module; the second accumulation sub-circuit, the fourth accumulation sub-circuit, the sixth accumulation sub-circuit and the eighth accumulation sub-circuit are connected in parallel and connected with the comparator module; the first accumulation sub-circuit and the second accumulation sub-circuit are connected with the differential input signal, the third accumulation sub-circuit and the fourth accumulation sub-circuit are connected with two output terminals of the first integration module; the fifth accumulation sub-circuit and the sixth accumulation sub-circuit are connected with two output terminals of the second integration module; the seventh accumulation sub-circuit and the eighth accumulation sub-circuit are connected with two output terminals of the second integration module.

[0011] Further, in the embodiment of the present application, the first accumulation sub-circuit, the second accumulation sub-circuit, the third accumulation sub-circuit, the fourth accumulation sub-circuit, the fifth accumulation sub-circuit, the sixth accumulation sub-circuit, the seventh accumulation sub-circuit and the eighth accumulation sub-circuit are of the same structure; each accumulation sub-circuit comprises a second capacitor, an eighth switch and a ninth switch; one end of the eighth switch is an input terminal of each accumulation sub-circuit, the other end of the eighth switch is connected with one end of the second capacitor, one end of the second capacitor is connected with the common mode level through the ninth switch; the other end of the second capacitor is an output terminal of each accumulation sub-circuit.

[0012] Further, in the embodiment of the present application, the modulator comprises a first adjustment switch and a second adjustment switch; the first accumulation sub-circuit, the third accumulation sub-circuit, the fifth accumulation sub-circuit and the seventh accumulation sub-circuit are connected in parallel and connected with the common mode level through the first adjustment switch; the second accumulation sub-circuit, the fourth accumulation sub-circuit, the sixth accumulation sub-circuit and the eighth accumulation sub-circuit are connected in parallel and connected with the common mode level through the second adjustment switch.

[0013] Further, in the embodiment of the present application, the second switch, the fourth switch, the first adjustment switch and the second adjustment switch are switches modulated by a continuous waveform signal, wherein the duty cycle of the signal is equal to 10%.

[0014] Further, in the embodiment of the present application, the second integration module comprises a second trans-impedance amplifier, a second non-inverting input structure, a second inverting input structure, a third feedback capacitor and a fourth feedback capacitor; the second non-inverting input structure is connected with a non-inverting input end of the second trans-impedance amplifier; the second inverting input structure is connected with an inverting input end of the second trans-impedance amplifier; one end of the third feedback capacitor is connected with the non-inverting input end of the second trans-impedance amplifier; the other end of the third feedback capacitor is connected with an inverting output end of the second trans-impedance amplifier; one end of the fourth feedback capacitor is connected with the inverting input end of the second trans-impedance amplifier; the other end of the fourth feedback capacitor is connected with a non-inverting output end of the second trans-impedance amplifier.

[0015] Further, in the embodiment of the present application, the third integration module comprises a third trans-impedance amplifier, a third non-inverting input structure, a third inverting input structure, a fifth feedback capacitor and a sixth feedback capacitor;

[0016] the third non-inverting input structure is connected with a non-inverting input end of the third trans-impedance amplifier; the third inverting input structure is connected with an inverting input end of the third trans-impedance amplifier; one end of the fifth feedback capacitor is connected with the non-inverting input end of the third trans-impedance amplifier; the other end of the fifth feedback capacitor is connected with an inverting output end of the third trans-impedance amplifier; one end of the sixth feedback capacitor is connected with the inverting input end of the third trans-impedance amplifier; the other end of the sixth feedback capacitor is connected with a non-inverting output end of the third trans-impedance amplifier.

[0017] Further, in the embodiment of the present application, the third non-inverting input structure, the third inverting input structure, the second non-inverting input structure and the second inverting input structure are the same, and any one input structure comprises a third capacitor, a tenth switch, an eleventh switch, a twelfth switch and a thirteenth switch;

[0018] one end of the tenth switch is used as an input end of the input structure, the other end of the tenth switch is connected with one end of the third capacitor, and the common-mode level is connected with one end of the third capacitor through the eleventh switch; the other end of the third capacitor is connected with one end of the thirteenth switch, and the common-mode level is connected with the other end of the third capacitor through the twelfth switch; the other end of the thirteenth switch is used as the input end of the input structure.

[0019] Further, in the embodiment of the present application, the comparator module comprises a comparator and a fourteenth switch; an output end of the comparator is an output end of the Delta-Sigma modulator; the first integration module, the second integration module and the third integration module are connected with the fourteenth switch through the accumulation module; the fourteenth switch is connected with the comparator.

[0020] Further, in the embodiments of the present application, the first switch, the thirteenth switch and the fourteenth switch are all switches modulated by a continuous waveform signal, wherein the duty cycle of the signal is equal to 90%; the twelfth switch is a switch modulated by a continuous waveform signal, wherein the duty cycle of the signal is equal to 10%.

[0021] The advantages and beneficial effects of the present application will be partially given in the following description, partially will become obvious from the following description, or will be learned by the practice of the present application:

[0022] The present application is a Delta-Sigma modulator composed of a first integration module, a second integration module, a third integration module, an accumulation module and a comparator module, and there is a first integration module composed of a first non-inverting input structure, a first inverting input structure, a first switch, an input chopper, a first trans-impedance amplifier, an output chopper, a first feedback capacitor and a second feedback capacitor in the Delta-Sigma modulator, and a first non-inverting input structure composed of a first resistor, a first capacitor, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch and a seventh switch instead of the traditional Delta-Sigma modulator, the non-inverting input structure of the present application can improve the linearity of the Delta-Sigma modulator, improve the defect of generating large voltage spikes and reduce the thermal noise. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 It is a circuit structure schematic diagram of a Delta-Sigma modulator in one specific embodiment of the present application;

[0024] Figure 2 It is a schematic diagram of switch control waveform of the Delta-Sigma modulator in one specific embodiment of the present application;

[0025] Figure 3 It is a circuit structure schematic diagram of another Delta-Sigma modulator in one specific embodiment of the present application;

[0026] Figure 4 It is a structure schematic diagram of a Delta-Sigma modulator in the related art;

[0027] Figure 5 It is a schematic diagram of the trans-impedance amplifier OTA1 in the first stage integrator in one specific embodiment of the present application;

[0028] Figure 6 It is a circuit structure schematic diagram of the first stage common mode feedback circuit in one specific embodiment of the present application;

[0029] Figure 7A schematic diagram of a circuit structure of a second-stage common-mode feedback circuit in one embodiment of the present application;

[0030] Figure 8 An equivalent circuit diagram of the first-stage integrator when the first-stage integrator operates as an SC integrator in one embodiment of the present application;

[0031] Figure 9 An equivalent circuit diagram of the first-stage integrator when the RC integrator operates in one embodiment of the present application. DETAILED DESCRIPTION

[0032] The principles and processes of the Delta-Sigma modulator in the embodiments of the present application are described below in detail.

[0033] Referring to Figure 1 , the present application provides a Delta-Sigma modulator.

[0034] The Delta-Sigma modulator can include a first integrator module, a second integrator module, a third integrator module, an accumulation module, and a comparator module; the first integrator module, the second integrator module, and the third integrator module are connected to the accumulation module and the comparator module.

[0035] The first integrator module includes a first non-inverting input structure, a first inverting input structure, a first switch S1, an input chopper X1, a first trans-impedance amplifier OTP1, an output chopper X2, a first feedback capacitor C4a, and a second feedback capacitor C4b; the first non-inverting input structure and the first inverting input structure are connected through the first switch S1; one end of the first feedback capacitor C4a and the first non-inverting input structure are connected to the non-inverting input terminal of the first trans-impedance amplifier OTP1 through the input chopper X1; one end of the second feedback capacitor C4b and the first inverting input structure are connected to the inverting input terminal of the first trans-impedance amplifier OTP1 through the input chopper X1; the other end of the first feedback capacitor C4a is connected to the inverting output terminal of the first trans-impedance amplifier OTP1 through the output chopper X2; the other end of the second feedback capacitor C4b is connected to the non-inverting output terminal of the first trans-impedance amplifier OTP1 through the output chopper X2;

[0036] The circuit structure of the first non-inverting input structure is the same as that of the first inverting input structure;

[0037] Referring to Figure 1 , the first non-inverting input structure includes a first resistor R1a, a first capacitor C1a, a second switch S2a, a third switch S3a, a fourth switch S4a, a fifth switch S5a, a sixth switch S6a, and a seventh switch S7a;

[0038] Referring to Figure 1, one end of the first resistor R1a is connected to the differential input signal V inn . The other end of the first resistor R1a is connected to the input chopper through the second switch S2a; one end of the first capacitor C1a is connected to the common mode voltage V cm through the third switch S3a, the other end of the first capacitor C1a is connected to the common mode voltage V cm through the fourth switch S4a, the other end of the first capacitor C1a is connected to the first reference voltage through the sixth switch S6a, the other end of the first capacitor C1a is connected to the second reference voltage through the seventh switch S7a, and one end of the first capacitor C1a is connected to the input chopper X1 through the third switch S3a.

[0039] Similarly, referring to Figure 1 , the first inverting input structure includes a first resistor R1b, a first capacitor C1b, a second switch S2b, a third switch S3b, a fourth switch S4b, a fifth switch S5b, a sixth switch S6b, and a seventh switch S7b;

[0040] One end of the first resistor R1b is connected to the differential input signal V inp . The other end of the first resistor R1b is connected to the input chopper through the second switch S2b; one end of the first capacitor C1b is connected to the common mode voltage through the third switch S3b, the other end of the first capacitor C1b is connected to the common mode voltage through the fourth switch S4b, the other end of the first capacitor C1b is connected to the first reference voltage through the sixth switch S6b, the other end of the first capacitor C1b is connected to the second reference voltage through the seventh switch S7b, and one end of the first capacitor C1b is connected to the input chopper X1 through the third switch S3b.

[0041] It can be understood that the input chopper X1 and the output chopper X2 both have a non-inverting input end and an inverting input end, and have a non-inverting input end and an inverting output end. The input chopper X1 does not change the positive and negative phases of the signal input to the input chopper X1, and the output chopper X2 also does not change the positive and negative phases of the signal input to the output chopper X2.

[0042] Further, referring to Figure 1 , in some possible embodiments of the present application, the accumulation module includes first to eighth accumulation sub-circuits; the first, third, fifth, and seventh accumulation sub-circuits are connected in parallel and connected to the comparator module; the second, fourth, sixth, and eighth accumulation sub-circuits are connected in parallel and connected to the comparator module; and the first and second accumulation sub-circuits are connected to the differential input signal. Specifically, the first accumulation sub-circuit is connected to the positive signal V inp of the differential input signal, and the second accumulation sub-circuit is connected to the negative signal V innThe third and fourth accumulation sub-circuits are connected with two output terminals of the first integration module. Specifically, the third accumulation sub-circuit is connected with a negative signal of the first integration module, and the fourth accumulation sub-circuit is connected with a negative signal of the first integration module. The fifth and sixth accumulation sub-circuits are connected with two output terminals of the second integration module. Specifically, the fifth accumulation sub-circuit is connected with a negative signal of the second integration module, and the sixth accumulation sub-circuit is connected with a negative signal of the second integration module. The seventh and eighth accumulation sub-circuits are connected with two output terminals of the third integration module. Specifically, the seventh accumulation sub-circuit is connected with a negative signal of the third integration module, and the eighth accumulation sub-circuit is connected with a negative signal of the third integration module.

[0043] Further, in some possible embodiments of the present application, the first, second, third, fourth, fifth, sixth, seventh and eighth accumulation sub-circuits have the same structure.

[0044] Each accumulation sub-circuit comprises a second capacitor, an eighth switch and a ninth switch. One end of the eighth switch serves as an input terminal of each accumulation sub-circuit, the other end of the eighth switch is connected with one end of the second capacitor, and one end of the second capacitor is connected with a common mode level through the ninth switch. The other end of the second capacitor serves as an output terminal of each accumulation sub-circuit.

[0045] Specifically, the first accumulation sub-circuit comprises a second capacitor C2a, an eighth switch S8a and a ninth switch S9a. One end of the eighth switch S8a serves as an input terminal of each accumulation sub-circuit, the other end of the eighth switch S8a is connected with one end of the second capacitor C2a, and one end of the second capacitor C2a is connected with a common mode level through the ninth switch S9a. The other end of the second capacitor C2a serves as an output terminal of the first accumulation sub-circuit.

[0046] Specifically, the second accumulation sub-circuit comprises a second capacitor C2b, an eighth switch S8b and a ninth switch S9b. One end of the eighth switch S8b serves as an input terminal of each accumulation sub-circuit, the other end of the eighth switch S8b is connected with one end of the second capacitor C2b, and one end of the second capacitor C2b is connected with a common mode level through the ninth switch S9b. The other end of the second capacitor C2b serves as an output terminal of the second accumulation sub-circuit.

[0047] Specifically, the third accumulation sub-circuit comprises a second capacitor C2c, an eighth switch S8c and a ninth switch S9c. One end of the eighth switch S8c serves as an input terminal of each accumulation sub-circuit, the other end of the eighth switch S8c is connected with one end of the second capacitor C2c, and one end of the second capacitor C2c is connected with a common mode level through the ninth switch S9c. The other end of the second capacitor C2c serves as an output terminal of the third accumulation sub-circuit.

[0048] Specifically, the fourth accumulation sub-circuit each comprises a second capacitor C2d, an eighth switch S8d and a ninth switch S9d; one end of the eighth switch S8d is an input end of each accumulation sub-circuit, the other end of the eighth switch S8d is connected with one end of the second capacitor C2d, one end of the second capacitor C2d is connected with the common mode level through the ninth switch S9d; the other end of the second capacitor C2d is an output end of the fourth accumulation sub-circuit.

[0049] Specifically, the fifth accumulation sub-circuit each comprises a second capacitor C2e, an eighth switch S8e and a ninth switch S9e; one end of the eighth switch S8e is an input end of each accumulation sub-circuit, the other end of the eighth switch S8e is connected with one end of the second capacitor C2e, one end of the second capacitor C2e is connected with the common mode level through the ninth switch S9e; the other end of the second capacitor C2e is an output end of the fifth accumulation sub-circuit.

[0050] Specifically, the sixth accumulation sub-circuit each comprises a second capacitor C2f, an eighth switch S8f and a ninth switch S9f; one end of the eighth switch S8f is an input end of each accumulation sub-circuit, the other end of the eighth switch S8f is connected with one end of the second capacitor C2f, one end of the second capacitor C2f is connected with the common mode level through the ninth switch S9f; the other end of the second capacitor C2f is an output end of the sixth accumulation sub-circuit.

[0051] Specifically, the seventh accumulation sub-circuit each comprises a second capacitor C2g, an eighth switch S8g and a ninth switch S9g; one end of the eighth switch S8g is an input end of each accumulation sub-circuit, the other end of the eighth switch S8g is connected with one end of the second capacitor C2g, one end of the second capacitor C2g is connected with the common mode level through the ninth switch S9g; the other end of the second capacitor C2g is an output end of the seventh accumulation sub-circuit.

[0052] Specifically, the eighth accumulation sub-circuit each comprises a second capacitor C2h, an eighth switch S8h and a ninth switch S9h; one end of the eighth switch S8h is an input end of each accumulation sub-circuit, the other end of the eighth switch S8h is connected with one end of the second capacitor C2h, one end of the second capacitor C2h is connected with the common mode level through the ninth switch S9h; the other end of the second capacitor C2h is an output end of the eighth accumulation sub-circuit.

[0053] Further, in some possible embodiments of the present application, the modulator comprises a first adjusting switch S15a and a second adjusting switch S15b; the first accumulation sub-circuit, the third accumulation sub-circuit, the fifth accumulation sub-circuit and the seventh accumulation sub-circuit are connected in parallel and then connected with the common mode level V cmThe second, fourth, sixth and eighth accumulation sub-circuits are connected in parallel and then connected with a common mode level V through a second adjusting switch S15b. cm are connected.

[0054] Further, referring to Figure 1 and Figure 2 In some possible embodiments of the present application, the second switch, the fourth switch, the first adjusting switch and the second adjusting switch are all switches modulated by a continuous waveform signal, and the duty cycle of the signal is equal to 10%. Specifically, in Figure 1 each switch is a switch modulated by a continuous waveform signal, and the switches with labels P1 and P1D are control waveforms with a duty cycle of 10%, and the switches with labels P2 and P2D are control waveforms with a duty cycle of 90%.

[0055] Further, referring to Figure 1 In some possible embodiments of the present application, the second integration module comprises a second trans-impedance amplifier OTP2, a second non-inverting input structure, a second inverting input structure, a third feedback capacitor C5a and a fourth feedback capacitor C5b; the second non-inverting input structure is connected with a non-inverting input end of the second trans-impedance amplifier OTP2; the second inverting input structure is connected with an inverting input end of the second trans-impedance amplifier OTP2; one end of the third feedback capacitor C5a is connected with the non-inverting input end of the second trans-impedance amplifier OTP2; the other end of the third feedback capacitor C5a is connected with an inverting output end of the second trans-impedance amplifier OTP2; one end of the fourth feedback capacitor C5b is connected with the inverting input end of the second trans-impedance amplifier OTP2; the other end of the fourth feedback capacitor C5b is connected with a non-inverting output end of the second trans-impedance amplifier OTP2.

[0056] Further, referring to Figure 1 In some possible embodiments of the present application, the third integration module comprises a third trans-impedance amplifier OTP3, a third non-inverting input structure, a third inverting input structure, a fifth feedback capacitor C5c and a sixth feedback capacitor C5d.

[0057] The third non-inverting input structure is connected with a non-inverting input end of the third trans-impedance amplifier OTP3; the third inverting input structure is connected with an inverting input end of the third trans-impedance amplifier OTP3; one end of the fifth feedback capacitor C5c is connected with the non-inverting input end of the third trans-impedance amplifier OTP3; the other end of the fifth feedback capacitor C5c is connected with an inverting output end of the third trans-impedance amplifier OTP3; one end of the sixth feedback capacitor C5d is connected with the inverting input end of the third trans-impedance amplifier OTP3; the other end of the sixth feedback capacitor C5d is connected with a non-inverting output end of the third trans-impedance amplifier OTP3.

[0058] Further, in some possible embodiments of the present application, the third non-inverting input structure, the third inverting input structure, the second non-inverting input structure and the second inverting input structure are the same.

[0059] Specifically, referring to Figure 1 , the second non-inverting input structure includes a third capacitor C3a, a tenth switch S10a, an eleventh switch S11a, a twelfth switch S12a and a thirteenth switch S13a. In the second non-inverting input structure, one end of the tenth switch S10a is an input end of the input structure, the other end of the tenth switch S10a is connected with one end of the third capacitor C3a, and the common mode level is connected with one end of the third capacitor C3a through the eleventh switch S11a; the other end of the third capacitor C3a is connected with one end of the thirteenth switch S13a, and the common mode level is connected with the other end of the third capacitor C3a through the twelfth switch S12a; the other end of the thirteenth switch S13a is an input end of the input structure.

[0060] Referring to Figure 1 , the second inverting input structure includes a third capacitor C3b, a tenth switch S10b, an eleventh switch S11b, a twelfth switch S12b and a thirteenth switch S13b. In the second inverting input structure, one end of the tenth switch S10b is an input end of the input structure, the other end of the tenth switch S10b is connected with one end of the third capacitor C3b, and the common mode level is connected with one end of the third capacitor C3b through the eleventh switch S11b; the other end of the third capacitor C3b is connected with one end of the thirteenth switch S13b, and the common mode level is connected with the other end of the third capacitor C3b through the twelfth switch S12b; the other end of the thirteenth switch S13b is an input end of the input structure.

[0061] Referring to Figure 1 , the third non-inverting input structure includes a third capacitor C3c, a tenth switch S10c, an eleventh switch S11c, a twelfth switch S12c and a thirteenth switch S13c. In the third non-inverting input structure, one end of the tenth switch S10c is an input end of the input structure, the other end of the tenth switch S10c is connected with one end of the third capacitor C3c, and the common mode level is connected with one end of the third capacitor C3c through the eleventh switch S11c; the other end of the third capacitor C3c is connected with one end of the thirteenth switch S13c, and the common mode level is connected with the other end of the third capacitor C3c through the twelfth switch S12c; the other end of the thirteenth switch S13c is an input end of the input structure.

[0062] Referring to Figure 1The third inverting input structure includes a third capacitor C3d, a tenth switch S10d, an eleventh switch S11d, a twelfth switch S12d, and a thirteenth switch S13d. In the third inverting input structure, one end of the tenth switch S10d is an input end of the input structure, the other end of the tenth switch S10d is connected with one end of the third capacitor C3d, and the common mode level is connected with one end of the third capacitor C3d through the eleventh switch S11d; the other end of the third capacitor C3d is connected with one end of the thirteenth switch S13d, and the common mode level is connected with the other end of the third capacitor C3d through the twelfth switch S12d; the other end of the thirteenth switch S13d is an input end of the input structure.

[0063] Further, in some possible embodiments of the present application, the comparator module includes a comparator M1 and two fourteenth switches. The two fourteenth switches are S14a and S14b respectively; the output end of the comparator M1 is the output end of the Delta-Sigma modulator; the first integral module, the second integral module, and the third integral module are connected with the fourteenth switches through the accumulation module; and the fourteenth switches are connected with the comparator.

[0064] Further, in some possible embodiments of the present application, the first switch, the thirteenth switch, and the fourteenth switch are all switches modulated by continuous wave signals, wherein the duty cycle of the signals is equal to 90%; and the twelfth switch is a switch modulated by a continuous wave signal, wherein the duty cycle of the signal is equal to 10%. Specifically, in the Figure 1 , each switch is a switch modulated by a continuous wave signal, wherein the switches marked as P1 and P1D are control waveforms with a duty cycle of 10%, and the switches marked as P2 and P2D are control waveforms with a duty cycle of 90%.

[0065] The specific calculation principle of the present application will be described below in combination with the drawings:

[0066] The internal circuit of the Delta-Sigma modulator of the present application includes a three-stage integrator and a comparator. The power supply voltage is 1.5V, Vrefp is 1.5V, V refn is 0V, and V cm is 0.75V. For a 1kHz bandwidth, the sampling clock frequency FS is set to 256kHz, and the oversampling ratio (OSR) is 128. The entire Delta-Sigma analog-to-digital converter is shown in Figure 3 .

[0067] The internal detailed architecture of the Delta-Sigma modulator is shown in Figure 3 , which includes a three-stage integrator and a subsequent comparator. Since the fully differential circuit structure has the advantages of improving the common mode rejection ratio and eliminating even harmonics, the modulator is implemented in a fully differential structure.

[0068] The modulator proposed in the embodiment adopts a third-order integrator cascaded feedforward (CIFF) structure. It uses a one-bit quantizer to ensure excellent linearity of the DAC. The coefficients are selected so that the out-of-band gain (OBG) of the noise transfer function (NTF) is limited to 1.42 to ensure system stability.

[0069] The analog circuit and the digital circuit of the conventional technology use a low-voltage power supply to simplify power management, reduce power consumption and area. However, under the condition of low-voltage power supply, the use of switched capacitor (SC) faces great challenges.

[0070] The conventional technology uses complementary switching to improve the switching linearity, but the improvement is limited in range and cannot meet the high-precision requirement. The clock boosting technology and bootstrap switching can effectively enhance the switching linearity by generating a higher voltage level, but require additional hardware overhead.

[0071] The replacement of the input switching capacitor integrator and the resistive integrator in the related art is a direct solution, as shown in Figure 4 However, due to the large voltage spike generated at the input node of the OTA during the operation of the switching capacitor integrator, the continuous-time (CT) integration of the input signal is disturbed, and the R I A considerable thermal noise is also introduced.

[0072] To solve the above problems, the embodiment proposes a low-voltage design based on a hybrid switching integrator, which effectively improves the linearity without the need for bootstrap switching or clock boosting technology. In addition, a non-50% duty cycle timing is also proposed. This timing extends the integration time of the SC integrator, thereby relaxing the requirement on the OTA. At the same time, it reduces the resistance value in the resistive-capacitive (RC) integrator and alleviates the thermal noise introduced by the integration resistor. In order to adapt to this timing, a corresponding design of adjustable Miller-compensated two-stage A / AB class OTA is proposed.

[0073] The implementation of the circuit stage as shown in Figure 3 and the implementation of the timing diagram as shown in Figure 2 achieves a two-phase non-overlapping clock scheme to alleviate the channel charge injection effect.

[0074] Figure 3In the circuit of FIG. 1, the first integrator is a hybrid switched integrator. During P1, the input signal is integrated by the RC integrator. The integration resistance R1 is kept at a fixed value (195 kQ) at this time, thus eliminating the nonlinearity caused by the switching conductance. In the P2 phase, the feedback signal of the DAC is integrated by the SC integrator, avoiding the sensitivity to clock jitter associated with continuous-time Delta-Sigma modulators. The operation of the RC integrator and the SC integrator are separated by a switch, allowing them to operate in different phases. This avoids the effect of voltage spikes generated during the operation of the SC integrator on the integration of the input signal.

[0075] At low frequencies, the 1 / f noise of the OTA limits the accuracy of the ADC. To suppress the low frequency noise, a chopping technique is employed in the first integrator with a chopping frequency of Fs / 2. The DC offset and the 1 / f noise of the OTA are modulated to the high frequency band, which is subsequently filtered out by the digital filter.

[0076] For the hybrid switched integrator structure, the value of the integrator resistance R1 is given by (1):

[0077]

[0078] Tint, in represents the time during which the input signal is integrated by the RC integrator in each sampling period. Assuming the duty cycle of phase P1 is x, the sampling period is T S , then R I should be determined as follows:

[0079]

[0080] As shown in (2), it can be observed that the smaller the duty cycle x, the smaller the value of R I . Therefore, the baseband thermal noise power introduced by R1 in the first integrator is:

[0081]

[0082] Assuming the on-resistance of S1 in the first integrator is Ron S1 = a * R I , then the thermal noise introduced by the switch is:

[0083]

[0084] where k is the Boltzmann constant and T is the absolute temperature

[0085] C S1 introduced by the switch is:

[0086]

[0087] Thus, the total baseband thermal noise power introduced by the first integrator is:

[0088]

[0089] In R I = 195 kΩ and Ron S1 When a = Ron S1 / R I is estimated to be in the range of 0.1% to 0.4%. Thus, the thermal noise and nonlinearity introduced by the switch S1 are practically negligible.

[0090] From (6), it is known that by effectively increasing the sampling capacitor CS1, the thermal noise can be reduced. However, this comes at the cost of increasing the equivalent load capacitance of the integrator OTA, which requires more power consumption. In addition, reducing the duty cycle of the P1 phase also helps to minimize the overall thermal noise. Therefore, we propose a non-50% duty cycle timing, as shown in Figure 2 The duty cycle of P1 is 0.1 and that of P2 is 0.9, which can reduce the thermal noise introduced by RI by 90% compared to the continuous-time integrator.

[0091] The DC gain, slew rate (SR), unity gain bandwidth (UGB), and output swing of the first stage integrator OTA limit the overall accuracy of the modulator. So the design of the first stage integrator OTA employs a two-stage A / AB class OTA to achieve the necessary output swing and gain, as shown in Figure 5 Since the second stage works in AB class mode of operation, the slew rate limitation only applies to the first stage. In addition, due to the push-pull operation in the second stage, it exhibits twice the rectification efficiency of the class A stage. For the same non-dominant pole, the output branch current can be approximated to half of the current used in the two-stage class A circuit. The common-mode feedback circuits of the first and second stages of the OTA are shown in Figure 6 and Figure 7 They stabilize the common-mode output voltage of the first stage at V b2 to establish the required quiescent current of the second stage, while stabilizing the common-mode output voltage of the second stage at V cm . Since the requirements on the OTAs of the second and third integrators are relaxed, they are designed as simple identical single-stage OTAs.

[0092] The increase in the duty cycle of phase P2 implies an increase in the integration time of the SC integrator per sampling period. Therefore, the requirements for SR and UGB of OTA1 become less stringent. However, for the RC integrator, due to the decrease in RI, the UGB of the RC integrator (UGB = 1 / (RI*CI1)) increases. To ensure that the poles introduced by the finite UGB of OTA1 have a negligible impact on the system, the UGB of OTA1 needs to be significantly higher than that of the RC integrator. Therefore, when switching from an SC integrator to an RC integrator, the challenge becomes how to achieve higher speeds without incurring additional power consumption. This design effectively utilizes the different equivalent load capacitances between the RC and SC integrators to address this issue.

[0093] Figure 8 This represents the equivalent circuit diagram when the first-stage integrator is used as an SC integrator.

[0094] Figure 9 This represents the equivalent circuit diagram of the first-stage integrator when the RC integrator is operating.

[0095] exist Figure 8 In the above, the equivalent load capacitance is:

[0096] C LE,SC =C L1 +C I1 / / (C S1 +C P1 (7)

[0097] exist Figure 9 In the above, the equivalent load capacitance is:

[0098] C LE,RC =C L2 +C I1 / / C P2 (8)

[0099] In the SC integrator, to mitigate KT / C noise, the sampling capacitor CS1 (2pF) and the integrator capacitor CI1 (10pF) are designed to be larger than other parasitic capacitances CP1 and CP2, as well as load capacitances CL1 and CL2. Therefore, CLE,RC is significantly smaller than CLE,SC. Consequently, when switching from an SC integrator to an RC integrator, the lowest non-dominant pole of OTA shifts from 2gm1 / CLE,SC to a much larger value of 2gm1 / CLE,RC. This characteristic allows for greater adjustability of the Miller compensation capacitor, significantly reducing its size in RC integration mode while still meeting phase margin requirements. Figure 5 The specific circuit implementation is shown, where the Miller capacitor is configured in adjustable mode. When the RC integrator is active, switches SW1 and SW2 are off, and the Miller capacitor C... M，RC =C M0In the case of SC integrator operation, switches SW1 and SW2 are closed, and the Miller capacitor C M，SC = C M0 + N x C M0 = (N + 1)C M0 = (N + 1)C M，RC .

[0100] When the SC integrator is operating, the UGB and SR of the OTA are as follows:

[0101]

[0102] When the RC integrator is operating, the UGB and SR of the OTA are as follows:

[0103]

[0104] During SC integration, the UGB and SR of the OTA are increased by N times without changing the size, structure or power consumption of the OTA.

[0105] In the above description of the present specification, the description referring to the terms "one embodiment", "another embodiment" or "certain embodiments" or the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. The illustrative expressions of the above terms in the present specification do not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0106] Although the embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made thereto without departing from the principles and spirit of the application, the scope of which is defined by the claims and their equivalents.

[0107] The above is a specific description of the preferred embodiments of the present application, but the present application is not limited to the described embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present application, and these equivalent modifications or substitutions are included in the scope defined by the claims of the present application.

Claims

1. A delta-sigma modulator characterized by, The application relates to an integrated circuit, which comprises a first integration module, a second integration module, a third integration module, an accumulation module and a comparator module. The first integration module, the second integration module and the third integration module are connected with the accumulation module and the comparator module. The first integration module comprises a first same-phase input structure, a first reverse-phase input structure, a first switch, an input chopper, a first trans-impedance amplifier, an output chopper, a first feedback capacitor and a second feedback capacitor; the first same-phase input structure and the first reverse-phase input structure are connected through the first switch. One end of the first feedback capacitor and the first same-phase input structure are connected with the same-phase input end of the first trans-impedance amplifier through the input chopper. One end of the second feedback capacitor and the first reverse-phase input structure are connected with the reverse-phase input end of the first trans-impedance amplifier through the input chopper. The other end of the first feedback capacitor is connected with the reverse-phase output end of the first trans-impedance amplifier through the output chopper; the other end of the second feedback capacitor is connected with the same-phase output end of the first trans-impedance amplifier through the output chopper. The circuit structure of the first same-phase input structure is the same as that of the first reverse-phase input structure. The first same-phase input structure comprises a first resistor, a first capacitor, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch and a seventh switch. One end of the first resistor is connected with a differential input signal; the other end of the first resistor is connected with the input chopper through the second switch; one end of the first capacitor is connected with a common-mode level through the third switch; the other end of the first capacitor is connected with the common-mode level through the fourth switch; the other end of the first capacitor is connected with a first reference voltage through the sixth switch; the other end of the first capacitor is connected with a second reference voltage through the seventh switch; one end of the first capacitor is connected with the input chopper through the third switch. The accumulation module comprises first to eighth accumulation sub-circuits; the first, third, fifth and seventh accumulation sub-circuits are connected in parallel and then connected with the comparator module; the second, fourth, sixth and eighth accumulation sub-circuits are connected in parallel and then connected with the comparator module; the first and second accumulation sub-circuits are connected with the differential input signal; the third and fourth accumulation sub-circuits are connected with two output ends of the first integration module; the fifth and sixth accumulation sub-circuits are connected with two output ends of the second integration module; the seventh and eighth accumulation sub-circuits are connected with two output ends of the third integration module.

2. A delta-sigma modulator as claimed in claim 1, characterized in that ​ 3. A delta-sigma modulator as claimed in claim 2, characterized in that The first, second, third, fourth, fifth, sixth, seventh and eighth accumulation sub-circuits have the same structure; each accumulation sub-circuit comprises a second capacitor, an eighth switch and a ninth switch; one end of the eighth switch is an input end of each accumulation sub-circuit, the other end of the eighth switch is connected with one end of the second capacitor, and one end of the second capacitor is connected with the common mode level through the ninth switch; the other end of the second capacitor is an output end of each accumulation sub-circuit.

4. A delta-sigma modulator as claimed in claim 3, characterized in that The modulator comprises a first adjusting switch and a second adjusting switch; the first, third, fifth and seventh accumulation sub-circuits are connected in parallel and then connected with the common mode level through the first adjusting switch; the second, fourth, sixth and eighth accumulation sub-circuits are connected in parallel and then connected with the common mode level through the second adjusting switch.

5. A delta-sigma modulator as claimed in claim 4, characterized in that The second, fourth, first and second adjusting switches are switches modulated by a continuous waveform signal, wherein the duty cycle of the signal is equal to 10%.

6. The delta-sigma modulator of claim 1, wherein, The second integration module comprises a second trans-impedance amplifier, a second non-inverting input structure, a second inverting input structure, a third feedback capacitor and a fourth feedback capacitor; the second non-inverting input structure is connected with a non-inverting input end of the second trans-impedance amplifier; the second inverting input structure is connected with an inverting input end of the second trans-impedance amplifier; one end of the third feedback capacitor is connected with the non-inverting input end of the second trans-impedance amplifier; the other end of the third feedback capacitor is connected with an inverting output end of the second trans-impedance amplifier; one end of the fourth feedback capacitor is connected with the inverting input end of the second trans-impedance amplifier; the other end of the fourth feedback capacitor is connected with a non-inverting output end of the second trans-impedance amplifier.

7. A delta-sigma modulator as claimed in claim 6, characterized in that The third integration module comprises a third trans-impedance amplifier, a third non-inverting input structure, a third inverting input structure, a fifth feedback capacitor and a sixth feedback capacitor; the third non-inverting input structure is connected with a non-inverting input end of the third trans-impedance amplifier; the third inverting input structure is connected with an inverting input end of the third trans-impedance amplifier; one end of the fifth feedback capacitor is connected with the non-inverting input end of the third trans-impedance amplifier; the other end of the fifth feedback capacitor is connected with an inverting output end of the third trans-impedance amplifier; one end of the sixth feedback capacitor is connected with the inverting input end of the third trans-impedance amplifier; the other end of the sixth feedback capacitor is connected with a non-inverting output end of the third trans-impedance amplifier.

8. A delta-sigma modulator as claimed in claim 7, characterised in that, The third non-inverting input structure, the third inverting input structure, the second non-inverting input structure and the second inverting input structure are the same, and each input structure comprises a third capacitor, a tenth switch, an eleventh switch, a twelfth switch and a thirteenth switch; One end of the tenth switch is an input end of the input structure, the other end of the tenth switch is connected with one end of the third capacitor, the common mode level is connected with one end of the third capacitor through the eleventh switch; the other end of the third capacitor is connected with one end of the thirteenth switch, the common mode level is connected with the other end of the third capacitor through the twelfth switch; the other end of the thirteenth switch is an input end of the input structure.

9. A delta-sigma modulator as claimed in claim 8, characterised in that, The comparator module comprises a comparator and a fourteenth switch; the output end of the comparator is the output end of the Delta-Sigma modulator; the first integral module, the second integral module and the third integral module are connected with the fourteenth switch through the accumulation module; the fourteenth switch is connected with the comparator.

10. A delta-sigma modulator as claimed in claim 9, characterized in that The first switch, the thirteenth switch and the fourteenth switch are switches modulated by continuous waveform signals, wherein the duty cycle of the signals is equal to 90%; the twelfth switch is a switch modulated by a continuous waveform signal, wherein the duty cycle of the signal is equal to 10%.

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