A broadband current mode receiver with PVT compensation function

Abstract

The present invention discloses a broadband current mode receiver with PVT compensation function. By introducing a loop bias circuit as a bias of a transistor in a low noise amplifier, the DC potential at the output end of the low noise amplifier is fixed at a reference potential, and is not affected by PVT changes, and has better robustness; at the same time, the bias circuit of the passive mixer of the present invention adopts a tracking bias circuit, and the tracking bias makes the mixer gate bias voltage change with PVT changes, thereby compensating for the influence of PVT changes, optimizing the stability and yield of the circuit, and making the circuit maintain stable performance in different processes, voltages and temperatures, and having better robustness. In addition, the present invention adds a low noise transconductance stage between the low noise amplifier and the orthogonal passive mixer, effectively attenuating the local oscillator signal leaking to the antenna, and improving the P1dB of the circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of radio frequency receivers, and in particular relates to a broadband current mode receiver with a PVT compensation function. Background Art

[0002] With the rapid development of Internet of Things technology, various intelligent devices and sensor nodes have been widely deployed. Wireless communication plays a vital role in the process of intelligent perception, data collection and transmission of these nodes. However, with the continuous increase in the number of nodes, communication spectrum resources are becoming increasingly tight, making the communication environment increasingly complex and interference more serious.

[0003] In such a communication scenario, the RF receiver is a key component for receiving wireless signals, and its linearity performance has a direct impact on the quality and reliability of the entire communication system. The nonlinear distortion of the receiver circuit mainly includes third-order intermodulation distortion (IMD3) and gain compression, which correspond to the third-order intermodulation cutoff point (IP3) and 1 dB compression point (1-dBGain Compression Point, P1dB) of the receiver circuit.

[0004] When a traditional voltage-mode receiver encounters strong blocking interference, the low-noise amplifier and mixer are easily driven into the nonlinear region by the input of strong blocking signals, causing the circuit to fail to work properly. To achieve better anti-blocking performance, on-chip receiver circuits tend to use a current-mode RF front end.

[0005] The current mode receiver first converts the RF signal into a current signal through a transconductance circuit. Then, the passive mixer (i.e., using a MOSFET switch controlled by a local oscillator signal) down-converts the current-form RF signal and outputs an intermediate frequency current signal. When processing RF input signals of the same power, the mixer and post-amplifier circuit with low impedance characteristics can maintain a smaller voltage swing, thereby preventing the low-noise amplifier, mixer, and post-IF amplifier from entering the nonlinear region, so that the receiver front end has better P1dB and IP3.

[0006] In the selection of mixers, according to whether the RF port is a differential input, it is divided into double-balanced mixers and single-balanced mixers. Single-balanced mixers do not need to use balun devices, and the driving circuit of the local oscillator signal is halved, which has the advantages of low cost and low power consumption, but the port isolation performance is not as good as that of double-balanced mixers. The local oscillator signal at the gate end of the input switch tube of the single-balanced mixer is more likely to be coupled to the RF link through parasitic capacitance. The local oscillator signal coupled to the RF link will leak to the antenna and transmit outward, causing interference to other devices, and will also self-mix with the local oscillator at the input gate end to produce a large DC component. When there is a mismatch in the mixer, the DC component of the differential port is offset, which reduces the output range of the receiver and deteriorates the second-order linearity of the subsequent circuit. In addition, the large DC offset will directly saturate the subsequent circuit and fail to work properly.

[0007] The passive mixer structure will transfer the low-pass characteristics of the low-pass filter in the intermediate frequency circuit to the bandpass characteristics of the RF port. Therefore, the load of the low-noise amplifier presents a bandpass characteristic. The input impedance of the single-stage low-noise transconductance stage is heavily dependent on the load impedance, which is not conducive to achieving broadband matching at the input end.

[0008] The performance of a passive mixer depends on the gate bias voltage. A suitable bias voltage can put the mixer switch in a critical conduction state. When the switch is in critical conduction, it can enter the on or off mode more quickly under the control of the local oscillator signal. However, when the process, voltage and temperature (PVT) of the circuit change, the transistor on-voltage threshold and bias voltage will change. A high or low on-voltage will make the on-time of a single switch greater or less than 25%, which will deteriorate the gain and noise performance of the receiver. Summary of the invention

[0009] In order to solve the above problems, the present invention provides a broadband current mode receiver circuit with local oscillator leakage suppression and PVT compensation functions. A cascade structure of a low noise amplifier and a low noise transconductance stage is adopted, which improves the reverse isolation while expanding the bandwidth of the low noise amplifier, and effectively suppresses the local oscillator strength leaking to the antenna. A feedback-based DC offset elimination circuit is introduced in the post-stage transimpedance amplifier of the mixer to suppress the offset current generated by the mixer.

[0010] The present invention provides a broadband current mode receiver with PVT compensation function, which comprises a low noise amplifier, an orthogonal passive mixer and two transimpedance amplifiers connected in sequence; the low noise amplifier comprises a transistor M1, a transistor M2, a matching network, a loop bias circuit and a current bias circuit; the source end of the transistor M1 is grounded, and the source end of the transistor M2 is connected to a power supply voltage V DD ;

[0011] The matching network includes a capacitor C M and inductanceL M ; A capacitor in series with the input of the low noise amplifier C M After that, they are respectively passed through the DC blocking capacitors C M1 and DC blocking capacitors C M2 Connect the gate terminals of transistor M1 and transistor M2; capacitor C M The end away from the input of the low noise amplifier is connected through an inductor L M connected to the ground line; the current bias circuit in the low noise amplifier is used to provide a bias for the gate terminal of the transistor M1;

[0012] The loop bias circuit includes an operational transconductance amplifier OTA1, a resistor R 0 and resistance R b2 ; The drain terminals of transistors M1 and M2 are connected through resistors R 0 is connected to the non-inverting input of the operational transconductance amplifier OTA1; the inverting input of the operational transconductance amplifier OTA1 is connected to the reference potential V cm_ref ; The output of the operational transconductance amplifier OTA1 is connected through a resistor R b2 Connected to the gate terminal of transistor M2.

[0013] Preferably, the orthogonal passive mixer includes a DC bias circuit for providing a required DC bias for the switch tubes provided in the orthogonal passive mixer; the DC bias circuit of the orthogonal passive mixer includes a current mirror circuit, an operational amplifier AMP1 and an operational amplifier AMP2, and a replica tube M3, a switch tube M4, a switch tube M5, and a switch tube M6. 3_rep , Copy tube M 4_rep , Copy tube M 5_rep and replication tube M 6_rep The replica tube has the same width-to-length ratio as the switch tube, and the replica tube and the switch tube have the same process angle and operating temperature; the current mirror circuit includes a transistor M 7_rep 、M 8_rep 、M 9_rep ; Transistor M 7_rep The gate and drain terminals of transistor M are connected to the bias current source; 7_rep The gate and source terminals of transistor M 8_rep and transistor M 9_rep The gate terminal and source terminal of transistor M are connected; 8_rep and transistor M 9_rep The gate terminal of transistor M is connected; 8_rep The drain end of the replication tube M3_rep and replication tube M 4_rep The source terminal of transistor M 9_rep The drain end of the replication tube M 5_rep and replication tube M 6_rep The source terminal of the operational amplifier AMP1 is connected to the reference potential. V cm_ref The negative input terminal is connected to the replica tube M 3_rep and replication tube M 4_rep The source end of the output is connected to the replication pipe M 3_rep and replication tube M 4_rep Gate end; replication tube M 3_rep and replication tube M 4_rep The gate terminal of the operational amplifier AMP2 is connected to the reference potential. V cm_ref The negative input terminal is connected to the replica tube M 5_rep and replication tube M 6_rep The source end of the output is connected to the replication pipe M 5_rep and replication tube M 6_rep Gate end; replication tube M 5_rep and replication tube M 6_rep The outputs of operational amplifier AMP1 and operational amplifier AMP2 are used as DC bias voltages. V b_ICH and DC bias voltage V b_QCH .

[0014] Preferably, the broadband current mode receiver further comprises a low noise transconductance stage; the low noise transconductance stage is connected between the low noise amplifier and the orthogonal passive mixer; the low noise transconductance stage comprises a programmable capacitor array and one or a plurality of transconductance units connected in parallel.

[0015] Preferably, the transconductance unit comprises a transistor M 21 , transistor M 22 and transistor M 21 and transistor M 22 The gate terminal DC bias of transistor M 21 The source terminal of transistor M is grounded. 22 The source terminal is connected to the power supply voltage V DD ; The input end of the transconductance unit is connected through two DC blocking capacitors C 21 and DC blocking capacitors C 22 With transistor M 21 and transistor M 22 The gate terminal of transistor M 21 The gate DC bias circuit includes a transistor M20 ,resistance R a0 ,resistance R a1 and capacitor C 20 ;resistance R a0 One end of transistor M 20 The gate and drain terminals of the resistor are connected to the bias current source; R a0 The other end passes through the resistor R a1 Through switch S1 and switch S2 and transistor M 21 The source and gate terminals of the capacitor are connected; C 20 Connect one end of the resistor to R a0 With resistance R a1 The other end is connected to transistor M 20 The source connection of

[0016] Transistor M 22 The gate DC bias circuit includes resistor R a ,resistance R a2 , switch S3 and switch S 4. Resistance R a One end of transistor M 21 and transistor M 22 The drain terminal is connected to the O Connect to the output of the transconductance unit; resistor R a The other end is connected through the series switch S3 and switch S 4, with transistor M 22 The source end of the resistor R a2 One end of the switch S 4 and transistor M 22 The other end is connected to the source end of transistor M 22 When the switch S2 and the switch S3 are closed and the switch S1 and the switch S4 are opened, the transconductance unit is turned on; when the switch S1 and the switch S4 are closed and the switch S2 and the switch S3 are opened, the transconductance unit is opened;

[0017] The input of the programmable capacitor array is connected to the output of the transconductance unit. The programmable capacitor array includes one or more capacitors in parallel. Except for the selected branch, the remaining branches are equipped with switches S C and switch S Cb ; Switch SCb One end is grounded, and the other end is connected through a capacitor and a switch S C Connect to the input and output of the programmable capacitor array; switch S C and switch S Cb The on and off states are opposite to each other.

[0018] Preferably, the number of transconductance units in the low-noise transconductance stage is five, and the transconductance values ​​of the five transconductance units are respectively G m , 2´ G m , 2´ G m , 4´ G m , 8´ G m ; except for the transconductance value G m Except for the transconductance unit, the corresponding branches of the other transconductance units are equipped with switches S GM ; Through the switch S corresponding to each transconductance unit GM Gains can range from G m ~16´ G m The adjustable step size is G m ;

[0019] The programmable capacitor array includes four parallel capacitors; the capacitance values ​​of the four parallel capacitors are respectively C GM , C GM , 2´ C GM , 4´ C GM ; The value of the subtraction is C GM Except for one branch of the circuit, the other three branches are equipped with switches S C and switch S Cb .

[0020] Preferably, the orthogonal passive mixer comprises an in-phase end mixer and an orthogonal end mixer; the in-phase end mixer comprises a switch tube M3 and a switch tube M4 constituting an in-phase link; the orthogonal end mixer comprises a switch tube M5 and a switch tube M6 constituting an orthogonal link; the intermediate frequency signals generated by the in-phase link and the orthogonal link differ in phase by 90°; the source ends of the switch tubes M3, M4, M5 and M6 are all connected to the output end of the low-noise transconductance stage; the drain ends of the switch tubes M3 and M4 are connected via sampling capacitors C P1 Connection: The drain end of the switch tube M5 and the switch tube M6 is connected through the sampling capacitorC P2 Connection; the quadrature passive mixer passes the four-phase local oscillator signal LO IP ,LO IN ,LO QP and LO QN Realize switching behavior; local oscillator signal LO IP , local oscillator signal LO IN , local oscillator signal LO QP and the local oscillator signal LO QN Through AC coupling capacitors C LO3 , AC coupling capacitor C LO4 , AC coupling capacitor C LO5 and AC coupling capacitors C LO6 The gate terminals of the input switch tubes M3, M4, M5, and M6; the DC bias voltage of the mixer at the in-phase terminal V b_ICH Through the bias resistor R LO3 and bias resistors R LO4 Bias the gate terminals of switch tubes M3 and M4; DC bias voltage of the orthogonal mixer V b_QCH Through the bias resistor R LO5 and bias resistors R LO6 The gate terminals of the switch tube M5 and the switch tube M6 are biased.

[0021] Preferably, the two transimpedance amplifiers have the same structure and are respectively connected to the in-phase mixer and the quadrature mixer; the transimpedance amplifier includes an amplifier circuit; the amplifier circuit includes an operational amplifier OTA2, a resistor R TIA1 ,resistance R TIA2 ,capacitance C TIA1 and capacitor C TIA2 ; The negative output terminal of the operational amplifier OTA2 is connected through a resistor R TIA1 and capacitor C TIA1 Connect to the positive input terminal; the positive output terminal of the operational amplifier OTA2 is connected to the positive input terminal through the resistor R TIA2 and capacitor C TIA2Connected to the negative input terminal; the output of the negative output terminal and the positive output terminal of the operational amplifier OTA2 are used as the differential output signals of the transimpedance amplifier V outIP and V outIN .

[0022] Preferably, the transimpedance amplifier further includes a DC offset elimination circuit; the DC offset elimination circuit includes an operational amplifier OTA3, a resistor R I1 ,resistance R I2 ,resistance R LPF1 ,resistance R LPF2 、Filter capacitor C LPF1 and filter capacitors C LPF2 ; The positive input terminal and negative input terminal of the operational amplifier OTA3 are connected through resistors R LPF1 and resistor R LPF2 Connect to the positive and negative output terminals of the operational amplifier OTA2; filter capacitor C LPF1 Connected across the negative output terminal and positive input terminal of the operational amplifier OTA3, the filter capacitor C LPF2 The positive output terminal and the negative input terminal of the operational amplifier OTA3 are connected across the positive output terminal and the negative output terminal through resistors. R I1 and resistor R I2 Connect to the negative input and positive input of operational amplifier OTA2.

[0023] Preferably, the current bias circuit in the low noise amplifier comprises a transistor M0, a resistor R b0 ,resistance R b1 and capacitor C 0; Resistance R b0 One end of the resistor and the gate and drain of the transistor M0 are connected to the bias current source; R b0 The other end of the resistor R b1 Connected to the gate terminal of transistor M1; capacitor C One end of 0 is connected to the resistor R b0 With resistance R b1The other end is grounded with the source end of the transistor M0; the current bias circuit provides a DC bias for the gate end of the transistor M1.

[0024] Preferably, the low noise amplifier further comprises a parallel feedback branch, a switch S p1 , switch S p2 and resistor R p ; The parallel feedback branch includes a resistor R F and capacitor C F ;capacitance C F One end of the DC blocking capacitor C M1 Far away from the end of transistor M1; capacitor C F The other end of the resistor R F Connect one end of the resistor R F The other end of the switch S is connected to the drain end of the transistor M1; p1 One end of the inductor L M Ground, and the other end through a resistor R p Ground; switch S p2 One end of the capacitor is connected through a DC blocking capacitor C M1 One end is connected to the gate end of transistor M1, and the other end is connected to the drain end of transistor M1; switch S p1 and switch S p2 They are disconnected at the same time when the low noise amplifier works at the maximum gain, and are closed at the same time when the RF signal input is too large.

[0025] The present invention has the following beneficial effects:

[0026] 1. The present invention introduces a loop bias circuit as a bias of the transistor in the low noise amplifier, so that the DC potential at the output end of the low noise amplifier is fixed at the reference potential and is not affected by PVT changes, thereby having better robustness; at the same time, the present invention expands the input matching bandwidth by adding a parallel feedback structure to the low noise amplifier.

[0027] 2. The bias circuit of the passive mixer of the present invention adopts a tracking bias circuit. The tracking bias makes the gate bias voltage of the mixer change with the PVT change, thereby compensating for the impact of the PVT change, optimizing the stability and yield of the circuit, and making the circuit maintain stable performance under different processes, voltages and temperatures, and having better robustness.

[0028] 3. The present invention adds a low-noise transconductance stage between the low-noise amplifier and the orthogonal passive mixer. The cascade structure of the low-noise amplifier and the low-noise transconductance stage provides sufficiently high reverse isolation, effectively attenuates the local oscillator signal leaking to the antenna, and the transconductance stage converts the voltage signal into a current signal to ensure the low voltage swing at the input and output ends of the mixer, thereby improving the P1dB of the circuit. At the same time, both the low-noise amplifier and the low-noise transconductance stage adopt a current multiplexing structure without on-chip inductance, thereby realizing a low-power design and saving chip area to a great extent.

[0029] 4. The present invention adopts a multi-level gain design strategy with a large adjustable gain range, which can maintain the intermediate frequency signal swing of the receiver output within a reasonable range under different RF signal input strengths, thereby maintaining excellent performance in the low gain mode of the receiver to a great extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is the overall circuit principle diagram of the present invention.

[0031] Figure 2 This is a schematic diagram of the low noise amplifier circuit in the present invention.

[0032] Figure 3 This is a schematic diagram of the low noise transconductance stage circuit in the present invention.

[0033] Figure 4 This is a schematic diagram of the transconductance unit circuit in the present invention.

[0034] Figure 5 This is a schematic diagram of the programmable capacitor array circuit in the present invention.

[0035] Figure 6 This is a schematic diagram of the orthogonal passive mixer circuit in the present invention.

[0036] Figure 7 The diagram is a schematic diagram of a 25% duty cycle local oscillator signal generation circuit and a timing diagram of a local oscillator signal in the present invention.

[0037] Figure 8 The diagram is a schematic diagram of a DC bias circuit of an orthogonal passive mixer in the present invention.

[0038] Fig. 9 This is a schematic diagram of the transimpedance amplifier circuit in the present invention. DETAILED DESCRIPTION

[0039] The present invention will be further described below in conjunction with the accompanying drawings.

[0040] like Figure 1 and Figure 2As shown, a broadband current mode receiver with PVT compensation function includes a low noise amplifier 1, a low noise transconductance stage 2, an orthogonal passive mixer 3 and two transimpedance amplifiers 4 connected in sequence. The low noise amplifier 1 includes a transistor M1, a transistor M2, a matching network, a loop bias circuit, a current bias circuit, a parallel feedback branch and a switch S p1 , switch S p2 and resistor R p The transistor M1 is an NMOS transistor, and the transistor M2 is a PMOS transistor;

[0041] The source terminal of transistor M1 is grounded, and the source terminal of transistor M2 is connected to the power supply voltage V DD ; The matching network includes capacitors C M and inductance L M ; The input terminal of low noise amplifier 1 is connected in series with capacitor C M And through two DC blocking capacitors C M1 and DC blocking capacitors C M2 Connected to the gate terminals of transistor M1 and transistor M2; L M One end of the capacitor C M Connect to the input of low noise amplifier 1, inductor L M The other end is grounded.

[0042] Loop bias circuit operational transconductance amplifier OTA1, resistor R 0 and resistance R b2 ; The drain terminals of transistors M1 and M2 are connected through resistors R 0 is connected to the non-inverting input of the operational transconductance amplifier OTA1; the inverting input of the operational transconductance amplifier OTA1 is connected to the reference potential V cm_ref ; The output of the operational transconductance amplifier OTA1 is connected through a resistor R b2 The gate terminal of transistor M2 is connected to the gate terminal of transistor M2 and serves as the gate terminal bias voltage of transistor M2. The structure of the loop bias can fix the DC potential of the output terminal of the low noise amplifier at V cm_ref , and is not affected by PVT changes, and has better robustness; in this embodiment, the reference potential V cm_ref The current bias circuit includes transistor M0, resistor R b0,resistance R b1 and capacitor C 0; Resistance R b0 One end of the resistor and the gate and drain of the transistor M0 are connected to the bias current source; R b0 The other end of the resistor R b1 Connected to the gate terminal of transistor M1; capacitor C One end of 0 is connected to the resistor R b0 With resistance R b1 The other end is connected to the source end of transistor M0 and grounded; the current bias circuit provides a DC bias for the gate end of transistor M1. The parallel feedback branch includes a resistor R F and capacitor C F ;capacitance C F One end of the capacitor is connected through a DC blocking capacitor C M1 Connected to the gate terminal of transistor M1 and the other end to the resistor R F Connect one end of the resistor R F The other end of is connected to the drain of transistor M1; the input matching bandwidth of the low noise amplifier is greatly expanded through the parallel feedback branch. Without considering the input matching network, the input impedance of the low noise amplifier is Z in for:

[0043]

[0044] in, Z F is the feedback branch impedance, Z F = R F +1 / ( JωC F ); A V is the gain of the low noise amplifier; g m1 and g m2 are the transconductances of transistor M1 and transistor M2 respectively; Z L is the load impedance of the low noise amplifier.

[0045] Load impedance of low noise amplifier Z Lis the input impedance of the low noise transconductance stage, and the load impedance Z L is approximately equal to the parasitic capacitance of the transistor in the low noise transconductance stage, so Z L >> Z F , the gain of the low noise amplifier A V The expression is:

[0046]

[0047] The expression of the noise factor F of the low noise amplifier is:

[0048]

[0049] in, g is a parameter related to the process and MOSFET channel length; Y L is the load admittance, Y L =1 / Z L ; Z th is the equivalent impedance; Re is the real part symbol.

[0050] Equivalent impedance Z th Including resistor R p The impedance, matching network impedance and source impedance of the antenna that inputs the signal to the low noise amplifier. If the input is perfectly matched, the source impedance of the matching network and the input antenna is equal to the input impedance Z * in. Input impedance Z * in is the equivalent impedance of the low noise amplifier Z th The impedance of other devices.

[0051] Switch S p1 One end of the inductor L M Ground, and the other end through a resistor R p Ground; switch S p2 One end of the capacitor is connected through a DC blocking capacitor C M1 One end is connected to the gate terminal of transistor M1, and the other end is connected to the drain terminal of transistor M1. p1 and switch S p2 When the low noise amplifier is working at the maximum gain, the resistor is disconnected at the same time, and the low noise amplifier can work normally. R pIt does not affect the signal link; when the RF signal input is too large, in order to avoid saturation of the low noise amplifier, the low noise amplifier needs to be bypassed, and the switch S p1 and switch S p2 Closed, the LNA output and input are directly short-circuited, and through the resistor R p The input impedance is compensated to meet the input impedance matching in the bypass state.

[0052] like Figure 3 As shown, the low noise transconductance stage 2 includes a programmable capacitor array and five transconductance units connected in parallel. The transconductance values ​​of the five transconductance units are respectively G m , 2´ G m , 2´ G m , 4´ G m , 8´ G m ; except for the transconductance value G m Except for the transconductance unit, switches are provided on the corresponding branches of the other transconductance units, and the gain of the transconductance stage is controlled by opening or closing the switches.

[0053] like Figure 4 As shown, the transconductance unit includes a transistor M 21 , transistor M 22 and transistor M 21 and transistor M 22 The gate terminal of transistor M is DC biased. 21 The source terminal of transistor M is grounded. 22 The source terminal is connected to the power supply voltage V DD ; The input end of the transconductance unit is connected through two DC blocking capacitors C 21 and DC blocking capacitors C 22 With transistor M 21 and transistor M 22 The gate terminal of transistor M 21 The gate DC bias circuit includes a transistor M 20 ,resistance R a0 ,resistance R a1 and capacitor C 20 ;resistance R a0 One end of transistor M 20 The gate and drain terminals of the resistor are connected to the bias current source; R a0The other end passes through the resistor R a1 Through switch S1 and switch S2 and transistor M 21 The source and gate terminals of the capacitor are connected; C 20 Connect one end of the resistor to R a0 With resistance R a1 The other end is connected to transistor M 20 The source connection.

[0054] Transistor M 22 The gate DC bias circuit includes resistor R a ,resistance R a2 , switch S3 and switch S 4. Resistance R a One end of transistor M 21 and transistor M 22 The drain terminal is connected to the O Connect to the output of the transconductance unit; resistor R a The other end is connected through the series switch S3 and switch S 4, with transistor M 22 The source end of the resistor R a2 One end of the switch S 4 and transistor M 22 The other end is connected to the source end of transistor M 22 Unlike transistor M2, the transistor M of the transconductance unit 22 The loop bias form of the stable output voltage is not adopted. Since the low noise transconductance stage needs to adjust the transconductance gain, when only the transconductance unit with a small transconductance value in the low noise transconductance stage is working, the transistor M 22 The total parasitic capacitance value of the gate node decreases, the main pole frequency of the loop increases, and the loop phase margin decreases, which is not conducive to loop stability. Therefore, the transconductance unit directly uses a resistor cross-connection for biasing in order to achieve gain adjustment.

[0055] When switch S2 and switch S3 are closed, and switch S1 and switch S4 are open, the transconductance unit is turned on; the transistor is normally biased, and the transconductance unit converts the RF voltage signal into a current signal and outputs it. When switch S1 and switch S4 are closed, and switch S2 and switch S3 are open, the transconductance unit is turned off, and transistor M 21 The gate terminal is grounded, and the transistor M 22 Gate terminal through resistor R a2 Connecting the supply voltageV DD , transistor M 21 and transistor M 22 Entering the cut-off region. To simplify the representation, by switching S GM Closed means that switches S2 and S3 are closed, and switches S1 and S4 are open; GM Disconnection means that switch S1 and switch S4 are closed, and switch S2 and switch S3 are disconnected; through the switch S corresponding to each transconductance unit GM Gains can range from G m ~16´ G m The adjustable step size is G m .

[0056] like Figure 5 As shown, the input of the programmable capacitor array is connected to the output of the transconductance unit, which includes four parallel capacitors; the capacitance values ​​of the four parallel capacitors are respectively C GM , C GM , 2´ C GM , 4´ C GM The value of the capacity is C GM Except for one branch of the circuit, the other three branches are equipped with switches S C and switch S Cb ; Switch S Cb One end is grounded, and the other end is connected through a capacitor and a switch S C Connected to the input and output of the programmable capacitor array. By adjusting the capacitance at the same time, the proportion of RF current flowing into the subsequent stage can be further controlled to adjust the receiver gain. Switch S C and switch S Cb The on and off states of the switch S are opposite to each other. C On, switch S Cb If the on-resistance of the passive mixer and the input impedance of the transimpedance amplifier are ignored and regarded as 0, the current in each branch is proportionally determined by the capacitance. The larger the capacitance of the branch, the greater the current. This switch control form changes the current flow without affecting the load impedance of the previous circuit, thereby achieving the purpose of accurately controlling the gain.

[0057] This will be further explained below. The current flowing into the capacitor array from the input terminal IN is divided into 8 parts, and the 1st, 2nd, 3rd and 4th branches receive 1, 1, 2 and 4 parts of current respectively. Using a 2-bit control word to control 3 groups of switches, the programmable capacitor array has four states:

[0058] (1) If the control word is 2'b11, switch S C1 , switch S C2 and switch S C3 Closed, switch S C1b , switch S C2b and switch S C3b Disconnected, a total of 8 currents flow to the output, and the gain is maximum;

[0059] (2) If the control word is 2'b10, switch S C1 , switch S C2 and switch S C3b Closed, switch S C1b , switch S C2b and switch S C3 Disconnected, 4 parts of the current flow to the output, 4 parts of the current flow to the ground, the gain is 1 / 2 of the maximum gain, and the gain is reduced by 6 dB;

[0060] (3) If the control word is 2'b01, switch S C1 , switch S C2b and switch S C3b Closed, switch S C1b , switch S C2 and switch S C3 Disconnected, 2 parts of the current flow to the output, 6 parts of the current flow to the ground, the gain is 1 / 4 of the maximum gain, and the gain is reduced by 12 dB;

[0061] (4) If the control word is 2'b00, switch S C1b , switch S C2b and switch S C3b Closed, switch S C1 , switch S C2 and switch S C3 When disconnected, 1 part of the current flows to the output and 7 parts of the current flows to ground. The gain is 1 / 8 of the maximum gain, and the gain is reduced by 18 dB.

[0062] The capacitor array at the output of the transconductance stage achieves an 18 dB gain adjustment range with a 6 dB adjustment step.

[0063] like Figure 6As shown, the orthogonal passive mixer 3 includes an in-phase mixer, a quadrature mixer and a DC bias circuit; the in-phase mixer includes a switch tube M3 and a switch tube M4 that form an in-phase (In-phase, I) link, i.e., the I path; the quadrature mixer includes a switch tube M5 and a switch tube M6 that form a quadrature (Quadrature, Q) link, i.e., the Q path; the intermediate frequency signals generated by the in-phase link and the quadrature link differ in phase by 90°. The source ends of the switch tubes M3, M4, M5 and M6 are all connected to the output end of the low-noise transconductance stage; the drain ends of the switch tubes M3 and M4 are connected to the output end of the low-noise transconductance stage through the sampling capacitor. C P1 Connection: The drain end of the switch tube M5 and the switch tube M6 is connected through the sampling capacitor C P2 Connection; sampling capacitor C P1 and sampling capacitor C P2 An additional pole is formed with the on-impedance of the orthogonal passive mixer, which improves the out-of-band suppression capability, effectively suppresses the local oscillator signal leaking to the baseband, input blocking and adjacent channel interference signals, and optimizes the receiver's anti-blocking capability.

[0064] The quadrature passive mixer 3 uses a four-phase local oscillator signal LO with a duty cycle of 25%. IP ,LO IN ,LO QP and LO QN Realize switching behavior; local oscillator signal LO IP , local oscillator signal LO IN , local oscillator signal LO QP and the local oscillator signal LO QN Through AC coupling capacitors C LO3 , AC coupling capacitor C LO4 , AC coupling capacitor C LO5 and AC coupling capacitors C LO6 Input the gate terminals of switch tubes M3, M4, M5 and M6. DC bias voltage of the mixer at the in-phase terminal V b_ICH Through the bias resistor R LO3 and bias resistors R LO4 Bias the gate terminals of switch tubes M3 and M4; DC bias voltage of the orthogonal mixer V b_QCH Through the bias resistor R LO5 and bias resistors RLO6 The gate terminals of the switch tube M5 and the switch tube M6 are biased.

[0065] like Figure 7 As shown, clkp and clkm are double-frequency local oscillator signal sources, that is, the frequency is 2´ f LO , provided by the phase-locked loop circuit. The 2-frequency division circuit includes two D latches Latch1 and D latch Latch2; clkp is connected to the positive clock terminals of D latch Latch1 and D latch Latch2, clkm is connected to the negative clock terminals of D latch Latch1 and D latch Latch2, the positive output terminal of D latch Latch1 is connected to the positive input terminal of D latch Latch2, the negative output terminal of D latch Latch1 is connected to the negative input terminal of D latch Latch2, the positive output terminal of D latch Latch2 is connected to the negative input terminal of D latch Latch1, and the negative output terminal of D latch Latch2 is connected to the positive input terminal of D latch Latch1. The positive output terminal of D latch Latch1 is output DIV2 IP Signal, the negative output of D latch Latch1 DIV2 IN Signal; positive output of D latch Latch2 DIV2 QP Signal, the negative output of D latch Latch2 DIV2 QN Signal. DIV2 IP , DIV2 IN , DIV2 QP and DIV2 QN The frequency is f LO , a quadrature local oscillator signal with a duty cycle of 50%. DIV2 IP , orthogonal local oscillator signal DIV2 IN , orthogonal local oscillator signal DIV2 QP and quadrature local oscillator signals DIV2 QN The non-overlapping 25% duty cycle local oscillator signal is generated by the NAND gate and the NOT gate. DIV2 IP and quadrature local oscillator signals DIV2 QN They are connected to the two input terminals of the two-input NAND gate, and the input terminal of the NAND gate is connected to the NOT gate to output the local oscillator signal. LO IP . Orthogonal local oscillator signal DIV2 IN and quadrature local oscillator signals DIV2 QP They are connected to the two input terminals of the two-input NAND gate, and the input terminal of the NAND gate is connected to the NOT gate to output the local oscillator signal. LO IN . Orthogonal local oscillator signal DIV2 QP and quadrature local oscillator signals DIV2 IP They are connected to the two input terminals of the two-input NAND gate, and the input terminal of the NAND gate is connected to the NOT gate to output the local oscillator signal. LO QP . Orthogonal local oscillator signal DIV2 QN and quadrature local oscillator signals DIV2 IN They are connected to the two input terminals of the two-input NAND gate, and the input terminal of the NAND gate is connected to the NOT gate to output the local oscillator signal. LO QN Finally, a 25% duty cycle quadrature local oscillator signal is generated to control the quadrature mixer. LO IP , LO IN , LO QP and LO QN .

[0066] The input impedance of the passive mixer controlled by a 25% duty cycle local oscillator signal is:

[0067]

[0068] in, R SW is the on-resistance of the switch tube, Z bb ( ω ) is the input impedance of the transimpedance amplifier; ω LO is the local oscillator signal frequency.

[0069] Input Impedance Z bb ( ω ) has the characteristics of a low-pass filter; the load of the low-noise transconductance stage has band-pass filtering characteristics, which can effectively suppress out-of-band blocking signals, adjacent channels and inter-channel interference, and optimize the out-of-band linearity of the receiver.

[0070] like Figure 8As shown, the DC bias circuit of the orthogonal passive mixer 3 adopts a tracking bias circuit, which includes a current mirror circuit, an operational amplifier AMP1 and an amplifier AMP2, and a replica of a switch tube M3, a switch tube M4, a switch tube M5 and a switch tube M6. 3_rep , Copy tube M 4_rep , Copy tube M 5_rep and replication tube M 6_rep The replica tube has the same width-to-length ratio as the switch tube, and the replica tube is closely placed with the switch tube, so that the replica tube and the switch tube have the same process angle and operating temperature. The current mirror circuit includes a transistor M 7_rep , transistor M 8_rep , transistor M 9_rep ; Transistor M 7_rep The gate and drain terminals of transistor M are connected to the bias current source; 7_rep The gate and source terminals of transistor M 8_rep and transistor M 9_rep The gate terminal and source terminal of transistor M are connected; 8_rep and transistor M 9_rep The gate terminal of transistor M is connected; 8_rep The drain end of the replication tube M 3_rep and replication tube M 4_rep The source terminal of transistor M 9_rep The drain end of the replication tube M 5_rep and replication tube M 6_rep The source terminal of the operational amplifier AMP1 is connected to the reference potential. V cm_ref The negative input terminal is connected to the replica tube M 3_rep and replication tube M 4_rep The source end of the output is connected to the replication pipe M 3_rep and replication tube M 4_rep Gate end; replication tube M 3_rep and replication tube M 4_rep The gate terminal of the operational amplifier AMP2 is connected to the reference potential. V cm_ref The negative input terminal is connected to the replica tube M 5_rep and replication tube M 6_rep The source end of the output is connected to the replication pipe M 5_rep and replication tube M 6_rep Gate end; replication tube M 5_rep and replication tube M 6_rep The outputs of operational amplifier AMP1 and operational amplifier AMP2 are used as DC bias voltages. V b_ICH and DC bias voltage V b_QCH .

[0071] By adjusting the mirror ratio of the current mirror circuit, the replica tube M 3_rep , Copy tube M 4_rep , Copy tube M 5_rep and replication tube M 6_rep In the on state, the DC bias voltage generated at this time V b_ICH Exactly equal to ( V cm_ref + V th,3 / 4 ), V b_QCH Exactly equal to ( V cm_ref + V th,5 / 6 );in V th,3 / 4 and V th,5 / 6 Replication tube M 3_rep / M 4_rep and M 5_rep / M 6_rep The turn-on threshold voltage; reference potential V cm_ref The gate bias voltage of switch tubes M3, M4, M5 and M6 is just one level higher than the source voltage, which is consistent with the common mode level of the transimpedance amplifier. V th,3 / 4 or V th,5 / 6 .

[0072] Since the replica tube and the switch tube have the same process angle and operating temperature, the random mismatch in manufacturing is smaller, so the on-threshold voltage of the replica tube and the switch tube is also consistent. Even if the PVT changes, the mixer bias voltage can ensure that the switch tube is in the on state, ensuring performance stability.

[0073] like Fig. 9 As shown, the two transimpedance amplifiers 4 have the same structure and are connected to the in-phase mixer and the quadrature mixer respectively. The transimpedance amplifier 4 includes an amplifier circuit and a DC offset elimination circuit; the amplifier circuit includes an operational amplifier OTA2, a resistor R TIA1 ,resistance R TIA2 ,capacitance C TIA1 and capacitor C TIA2 ; The negative output terminal of the operational amplifier OTA2 is connected through a resistor R TIA1 and capacitor C TIA1Connect to the positive input terminal; the positive output terminal of the operational amplifier OTA2 is connected to the positive input terminal through the resistor R TIA2 and capacitor C TIA2 Connected to the negative input terminal; the output of the negative output terminal and the positive output terminal of the operational amplifier OTA2 are used as the differential output signals of the transimpedance amplifier V outIP and V outIN .resistance R TIA1 and resistor R TIA2 The resistor array is implemented with a 3-bit control word to achieve 5-level gain adjustment. The gain difference of each level is 6 dB, and the total gain adjustment range is 30 dB. R TIA1 ´ C TIA1 and R TIA2 ´ C TIA2 A pole is provided, so the transimpedance amplifier 4 provides a large transimpedance gain while also having filtering capability, effectively suppressing out-of-band blocking. The input impedance of the transimpedance amplifier 4 is approximately 0, so that current flows in and does not generate a large voltage swing at the input end. After filtering by the transimpedance amplifier 4, strong blocking interference is effectively suppressed, so that the amplifier has good blocking suppression.

[0074] The DC offset cancellation circuit suppresses the DC offset caused by the mixer mismatch to prevent the DC component of the offset from deteriorating the linearity and dynamic range of the subsequent circuit; the DC offset cancellation circuit uses analog feedback to achieve DC offset cancellation. The DC offset cancellation circuit includes an operational amplifier OTA3, a resistor R I1 ,resistance R I2 ,resistance R LPF1 ,resistance R LPF2 、Filter capacitor C LPF1 and filter capacitors C LPF2 The positive input terminal and negative input terminal of the operational amplifier OTA3 are connected through resistors R LPF1 and resistor R LPF2 Connect to the positive and negative output terminals of the operational amplifier OTA2; filter capacitor C LPF1Connected across the negative output terminal and positive input terminal of the operational amplifier OTA3, the filter capacitor C LPF2 The positive output terminal and the negative input terminal are connected across to form an integration circuit, which can achieve an extremely low low-pass filter cutoff frequency, so that the DC offset elimination circuit does not affect the useful signal frequency band when suppressing the DC component. R I1 and large resistor R I2 The negative input terminal and the positive input terminal connected to the operational amplifier OTA2 form a negative feedback loop for DC and low-frequency signals. The generated DC offset current is inverted and amplified by the transimpedance amplifier, and then inverted and amplified by the feedback loop to output the compensation current, thereby eliminating the offset current at the input end of the transimpedance amplifier and effectively suppressing the DC offset component.

[0075] In summary, the receiver front-end circuit provides four gain adjustment points: (1) the amplification or bypass mode of the low-noise amplifier controlled by a 1-bit control word; (2) the low-noise transconductance stage controlled by a 4-bit control word; (3) the output capacitor array controlled by a 2-bit control word; and (4) the transimpedance gain of the transimpedance amplifier controlled by a 3-bit control word.

[0076] A parallel compensation array is introduced at the input of the low noise amplifier so that it can meet the input matching requirements in bypass mode. The transconductance stage adopts a transconductance unit array, and the transconductance gain is controlled by switching on and off. It has a high input impedance characteristic. The on and off of the transconductance unit has little effect on the low noise amplifier of the previous stage, and turning off the transconductance unit is conducive to saving power consumption in low gain mode. Since the transconductance of the current mode depends on the input impedance of the subsequent stage, the capacitor array at the output end of the transconductance stage adopts two forms: series connection to the subsequent stage circuit and parallel connection to the ground. Through switch control, the total amount of capacitance in the two forms is constant, and there is no impact on the previous stage when adjusting the current flowing into the subsequent stage.

[0077] In this embodiment, the gain of the low noise amplifier in the amplification mode reaches 20 dB, the maximum equivalent transconductance gain of the low noise transconductance stage is 40 mS, and the conduction loss is ignored. The conversion gain of the passive mixer from the RF input to the IF output is , and the maximum transimpedance value of the transimpedance amplifier is 40KΩ. There is a total loss of 5 dB in the path from the transconductance stage to the transimpedance amplifier, so the maximum gain of the receiver is about 4050 times ≈ 72 dB. The transconductance unit, programmable capacitor array and transimpedance amplifier provide a total adjustment range of 72 dB. When the low-noise amplifier works in bypass mode, its gain drops to 0dB, so the minimum gain of the receiver is -20 dB. This planning strategy enables the receiver to obtain a total of 92 dB of large gain adjustment range, with an adjustment step of 6 dB, which can meet the conditions of different input RF signal strengths.

Claims

1. A broadband current mode receiver with PVT compensation function, comprising a low noise amplifier (1), an orthogonal passive mixer (3) and two transimpedance amplifiers (4) connected in sequence; characterized in that: The low noise amplifier (1) comprises a transistor M1, a transistor M2, a matching network, a loop bias circuit and a current bias circuit; The source terminal of transistor M1 is grounded, and the source terminal of transistor M2 is connected to the power supply voltage V DD ; The matching network includes a capacitor C M and inductance L M ; A capacitor is connected in series with the input of the low noise amplifier (1) C M After that, they are respectively passed through the DC blocking capacitors C M1 and DC blocking capacitors C M2 Connect the gate terminals of transistor M1 and transistor M2; capacitor C M The end away from the input of the low noise amplifier (1) is connected through an inductor L M Connect to ground; The current bias circuit in the low noise amplifier (1) is used to provide a bias for the gate terminal of the transistor M1; The loop bias circuit includes an operational transconductance amplifier OTA1, a resistor R 0 and resistor R b2 ; The drain terminals of transistors M1 and M2 are connected through resistors R 0 is connected to the non-inverting input of the operational transconductance amplifier OTA1; the inverting input of the operational transconductance amplifier OTA1 is connected to the reference potential V cm_ref ; The output of the operational transconductance amplifier OTA1 is connected through a resistor R b2 connected to the gate terminal of transistor M2; The low noise amplifier (1) further comprises a parallel feedback branch, a switch S p1 , switch S p2 and resistor R p ; The parallel feedback branch includes a resistor R F and capacitor C F ;capacitance C F One end of the DC blocking capacitor C M1 The end away from the gate terminal of transistor M1 is connected; capacitor C F The other end of the resistor R F Connect one end of the resistor R F The other end of the switch S is connected to the drain end of the transistor M1; p1 One end of the inductor L M Ground, and the other end through a resistor R p Ground; switch S p2 One end of the capacitor is connected through a DC blocking capacitor C M1 One end is connected to the gate end of transistor M1, and the other end is connected to the drain end of transistor M1; switch S p1 and switch S p2 The two terminals are simultaneously disconnected when the low noise amplifier (1) operates at a maximum gain, and simultaneously closed when the RF signal input is too large; The orthogonal passive mixer (3) comprises a DC bias circuit for providing a required DC bias for a switch tube provided in the orthogonal passive mixer (3); the DC bias circuit of the orthogonal passive mixer (3) comprises a current mirror circuit, an operational amplifier AMP1 and an operational amplifier AMP2, and a replica tube M3, a switch tube M4, a switch tube M5, and a switch tube M6. 3_rep , Copy tube M 4_rep , Copy tube M 5_rep and replication tube M 6_rep The replica tube has the same width-to-length ratio as the switch tube, and the replica tube and the switch tube have the same process angle and operating temperature; the current mirror circuit includes a transistor M 7_rep 、M 8_rep 、M 9_rep ; Transistor M 7_rep The gate terminal and the drain terminal are both connected to a bias current source; Transistor M 7_rep The gate and source terminals of transistor M 8_rep and transistor M 9_rep The gate terminal and source terminal of transistor M are connected; 8_rep The drain end of the replication tube M 3_rep and replication tube M 4_rep The source terminal of transistor M 9_rep The drain end of the replication tube M 5_rep and replication tube M 6_rep The source terminal of the operational amplifier AMP1 is connected to the reference level. V cm_ref The negative input terminal is connected to the replica tube M 3_rep and replication tube M 4_rep The source end of the output is connected to the replication pipe M 3_rep and replication tube M 4_rep The gate terminal of the operational amplifier AMP2 is connected to the reference level. V cm_ref The negative input terminal is connected to the replica tube M 5_rep and replication tube M 6_rep The source end of the output is connected to the replication pipe M 5_rep and replication tube M 6_rep The gate terminal of the operational amplifier AMP1 and the output of the operational amplifier AMP2 are used as the DC bias voltage V b_ICH and DC bias voltage V b_QCH .

2. A broadband current mode receiver with PVT compensation function according to claim 1, characterized in that: The broadband current mode receiver also includes a low noise transconductance stage (2); the low noise transconductance stage (2) is connected between the low noise amplifier (1) and the orthogonal passive mixer (3); the low noise transconductance stage (2) includes a programmable capacitor array and one or a plurality of transconductance units connected in parallel.

3. A broadband current mode receiver with PVT compensation function according to claim 2, characterized in that: The transconductance unit includes a transistor M 21 , transistor M 22 and transistor M 21 and transistor M 22 The gate DC bias of Transistor M 21 The source terminal of transistor M is grounded. 22 The source terminal is connected to the power supply voltage V DD ; The input end of the transconductance unit is connected through two DC blocking capacitors C 21 and DC blocking capacitors C 22 With transistor M 21 and transistor M 22 The gate terminal connection; Transistor M 21 The gate DC bias circuit includes a transistor M 20 ,resistance R a0 ,resistance R a1 and capacitor C 20 ;resistance R a0 One end of transistor M 20 The gate and drain terminals of the resistor are connected to the bias current source; R a0 The other end passes through the resistor R a1 Through switch S1 and switch S2 and transistor M 21 The source and gate terminals of the capacitor are connected; C 20 Connect one end of the resistor to R a0 With resistance R a1 The other end is connected to transistor M 20 The source connection of Transistor M 22 The gate DC bias circuit includes resistor R a ,resistance R a2 , switch S3 and switch S 4. Resistance R a One end of transistor M 21 and transistor M 22 The drain terminal is connected to the O Connect to the output of the transconductance unit; resistor R a The other end is connected through the series switch S3 and switch S 4, with transistor M 22 The source end of the resistor R a2 One end of the switch S 4 and transistor M 22 The other end is connected to the source end of transistor M 22 When the switch S2 and the switch S3 are closed and the switch S1 and the switch S4 are opened, the transconductance unit is turned on; when the switch S1 and the switch S4 are closed and the switch S2 and the switch S3 are opened, the transconductance unit is opened; The input of the programmable capacitor array is connected to the output of the transconductance unit. The programmable capacitor array includes one or more capacitors in parallel. Except for the selected branch, the remaining branches are equipped with switches S C and switch S Cb ; Switch S Cb One end is grounded, and the other end is connected through a capacitor and a switch S C Connect to the input and output of the programmable capacitor array; switch S C and switch S Cb The on and off states are opposite to each other.

4. A broadband current mode receiver with PVT compensation function according to claim 2, characterized in that: The number of transconductance units in the low-noise transconductance stage (2) is five, and the transconductance values ​​of the five transconductance units are respectively G m , 2´ G m , 2´ G m , 4´ G m , 8´ G m ; except for the transconductance value G m Except for the transconductance unit, the corresponding branches of the other transconductance units are equipped with switches S GM ; Through the switch S corresponding to each transconductance unit GM Gains can range from G m ~16´ G m The adjustable step size is G m ; The programmable capacitor array includes four parallel capacitors; the capacitance values ​​of the four parallel capacitors are respectively C GM , C GM , 2´ C GM , 4´ C GM ; The value of the subtraction is C GM Except for one branch of the circuit, the other three branches are equipped with switches S C and switch S Cb .

5. The broadband current mode receiver with PVT compensation function according to claim 1, characterized in that: The orthogonal passive mixer (3) comprises an in-phase end mixer and an orthogonal end mixer; the in-phase end mixer comprises a switch tube M3 and a switch tube M4 constituting an in-phase link; the orthogonal end mixer comprises a switch tube M5 and a switch tube M6 constituting an orthogonal link; the intermediate frequency signals generated by the in-phase link and the orthogonal link differ in phase by 90°; the source ends of the switch tubes M3, M4, M5 and M6 are all connected to the output end of the low-noise transconductance stage (2); the drain ends of the switch tubes M3 and M4 are connected via sampling capacitors C P1 Connection: The drain end of the switch tube M5 and the switch tube M6 is connected through the sampling capacitor C P2 Connection; The quadrature passive mixer (3) passes the four-phase local oscillator signal LO IP ,LO IN , LO QP and LO QN Realize switching behavior; local oscillator signal LO IP , local oscillator signal LO IN , local oscillator signal LO QP and the local oscillator signal LO QN Through AC coupling capacitors C LO3 , AC coupling capacitor C LO4 , AC coupling capacitor C LO5 and AC coupling capacitors C LO6 The gate terminals of the input switch tubes M3, M4, M5, and M6; the DC bias voltage of the mixer at the in-phase terminal V b_ICH Through the bias resistor R LO3 and bias resistors R LO4 Bias the gate terminals of switch tubes M3 and M4; DC bias voltage of the orthogonal mixer V b_QCH Through the bias resistor R LO5 and bias resistors R LO6 The gate terminals of the switch tube M5 and the switch tube M6 are biased.

6. A broadband current mode receiver with PVT compensation function according to claim 1, characterized in that: The two transimpedance amplifiers (4) have the same structure and are respectively connected to the in-phase mixer and the quadrature mixer; the transimpedance amplifier (4) comprises an amplifier circuit; the amplifier circuit comprises an operational amplifier OTA2, a resistor R TIA1 ,resistance R TIA2 ,capacitance C TIA1 and capacitor C TIA2 ; The negative output terminal of the operational amplifier OTA2 is connected through a resistor R TIA1 and capacitor C TIA1 Connect to the positive input terminal; the positive output terminal of the operational amplifier OTA2 is connected to the positive input terminal through the resistor R TIA2 and capacitor C TIA2 Connected to the negative input terminal; the output of the negative output terminal and the positive output terminal of the operational amplifier OTA2 are respectively used as the differential output signal of the transimpedance amplifier (4) V outIP and V outIN .

7. A broadband current mode receiver with PVT compensation function according to claim 6, characterized in that: The transimpedance amplifier (4) further includes a DC offset elimination circuit; the DC offset elimination circuit includes an operational amplifier OTA3, a resistor R I1 ,resistance R I2 ,resistance R LPF1 ,resistance R LPF2 、Filter capacitor C LPF1 and filter capacitors C LPF2 ; The positive input terminal and negative input terminal of the operational amplifier OTA3 are connected through resistors R LPF1 and resistor R LPF2 Connect to the positive and negative output terminals of the operational amplifier OTA2; filter capacitor C LPF1 Connected across the negative output terminal and positive input terminal of the operational amplifier OTA3, the filter capacitor C LPF2 The positive output terminal and the negative input terminal of the operational amplifier OTA3 are connected across the positive output terminal and the negative output terminal through resistors. R I1 and resistor R I2 Connect to the negative input and positive input of operational amplifier OTA2.

8. The broadband current mode receiver with PVT compensation function according to claim 1, characterized in that: The current bias circuit in the low noise amplifier (1) comprises a transistor M0, a resistor R b0 ,resistance R b1 and capacitor C 0; Resistance R b0 One end of the resistor and the gate and drain of the transistor M0 are connected to the bias current source; R b0 The other end of the resistor R b1 Connected to the gate terminal of transistor M1; capacitor C One end of 0 is connected to the resistor R b0 With resistance R b1 The other end is grounded with the source end of the transistor M0; the current bias circuit provides a DC bias for the gate end of the transistor M1.

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