A time synchronization method and system based on time synchronization gateway

Abstract

The present invention relates to a time synchronization method and system based on a time synchronization gateway, which belongs to the field of computer networks, including: on the gateway timing side, establishing a master-slave relationship between the gateway and the upstream PTP device to complete PTP synchronization; parsing messages through the data plane to obtain timestamp information, and sending the timestamp information to the control plane; determining the clock offset through the control plane according to the timestamp information; adjusting the local clock of the gateway according to the clock offset; on the gateway timing side, establishing a master-slave relationship between the gateway and the downstream network device to complete SD-PTP synchronization. The present invention enables time synchronization to exist not only in the control plane of the switch, avoids the impact of clock drift of the device during software processing delays, and eliminates the need for the client to perform multiple rounds of synchronization and statistical filtering. Large-scale network deployment and expansion can also be achieved without increasing delays and affecting accuracy.

Description

Technical Field

[0001] The invention belongs to the field of computer networks, and in particular relates to a time synchronization method and system based on a time synchronization gateway. Background Art

[0002] With the development of network technology, delay-sensitive applications increasingly require cross-device collaborative processing. For these applications, time synchronization is a key factor in ensuring the consistency of data reception, processing, and presentation at each node in the network.

[0003] In the prior art, the most widely used is the Precise Time Protocol (PTP), which can theoretically achieve a time synchronization accuracy of hundreds of nanoseconds.

[0004] However, most proprietary implementations of PTP exist only in the control plane of the switch, which brings three major technical problems: First, in order to offset the impact of clock drift in the device during software processing delays, the client needs to perform multiple rounds of synchronization and statistical filtering. Second, when the network load is heavy, the synchronization accuracy achieved by the PTP protocol will drop to the microsecond level. Third, the software implementation of PTP cannot achieve large-scale network deployment and expansion without increasing latency and affecting accuracy.

[0005] In addition, since dedicated PTP hardware equipment is expensive, it will cause a certain economic burden for larger-scale network deployments. Summary of the invention

[0006] In view of the above deficiencies in the prior art, the purpose of the invention is to provide a time synchronization method and system based on a time synchronization gateway, which can parse messages through the data plane to obtain timestamp information, and send the timestamp information to the control plane, so that time synchronization exists not only in the control plane of the switch, avoiding the impact of clock drift of the device during software processing delays, and allowing the client to no longer need to perform multiple rounds of synchronization and statistical filtering. According to the timestamp information, the clock offset is determined through the control plane, and the local clock of the gateway is adjusted according to the clock offset, which helps to maintain a high synchronization accuracy when the network load is heavy, avoids the problem of reduced synchronization accuracy, and can achieve large-scale network deployment and expansion without increasing delays and affecting accuracy, avoiding the problem of expensive dedicated PTP hardware equipment, and will not cause an economic burden for large-scale network deployment.

[0007] A first aspect of the present invention provides a time synchronization method based on a time synchronization gateway, comprising:

[0008] S1, on the gateway timing side, establish a master-slave relationship between the gateway and the upstream PTP device to complete PTP synchronization;

[0009] S2, parsing the message through the data plane, obtaining timestamp information, and sending the timestamp information to the control plane;

[0010] S3, determining a clock offset through the control plane according to the timestamp information;

[0011] S4, adjusting the local clock of the gateway according to the clock offset;

[0012] S5, on the gateway timing side, establish a master-slave relationship between the gateway and the downstream network device to complete SD-PTP synchronization.

[0013] Furthermore, the S2 specifically includes:

[0014] Get data stream;

[0015] Identify PTP protocol data packets through the in-pipeline parser;

[0016] Process the SYNC message, Follow_up message, and Delay_Resp message in the PTP protocol data packet to obtain timestamp information;

[0017] The timestamp information is sent to the control plane through the ingress pipeline reverse parser according to the value of the summary type field of the ingress pipeline inherent metadata.

[0018] Further, the identifying of the PTP protocol data packet by the in-pipeline parser specifically includes:

[0019] Extract the 14-byte Ethernet header of the PTP protocol data packet;

[0020] Determine whether the Ethernet upper layer protocol type in the Ethernet header is 0X88F7; if so, determine that the current processed message is a PTP protocol message and proceed to the next step;

[0021] Extract the 44-byte PTP message;

[0022] The value of the first 8 bytes in the extracted PTP message is assigned to the protocol type field of the custom metadata.

[0023] Furthermore, the processing method of the SYNC message in the handle_sync matching action table specifically includes:

[0024] Record the MAC timestamp t2 when the SYNC message arrives at the data plane, and store the MAC timestamp in the custom metadata. The MAC timestamp is a 48-bit timestamp, the upper 16 bits are recorded in t2hi, and the lower 32 bits are recorded in t2lo. The MAC timestamp is specifically:

[0025] t2=t2hi·2 32 +t2lo

[0026] Among them, t2 represents the MAC timestamp, t2hi represents the high-order record of the MAC timestamp, and t2lo represents the low-order record of the MAC timestamp;

[0027] Record the hardware timestamp t2ingress when the SYNC message arrives at the data plane, and store the hardware timestamp in the custom metadata. The hardware timestamp is a 48-bit timestamp, the upper 16 bits are recorded in t2ingresshi, and the lower 32 bits are recorded in t2ingresslo. The hardware timestamp is specifically:

[0028] t2ingress=t2ingressshi·2 32 +t2ingresslo

[0029] Among them, t2ingress represents the hardware timestamp, t2ingresshi represents the high-order record of the hardware timestamp, and t2ingresslo represents the low-order record of the hardware timestamp;

[0030] Record the serial number of the SYNC message and store the serial number in the serial number field of the custom metadata;

[0031] Modify the values ​​of the fields in the SYNC message to convert the SYNC message into a Delay_Req message;

[0032] Modify the value of the Summary Type field of the intrinsic metadata of the incoming pipeline and set the value to 1.

[0033] Furthermore, the processing method of the SYNC message in the forward_delayrequest matching action table specifically includes:

[0034] Forward the Delay_Req message, exchange the source MAC address and destination MAC address of the current PTP protocol data packet, and set the forwarding port to send the Delay_Req message to the upstream PTP device.

[0035] Furthermore, the processing method of the Follow_up message in the handle_followup matching action table specifically includes:

[0036] Record the timestamp t1 carried by the Follow_up message, and store the timestamp carried by the Follow_up message in the custom metadata. The timestamp carried by the Follow_up message is an 80-bit timestamp, 32 bits of the nanosecond value are recorded in t1nano, the high 16 bits of the second value are recorded in t1msb, and the low 32 bits of the second value are recorded in t1lsb. The timestamp carried by the Follow_up message is specifically:

[0037] t1=(t1msb·2 32 +t1lsb)·10 9 +t1nano

[0038] Among them, t1 indicates the timestamp carried by the Follow_up message, t1msb indicates the high-order record of the timestamp seconds value carried by the Follow_up message, t1lsb indicates the low-order record of the timestamp seconds value carried by the Follow_up message, and t1nano indicates the nanoseconds value record of the timestamp carried by the Follow_up message;

[0039] Record the sequence number of the Follow_up message and store the sequence number in the sequence number field of the custom metadata;

[0040] Modify the value of the Summary Type field of the intrinsic metadata of the incoming pipeline and set the value to 2.

[0041] Furthermore, the processing method of the Delay_Resp message in the handle_delayresp matching action table specifically includes:

[0042] Record the timestamp t4 carried by the Delay_Resp message, and store the timestamp carried by the Delay_Resp message in the custom metadata. The timestamp carried by the Delay_Resp message is an 80-bit timestamp, 32 bits of the nanosecond value are recorded in t4nano, the high 16 bits of the second value are recorded in t4msb, and the low 32 bits of the second value are recorded in t4lsb. The timestamp carried by the Delay_Resp message is specifically:

[0043] t4=(t4msb·2 32 +t4lsb)·10 9 +t4nano

[0044] Among them, t4 indicates the timestamp carried by the Delay_Resp message, t4msb indicates the high-order record of the timestamp seconds value carried by the Delay_Resp message, t4lsb indicates the low-order record of the timestamp seconds value carried by the Delay_Resp message, and t4nano indicates the nanoseconds value record of the timestamp carried by the Delay_Resp message;

[0045] Record the sequence number of the Delay_Resp message and store the sequence number in the sequence number field of the custom metadata;

[0046] Modify the value of the Summary Type field of the intrinsic metadata of the incoming pipeline and set the value to 3.

[0047] Furthermore, the S2 specifically includes:

[0048] At the outgoing pipeline of the data plane, define the matching action table do_ptp_cap, and use the protocol type field of the custom metadata to determine whether the currently processed message is a Delay_Req message; if so, set the control bit to 1, obtain the MAC timestamp generated when the PTP protocol data packet is sent, and read the timestamp t3 of the Delay_Req message sent by the data plane in the control plane.

[0049] Furthermore, the S3 specifically includes:

[0050] Determine whether the values ​​of the sequence number fields in the summary information of each message are consistent; if so, calculate the one-way link delay:

[0051] wiredelay=((t4-t1)-(t3-t2)) / 2

[0052] Among them, wiredelay represents the one-way link delay, and t3 represents the timestamp of sending the Delay_Req message;

[0053] According to the delay request response mechanism of the PTP protocol, the first control plane real-time time T2_ingress when the data plane generates the timestamp t2ingress is calculated:

[0054] T2_ingress=t1+wiredelay+t2ingress-t2

[0055] Wherein, T2_ingress represents the real time of the first control plane when the data plane generates the timestamp t2ingress;

[0056] According to the local clock, calculate the second control plane real-time time T2_ingress_sw when the data plane generates the timestamp t2ingress:

[0057] T2_ingress_sw=Tc-T_global+T_era+t2ingress

[0058] Among them, T2_ingress_sw represents the real-time time of the second control plane when the data plane generates the timestamp t2ingress, Tc represents the real-time time of the control plane at any time of the switch, T_global represents the global time of the data plane corresponding to the time Tc read through the API of the switch, and T_era represents the time used to record whether the global time of the data plane overflows;

[0059] The clock offset is calculated based on the first control plane real time T2_ingress when the data plane generates the timestamp t2ingress and the second control plane real time T2_ingress_sw when the data plane generates the timestamp t2ingress:

[0060] offset=T2_ingress-T2_ingress_sw

[0061] Here, offset indicates the clock offset.

[0062] A second aspect of the present invention provides a time synchronization system based on a time synchronization gateway, comprising:

[0063] processor;

[0064] A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the above-mentioned time synchronization method based on the time synchronization gateway is implemented.

[0065] The beneficial effects of the present invention are as follows:

[0066] The method and system of the present invention parse messages through the data plane to obtain timestamp information, and send the timestamp information to the control plane, so that time synchronization exists not only in the control plane of the switch, avoiding the impact of clock drift of the device during software processing delay, and eliminating the need for the client to perform multiple rounds of synchronization and statistical filtering. According to the timestamp information, the clock offset is determined through the control plane, and the local clock of the gateway is adjusted according to the clock offset, which helps to maintain high synchronization accuracy when the network load is heavy, avoids the problem of reduced synchronization accuracy, can achieve large-scale network deployment and expansion without increasing delay and affecting accuracy, avoids the problem of expensive dedicated PTP hardware equipment, and does not cause an economic burden for large-scale network deployment. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The accompanying drawings are only used to illustrate specific embodiments and are not considered to limit the present invention. In the entire drawings, the same reference symbols represent the same components. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings.

[0068] Figure 1 A schematic diagram of a time synchronization method based on a time synchronization gateway provided in an embodiment of the present invention;

[0069] Figure 2 A schematic diagram of the structure of a time synchronization system based on a time synchronization gateway provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0070] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work should fall within the scope of protection of the present invention.

[0071] Furthermore, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts disclosed in the present invention.

[0072] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the orientation or position relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. The terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0073] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of methods and systems consistent with some aspects of the present invention as detailed in the appended claims.

[0074] The present invention proposes a time synchronization method and system based on a time synchronization gateway, which solves the problem that in order to offset the impact of clock drift of the device during software processing delay in the prior art, the client needs to perform multiple rounds of synchronization and statistical filtering. When the network load is heavy, the synchronization accuracy achieved by the PTP protocol will drop to the microsecond level. The software implementation of PTP cannot achieve large-scale network deployment and expansion without increasing delay and affecting accuracy. And because the dedicated PTP hardware equipment is expensive, it will cause a certain economic burden for large-scale network deployment.

[0075] Method Embodiment

[0076] Reference Manual Attached Figure 1 , shows a flow chart of a time synchronization method based on a time synchronization gateway provided in an embodiment of the present invention.

[0077] An embodiment of the present invention provides a time synchronization method based on a time synchronization gateway, comprising:

[0078] Specifically, the method includes steps S1 to S5.

[0079] S1, on the gateway timing side, establish a master-slave relationship between the gateway and the upstream PTP device to complete PTP synchronization.

[0080] It should be noted that the upstream PTP device is the master clock device, and the gateway is the slave clock of the upstream PTP device.

[0081] It should be noted that the implementation process of the gateway timing side includes the data plane processing process and the control plane processing process.

[0082] It should be noted that the data plane is the data plane of the P4 switch.

[0083] Among them, the P4 switch is a highly programmable network switch that defines the processing logic and forwarding rules of data packets based on the P4 programming language. Unlike traditional switches, the P4 switch allows users to flexibly specify how to parse, process and forward network data packets through programming, thereby achieving precise control and optimization of network traffic. The P4 switch supports dynamic adjustment and updating of network functions, and is suitable for scenarios that require rapid changes and customization of network services.

[0084] Among them, the data plane uses a pipeline processing architecture, and the data plane processing flow is subdivided into ingress parser parsing (SwitchIngressParser), ingress processing (SwitchIngress), ingress deparser parsing (SwitchIngressDeParser), and outgress processing (SwitchEgress).

[0085] In the present invention, the upstream PTP device acts as the master clock device to ensure the authority and accuracy of the time source, and the gateway acts as a slave clock to receive and synchronize the time of the upstream PTP device, so that the accumulation of time errors can be reduced. Using a pipeline processing architecture (including an in-pipeline parser, in-pipeline processing, in-pipeline reverse parser, and out-pipeline processing), multiple messages can be processed in parallel, data processing efficiency can be improved, and latency can be reduced. Through a strict master-slave relationship and precise timestamp processing, the stability and reliability of the time synchronization of the entire system are guaranteed, and network failures or performance degradation caused by time errors are avoided.

[0086] S2, parse the message through the data plane, obtain timestamp information, and send the timestamp information to the control plane.

[0087] In the present invention, the data plane can quickly process the messages entering and leaving the gateway, and extract the summary information required for time synchronization (such as timestamp, sequence number, etc.) in real time. In this way, the control plane can obtain accurate data in a timely manner, thereby more accurately calculating the clock offset and improving the accuracy of time synchronization. The tasks of the data plane and the control plane are separated, making the system design more modular. In this way, when it is necessary to expand or optimize the time synchronization function, the data plane or the control plane can be adjusted independently without affecting the other parts.

[0088] In a possible implementation, S2 specifically includes:

[0089] Get the data stream.

[0090] It should be noted that the PTP protocol data packet is received by the data plane of the P4 switch.

[0091] The PTP protocol data packets are identified through the in-pipeline parser.

[0092] Among them, PTP (Precision Time Protocol) is a protocol for time synchronization of network devices, which aims to provide higher precision time synchronization than the traditional Network Time Protocol (NTP). PTP calibrates the clock of the device by exchanging timestamp messages in the network, achieving microsecond or even nanosecond synchronization accuracy, and is widely used in fields that require high-precision time synchronization, such as financial transactions, industrial control, and communication networks.

[0093] Among them, NTP (Network Time Protocol) is a protocol used to synchronize time in computer networks. It obtains standard time from a time server through the network and adjusts it to the clock of the local computer to ensure that the time of each device in the network is consistent. NTP is widely used in computer systems, network equipment and services. Although its synchronization accuracy is usually at the millisecond level, it supports time synchronization across different network structures and is suitable for most common application scenarios.

[0094] In a possible implementation, identifying the PTP protocol data packet through the in-pipeline parser specifically includes:

[0095] Extract the 14-byte Ethernet header of the PTP protocol data packet.

[0096] Determine whether the Ethernet upper layer protocol type in the Ethernet header is 0X88F7. If so, determine that the current processed message is a PTP protocol message and proceed to the next step.

[0097] Extract the 44-byte PTP message.

[0098] The value of the first 8 bytes in the extracted PTP message is assigned to the protocol type field of the custom metadata.

[0099] Further, it switches to the receiving state and forwards the PTP protocol data packet to the in-pipeline for processing.

[0100] In the present invention, the PTP protocol data packet is identified by the ingress parser (SwitchIngressParser), and the hardware is used to accelerate the parsing process, so that the PTP message can be quickly extracted and processed, and the data processing efficiency is improved. By extracting the 14-byte Ethernet header and judging the protocol type, the PTP protocol data packet can be accurately identified, avoiding the misprocessing of other types of messages.

[0101] Process the SYNC message, Follow_up message, and Delay_Resp message in the PTP protocol data packet to obtain timestamp information.

[0102] It should be noted that in the PTP (Precision Time Protocol) protocol, the SYNC message is used to synchronize the time between the master clock and the slave clock, and carries the timestamp sent by the master clock. The Follow_up message is used to supplement the timestamp in the SYNC message and provide the precise time when the master clock sent the SYNC message. The Delay_Resp message is used to respond to the Delay_Req message sent by the slave clock, and carries the timestamp of the SYNC message received by the slave clock, which is used to calculate the link delay. Through the exchange of these messages, the PTP protocol can achieve high-precision time synchronization.

[0103] Specifically, at the pipeline, the processing logic for the SYNC message, the Follow_up message, and the Delay_Resp message is defined.

[0104] Optionally, for a SYNC message, two matching action tables are defined: a handle_sync matching action table and a forward_delayrequest matching action table.

[0105] It should be noted that the handle_sync matching action table is used to process the SYNC message in the PTP protocol, record the timestamp and sequence number of the message, and convert the SYNC message into a Delay_Req message for link delay measurement. The forward_delayrequest matching action table is used to process the Delay_Req message converted by the handle_sync matching action table, and is responsible for forwarding the message to the upstream PTP device and exchanging the source and destination MAC addresses to ensure that the message can reach the target correctly.

[0106] Optionally, for the Follow_up message, a handle_followup matching action table is defined.

[0107] It should be noted that the handle_followup matching action table is used to process the Follow_Up message in the PTP protocol and record the timestamp and sequence number in the message to provide the accurate time when the master clock sends the SYNC message during the synchronization process.

[0108] Optionally, corresponding to the Delay_Resp message, a handle_delayresp matching action table is defined.

[0109] It should be noted that the handle_delayresp matching action table is used to process the Delay_Resp message in the PTP protocol, record the timestamp and sequence number of the message, and is used to calculate the link delay and complete the time synchronization process.

[0110] In a possible implementation manner, the processing method of the SYNC message in the handle_sync matching action table specifically includes:

[0111] Specifically, the handle_sync matching action table uses the protocol type field of the custom metadata in the in-pipeline parser to determine whether the message is a SYNC message. If so, perform the following steps:

[0112] Record the MAC timestamp t2 when the SYNC message arrives at the data plane, and store the MAC timestamp in the custom metadata. The MAC timestamp is a 48-bit timestamp, the upper 16 bits are recorded in t2hi, and the lower 32 bits are recorded in t2lo. The specific MAC timestamp is:

[0113] t2=t2hi·2 32 +t2lo

[0114] Among them, t2 represents the MAC timestamp, t2hi represents the high-order record of the MAC timestamp, and t2lo represents the low-order record of the MAC timestamp.

[0115] Among them, MAC timestamp refers to the timestamp recorded on the network switch or network interface card (NIC), which is usually used to mark the exact time when the data packet arrives or leaves. In the Ethernet environment, MAC timestamp is a time record based on the MAC (Media Access Control) layer, which is used to calculate link delay, synchronize network device clocks or optimize network performance. This timestamp is essential for high-precision time synchronization protocols (such as PTP) and network performance monitoring.

[0116] Record the hardware timestamp t2ingress when the SYNC message arrives at the data plane, and store the hardware timestamp in the custom metadata. The hardware timestamp is a 48-bit timestamp, the upper 16 bits are recorded in t2ingresshi, and the lower 32 bits are recorded in t2ingresslo. The hardware timestamp is specifically:

[0117] t2ingress=t2ingressshi·2 32 +t2ingresslo

[0118] Among them, t2ingress represents the hardware timestamp, t2ingresshi represents the high-order record of the hardware timestamp, and t2ingresslo represents the low-order record of the hardware timestamp.

[0119] Record the sequence number of the SYNC message and store the sequence number in the sequence number field of the custom metadata.

[0120] The values ​​of the fields in the SYNC message are modified to convert the SYNC message into a Delay_Req message.

[0121] Modify the value of the Summary Type field of the intrinsic metadata of the incoming pipeline and set the value to 1.

[0122] In the present invention, the MAC timestamp and hardware timestamp when the SYNC message arrives at the data plane are recorded in the handle_sync matching action table. These accurate timestamp records are crucial for the subsequent clock offset calculation and help improve the accuracy of time synchronization. By recording the MAC timestamp and hardware timestamp, the integrity of the time information is ensured and the reliability of time synchronization is improved. Preprocessing and timestamp recording are performed on the data plane, reducing the amount of data that needs to be forwarded to the control plane, thereby optimizing the use of network resources.

[0123] In a possible implementation manner, the processing method of the SYNC message in the forward_delayrequest matching action table specifically includes:

[0124] Specifically, the forward_delayrequest matching action table uses the protocol type field of the custom metadata in the inbound pipeline parser to determine whether the message is a SYNC message. If so, perform the following steps:

[0125] Forward the Delay_Req message, exchange the source MAC address and destination MAC address of the current PTP protocol data packet, and set the forwarding port to send the Delay_Req message to the upstream PTP device.

[0126] In the present invention, the SYNC message is converted into a Delay_Req message and sent to the upstream PTP device to achieve rapid sending of time requests, thereby improving the efficiency of time synchronization. By exchanging the source MAC address and the destination MAC address, it is ensured that the message can be correctly returned to the original sender, maintaining the reliability and stability of the communication link.

[0127] In a possible implementation manner, the processing method of the Follow_up message in the handle_followup matching action table specifically includes:

[0128] Specifically, the handle_followup matching action table uses the protocol type field of the custom metadata in the inbound pipeline parser to determine whether the message is a Follow_up message. If so, perform the following steps:

[0129] Record the timestamp t1 carried by the Follow_up message and store it in the custom metadata. The timestamp carried by the Follow_up message is an 80-bit timestamp. The 32 bits of the nanosecond value are recorded in t1nano, the high 16 bits of the second value are recorded in t1msb, and the low 32 bits of the second value are recorded in t1lsb. The timestamp carried by the Follow_up message is as follows:

[0130] t1=(t1msb·2 32 +t1lsb)·10 9 +t1nano

[0131] Among them, t1 indicates the timestamp carried by the Follow_up message, t1msb indicates the high-order record of the timestamp seconds value carried by the Follow_up message, t1lsb indicates the low-order record of the timestamp seconds value carried by the Follow_up message, and t1nano indicates the nanoseconds value record of the timestamp carried by the Follow_up message.

[0132] Record the sequence number of the Follow_up message and store it in the sequence number field of the custom metadata.

[0133] Modify the value of the Summary Type field of the intrinsic metadata of the incoming pipeline and set the value to 2.

[0134] In the present invention, the 80-bit timestamp (including nanoseconds and seconds) carried by the Follow_up message is recorded to ensure the accuracy of the time information, which is essential for calculating the clock offset and performing time synchronization. The protocol type field of the custom metadata is used to determine the message type, and the timestamp and sequence number are recorded, which increases the flexibility of processing and facilitates the expansion and adjustment of processing logic. Recording timestamps and sequence numbers in the data plane reduces the amount of data that needs to be transmitted to the control plane, optimizes the use of network resources, and improves the utilization efficiency of network bandwidth.

[0135] In a possible implementation manner, the processing method of the Delay_Resp message in the handle_delayresp matching action table specifically includes:

[0136] Specifically, the handle_delayresp matching action table uses the protocol type field of the custom metadata in the inbound pipeline parser to determine whether the message is a Delay_Resp message. If so, perform the following steps:

[0137] Record the timestamp t4 carried by the Delay_Resp message, and store the timestamp carried by the Delay_Resp message in the custom metadata. The timestamp carried by the Delay_Resp message is an 80-bit timestamp. The 32 bits of the nanosecond value are recorded in t4nano, the high 16 bits of the second value are recorded in t4msb, and the low 32 bits of the second value are recorded in t4lsb. The timestamp carried by the Delay_Resp message is as follows:

[0138] t4=(t4msb·2 32 +t4lsb)·10 9 +t4nano

[0139] Among them, t4 indicates the timestamp carried by the Delay_Resp message, t4msb indicates the high-order record of the timestamp seconds value carried by the Delay_Resp message, t4lsb indicates the low-order record of the timestamp seconds value carried by the Delay_Resp message, and t4nano indicates the nanoseconds value record of the timestamp carried by the Delay_Resp message.

[0140] Record the sequence number of the Delay_Resp message and store it in the sequence number field of the custom metadata.

[0141] Modify the value of the Summary Type field of the intrinsic metadata of the incoming pipeline and set the value to 3.

[0142] In the present invention, the 80-bit timestamp (including nanoseconds and seconds) carried by the Delay_Resp message is recorded to ensure the accuracy of the time information, which is crucial for calculating the clock offset and performing time synchronization. Recording the timestamp and sequence number on the data plane reduces the amount of data that needs to be processed by the control plane and improves the processing efficiency of the overall system. Recording the timestamp and sequence number on the data plane reduces the amount of data that needs to be transmitted to the control plane, optimizes the use of network resources, and improves the utilization efficiency of network bandwidth.

[0143] The timestamp information is sent to the control plane through the ingress pipeline reverse parser according to the value of the summary type field of the ingress pipeline inherent metadata.

[0144] Among them, when the value of the summary type field is 1, the current PTP protocol data packet is a SYNC message, and the summary information is the MAC timestamp t2, the hardware timestamp t2ingresshi and the sequence number (sequenceId).

[0145] Among them, when the value of the summary type field is 2, the current PTP protocol data packet is a Follow_up message, and the summary information is the timestamp t1 and the sequence number (sequenceId) carried by the Follow_up message.

[0146] When the value of the summary type field is 3, the current PTP protocol data packet is a Delay_Resp message, and the summary information is the timestamp t4 and the sequence number (sequenceId) carried by the Delay_Resp message.

[0147] In the present invention, specific summary information (such as timestamp and sequence number) is sent according to different message types (SYNC message, Follow_up message, Delay_Resp message) to ensure that the information received by the control plane is accurate and useful, which helps to improve the accuracy and reliability of time synchronization. Only key summary information (such as timestamp and sequence number) is sent to the control plane instead of the entire PTP protocol data packet, which significantly reduces the amount of data that needs to be transmitted and processed, thereby reducing the load of the control plane and improving the processing efficiency of the overall system.

[0148] In a possible implementation manner, S2 specifically further includes:

[0149] At the outgoing pipeline of the data plane, define the matching action table do_ptp_cap, and use the protocol type field of the custom metadata to determine whether the currently processed message is a Delay_Req message. If so, enable the control bit of the MAC timestamp when the PTP protocol data packet is sent.

[0150] In the present invention, the control bit of the MAC timestamp when the PTP protocol data packet is sent specifically refers to setting the control bit to 1, ensuring that the timestamp t3 of the Delay_Req message can be accurately recorded, thereby improving the accuracy of time synchronization. The timestamp is directly obtained at the outflow pipeline, reducing the timestamp error caused by message transmission delay or loss, and ensuring the accuracy of time synchronization.

[0151] S3: Determine a clock offset through the control plane according to the timestamp information.

[0152] In a possible implementation, S3 specifically includes:

[0153] Determine whether the values ​​of the sequence number fields in the summary information of each message are consistent. If so, calculate the one-way link delay:

[0154] wiredelay=((t4-t1)-(t3-t2)) / 2

[0155] Among them, wiredelay represents the unidirectional link delay, and t3 represents the timestamp of sending the Delay_Req message.

[0156] According to the delay request response mechanism of the PTP protocol, the first control plane real-time time T2_ingress when the data plane generates the timestamp t2ingress is calculated:

[0157] T2_ingress=t1+wiredelay+t2ingress-t2

[0158] Among them, T2_ingress represents the real time of the first control plane when the data plane generates the timestamp t2ingress.

[0159] It should be noted that the first control plane real-time time is the control plane real-time time T2_ingress when the switch data plane generates the timestamp t2ingress calculated according to the delay request response mechanism of the PTP protocol.

[0160] According to the local clock, calculate the second control plane real-time time T2_ingress_sw when the data plane generates the timestamp t2ingress:

[0161] T2_ingress_sw=Tc-T_global+T_era+t2ingress

[0162] Among them, T2_ingress_sw represents the real-time time of the second control plane when the data plane generates the timestamp t2ingress, Tc represents the real-time time of the control plane at any time of the switch, T_global represents the global time of the data plane corresponding to the time Tc read through the API of the switch, and T_era represents the time used to record whether the global time of the data plane overflows.

[0163] It should be noted that the second control plane real time is the control plane real time T2_ingress_sw when the data plane generates the timestamp t2ingress calculated according to the local clock of the switch.

[0164] The clock offset is calculated based on the first control plane real time T2_ingress when the data plane generates the timestamp t2ingress and the second control plane real time T2_ingress_sw when the data plane generates the timestamp t2ingress:

[0165] offset=T2_ingress-T2_ingress_sw

[0166] Here, offset indicates the clock offset.

[0167] In the present invention, by judging whether the sequence number field values ​​of the messages are consistent, the accuracy of calculating the unidirectional link delay is ensured, which helps to more accurately correct the clock offset. The real-time times of the first and second control planes when the data plane generates the timestamp are calculated respectively, which ensures the accuracy of the timestamp, thereby improving the accuracy of clock synchronization. According to the offsets calculated based on different timestamps, the clock can be adjusted in real time, the time synchronization requirements can be quickly responded to, and the time synchronization efficiency of the system is improved.

[0168] S4, adjust the local clock of the gateway according to the clock offset.

[0169] In the present invention, by using the calculated clock offset, the local clock of the gateway is accurately adjusted to ensure that the gateway clock is highly consistent with the master clock of the upstream PTP device, thereby improving the accuracy of time synchronization. The local clock is accurately adjusted to ensure the time synchronization of the gateway and other network devices (such as downstream network devices), thereby enhancing the compatibility and interoperability of the system. By automatically adjusting the clock offset, the need for manual clock correction is reduced, system maintenance and management are simplified, and operation and maintenance costs are reduced.

[0170] S5, on the gateway timing side, establish a master-slave relationship between the gateway and the downstream network device to complete SD-PTP synchronization.

[0171] It should be noted that the gateway is the master clock device and the downstream network device is the slave clock of the gateway.

[0172] Specifically, the SD-PTP protocol is deployed on the gateway.

[0173] Among them, the SD-PTP protocol (Software-Defined Precision Time Protocol) is a time synchronization protocol based on software-defined networking (SDN) technology, which aims to improve the time synchronization accuracy in the network. The SD-PTP protocol combines the traditional PTP protocol with the flexibility of SDN in the SDN environment, and uses programmable network devices and control planes to achieve fine control and optimization of the time synchronization process, thereby providing a more accurate time synchronization service, which is suitable for application scenarios that require high time accuracy.

[0174] Among them, Software-Defined Networking (SDN) is a network architecture that separates the network control plane from the data plane and centralizes the network control function into the software controller, thereby realizing centralized management and dynamic configuration of the network. SDN enables network administrators to flexibly configure and optimize network resources through programming interfaces, improve the scalability, flexibility and automation level of the network, and cope with rapidly changing business needs and network environments.

[0175] Furthermore, the gateway receives a synchronization request from a downstream network device and performs SD-PTP synchronization to achieve clock information transmission within the gateway.

[0176] It should be noted that the above process is the clock information transmission process from the PTP domain to the SD-PTP domain. As a network device capable of bidirectional clock information transmission, the gateway also needs to have the function of transmitting clock information from the SD-PTP domain to the PTP domain. The specific implementation process can be completed by establishing a PTP master clock on the P4 switch, which is the same as the above process.

[0177] In the present invention, by setting the gateway as the master clock device, the downstream network devices will synchronize the time from the gateway. This ensures that all downstream devices operate with the same time reference, avoiding the impact of time deviation on data processing and transmission. The gateway as the master clock device can provide a high-precision time synchronization signal, allowing downstream devices to accurately synchronize with the gateway's clock, thereby improving the time synchronization accuracy of the entire system.

[0178] System Example

[0179] Reference Manual Attached Figure 2 , shows a structural diagram of a time synchronization system based on a time synchronization gateway provided in an embodiment of the present invention.

[0180] The present invention proposes a time synchronization system 30 based on a time synchronization gateway, comprising: a processor 301;

[0181] The memory 303 stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the time synchronization method based on the time synchronization gateway described in the method embodiment is implemented.

[0182] The time synchronization system 30 based on the time synchronization gateway includes: a processor 301 and a memory 303. The processor 301 and the memory 303 are connected, for example, through a bus 302.

[0183] The structure of the time synchronization system 30 based on the time synchronization gateway does not constitute a limitation on the embodiment of the present invention.

[0184] Processor 301 may be a CPU, a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, a transistor logic device, a hardware component or any combination thereof. It may implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of the present invention. Processor 301 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0185] The bus 302 may include a path to transmit information between the above components. The bus 302 may be a PCI bus or an EISA bus, etc. The bus 302 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0186] The memory 303 can be a ROM or other type of static storage device that can store static information and instructions, a RAM or other type of dynamic storage device that can store information and instructions, or an EEPROM, a CD-ROM or other optical disk storage, an optical disk storage (including a compressed optical disk, a laser disk, an optical disk, a digital versatile disk, a Blu-ray disk, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to these.

[0187] Computer Readable Storage Medium Embodiments

[0188] The present invention provides a computer-readable storage medium on which a computer program is stored. The computer program can be loaded and executed by a processor to implement the time synchronization method based on a time synchronization gateway as described in the first aspect.

[0189] The applicant of the present invention has made a detailed explanation and description of the implementation examples of the present invention in conjunction with the drawings in the specification. However, those skilled in the art should understand that the above implementation examples are only preferred implementation schemes of the present invention, and the detailed description is only to help readers better understand the spirit of the present invention, but not to limit the scope of protection of the present invention. On the contrary, any improvements or modifications based on the inventive spirit of the present invention should fall within the scope of protection of the present invention.

[0190] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the above embodiments, or replace some of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or replacements that can be easily thought of by those skilled in the art within the technical scope disclosed in the present invention should be covered within the protection scope of the present invention.

Claims

1. A time synchronization method based on a time synchronization gateway, characterized in that: include: S1, on the gateway timing side, establish a master-slave relationship between the gateway and the upstream PTP device to complete PTP synchronization; S2, parsing the message through the data plane, obtaining timestamp information, and sending the timestamp information to the control plane; S3, determining a clock offset through the control plane according to the timestamp information; S4, adjusting the local clock of the gateway according to the clock offset; S5, on the gateway timing side, establish a master-slave relationship between the gateway and the downstream network device to complete SD-PTP synchronization.

2. The time synchronization method based on the time synchronization gateway according to claim 1, characterized in that: The S2 specifically includes: S201, obtaining data stream; S202, identifying the PTP protocol data packet through the in-pipeline parser; S203, processing the SYNC message, Follow_up message and Delay_Resp message in the PTP protocol data packet to obtain timestamp information; S204: Send the timestamp information to the control plane through the inbound pipeline reverse parser according to the value of the summary type field of the inbound pipeline inherent metadata.

3. The time synchronization method based on the time synchronization gateway according to claim 2 is characterized in that: The S202 specifically includes: S2021, extracting a 14-byte Ethernet header of a PTP protocol data packet; S2022, determine whether the Ethernet upper layer protocol type in the Ethernet header is 0X88F7; if so, determine that the currently processed message is a PTP protocol message, and proceed to the next step; S2023, extracting a 44-byte PTP message; S2024: Assign the value of the first 8 bytes in the extracted PTP message to the protocol type field of the custom metadata.

4. The time synchronization method based on the time synchronization gateway according to claim 2 is characterized in that: The processing method of the SYNC message in the handle_sync matching action table specifically includes: Record the MAC timestamp t2 when the SYNC message arrives at the data plane, and store the MAC timestamp in the custom metadata. The MAC timestamp is a 48-bit timestamp, the upper 16 bits are recorded in t2hi, and the lower 32 bits are recorded in t2lo. The MAC timestamp is specifically: <h2 style=";text-align:left;direction:ltr">t2 = t2hi·2<h2 style=";text-align:left;direction:ltr"> 32 <h2 style=";text-align:left;direction:ltr"> +t2lo Among them, t2 represents the MAC timestamp, t2hi represents the high-order record of the MAC timestamp, and t2lo represents the low-order record of the MAC timestamp; Record the hardware timestamp t2ingress when the SYNC message arrives at the data plane, and store the hardware timestamp in the custom metadata. The hardware timestamp is a 48-bit timestamp, the upper 16 bits are recorded in t2ingresshi, and the lower 32 bits are recorded in t2ingresslo. The hardware timestamp is specifically: t2ingress=t2ingresshi·2 32 +t2ingresslo Among them, t2ingress represents the hardware timestamp, t2ingresshi represents the high-order record of the hardware timestamp, and t2ingresslo represents the low-order record of the hardware timestamp; Record the serial number of the SYNC message and store the serial number in the serial number field of the custom metadata; Modify the values ​​of the fields in the SYNC message to convert the SYNC message into a Delay_Req message; Modify the value of the Summary Type field of the intrinsic metadata of the incoming pipeline and set the value to 1.

5. The time synchronization method based on the time synchronization gateway according to claim 2, characterized in that: The processing method of the SYNC message in the forward_delayrequest matching action table specifically includes: Forward the Delay_Req message, exchange the source MAC address and destination MAC address of the current PTP protocol data packet, and set the forwarding port to send the Delay_Req message to the upstream PTP device.

6. The time synchronization method based on the time synchronization gateway according to claim 2, characterized in that: The processing method of the Follow_up message in the handle_followup matching action table specifically includes: Record the timestamp t1 carried by the Follow_up message, and store the timestamp carried by the Follow_up message in the custom metadata. The timestamp carried by the Follow_up message is an 80-bit timestamp, 32 bits of the nanosecond value are recorded in t1nano, the high 16 bits of the second value are recorded in t1msb, and the low 32 bits of the second value are recorded in t1lsb. The timestamp carried by the Follow_up message is specifically: t1=(t1msb·2 32 +t1lsb)·10 9 +t1nano Among them, t1 indicates the timestamp carried by the Follow_up message, t1msb indicates the high-order record of the timestamp seconds value carried by the Follow_up message, t1lsb indicates the low-order record of the timestamp seconds value carried by the Follow_up message, and t1nano indicates the nanoseconds value record of the timestamp carried by the Follow_up message; Record the sequence number of the Follow_up message and store the sequence number in the sequence number field of the custom metadata; Modify the value of the Summary Type field of the intrinsic metadata of the incoming pipeline and set the value to 2.

7. The time synchronization method based on the time synchronization gateway according to claim 2, characterized in that: The processing method of the Delay_Resp message in the handle_delayresp matching action table specifically includes: Record the timestamp t4 carried by the Delay_Resp message, and store the timestamp carried by the Delay_Resp message in the custom metadata. The timestamp carried by the Delay_Resp message is an 80-bit timestamp, 32 bits of the nanosecond value are recorded in t4nano, the high 16 bits of the second value are recorded in t4msb, and the low 32 bits of the second value are recorded in t4lsb. The timestamp carried by the Delay_Resp message is specifically: t4=(t4msb·2 32 +t4lsb)·10 9 +t4nano Among them, t4 indicates the timestamp carried by the Delay_Resp message, t4msb indicates the high-order record of the timestamp seconds value carried by the Delay_Resp message, t4lsb indicates the low-order record of the timestamp seconds value carried by the Delay_Resp message, and t4nano indicates the nanoseconds value record of the timestamp carried by the Delay_Resp message; Record the sequence number of the Delay_Resp message and store the sequence number in the sequence number field of the custom metadata; Modify the value of the Summary Type field of the intrinsic metadata of the incoming pipeline and set the value to 3.

8. The time synchronization method based on the time synchronization gateway according to claim 2, characterized in that: The S2 specifically includes: S205, at the outgoing pipeline of the data plane, define the matching action table do_ptp_cap, and use the protocol type field of the custom metadata to determine whether the currently processed message is a Delay_Req message; if so, enable the control bit of obtaining the MAC timestamp when the PTP protocol data packet is sent, so as to read the timestamp t3 of the Delay_Req message sent by the data plane in the control plane.

9. The time synchronization method based on the time synchronization gateway according to claim 1, characterized in that: The S3 specifically includes: S301, determine whether the values ​​of the sequence number fields in the summary information of each message are consistent; if so, calculate the unidirectional link delay: wiredelay=((t4-t1)-(t3-t2)) / 2 Among them, wiredelay represents the one-way link delay, and t3 represents the timestamp of sending the Delay_Req message; S302, according to the delay request response mechanism of the PTP protocol, calculate the first control plane real-time time T2_ingress when the data plane generates the timestamp t2ingress: T2_ingress=t1+wiredelay+t2ingress-t2 Wherein, T2_ingress represents the real time of the first control plane when the data plane generates the timestamp t2ingress; S303, calculate the second control plane real-time time T2_ingress_sw when the data plane generates the timestamp t2ingress according to the local clock: T2_ingress_sw=Tc-T_global+T_era+t2ingress Among them, T2_ingress_sw represents the real-time time of the second control plane when the data plane generates the timestamp t2ingress, Tc represents the real-time time of the control plane at any time of the switch, T_global represents the global time of the data plane corresponding to the time Tc read through the API of the switch, and T_era represents the time used to record whether the global time of the data plane overflows; S304, calculate the clock offset according to the first control plane real time T2_ingress when the data plane generates the timestamp t2ingress and the second control plane real time T2_ingress_sw when the data plane generates the timestamp t2ingress: offset=T2_ingress-T2_ingress_sw Here, offset indicates the clock offset.

10. A time synchronization system based on a time synchronization gateway, characterized in that: include: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the time synchronization method based on the time synchronization gateway as described in any one of claims 1 to 9 is implemented.

Images