Memory structure and its formation method

Abstract

A memory structure and a method for forming the same are disclosed. The method includes: providing a substrate; forming a floating gate precursor layer on the substrate; and providing a ligand material to react with the floating gate precursor layer to form a charge trapping structure, wherein the material of the charge trapping structure is a derivative of a metal-organic framework. The metal-organic framework derivative has a complex microporous periodic topology, which makes the charge trapping structure porous with a high defect state density and strong carrier trapping capability. This allows for charge storage at low operating voltages, improving the reliability of the memory structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a memory structure and a method for forming the same. Background Technology

[0002] There are many types of memory. Based on the storage material, they can be divided into magnetic surface memory and semiconductor memory. Semiconductor memory can be further divided into volatile memory and non-volatile memory based on whether data retention depends on an external power source. Volatile memory loses all stored data when power is off, such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). Conversely, non-volatile memory retains stored data even when power is off, such as embedded flash memory (EFlash) and charge trapping memory (CTM). Charge trapping memory features low power consumption, good fatigue characteristics, and strong data retention capabilities, making it one of the mainstream non-volatile memory types currently in use. Data writing, erasing, and storage are achieved by applying different voltages to the storage layer to control the tunneling of charges into and out of the storage layer.

[0003] However, current charge-trapping memories still face many challenges. Summary of the Invention

[0004] The problem addressed by this invention is how to optimize the charge trapping layer to improve the performance of charge trapping memory.

[0005] To address the aforementioned problems, the present invention provides a method for forming a memory structure, comprising: providing a substrate; forming a floating gate precursor layer on the substrate; and providing a ligand material to react with the floating gate precursor layer to form a charge trapping structure, wherein the material of the charge trapping structure is a derivative of a metal-organic framework.

[0006] Optionally, in the step of forming the floating gate precursor layer on the substrate, the floating gate precursor layer is formed by atomic deposition.

[0007] Optionally, in the step of forming the floating gate precursor layer on the substrate, the thickness of the floating gate precursor layer is in the range of 300 angstroms to 600 angstroms.

[0008] Optionally, the step of providing a ligand material to react with the floating gate precursor layer to form the charge trapping structure includes:

[0009] Deposit ligand material, and allow the ligand material to react with the floating gate precursor layer to form an initial charge trapping structure;

[0010] The initial charge trapping structure is annealed to form the charge trapping structure.

[0011] Optionally, in the step of depositing the ligand material, the ligand material is deposited by chemical vapor deposition.

[0012] Optionally, in the step of depositing the ligand material by chemical vapor deposition, the reaction parameters include: a reaction time range of 2h to 4h; and a reaction temperature range of 100℃ to 150℃.

[0013] Optionally, in the step of annealing the initial charge trapping structure to form the charge trapping structure, the annealing parameters include: the annealing temperature range is 250℃~300℃; and the annealing time range is 2h~3h.

[0014] Optionally, the material of the floating gate precursor layer includes metal oxides.

[0015] Optionally, the metal oxide includes zinc oxide.

[0016] Optionally, the ligand material includes organic ligand materials.

[0017] Optionally, the organic ligand material includes terephthalic acid and naphthalenedicarboxylic acid.

[0018] Optional, also includes:

[0019] After providing the substrate and before forming the floating gate precursor layer, a tunneling layer is formed on the substrate; after forming the charge trapping structure, a dielectric layer is formed on the charge trapping structure.

[0020] After the dielectric layer is formed, source and drain regions are formed in the substrate on both sides of the charge trapping structure;

[0021] After the source / drain regions are formed, a control gate is formed on the dielectric layer.

[0022] Optionally, the method further includes: patterning between any two steps in the steps of forming a tunneling layer on the substrate, forming a floating gate precursor layer on the substrate, forming an initial charge trapping structure, annealing the initial charge trapping structure, and forming a dielectric layer on the charge trapping structure.

[0023] Optionally, in the step of forming a dielectric layer on the charge trapping structure, the dielectric layer is formed on the charge trapping structure by chemical vapor deposition.

[0024] Accordingly, the present invention also provides a memory structure, which is formed by the memory structure forming method described in any of the above technical solutions.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0026] In the method for forming the memory structure of the present invention, a ligand material is provided to react with the floating gate precursor layer to form a charge trapping structure. The material of the charge trapping structure is a derivative of a metal-organic framework. The derivative of the metal-organic framework has a complex microporous periodic topology, which makes the charge trapping structure porous and has a large defect state density, strong carrier trapping ability, and can achieve charge storage at a low operating voltage, thereby improving the reliability of the memory structure. Attached Figure Description

[0027] Figure 1 This is a process flow diagram of the formation process of the memory structure according to an embodiment of the present invention;

[0028] Figures 2 to 6 This is a cross-sectional structural diagram of each step in the formation process of the memory structure according to an embodiment of the present invention. Detailed Implementation

[0029] As can be seen from the background technology, with the advent of advanced technology nodes, the use of silicon nitride crystals as charge trapping layers in traditional charge trapping memories has limited the performance of charge trapping memories.

[0030] To address the aforementioned technical problem, the present invention provides a method for forming a memory structure, comprising: providing a substrate; forming a floating gate precursor layer on the substrate; and providing a ligand material to react with the floating gate precursor layer to form a charge trapping structure, wherein the material of the charge trapping structure is a derivative of a metal-organic framework.

[0031] In the method for forming the memory structure of the present invention, a ligand material is provided to react with the floating gate precursor layer to form a charge trapping structure. The material of the charge trapping structure is a derivative of a metal-organic framework. The derivative of the metal-organic framework has a complex microporous periodic topology, which makes the charge trapping structure porous and has a large defect state density, strong carrier trapping ability, and can achieve charge storage at a low operating voltage, thereby improving the reliability of the memory structure.

[0032] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] Please refer to Figure 1 and in conjunction with references Figures 2 to 6 ,in Figure 1This is a process flow diagram illustrating the formation process of the memory structure according to an embodiment of the present invention. Figures 2 to 6 This is a cross-sectional structural schematic diagram of each step in the formation process of a memory structure according to an embodiment of the present invention.

[0034] The process of forming the memory structure includes:

[0035] Step S10: Provide substrate 100;

[0036] Step S11: A tunneling layer 101 is formed on the substrate 100;

[0037] Step S12: A floating gate precursor layer 102 is formed on the substrate 100;

[0038] Step S13: A ligand material is provided to react with the floating gate precursor layer 102 to form a charge trapping structure 104, wherein the charge trapping structure has a structure with metal-organic framework pores.

[0039] Step S14: After forming the charge trapping structure 104, a dielectric layer 105 is formed on the charge trapping structure 104.

[0040] Step S15: After forming the dielectric layer 105, source and drain regions are formed in the substrate 100 on both sides of the charge trapping structure 104.

[0041] Step S16: After forming the source / drain region, a control gate 108 is formed on the dielectric layer 105.

[0042] The following will provide a detailed explanation of each step in the formation process of the memory structure.

[0043] Please refer to Figure 2 In step S10, a substrate 100 is provided.

[0044] The substrate 100 is made of materials including silicon, silicon carbide, silicon germanium, silicon-on-insulator (SOI), or germanium-on-insulator (GOI).

[0045] The substrate 100 provides a structural basis for forming the floating gate precursor layer 102.

[0046] Please continue to refer to this. Figure 2 In step S11, a tunneling layer 101 is formed on the substrate 100.

[0047] The material of the tunneling layer 101 includes silicon oxide.

[0048] Please continue to refer to this. Figure 2 In step S12, a floating gate precursor layer 102 is formed on the substrate 100.

[0049] In the step of forming the floating gate precursor layer 102 on the substrate 100, the floating gate precursor layer 102 is formed by atomic deposition. The floating gate precursor layer 102 formed by atomic deposition has high quality and good uniformity.

[0050] In the step of forming the floating gate precursor layer 102 on the substrate 100, the thickness of the floating gate precursor layer 102 is in the range of 300 angstroms to 600 angstroms.

[0051] The material of the floating gate precursor layer 102 includes a metal oxide. Specifically, in some embodiments of the present invention, the metal oxide includes zinc oxide (ZnO). In other embodiments, the metal oxide also includes other metal oxides besides zinc oxide.

[0052] Specifically, in some embodiments of the present invention, the chemical reaction equations for preparing the floating gate precursor layer 102 of zinc oxide (ZnO) material include:

[0053] Zn(C2H5)2(g)+H2O(g)→ZnO(s)+2C2H6(g).

[0054] Please refer to Figures 3 to 4 In step S13, a ligand material is provided to react with the floating gate precursor layer 102 to form a charge trapping structure 104, wherein the material of the charge trapping structure 104 is a derivative of a metal-organic framework.

[0055] The step of providing ligand material to react with the floating gate precursor layer to form the charge trapping structure includes: Figure 3 As shown, a ligand material is deposited, which reacts with the floating gate precursor layer 102 to form an initial charge trapping structure 103; as Figure 4 As shown, the initial charge trapping structure 103 is annealed to form the charge trapping structure 104.

[0056] In the step of depositing the ligand material, the ligand material is deposited by chemical vapor deposition. Depositing the ligand material by chemical vapor deposition results in a smooth, flat, and uniform surface of the initial charge-trapping structure 103 formed by the reaction. The material of the initial charge-trapping structure 103 is a metal-organic framework (MOF). MOFs are crystalline substances with a periodic topological structure containing complex micropores. MOFs possess porous structures that allow for systematic structural design and can be synthesized at the nanoscale. The initial charge-trapping structure 103 of the MOF provides the basis for forming the charge-trapping structure 104 with MOF pores. In some specific embodiments, the material of the floating gate precursor layer 102 includes zinc oxide (ZnO), and the initial charge-trapping structure 103 formed by the reaction is a Zn-MOF material.

[0057] The ligand material includes organic ligand materials. Specifically, in some embodiments of the present invention, the organic ligand material includes terephthalic acid (H2BDC) and naphthalenedicarboxylic acid (H2NDC). In other embodiments, the ligand material also includes other organic materials. The ligand material can be selected according to the actual process requirements to obtain the desired initial charge trapping structure of the metal-organic framework material and to regulate the performance of the memory structure.

[0058] Specifically, in some embodiments of the present invention, the chemical reaction equation for preparing the initial charge-trapping structure 103 using terephthalic acid (H2BDC) as a ligand material includes:

[0059] ZnO(s)+H2BDC(g)→H2O(g)+Zn-BDC(s).

[0060] In the step of depositing the ligand material by chemical vapor deposition, the reaction parameters include: reaction time range of 2h to 4h; reaction temperature range of 100℃ to 150℃.

[0061] The initial charge trapping structure 103 is annealed so that the annealed derivative of the initial charge trapping structure 103 (i.e., charge trapping structure 104) retains the porosity of the metal-organic framework pore structure. This results in a high defect state density and strong carrier trapping capability of the charge trapping structure 104, enabling charge storage at a lower operating voltage and improving the reliability of the storage device.

[0062] In the step of annealing the initial charge trapping structure 103 to form the charge trapping structure 104, the annealing parameters include: the annealing temperature range is 250℃~300℃; the annealing time range is 2h~3h.

[0063] The thickness of the charge trapping structure 104 is less than 10 nm. Specifically, in some embodiments of the present invention, the material of the charge trapping structure 104 is zinc oxide (ZnO).

[0064] Please refer to Figure 5 In step S14, after forming the charge trapping structure 104, a dielectric layer 105 is formed on the charge trapping structure 104.

[0065] The material of the dielectric layer 105 includes silicon oxide.

[0066] Specifically, in some embodiments of the present invention, after the dielectric layer 105 is formed, the charge trapping structure 104, the tunneling layer 101, and the dielectric layer 105 are patterned to form a floating gate.

[0067] In other embodiments, patterning is performed between any two of the steps of forming a tunneling layer on the substrate, forming a floating gate precursor layer on the substrate, forming an initial charge trapping structure, annealing the initial charge trapping structure, and forming a dielectric layer on the charge trapping structure to form a floating gate.

[0068] Please refer to Figure 6 In step S15, after the dielectric layer 105 is formed, source and drain regions are formed in the substrate 100 on both sides of the charge trapping structure 104.

[0069] The source / drain region includes a source 106 and a drain 107. The source 106 and drain 107 are formed by ion implantation.

[0070] Please continue to refer to this. Figure 6 In step S16, after the source-drain region is formed, a control gate 108 is formed on the dielectric layer 105.

[0071] In the step of forming the control gate 108 on the dielectric layer 105, polysilicon is deposited by chemical vapor deposition and the polysilicon is doped to form the control gate 108.

[0072] Accordingly, this embodiment of the invention also provides a memory structure, which is formed by the above-described method for forming a memory structure, and will not be described in detail here.

[0073] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a memory structure, characterized in that, include: Provide substrate; A floating gate precursor layer is formed on the substrate; A ligand material is provided to react with the floating gate precursor layer to form a charge trapping structure, wherein the material of the charge trapping structure is a derivative of a metal-organic framework.

2. The method for forming a memory structure as described in claim 1, characterized in that, In the step of forming a floating gate precursor layer on the substrate, the floating gate precursor layer is formed by atomic deposition.

3. The method for forming the memory structure as described in claim 1 or 2, characterized in that, In the step of forming a floating gate precursor layer on the substrate, the thickness of the floating gate precursor layer ranges from 300 angstroms to 600 angstroms.

4. The method for forming a memory structure as described in claim 1, characterized in that, The step of providing ligand material to react with the floating gate precursor layer to form the charge trapping structure includes: Deposit ligand material, and allow the ligand material to react with the floating gate precursor layer to form an initial charge trapping structure; The initial charge trapping structure is annealed to form the charge trapping structure.

5. The method for forming a memory structure as described in claim 4, characterized in that, In the step of depositing ligand materials, the ligand materials are deposited by chemical vapor deposition.

6. The method for forming a memory structure as described in claim 5, characterized in that, In the step of depositing the ligand material by chemical vapor deposition, the reaction parameters include: reaction time range of 2h to 4h; reaction temperature range of 100℃ to 150℃.

7. The method for forming a memory structure as described in claim 4, characterized in that, In the step of annealing the initial charge trapping structure to form the charge trapping structure, the annealing parameters include: the annealing temperature range is 250℃~300℃; the annealing time range is 2h~3h.

8. The method for forming a memory structure as described in claim 1, characterized in that, The material of the floating gate precursor layer includes metal oxides.

9. The method for forming a memory structure as described in claim 8, characterized in that, The metal oxide includes zinc oxide.

10. The method for forming a memory structure as described in claim 1, characterized in that, The ligand materials include organic ligand materials.

11. The method for forming a memory structure as described in claim 10, characterized in that, The organic ligand materials include terephthalic acid and naphthalenedicarboxylic acid.

12. The method for forming a memory structure as described in claim 4, characterized in that, Also includes: After providing the substrate and before forming the floating gate precursor layer, a tunneling layer is formed on the substrate; After forming the charge trapping structure, a dielectric layer is formed on the charge trapping structure; After the dielectric layer is formed, source and drain regions are formed in the substrate on both sides of the charge trapping structure; After the source / drain regions are formed, a control gate is formed on the dielectric layer.

13. The method for forming a memory structure as described in claim 12, characterized in that, Also includes: Patterning is performed between any two steps in the steps of forming a tunneling layer on the substrate, forming a floating gate precursor layer on the substrate, forming an initial charge trapping structure, annealing the initial charge trapping structure, and forming a dielectric layer on the charge trapping structure.

14. The method for forming a memory structure as described in claim 12, characterized in that, In the step of forming a dielectric layer on the charge trapping structure, the dielectric layer is formed on the charge trapping structure by chemical vapor deposition.

15. A memory structure, characterized in that, The memory structure is formed by the method for forming a memory structure as described in any one of claims 1 to 14.

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