Resistive memory device and manufacturing method thereof

Abstract

The invention discloses a resistive memory device and a manufacturing method thereof. The resistive memory device includes a dielectric layer, a trench, a first resistance switching element, a diode via structure, and a signal line structure. The trench is disposed in the dielectric layer, the first resistance switching element is disposed in the trench, and the first resistance switching element includes a first lower electrode, a first upper electrode disposed over the first lower electrode, and a first variable resistance layer disposed between the first lower electrode and the first upper electrode. The diode through hole structure is arranged in the dielectric layer and located below the groove, and the diode through hole structure is connected with the first lower electrode. The signal line structure is arranged in the groove, a part of the signal line structure is arranged on the first resistance switching element, and the signal line structure is electrically connected with the first upper electrode.

Description

Technical Field

[0001] The present invention relates to a resistive memory device and a manufacturing method thereof, and in particular to a resistive memory device including a resistance switching element and a signal line structure arranged in a groove and a manufacturing method thereof. Background Art

[0002] Semiconductor memory is a semiconductor device used to store data in computers or electronic products. It can be roughly divided into volatile memory and non-volatile memory. Volatile memory refers to computer memory in which the stored data disappears when the operating power is interrupted. In contrast, non-volatile memory has the characteristic that the stored data will not be lost due to power supply interruption. Resistive random access memory (RRAM) is a type of non-volatile memory. It has the characteristics of low operating voltage, low power consumption and high write speed, and is considered to be a memory structure that can be used in many electronic devices. Summary of the invention

[0003] The present invention provides a resistive memory device and a manufacturing method thereof, wherein a resistive switching element and a corresponding signal line structure are formed in a groove, thereby forming a three-dimensional resistive switching element. In addition, the manufacturing method of the resistive switching element and the signal line structure can be integrated with the manufacturing process of other conductive lines, thereby achieving the effect of simplifying the overall manufacturing process.

[0004] One embodiment of the present invention provides a resistive memory device, comprising a dielectric layer, a trench, a first resistance switching element, a diode via structure and a signal line structure. The trench is arranged in the dielectric layer, and the trench extends along a first horizontal direction. The first resistance switching element is arranged in the trench, and the first resistance switching element includes a first lower electrode, a first upper electrode and a first variable resistance layer. The first upper electrode is arranged on the first lower electrode, and the first variable resistance layer is arranged between the first lower electrode and the first upper electrode. The diode via structure is arranged in the dielectric layer and is located below the trench, and the diode via structure is connected to the first lower electrode. The signal line structure is arranged in the trench, wherein a portion of the signal line structure is arranged on the first resistance switching element, and the signal line structure is electrically connected to the first upper electrode.

[0005] One embodiment of the present invention provides a method for manufacturing a resistive memory device, comprising the following steps. A diode via structure is formed in a dielectric layer, and a first trench is formed in the dielectric layer, and the diode via structure is located below the first trench. A first resistance switching element is formed in the first trench, and the first resistance switching element includes a first lower electrode, a first upper electrode, and a first variable resistance layer. The diode via structure is connected to the first lower electrode, the first upper electrode is arranged on the first lower electrode, and the first variable resistance layer is arranged between the first lower electrode and the first upper electrode. A signal line structure is formed in the first trench, a portion of the signal line structure is formed on the first resistance switching element, and the signal line structure is electrically connected to the first upper electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a three-dimensional schematic diagram of a resistive memory device according to an embodiment of the present invention;

[0007] Figures 2 to 18 FIG. 1 is a schematic diagram of a method for manufacturing a resistive memory device according to an embodiment of the present invention, wherein

[0008] Figure 2 It is a top view schematic diagram;

[0009] Figure 3 For along Figure 2 A schematic cross-sectional view shown along the A1-A1' section line;

[0010] Figure 4 For along Figure 2 A cross-sectional schematic diagram depicted along the B1-B1' section line;

[0011] Figure 5 for Figure 3 Schematic diagram of the situation afterwards;

[0012] Figure 6 for Figure 4 Schematic diagram of the situation afterwards;

[0013] Figure 7 for Figure 5 Schematic diagram of the situation afterwards;

[0014] Figure 8 for Figure 6 Schematic diagram of the situation afterwards;

[0015] Fig. 9 for Figure 7 Schematic diagram of the situation afterwards;

[0016] Fig.10 for Figure 8 Schematic diagram of the situation afterwards;

[0017] Fig.11 for Fig. 9 Schematic diagram of the situation afterwards;

[0018] Fig.12 for Fig.10 Schematic diagram of the situation afterwards;

[0019] Fig.13 for Fig.11 Schematic diagram of the situation afterwards;

[0020] Fig.14 for Fig.12 Schematic diagram of the situation afterwards;

[0021] Fig.15 for Fig.13 Schematic diagram of the situation afterwards;

[0022] Fig.16 for Fig.14 Schematic diagram of the situation afterwards;

[0023] Fig.17 For the corresponding Fig.15 and Fig.16 A top view schematic diagram of

[0024] Fig.18 for Fig.16 Schematic diagram of the situation afterwards.

[0025] Explanation of symbols

[0026] 10: First floor

[0027] 10BS: Bottom surface

[0028] 10TS: Top surface

[0029] 12: Conductive materials

[0030] 14: Second layer

[0031] 14TS: Top surface

[0032] 22: First conductive layer

[0033] 22TS: Upper surface

[0034] 24: Variable resistor material

[0035] 24TS: Upper surface

[0036] 26: Second conductive layer

[0037] 26TS: Upper surface

[0038] 32: Patterned photoresist layer

[0039] 34: Patterned photoresist layer

[0040] 42: Barrier layer

[0041] 42TS: Upper surface

[0042] 44:Metal layer

[0043] 44TS: Upper surface

[0044] 46: Dielectric layer

[0045] 91: First patterning process

[0046] 92: Second patterning process

[0047] 93: Flattening process

[0048] 100: Resistive memory device

[0049] BE: Bottom Electrode

[0050] BE1: First lower electrode

[0051] BE2: Second lower electrode

[0052] BL: Bit Line Structure

[0053] D1: First horizontal direction

[0054] D2: Second horizontal direction

[0055] D3: vertical direction

[0056] DL: Dielectric Layer

[0057] DV: diode via structure

[0058] M1: Wire

[0059] M2: Wire

[0060] M3: Wire

[0061] RS: Resistor switching element

[0062] RS1: First resistance switching element

[0063] RS2: Second resistance switching element

[0064] SL:Signal line structure

[0065] TE: Upper electrode

[0066] TE1: First upper electrode

[0067] TE2: Second upper electrode

[0068] TR1: Groove

[0069] TR2: Groove

[0070] V1: Through-hole structure

[0071] V2: Through-hole structure

[0072] VR: variable resistance layer

[0073] VR1: First variable resistance layer

[0074] VR2: Second variable resistance layer DETAILED DESCRIPTION

[0075] The following detailed description of the present invention has disclosed enough details to enable those skilled in the art to practice the present invention. The embodiments set forth below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the present invention.

[0076] Before further describing each embodiment, specific terms used throughout the text are explained below.

[0077] The meanings of the terms "on," "over," and "over" should be interpreted in the broadest manner, so that "on" means not only "directly on" something, but also includes being on something with other intervening features or layers therebetween, and "over" or "over" means not only being "on" or "over" something, but also includes being "on" or "over" something with no other intervening features or layers therebetween (i.e., directly on something).

[0078] The ordinal numbers used in the specification and claims, such as "first", "second", etc., are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any previous ordinal number of the requested element, nor do they represent the order of one requested element and another requested element, or the order in the manufacturing method. The use of these ordinals is only used to clearly distinguish a requested element with a certain name from another requested element with the same name.

[0079] The term "etching" is generally used herein to describe a process for patterning a material so that at least a portion of the material is left after the etching is complete. When "etching" a material, at least a portion of the material may be retained after the etching is complete. In contrast, when "removing" a material, substantially all of the material may be removed during the process. However, in some embodiments, "removing" may be considered a broad term to include etching.

[0080] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a material layer to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0081] See also Figure 1 as well as Fig.18 . Figure 1 FIG. 1 is a three-dimensional schematic diagram of a resistive memory device 100 according to an embodiment of the present invention. Fig.18 It can be regarded as a partial cross-sectional schematic diagram of the resistive memory device 100 (eg, a cross-sectional schematic diagram drawn along a section line or a section extending along the first horizontal direction D1 and passing through the trench TR1). Figure 1 and Fig.18 As shown, the resistive memory device 100 includes a dielectric layer DL, a trench TR1, a first resistive switching element RS1, a diode via structure DV, and a signal line structure SL. The trench TR1 is disposed in the dielectric layer DL, and the trench TR1 extends along a first horizontal direction D1. The first resistive switching element RS1 is disposed in the trench TR1, and the first resistive switching element RS1 includes a first lower electrode BE1, a first upper electrode TE1, and a first variable resistance layer VR1. The first upper electrode TE1 is disposed on the first lower electrode BE1, and the first variable resistance layer VR1 is disposed between the first lower electrode BE1 and the first upper electrode TE1. The diode via structure DV is disposed in the dielectric layer DL and is located below the trench TR1 in a vertical direction D3, and the diode via structure DV is connected to the first lower electrode BE1. The signal line structure SL is disposed in the trench TR1, a portion of the signal line structure SL is disposed on the first resistive switching element RS1, and the signal line structure SL is electrically connected to the first upper electrode TE1. By disposing a resistance switching element and a signal line structure SL corresponding to the resistance switching element in the trench TR1, the resistance switching element can have a three-dimensional shape, and the manufacturing method of the resistance switching element and the signal line structure SL can be integrated with the manufacturing process of other conductive lines, thereby achieving the effect of simplifying the overall manufacturing process.

[0082] In some embodiments, the resistive memory device 100 may further include a bit line structure BL disposed in the dielectric layer DL and located below the diode via structure DV in the vertical direction D3, and the bit line structure BL is connected to the diode via structure DV. In some embodiments, the dielectric layer DL may include a plurality of dielectric material layers stacked in the vertical direction D3. For example, the dielectric layer DL may include a first layer 10 and a second layer 14 disposed on the first layer 10, the bit line structure BL may be disposed in the first layer 10 of the dielectric layer DL, and the diode via structure DV and the trench TR1 may be disposed in the second layer 14 of the dielectric layer DL, but the present invention is not limited thereto. In addition, the first layer 10 and the second layer 14 may be single-layer or multi-layer dielectric materials, such as silicon oxide, silicon nitride, nitrogen doped carbide (NDC), nitride silicon carbide, fluorosilicate glass (FSG), or other suitable dielectric materials (such as but not limited to low dielectric constant dielectric materials with a dielectric constant lower than 2.7). In some embodiments, the diode via structure DV may be directly connected to the bit line structure BL and the lower electrode (e.g., the first lower electrode BE1) of the corresponding resistance switching element, and the signal line structure SL may be directly connected to the upper electrode (e.g., the first upper electrode TE1) of the corresponding resistance switching element. In some embodiments, the first layer 10 of the dielectric layer DL may be disposed on a substrate (not shown), and the substrate may include a semiconductor substrate such as a silicon substrate, a silicon germanium semiconductor substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable materials. In addition, before forming the first layer 10, an element (e.g., a transistor) or / and a circuit (not shown) may be formed on the above-mentioned substrate, and the bit line structure BL may be electrically connected downward to the element or / and the circuit on the substrate, but is not limited thereto. In some embodiments, the manufacturing method of the resistive memory device 100 may be integrated with the back end of line (BEOL) manufacturing process in the semiconductor manufacturing process, thereby achieving the effect of simplifying the manufacturing process, but is not limited thereto.

[0083] In some embodiments, the resistive memory device 100 may include a plurality of bit line structures BL, a plurality of diode via structures DV, a plurality of trenches TR1, and a plurality of resistance switching elements RS. The first resistance switching element RS1 mentioned above may be regarded as one of the plurality of resistance switching elements RS, so each resistance switching element RS may include a lower electrode BE, an upper electrode TE disposed on the lower electrode BE, and a variable resistance layer VR disposed between the lower electrode BE and the upper electrode TE. Each trench TR1 may extend along a first horizontal direction D1, and a plurality of trenches TR1 may be repeatedly arranged in a second horizontal direction D2, and the second horizontal direction D2 may be substantially orthogonal to the first horizontal direction D1, but is not limited thereto. A plurality of resistance switching elements RS may be disposed in each trench TR1, for example, another resistance switching element RS disposed in the same trench TR1 as the first resistance switching element RS1 mentioned above may be regarded as a second resistance switching element RS2. In other words, the resistive memory device 100 may further include a second resistance switching element RS2 disposed in the trench TR1, and the second resistance switching element RS2 may include a second lower electrode BE2, a second upper electrode TE2, and a second variable resistance layer VR2. The second upper electrode TE2 is disposed on the second lower electrode BE2, the second variable resistance layer VR2 is disposed between the second lower electrode BE2 and the second upper electrode TE2, another portion of the signal line structure SL can be disposed on the second resistance switching element RS2, and the signal line structure SL can contact the second upper electrode TE2 to form an electrical connection.

[0084] In some embodiments, each bit line structure BL may extend substantially along the second horizontal direction D2, and a plurality of bit line structures BL may be repeatedly arranged in the first horizontal direction D1. The bottom electrode BE of each resistance switching element RS may be connected to the corresponding bit line structure BL through a diode via structure DV, the bottom electrode BE of the resistance switching element RS disposed in the same trench TR1 may be respectively connected to the corresponding bit line structure BL through different diode via structures DV, and one bit line structure BL may be connected to the bottom electrode BE of the resistance switching element RS disposed in different trenches TR1 through different diode via structures DV. In some embodiments, each diode via structure DV may include a p-type semiconductor layer and an n-type semiconductor layer (not shown) stacked in the vertical direction D3, thereby forming a diode structure between the corresponding bottom electrode BE and the bit line structure BL, but the invention is not limited thereto. In some embodiments, each diode via structure DV may consist of the stacked p-type semiconductor layer and n-type semiconductor layer, but the invention is not limited thereto. In some embodiments, each diode via structure DV may also include other suitable structures having diode characteristics. In addition, the p-type semiconductor layer may include a p-type silicon semiconductor layer, a p-type copper oxide (CuO) semiconductor layer or other suitable p-type semiconductor materials, and the n-type semiconductor layer may include an n-type silicon semiconductor layer, an n-type indium zinc oxide (InZnO) semiconductor layer or other suitable n-type semiconductor materials. The arrangement of the diode via structure DV can reduce the signal interference between adjacent bit line structures BL, and prevent the resistance state of the non-specified resistance switching element RS from being affected when other resistance switching elements RS are operating, thereby facilitating the operation of the resistive memory device 100.

[0085] In some embodiments, the horizontal direction (for example, the first horizontal direction D1 and the second horizontal direction D2) may be substantially orthogonal to the vertical direction D3, the vertical direction D3 may be regarded as the thickness direction of the dielectric layer DL, the first layer 10 of the dielectric layer DL may have a relative upper surface 10TS and a bottom surface 10BS in the vertical direction D3, and the second layer 14 may be disposed on one side of the upper surface 10TS of the first layer 10. The distance between a relatively high position or / and component in the vertical direction D3 and the bottom surface 10BS of the first layer 10 in the vertical direction D3 described herein may be greater than the distance between a relatively low position or / and component in the vertical direction D3 and the bottom surface 10BS of the first layer 10 in the vertical direction D3, the lower part or bottom of each component may be closer to the bottom surface 10BS of the first layer 10 in the vertical direction D3 than the upper part or top of the component, another component above a certain component may be considered to be relatively far away from the bottom surface 10BS of the first layer 10 in the vertical direction D3, and another component below a certain component may be considered to be relatively close to the bottom surface 10BS of the first layer 10 in the vertical direction D3. It is worth noting that the upper surface of a certain component described herein may include the topmost surface of the component in the vertical direction D3, and the bottom surface of a certain component may include the bottommost surface of the component in the vertical direction D3, but the present invention is not limited thereto. Furthermore, the situation in which a specific component is disposed between two other objects in a certain direction described herein may include but is not limited to a situation in which the component is sandwiched between the two objects in this direction.

[0086] In some embodiments, in a cross-sectional view (eg, Figure 1 part of or Fig.15 ), the upper electrode TE (e.g., the first upper electrode TE1) of each resistance switching element RS may have a U-shaped structure surrounding the corresponding signal line structure SL in the second horizontal direction D2, the variable resistance layer VR (e.g., the first variable resistance layer VR1) of each resistance switching element RS may have a U-shaped structure surrounding the corresponding signal line structure SL and the upper electrode TE (e.g., the first upper electrode TE1) in the second horizontal direction D2, and the lower electrode BE (e.g., the first lower electrode BE1) of each resistance switching element RS may have a U-shaped structure surrounding the corresponding signal line structure SL, the upper electrode TE (e.g., the first upper electrode TE1) and the variable resistance layer VR (e.g., the first variable resistance layer VR1) in the second horizontal direction D2. A portion of each resistance switching element RS (e.g., the first resistance switching element RS1) may be sandwiched between the signal line structure SL and the dielectric layer DL in the second horizontal direction D2, and another portion of each resistance switching element RS may be sandwiched between the signal line structure SL and the dielectric layer DL in the first horizontal direction D1 (e.g., Fig.18In other words, each resistance switching element RS can be regarded as a 3D resistance switching element, and the variable resistance layer VR can be sandwiched between the upper electrode TE and the lower electrode BE in the vertical direction D3 and the horizontal direction (e.g., the first horizontal direction D1 and the second horizontal direction D2), thereby increasing the area where the variable resistance layer VR is sandwiched between the upper electrode TE and the lower electrode BE without increasing the area occupied by the resistance switching element RS in the vertical direction D3, which has a positive effect on the operating characteristics and / or the setting density of the resistance switching element RS. In addition, as Figure 1 and Fig.18 As shown, in each resistance switching element RS (for example, the first resistance switching element RS1), the upper surface 26TS of the upper electrode TE (for example, the first upper electrode TE1), the upper surface 24TS of the variable resistance layer VR (for example, the first variable resistance layer VR1), and the upper surface 22TS of the lower electrode BE (for example, the first lower electrode BE1) may be substantially coplanar, the upper surface 14TS of the dielectric layer DL and the upper surface 22TS of the lower electrode BE (for example, the first lower electrode BE1) may be substantially coplanar, and the upper surface of the signal line structure SL (for example, the upper surface 42TS or / and the upper surface 44TS) and the upper surface 26TS of the upper electrode TE (for example, the first upper electrode TE1) may be substantially coplanar, but is not limited to this.

[0087] like Figure 1 and Fig.18As shown, in some embodiments, the first bottom electrode BE1 of the first resistance switching element RS1 and the second bottom electrode BE2 of the second resistance switching element RS2 can be regarded as different parts of a first conductive layer 22 disposed in the trench TR1 and separated from each other and not directly connected, the first variable resistance layer VR1 and the second variable resistance layer VR2 can be regarded as different parts of a variable resistance material 24 disposed in the trench TR1 and directly connected to each other, and the first top electrode TE1 and the second top electrode TE2 can be regarded as different parts of a second conductive layer 26 disposed in the trench TR1 and directly connected to each other, but the present invention is not limited thereto. The first conductive layer 22 and the second conductive layer 26 can respectively include a single layer or multiple layers of conductive material, such as platinum, tungsten, silver, copper, titanium, tantalum, iridium, alloys of the above materials, conductive nitrides of the above materials, or other suitable conductive materials, and the variable resistance material 24 can include metal oxides such as transition metal oxides, perovskite oxides, or other suitable variable resistance materials. In some embodiments, the variable resistance material 24 or / and a portion of the second conductive layer 26 may be sandwiched between the first bottom electrode BE1 and the second bottom electrode BE2 in the first horizontal direction D1, but the present invention is not limited thereto. In some embodiments, the signal line structure SL may include a barrier layer 42 and a metal layer 44 disposed on the barrier layer 42, the barrier layer 42 may be sandwiched between the metal layer 44 and the second conductive layer 26, and the thickness of the metal layer 44 may be greater than the thickness of the barrier layer 42, the second conductive layer 26, the variable resistance material 24, and the first conductive layer 22, respectively. The barrier layer 42 may include titanium nitride, tantalum nitride, or other suitable conductive barrier materials, and the metal layer 44 may include a metal conductive material with relatively low resistivity, such as copper, aluminum, tungsten, etc., but the present invention is not limited thereto.

[0088] like Figure 1 and Fig.18As shown, in some embodiments, the resistive memory device 100 may further include a dielectric layer 46, a plurality of via structures V2, and a plurality of conductive lines M3. The dielectric layer 46 may be disposed on the dielectric layer DL, the resistance switching element RS, and the signal line structure SL, and the dielectric layer 46 may include a single layer or multiple layers of dielectric material, such as silicon oxide, silicon nitride, nitrogen-doped carbide, silicon carbide nitride, fluorosilicone glass, or other suitable dielectric materials (such as but not limited to low dielectric constant dielectric materials). The via structure V2 and the conductive line M3 may be disposed in the dielectric layer 46, and the conductive line M3 may be disposed on the via structure V2. In some embodiments, each conductive line M3 may extend substantially along the second horizontal direction D2, and a plurality of conductive lines M3 may be repeatedly arranged in the first horizontal direction D1. The via structure V2 may include a via conductor and contact the corresponding signal line structure SL and the conductive line M3 to form an electrical connection, and the conductive line M3 may be electrically connected to the upper electrode TE of the corresponding resistance switching element RS through the via structure V2 and the signal line structure SL. In some embodiments, the via structure V2, the conductive line M3, and the bit line structure BL may include a barrier layer and a low resistance material disposed on the barrier layer, respectively. The low resistance material may include a conductive material with a relatively low resistivity such as copper, aluminum, tungsten, etc., and the barrier layer may include titanium nitride, tantalum nitride, or other suitable conductive barrier materials, but not limited thereto. The conductive line M3 and the bit line structure BL are electrically connected to the upper electrode TE and the lower electrode BE of the resistance switching element RS, respectively. Appropriate voltages may be applied to the upper electrode TE and the lower electrode BE, respectively, to change the resistance value of the resistance switching element RS, so that the resistance switching element RS can be switched between a high resistance state (HRS) and a low resistance state (LRS), thereby realizing operation modes of the memory device such as storing data, reading data, and resetting.

[0089] See also Figure 1 as well as Figures 2 to 18 . Figures 2 to 18 FIG. 1 is a schematic diagram of a method for manufacturing a resistive memory device according to an embodiment of the present invention, wherein Figure 2 A top view diagram is shown. Figure 3 For along Figure 2 The cross-sectional view shown by the A1-A1' section line in FIG. Figure 4 For along Figure 2 The cross-sectional view shown by the B1-B1' section line in FIG. Figure 5 Draws Figure 3 The following diagram shows the situation: Figure 6 Draws Figure 4 The following diagram shows the situation: Figure 7 Draws Figure 5 The following diagram shows the situation: Figure 8 Draws Figure 6 The following diagram shows the situation: Fig. 9 Draws Figure 7 The following diagram shows the situation: Fig.10 Draws Figure 8 The following diagram shows the situation: Fig.11 Draws Fig. 9 The following diagram shows the situation: Fig.12 Draws Fig.10 The following diagram shows the situation: Fig.13 Draws Fig.11 The following diagram shows the situation: Fig.14 Draws Fig.12 The following diagram shows the situation: Fig.15 Draws Fig.13 The following diagram shows the situation: Fig.16 Draws Fig.14 The following diagram shows the situation: Fig.17 For the corresponding Fig.15 and Fig.16 A top view of Fig.18 Draws Fig.16 In some embodiments, Fig.15 Can be considered as Fig.17 The cross-sectional view shown by the A2-A2' section line in FIG. Fig.16 Can be considered as Fig.17 The cross-sectional view shown by the B2-B2' section line in FIG. Figure 1 can be considered as corresponding Fig.18 The present invention is a three-dimensional schematic diagram of the situation, but is not limited to this. Figure 1 and Fig.18 As shown, the manufacturing method of the resistive memory device 100 of the present embodiment may include the following steps. A diode via structure DV is formed in the dielectric layer DL, and a first trench (e.g., trench TR1) is formed in the dielectric layer DL, and the diode via structure DV is located below the trench TR1. A first resistance switching element RS1 is formed in the trench TR1, and the first resistance switching element RS1 includes a first lower electrode BE1, a first upper electrode TE1, and a first variable resistance layer VR1. The diode via structure DV is connected to the first lower electrode BE1, the first upper electrode TE1 is disposed on the first lower electrode BE1, and the first variable resistance layer VR1 is disposed between the first lower electrode BE1 and the first upper electrode TE1. A signal line structure SL is formed in the trench TR1, a portion of the signal line structure SL is formed on the first resistance switching element RS1, and the signal line structure SL is electrically connected to the first upper electrode TE1.

[0090] Further explanation, the preparation method of the present invention may include but is not limited to the following steps. Figures 2 to 4As shown, in some embodiments, after the bit line structure BL and the diode via structure DV are formed, a trench TR1 may be formed in the dielectric layer DL, and the trench TR1 exposes at least a portion of the diode via structure DV. In addition, in some embodiments, the manufacturing method may further include forming a conductive wire M1 and a via structure V1, the conductive wire M1 and the via structure V1 may be located in the dielectric layer DL, the conductive wire M1 may be located below the via structure V1 in the vertical direction D3, and the conductive wire M1 may be connected to the via structure V1. In some embodiments, the conductive wire M1 and the bit line structure BL may be formed together by the same manufacturing process and have the same material composition (for example, the conductive material 12), the via structure V1 and the openings corresponding to the diode via structure DV may be formed together by the same manufacturing process, but the material composition of the via structure V1 is different from the material composition of the diode via structure DV, for example, the material composition of the via structure V1 may be the same as that of the above-mentioned Figure 1 The material composition of the through-hole structure V3 in the conductive layer DL is the same or similar, but not limited thereto. In addition, in some embodiments, after forming the conductive layer M1 and the through-hole structure V1, a second trench (e.g., trench TR2) may be formed in the dielectric layer DL, and the trench TR2 may expose at least a portion of the through-hole structure V1. In some embodiments, the trench TR2 may extend substantially along the first horizontal direction D1, and the trench TR1 and the trench TR2 may be formed together by the same manufacturing process, but not limited thereto. In addition, when a plurality of resistance switching elements are subsequently formed in the trench TR1, the trench TR1 may correspond to a plurality of diode through-hole structures DV, and the trench TR1 may expose at least a portion of each diode through-hole structure DV.

[0091] Then, if Figure 5 and Figure 6 As shown, a first conductive layer 22 may be formed on the dielectric layer DL. The first conductive layer 22 may be conformally formed on the surface of the dielectric layer DL and in the trenches TR1 and TR2. Therefore, the first conductive layer 22 may be partially formed in the trenches TR1 and TR2 and partially formed outside the trenches TR1 and TR2. Figure 7 and Figure 8As shown, a first patterning process 91 may be performed on the first conductive layer 22, the first conductive layer 22 in the trench TR2 may be removed by the first patterning process 91, a portion of the first conductive layer 22 may be patterned by the first patterning process 91 to become a first lower electrode BE1, and another portion of the first conductive layer 22 may be patterned by the first patterning process 91 to become a second lower electrode BE2. A portion of the first conductive layer 22 in the trench TR1 may be removed by the first patterning process 91 to separate the first lower electrode BE1 from the second lower electrode BE2. In some embodiments, a patterned photoresist layer 32 may be formed on the first conductive layer 22, and the first conductive layer 22 may be etched using the patterned photoresist layer 32 as an etching mask to achieve a patterning effect, and the patterned photoresist layer 32 may be removed after the first patterning process 91, but is not limited thereto. Figures 7 to 10 As shown, after the first patterning process 91, a variable resistance material 24 may be formed, and a second conductive layer 26 may be formed on the variable resistance material 24. The variable resistance material 24 may be conformally formed on the first lower electrode BE1, the second lower electrode BE2, and the dielectric layer DL, the second conductive layer 26 may be conformally formed on the variable resistance material 24, the variable resistance material 24 may be partially formed in the trenches TR1 and TR2 and partially formed outside the trenches TR1 and TR2, and the second conductive layer 26 may be partially formed in the trenches TR1 and TR2 and partially formed outside the trenches TR1 and TR2. It is worth noting that the trench TR1 is not filled with the first conductive layer 22, the variable resistance material 24, and the second conductive layer 26, so as to reserve space for the subsequent formation of a signal line structure.

[0092] Then, if Fig.11 and Fig.12As shown, a second patterning process 92 may be performed, a portion of the second conductive layer 26 may be patterned by the second patterning process 92 to become the first upper electrode TE1, another portion of the second conductive layer 26 may be patterned by the second patterning process 92 to become the second upper electrode TE2, a portion of the variable resistance material 24 may be patterned by the second patterning process 92 to become the first variable resistance layer VR1, and another portion of the variable resistance material 24 may be patterned by the second patterning process 92 to become the second variable resistance layer VR2. The first lower electrode BE1, the first variable resistance layer VR1, and the first upper electrode TE1 may constitute the first resistance switching element RS1, and the second lower electrode BE2, the second variable resistance layer VR2, and the second upper electrode TE2 may constitute the second resistance switching element RS2. The second upper electrode TE2 may be directly connected to the first upper electrode TE1, and the second variable resistance layer VR2 may be directly connected to the first variable resistance layer VR1. In some embodiments, the second patterning process 92 may include forming a patterned photoresist layer 34 on the second conductive layer 26, and using the patterned photoresist layer 34 as an etching mask to etch the second conductive layer 26 and the variable resistance material 24 to achieve a patterning effect, and the patterned photoresist layer 34 may be removed after the second patterning process 92, but is not limited thereto. In addition, in some embodiments, the variable resistance material 24 and the second conductive layer 26 formed in the trench TR2 may be removed by the second patterning process 92, so after the second patterning process 92, there is no residual second conductive layer 26, variable resistance material 24, and first conductive layer 22 in the trench TR2. It is worth noting that the manufacturing method of the resistance switching element RS of this embodiment may include but is not limited to the above Figures 3 to 12 The steps shown are as follows, and the resistance switching element RS may be formed by other suitable methods according to design requirements.

[0093] like Fig.11 , Fig.12 , Fig.15 as well as Fig.16 As shown, after the second patterning process 92, a signal line structure SL may be formed in the trench TR1, and a conductive line M2 may be formed in the trench TR2. In some embodiments, the conductive line M2 and the signal line structure SL may be formed by the same process, so the material composition of the conductive line M2 may be the same as the material composition of the signal line structure SL, but this is not limited thereto. Figures 15 to 17As shown, a portion of the signal line structure SL may be formed on the first resistance switching element RS1, another portion of the signal line structure SL may be formed on the second resistance switching element RS2, and the signal line structure SL may be electrically connected to the first upper electrode TE1 and the second upper electrode TE2. In some embodiments, the trench TR1 and the trench TR2 may have substantially equal depths, and since the material layer in the trench TR2 has been removed before forming the conductive wire M2, the thickness TK2 of the conductive wire M2 in the vertical direction D3 may be greater than the thickness TK1 of the signal line structure SL formed on the resistance switching element RS (e.g., the first resistance switching element RS1 or the second resistance switching element RS2) in the vertical direction D3.

[0094] In some embodiments, the method of forming the conductive line M2 and the signal line structure SL may include but is not limited to the following steps. Figures 11 to 14 As shown, after the second patterning process 92, a barrier layer 42 may be formed on the dielectric layer DL and the resistance switching element RS, and a metal layer 44 may be formed on the barrier layer 42. The barrier layer 42 may be partially formed in the trenches TR1 and TR2 and partially formed outside the trenches TR1 and TR2, and the metal layer 44 may also be partially formed in the trenches TR1 and TR2 and partially formed outside the trenches TR1 and TR2. Then, as shown in FIG. Fig.15 and Fig.16 As shown, a planarization process 93 may be performed to remove the barrier layer 42 and the metal layer 44 outside the trenches TR1 and TR2 and form the signal line structure SL and the conductive wire M2 in the trenches TR1 and TR2, respectively. In addition, the first conductive layer 22 (e.g., the lower electrode BE outside the trenches TR1 and TR2), the variable resistance material 24 (e.g., the variable resistance layer VR outside the trenches TR1 and TR2), and the second conductive layer 26 (e.g., the upper electrode TE outside the trenches TR1 and TR2) outside the trenches TR1 and TR2 may be removed together by the planarization process 93. Therefore, the signal line structure SL may be regarded as the barrier layer 42 and the metal layer 44 remaining in the trenches TR1 after the planarization process 93, and the conductive wire M2 may be regarded as the barrier layer 42 and the metal layer 44 remaining in the trenches TR2 after the planarization process 93. In some embodiments, the planarization process 93 may include a chemical mechanical polishing (CMP) process or other suitable planarization methods, and after the planarization process 93, the upper surface 14TS of the dielectric layer DL, the upper surface 22TS of the lower electrode BE, the upper surface 24TS of the variable resistance layer VR, the upper surface 26TS of the upper electrode TE, the upper surface 42TS of the barrier layer 42, and the upper surface 44TS of the metal layer 44 may be substantially coplanar, but the present invention is not limited thereto. Fig.16 and Fig.18 As shown, after the planarization process 93, the dielectric layer 46, the through hole structure V2 and the conductive line M3 can be formed, and then the following can be formed: Figure 1 In some embodiments, the resistive memory device 100 is shown in FIG. Fig.15 The conductive line M1, the through hole structure V1, and the conductive line M2 in the semiconductor manufacturing process can be regarded as a part of the interconnect structure formed in the back-end of line (BEOL) manufacturing process in the semiconductor manufacturing process. Fig.18 and Figure 1 The via structure V2 and the conductive line M3 in the embodiment can also be regarded as another part of the interconnection structure. Therefore, the manufacturing method of the resistive memory device 100 can be integrated with the manufacturing method of the interconnection structure, thereby achieving the effect of simplifying the manufacturing process, but the present invention is not limited thereto.

[0095] In summary, in the resistive memory device and the manufacturing method thereof of the present invention, a resistance switching element and a corresponding signal line structure can be formed in a groove, thereby forming a three-dimensional resistance switching element, thereby improving the operating characteristics of the resistance switching element or / and relatively increasing the arrangement density of the resistance switching element. In addition, the manufacturing method of the resistance switching element and the signal line structure can be integrated with the manufacturing process of other conductive lines or / and interconnection structures, thereby achieving the effect of simplifying the overall manufacturing process.

[0096] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A resistive memory device, include: Dielectric layer; a trench disposed in the dielectric layer, wherein the trench extends along a first horizontal direction; A first resistance switching element is disposed in the trench, wherein the first resistance switching element comprises: a first lower electrode; A first upper electrode is disposed on the first lower electrode; and A first variable resistance layer is disposed between the first lower electrode and the first upper electrode; a diode via structure disposed in the dielectric layer and below the trench, wherein the diode via structure is connected to the first lower electrode; and A signal line structure is arranged in the groove, wherein a portion of the signal line structure is arranged on the first resistance switching element, and the signal line structure is electrically connected to the first upper electrode. 2 . The resistive memory device as claimed in claim 1 , wherein in a cross-sectional view of the resistive memory device, the first upper electrode has a U-shaped structure surrounding the signal line structure in the second horizontal direction. 3 . The resistive memory device as claimed in claim 1 , wherein in a cross-sectional view of the resistive memory device, the first variable resistance layer has a U-shaped structure surrounding the signal line structure and the first upper electrode in a second horizontal direction. 4 . The resistive memory device as claimed in claim 1 , wherein in a cross-sectional view of the resistive memory device, the first lower electrode has a U-shaped structure surrounding the signal line structure, the first upper electrode and the first variable resistance layer in a second horizontal direction. 5 . The resistive memory device of claim 1 , wherein a portion of the first resistance-switching element is sandwiched between the signal line structure and the dielectric layer in a second horizontal direction. 6 . The resistive memory device of claim 1 , wherein an upper surface of the first upper electrode, an upper surface of the first variable resistance layer, and an upper surface of the first lower electrode are coplanar. 7 . The resistive memory device of claim 1 , wherein an upper surface of the dielectric layer is coplanar with an upper surface of the first lower electrode. 8 . The resistive memory device as claimed in claim 1 , wherein an upper surface of the signal line structure is coplanar with an upper surface of the first upper electrode.

9. The resistive memory device according to claim 1, further comprising: include: A second resistance switching element is disposed in the trench, wherein the second resistance switching element comprises: a second lower electrode; A second upper electrode is disposed on the second lower electrode; and The second variable resistance layer is arranged between the second lower electrode and the second upper electrode, wherein another part of the signal line structure is arranged on the second resistance switching element, and the signal line structure is electrically connected to the second upper electrode.

10. The resistive memory device according to claim 1, further comprising: include: The bit line structure is disposed in the dielectric layer and below the diode through hole structure, wherein the bit line structure is connected to the diode through hole structure.

11. A method for manufacturing a resistive memory device, include: forming a diode via structure in the dielectric layer; forming a first trench in the dielectric layer, wherein the diode via structure is located below the first trench; A first resistance switching element is formed in the first trench, wherein the first resistance switching element comprises: a first lower electrode, wherein the diode through-hole structure is connected to the first lower electrode; A first upper electrode is disposed on the first lower electrode; and A first variable resistance layer is arranged between the first lower electrode and the first upper electrode; and a signal line structure is formed in the first groove, wherein a part of the signal line structure is formed on the first resistance switching element, and the signal line structure is electrically connected to the first upper electrode.

12. The method for manufacturing a resistive memory device according to claim 11, further comprising: include: forming a second trench in the dielectric layer; as well as A conductive line is formed in the second groove, wherein the conductive line and the signal line structure are formed by the same manufacturing process, and the thickness of the conductive line is greater than the thickness of the signal line structure formed on the first resistance switching element. 13 . The method for manufacturing a resistive memory device as claimed in claim 12 , wherein a material composition of the conductive line is the same as a material composition of the signal line structure.

14. The method for manufacturing a resistive memory device as claimed in claim 12, wherein a method for forming the first resistance switching element is include: forming a first conductive layer on the dielectric layer, wherein the first conductive layer is partially formed in the first trench and the second trench and partially formed outside the first trench and the second trench; Performing a first patterning process on the first conductive layer, wherein the first conductive layer in the second trench is removed by the first patterning process, and a portion of the first conductive layer is patterned by the first patterning process to become the first lower electrode; After the first patterning process, a variable resistance material is formed, wherein the variable resistance material is partially formed in the first trench and the second trench and partially formed outside the first trench and the second trench; forming a second conductive layer on the variable resistance material, wherein the second conductive layer is partially formed in the first trench and the second trench and partially formed outside the first trench and the second trench; as well as A second patterning process is performed, wherein a portion of the second conductive layer is patterned by the second patterning process to become the first upper electrode, and a portion of the variable resistance material is patterned by the second patterning process to become the first variable resistance layer. 15 . The method for manufacturing a resistive memory device as claimed in claim 14 , wherein the variable resistance material and the second conductive layer formed in the second trench are removed by the second patterning process.

16. A method for manufacturing a resistive memory device as described in claim 14, wherein another portion of the second conductive layer is patterned by the second patterning process to become a second upper electrode of a second resistance switching element, another portion of the variable resistance material is patterned by the second patterning process to become a second variable resistance layer of the second resistance switching element, the second upper electrode is connected to the first upper electrode, and the second variable resistance layer is connected to the first variable resistance layer. 17 . The method for manufacturing a resistive memory device as claimed in claim 16 , wherein another portion of the first conductive layer is patterned by the first patterning process to become a second bottom electrode of the second resistance switching element, and the second bottom electrode is separated from the first bottom electrode. 18 . The method for manufacturing a resistive memory device as claimed in claim 16 , wherein another portion of the signal line structure is formed on the second resistance switching element, and the signal line structure is electrically connected to the second upper electrode.

19. The method for manufacturing a resistive memory device as claimed in claim 14, wherein a method for forming the conductive line and the signal line structure is include: After the second patterning process, forming a barrier layer on the dielectric layer, wherein the barrier layer is partially formed in the first trench and the second trench and partially formed outside the first trench and the second trench; forming a metal layer on the barrier layer, wherein the metal layer is partially formed in the first trench and the second trench and partially formed outside the first trench and the second trench; as well as A planarization process is performed to remove the barrier layer and the metal layer outside the first trench and the second trench. 20 . The method for manufacturing a resistive memory device as claimed in claim 19 , wherein the first conductive layer, the variable resistance material and the second conductive layer outside the first trench and the second trench are removed by the planarization process.

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