Semiconductor device processing method and semiconductor device using instantaneous single event upset self-recovery technology

Abstract

The present invention discloses a semiconductor device processing method and semiconductor device utilizing transient single-particle upset self-recovery technology. The method comprises placing carbon nanotubes and a dispersant in a predetermined ratio into toluene, dispersing the mixture for a predetermined time using a disperser to obtain a dispersed solution; centrifuging the dispersed solution at least twice to obtain a carbon nanotube solution; diluting the carbon nanotube solution with toluene, placing a substrate into the diluted carbon nanotube solution, immersing the substrate, and baking the substrate to obtain a carbon nanotube film; constructing a carbon nanotube field-effect transistor using electron beam lithography; and sequentially subjecting the carbon nanotube field-effect transistor to single-particle irradiation and pulsed laser irradiation to form a charge spot. The present invention improves the device's radiation resistance and can meet the requirements for stable device performance in complex radiation environments.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor devices and discloses a semiconductor device processing method and a semiconductor device using an instantaneous single-particle upset self-recovery technology. Background Art

[0002] In the field of electronic devices, ensuring device reliability is always a critical issue. With humanity's increasing demand for outer space exploration, from launching spacecraft to building space stations, to landing on the moon and even Mars, radiation-hardened integrated circuits (ICs), as special-purpose integrated circuits, are receiving increasing attention for their ability to withstand high-energy solar particles and cosmic rays.

[0003] In the field of radiation resistance, total dose effect, displacement damage, and single event effects (SEEs) are three major radiation effects. Each affects materials and devices in different ways. These effects need to be considered when studying and designing radiation resistance. Total dose effect is a long-term damage that reduces carrier mobility and on-current, while increasing leakage current and threshold voltage drift. Displacement damage is a physical damage that primarily causes atomic dislocation within the device, creating deep-level defects. This increases the recombination rate and reduces carrier lifetime, leading to device damage or even failure. Single event effects are transient effects. A single high-energy particle generates a large amount of ionized charge in the sensitive region of a semiconductor device, causing a transient current flow and device failure. Specifically, a single particle entering a sensitive region of a semiconductor device causes its logic state to flip from "0" to "1" or vice versa, resulting in a single event upset. Although the damage caused is not permanent, it can seriously impact system safety, especially in space stations or nuclear power plants, where the incidence of SEEs is significantly increased, making it a significant issue that cannot be ignored. A single event upset (SEU) is the most common form of single event effect, in which a high-energy particle passing through a memory cell or logic circuit causes a data bit to flip. This flip can lead to calculation errors, instruction errors, or data loss.

[0004] Compared to total dose effects and displacement damage, the impact of single-event upsets (SEUs) is more direct and instantaneous. SEUs can cause transient system errors, and frequent occurrences can degrade system stability. Therefore, SEU mitigation measures, such as redundancy and error detection and correction (EDAC) technology, must be considered in radiation-hardened designs. In summary, SEUs, due to their random nature, sensitivity to memory, and the transient errors they can cause, constitute a crucial component of device radiation hardening research. Studying and mitigating SEUs is crucial to ensuring system reliability and stability in radiation environments.

[0005] Currently, a variety of hardening methods are being employed to combat single-event effects (SEEs), primarily categorized as hardware and software. The most common hardware hardening approach is hardware redundancy, which adds additional components to mask the effects of a fault. The most widely used is triple-modular redundancy (TMR). Its advantage lies in its speed. By providing three redundant components for each computing unit and employing a majority voting mechanism, it effectively mitigates errors caused by SEEs, improving system stability to a certain extent. However, the addition of additional components increases system mass, area, and power consumption, necessitating improvements to TMR. Similarly, common software hardening techniques rely on duplicate calculations, increasing the workload of the system at the software level. While this improves system stability, it also increases the complexity of the calculations, impacting system performance and complicating system design. Therefore, an analysis of existing hardening technologies suggests the need for new hardening techniques that can ensure system reliability while avoiding hardware complexity and the need for large amounts of data to be calculated during runtime. Summary of the Invention

[0006] The purpose of the invention is to provide a semiconductor device processing method and a semiconductor device using instantaneous single event upset self-recovery technology to solve the above-mentioned problems existing in the prior art.

[0007] A technical solution, a method for processing a semiconductor device using instantaneous single event upset self-recovery technology, includes the following steps:

[0008] S1. Adding carbon nanotubes and a dispersant in a predetermined ratio into toluene, and dispersing them for a predetermined time at a power P using a disperser to obtain a dispersed solution;

[0009] S2, centrifuging the dispersed solution at least twice under a centrifugal force G to obtain a carbon nanotube solution;

[0010] S3, diluting the carbon nanotube solution with toluene by at least ten times, placing a substrate in the diluted carbon nanotube solution for soaking time t1, rinsing the soaked substrate with toluene for time t2, purging the rinsed substrate with nitrogen, and baking it in air at temperature C for time t3 to obtain a carbon nanotube film;

[0011] S4. Based on a carbon nanotube film and a fast-frequency-response gate dielectric, a local bottom gate window is constructed using electron beam lithography. A diluted carbon nanotube solution is then deposited and etched to form a channel of a carbon nanotube field-effect transistor. An active channel region is constructed using electron beam lithography and etched to form an active channel of the carbon nanotube field-effect transistor. A top gate window is constructed in the active channel. Both ends of the active channel are patterned to form a source and a drain, thereby obtaining P-type contacts for the source and drain.

[0012] S5. Perform single particle irradiation and pulse laser irradiation on the carbon nanotube field effect transistor in sequence, use a microscope objective lens with a magnification of at least 100 times to focus the pulse laser beam, and form a charge spot on the carbon nanotube field effect transistor.

[0013] According to one aspect of the present application, step S2 is further:

[0014] S21, performing a first centrifugal operation on the dispersed solution under a centrifugal force G for a time of t to obtain a clear solution with a purity of at least 90%;

[0015] S22, centrifuging the supernatant for a second time under a centrifugal force G for a time of t' to obtain a carbon nanotube solution with a purity of at least 90%;

[0016] The centrifugal force G is 50000g, the first centrifugal operation time t is 0.5h, and the second centrifugal operation time t' is 2h.

[0017] According to one aspect of the present application, step S3 further includes:

[0018] The carbon nanotube film is annealed in a tube furnace at a temperature C1 with forming gas for at least 3 hours to remove polymers in the carbon nanotube film.

[0019] According to one aspect of the present application, the forming gas is a mixture of argon and hydrogen in a ratio of 5:1.

[0020] According to one aspect of the present application, the substrate is a silicon substrate or a silicon dioxide substrate.

[0021] According to one aspect of the present application, the purity of the nitrogen is not less than 99.999%, the carbon nanotubes are graphene, and the predetermined ratio is 1:1.

[0022] According to one aspect of the present application, step S4 is further:

[0023] Based on the carbon nanotube film and the fast frequency response gate dielectric, electron beam lithography is used for patterning to construct a local bottom gate window of the carbon nanotube field effect transistor. Palladium with a thickness of h1 is evaporated on the local bottom gate window by atomic layer deposition and hafnium oxide with a thickness of h2 is grown. A diluted carbon nanotube solution is deposited on the local bottom gate window with the hafnium oxide grown. The deposited carbon nanotube solution is etched for a time t4 using oxygen plasma to form a channel of the carbon nanotube field effect transistor. The channel is patterned using electron beam lithography to construct an active channel region. The active channel region is etched for a time t5 using oxygen plasma to form an active channel of the carbon nanotube field effect transistor.

[0024] The active channel is patterned using electron beam lithography to construct the top gate window of the carbon nanotube field-effect transistor. Hafnium oxide with a thickness of h3 is grown on the top gate window using atomic layer deposition, and palladium with a thickness of h4 is evaporated.

[0025] The two ends of the active channel are patterned by electron beam lithography to form the source and drain of the carbon nanotube field effect transistor, and titanium with a thickness of h5 and palladium with a thickness of h6 are evaporated to obtain P-type contacts of the source and drain.

[0026] According to one aspect of the present application, palladium thickness h1 is 20 nm, hafnium oxide thickness h2 is 10 nm, hafnium oxide thickness h3 is 10 nm, palladium thickness h4 is 20 nm, titanium thickness h5 is 0.3 nm, and palladium thickness h6 is 70 nm.

[0027] According to one aspect of the present application, it further includes:

[0028] S6. Use an oscilloscope to monitor the charge spot, record single event transient response data based on the monitoring results, and evaluate the single particle irradiation resistance of the carbon nanotube field effect transistor based on the response data.

[0029] A semiconductor device manufactured using the semiconductor device processing method using instantaneous single event upset self-recovery technology described in any of the above technical solutions comprises:

[0030] Carbon nanotube film, used as channel material;

[0031] The gate dielectric grown on the carbon nanotube film includes hafnium oxide.

[0032] Beneficial effect: The present invention proposes to use carbon nanotubes as channel materials and select high dielectric constant gate dielectrics such as HfO2 to reinforce semiconductor devices, so that they can use the single particle flip self-recovery ability to greatly improve the device's radiation resistance, improve the stability and consistency of the device itself, and can meet the requirements for stable device performance in complex radiation environments. At the same time, it also avoids the problems of hardware complexity and large amount of computation during operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Flowchart of the present invention.

[0034] Figure 2 This is a diagram of the SET results of a single device according to an embodiment of the present invention.

[0035] Figure 3 Charge collection curve of the device in an embodiment of the present invention.

[0036] Figure 4This is a SEUR result diagram of a single device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] like Figure 1 As shown, the present invention proposes a semiconductor device processing method using instantaneous single event upset self-recovery technology, comprising the following steps:

[0038] S1. Adding carbon nanotubes and a dispersant in a predetermined ratio into toluene, and dispersing them for a predetermined time at a power P using a disperser to obtain a dispersed solution;

[0039] S2, centrifuging the dispersed solution at least twice under a centrifugal force G to obtain a carbon nanotube solution;

[0040] S3, diluting the carbon nanotube solution with toluene by at least ten times, placing a substrate in the diluted carbon nanotube solution for soaking time t1, rinsing the soaked substrate with toluene for time t2, purging the rinsed substrate with nitrogen, and baking it in air at temperature C for time t3 to obtain a carbon nanotube film;

[0041] S4. Based on the carbon nanotube film and the fast frequency response gate dielectric, patterning is performed using electron beam lithography to construct a local bottom gate window of the carbon nanotube field effect transistor, palladium with a thickness of h1 is evaporated on the local bottom gate window using atomic layer deposition and hafnium oxide with a thickness of h2 is grown, a diluted carbon nanotube solution is deposited on the local bottom gate window with the hafnium oxide grown, the deposited carbon nanotube solution is etched using oxygen plasma for a time t4 to form a channel of the carbon nanotube field effect transistor, the channel is patterned using electron beam lithography to construct an active channel region, and the active channel region is etched using oxygen plasma for a time t5 to form an active channel of the carbon nanotube field effect transistor;

[0042] The active channel is patterned using electron beam lithography to construct the top gate window of the carbon nanotube field-effect transistor. Hafnium oxide with a thickness of h3 is grown on the top gate window using atomic layer deposition, and palladium with a thickness of h4 is evaporated.

[0043] The two ends of the active channel are patterned by electron beam lithography to form the source and drain of the carbon nanotube field effect transistor, and titanium with a thickness of h5 and palladium with a thickness of h6 are evaporated to obtain P-type contacts for the source and drain;

[0044] S5. sequentially performing single particle irradiation and pulse laser irradiation on the carbon nanotube field effect transistor, focusing the pulse laser beam using a microscope objective lens with a magnification of at least 100 times to form a charge spot on the carbon nanotube field effect transistor;

[0045] S6. Use an oscilloscope to monitor the charge spot, record single event transient response data based on the monitoring results, and evaluate the single particle irradiation resistance of the carbon nanotube field effect transistor based on the response data.

[0046] In this embodiment, carbon nanotubes are mixed with a dispersant, which can help the carbon nanotubes to be evenly dispersed in toluene, ensuring that the carbon nanotubes can be evenly deposited on the substrate in subsequent steps; the dispersed carbon nanotube solution is separated from the solution by centrifugation to obtain a high-purity carbon nanotube solution, which helps to obtain a high-quality film; the diluted carbon nanotube solution is deposited on the substrate, and then baked and annealed to remove excess polymer to ensure the quality of the carbon nanotube film; the film is patterned using electron beam lithography to construct a local bottom gate window, active channel and top gate window, which are key parts of the carbon nanotube field effect transistor; the carbon nanotube field effect transistor is subjected to single particle irradiation and pulsed laser irradiation to form a charge spot, which helps to evaluate the carbon nanotube field effect transistor's resistance to single particle irradiation. In this embodiment, carbon nanotubes are used as channel materials and a specific process is used to manufacture SRAM circuits, which have a single particle upset self-recovery effect and can well meet current needs. Because carbon nanotube FETs and integrated circuits have strong CC bonds, nanoscale cross-sections, and negligible parasitic effects in carbon nanotube channels, they are highly anticipated in the field of radiation resistance. At the same time, carbon nanotubes also have excellent low power consumption and low-temperature stability, so they can meet the needs of deep space exploration.

[0047] In one embodiment of the present application, a carbon nanotube film is prepared by obtaining carbon nanotubes (CNTs) prepared by an arc discharge method and synthesizing a dispersant (poly[9-(1-octylnonyl)-9H-carbazole]), referred to as PCz, using the Suzuki polycondensation method. 100 mg of CNTs and 100 mg of dispersant are added to 100 ml of toluene. The mixture is then dispersed using a Sonics VC700 at 300 W for 30 minutes to ensure that the CNTs are well dispersed in the solution. The dispersed solution is then centrifuged at 50,000 g for 0.5 hours to remove most of the metallic CNTs and insoluble matter. More than 90% of the supernatant is collected and centrifuged a second time at 50,000 g for 2 hours. Finally, more than 90% of the supernatant is collected and used to prepare a film using a dip coating method. The sorted CNT solution is diluted tenfold with toluene. The silicon / silicon dioxide (Si / SiO2) substrate was immersed in the diluted solution for 72 hours. The substrate was then removed from the solution, rinsed with toluene for 30 minutes, purged with 99.999% nitrogen (N2), and baked in air at 120°C for 30 minutes. Finally, to reduce the effect of the polymer on the radiation hardness of the carbon nanotubes, the film was annealed in a tube furnace at 600°C for 3 hours using a forming gas mixture of argon and hydrogen in a ratio of 5:1 to remove the polymer.

[0048] The local bottom gate of the carbon nanotube field-effect transistor (CNT FET) was fabricated by selecting a gate dielectric with high-k dielectric properties and fast frequency response, such as hafnium oxide. The local bottom gate window was patterned by electron beam lithography (EBL), followed by atomic layer deposition (ALD) using a standard rise-up process to evaporate 20 nm of palladium (Pd) and grow 10 nm of hafnium oxide (HfO2). Next, the CNT FET channel was defined by solution deposition and etched with oxygen plasma for 60 s. The active channel region was defined by electron beam lithography, followed by 60 s of oxygen plasma etching. The top gate window was patterned by electron beam lithography, followed by atomic layer deposition of 10 nm of hafnium oxide (HfO2) and evaporation of 20 nm of palladium using a standard rise-up process. Finally, the source and drain electrodes were patterned by electron beam lithography, followed by evaporation of 0.3 nm of titanium (Ti) and 70 nm of palladium (Pd).

[0049] The prepared device was subjected to single-particle irradiation and pulsed laser irradiation. An oscilloscope with an input impedance of 50Ω was used to display and record single-event transients (SETs). A 100x microscope objective was used to focus the laser beam, forming a charge spot approximately 2μm in size. The laser pulse had a wavelength of 1064nm, a normal pulse width of 150fs, and a repetition rate of 1kHz. During the single-event transient pulse laser test, the carbon nanotube field-effect transistor was fixed on an xyz stage with a resolution of 0.1μm.

[0050] To test the device's ability to withstand single-particle radiation, a pulsed laser was used. The pulsed laser emitted 1062nm laser light, which is larger than the bandgap width of the carbon nanotube. This produces a single-event charge effect, resulting in a peak current in the source-drain current, called a single-event transient (SET). This was compared with the peak current of a traditional silicon-based field-effect transistor (Si-FET). The results showed that the short tail of the peak current occurred in the carbon nanotube FET at 3ns, far lower than the 70ns of the Si-FET, demonstrating the carbon nanotube's low response to single-event transients. This means that the carbon nanotube FET can recover normal operation more quickly when hit by high-energy particles, demonstrating superior radiation resistance.

[0051] To address the current problem of single-event effect reinforcement, this embodiment discovers a novel single-event upset self-recovery effect in low-dimensional materials for reinforcement. The mechanisms of single-event occurrence can be categorized as channel material-induced and gate voltage-induced. Gate-voltage-induced single-event effects can self-recover under certain circumstances. This embodiment reduces the probability of single-event effects occurring directly in the channel material and instead utilizes gate voltage-induced effects, thereby leveraging this self-recovery effect for reinforcement and enhancing device stability.

[0052] Among single-event effects, single-event upsets (SEEs) are not uncommon in SRAM. Whether implemented with hardware or software hardening, they can impact system performance and even reduce the lifespan of the device itself. Therefore, the emergence of SEE self-recovery is a new type of hardening method that can overcome the redundant state caused by hardware or software hardening without increasing the complexity of system design and integration. Normally, in an SRAM circuit, when a SEE occurs in an inverter within a memory cell, feedback amplification occurs, causing SEEs to also occur in adjacent inverters, causing the entire memory cell to flip, resulting in a logic error.

[0053] In an SRAM made with carbon nanotubes as the channel material, after a single-particle upset occurs in an inverter, due to the particularity of its single-particle effect mechanism, discharge occurs during the current propagation to the second inverter, thus preventing the second inverter from flipping and the entire logic circuit from error. In other words, the single-particle upset self-recovery effect occurs.

[0054] The single-particle upset self-recovery effect occurs in two-dimensional materials. Its essence lies in the fact that the occurrence mechanism of the single-particle effect is different from that of silicon-based devices. Of the two mechanisms in two-dimensional materials, single-particle upset self-recovery will only occur when the gate voltage induces the single-particle effect. Therefore, in order to amplify this effect, the focus should be on increasing the gate voltage induction mechanism, reducing the thickness of the channel material and the thickness of the gate oxide layer, so that the single-particle upset self-recovery effect is more likely to occur.

[0055] A gate dielectric with high-k properties and fast frequency response was selected to fabricate a localized bottom-gate carbon nanotube field-effect transistor. During device fabrication, the device must ensure the occurrence of a single-event upset (SEE) self-recovery effect. The key focus is shifting the mechanism for SEE generation from channel-induced to gate-voltage-induced. Due to the inherent properties of carbon nanotubes, it is difficult for electron-hole pairs to be generated in the channel. Therefore, the thickness of the channel material is reduced to further reduce the probability of SEE generation. This ensures that SEE generation is gate-voltage-induced, thereby successfully triggering the SEE self-recovery effect and achieving the reinforcement goal.

[0056] Similarly, in the single-particle effect induced by gate voltage, in order to ensure the smooth occurrence of the single-particle upset self-recovery effect and achieve the effect of reinforcement, it is necessary to ensure better discharge of the gate capacitance, so that the thickness of the gate oxide layer can be reduced. Its discharge capacity can be enhanced by using gate dielectric materials with high-frequency response characteristics. The capacitor impedance formula is: Zc=1 / j2πfC, where j represents the imaginary unit, f represents the frequency, and C represents the capacitance; when the frequency is very high, its impedance is very low, and the discharge time is greatly shortened, so that it can discharge smoothly, the single-particle upset self-recovery effect occurs, and the purpose of reinforcement is achieved.

[0057] This application proposes the single-particle upset self-recovery effect for the first time, lowers the threshold of the self-recovery effect, and utilizes the single-particle upset self-recovery effect to strengthen the memory's ability to resist single particles.

[0058] According to another aspect of the present application, the carbon nanotubes are graphene, and an ultrathin two-dimensional material such as graphene is used as the channel material. Single-film growth is achieved using physical methods (vacuum evaporation, magnetron deposition) or chemical methods (liquid phase exfoliation, chemical vapor deposition), with the film grown directly on a Si / SiO2 substrate. A high-K gate dielectric, such as strontium titanate (SrTiO3), is used to increase the gate dielectric capacitance. When the charge of charged particles deposited on the gate dielectric is constant, the additional gate voltage offset generated is small. Based on the current characteristic curve generated by the gate voltage, the resulting current offset is small, reducing interference with the circuit.

[0059] The single-particle upset self-recovery effect is used to strengthen the device's radiation resistance. The effect of this embodiment comes from the fact that the gate dielectric with a fast frequency response under the ultra-thin channel can quickly self-recover after the single-particle effect occurs. In the case of selecting traditional channel materials, due to the large sensitive area of ​​traditional materials, a large number of electron-hole pairs will be generated when high-energy particles are incident. After the source and drain are absorbed, a large current will be generated, causing a single-particle effect. When ultra-thin carbon nanotubes are selected as channel materials, due to their relatively small sensitive area, very few electron-hole pairs will be generated. When high-energy particles enter the gate oxide layer, they will cause charge accumulation in the gate oxide layer, generate gate voltage, and thus cause a single-particle effect. The difference in the mechanism of generating the single-particle effect causes the SRAM circuit made of carbon nanotubes as the channel material to produce a single-particle upset self-recovery effect, thereby strengthening the circuit.

[0060] These high-energy particles not only affect the channel, but also the device's gate, which has capacitive properties. Charge from these high-energy particles can accumulate in these locations, generating additional gate voltage and single-event transient pulses, affecting memory storage. To address the upsets caused by single-event effects, reinforcement is necessary. Compared to traditional hardware and software reinforcement, the single-event upset self-recovery effect discovered when using two-dimensional materials as channel materials is a more efficient and simpler reinforcement method.

[0061] By clarifying the mechanism of SEE, two-dimensional materials can alter the thickness of the channel material, further reducing the already low probability of channel-induced SEEs. This in turn increases the probability of gate voltage-induced SEEs, leading to SEE self-recovery. Furthermore, to ensure the effectiveness of reinforcement and enhance SEE self-recovery, the gate oxide thickness can be reduced, capacitance increased, and discharge capacity improved, enabling SEE self-recovery in SRAM circuits.

[0062] A gate dielectric with fast frequency response characteristics is selected so that it can discharge quickly after accumulating charges. After the single-particle effect occurs, the extra current in the channel disappears quickly. By utilizing the single-particle flip self-recovery effect, the impact of the single particle on the performance of the device is greatly reduced, thereby completing the device's anti-radiation reinforcement effect.

[0063] According to the capacitor impedance formula: Zc=1 / j2πfC, it can be seen that the gate dielectric with fast frequency response characteristics (f>10 9hz) allows the device to quickly discharge and return to its original state after a single-particle effect occurs. By utilizing the single-particle flip and recovery effect, the potential change caused by a single particle has little effect on the circuit. New High-K gate dielectric materials such as HfO2 and Al2O3 have higher dielectric constants, better thermal stability, and lower leakage current, which can effectively improve the frequency response characteristics of the gate dielectric. At the same time, attention should also be paid to optimizing the interface quality. Improving the interface quality between the gate dielectric and the semiconductor can reduce interface charge traps and defect states, thereby increasing the capacitance density and response speed of the gate dielectric. This can be achieved by using appropriate interface layer materials, surface treatment technologies, or annealing processes.

[0064] In order to cope with the challenge of single particles to device stability, ultra-thin channels, high-k and gate dielectrics with fast frequency response characteristics can be used in combination. At the mechanism level, single-particle upset self-recovery is used to weaken the impact of high-energy particles on device stability, thereby greatly improving its single-particle resistance performance.

[0065] This application uses single-particle upset self-recovery technology to reinforce carbon nanotube field-effect transistors, which significantly increases resistance to single-particle effects. Monitor the impact position of high-energy particles, and when the detector detects a single-particle upset, record the affected node. Then wait for a period of time to ensure that the particle has left. Use electron beam lithography technology to reactivate the affected node and restore it to normal. Record the location, response time and current change of each single-particle event. The node state after recovery also needs to be recorded. The effect of the single-particle upset self-recovery technology can be evaluated by the following indicators: the frequency of single-particle upsets, the success rate of recovery, and the comparison of the current performance after recovery with the initial state. Through the single-particle upset self-recovery technology, we can significantly improve the single-particle irradiation resistance of carbon nanotube field-effect transistors. This helps to reduce device failures and performance degradation and improve system reliability.

[0066] Furthermore, a semiconductor device using transient single event upset self-recovery technology includes: a carbon nanotube film used as a channel material; and a gate dielectric grown on the carbon nanotube film, including hafnium oxide.

[0067] This application develops a semiconductor device processing technology that utilizes single-particle upset self-recovery technology. Compared to non-carbon nanotube field-effect transistors and devices that do not utilize single-particle upset self-recovery, its radiation resistance is substantially improved. Based on the use of carbon nanotubes as the channel material, the single-particle upset self-recovery analysis method combined with simulation organically combines experiment and simulation, achieving the complementary advantages of heavy ion wide-beam experiments, heavy ion microbeam experiments, and numerical simulations, significantly enhancing the device's resistance to single-particle effects. The use of low-dimensional materials as channel materials prevents high-energy particles from accumulating in the channel. The use of High-K gate dielectrics further reduces the device's single-particle effect.

[0068] like Figure 2 As shown in the figure, the transient current magnitude after a single event effect occurs, the highest point is the peak current, and the pulse width is the peak width. The tail current indicates that the current drops rapidly after reaching the peak value and stabilizes within a very short time scale (about 0.7 nanoseconds). Figure 3 As shown, the vertical axis is Figure 2 The integral of V, that is, the total charge accumulated in the channel, is used to excite the charge in the channel, thereby causing a single-particle effect. Under this laser energy, the total charge accumulated in the channel changes over time. GS is the potential difference between the gate and source, V DS is the potential difference between the drain and source, λ is the laser wavelength, and single-event effect is excited by single photons. Figure 2 and Figure 3 This reflects that the device generates a transient current after a single particle is injected, and then quickly returns to its original state.

[0069] like Figure 4 The figure shows the result of single event upset self-recovery (SEUR) of a single device. The waveform in the figure rises first and then falls, indicating that the device state recovers to its previous state after the change, verifying the single event upset self-recovery effect. DD Represents the positive power supply voltage of the circuit, V BL Indicates a bit line, which is used for signal transmission when reading or writing data.

[0070] The preferred embodiments of the present invention are described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the scope of protection of the present invention.

Claims

1. A method for processing a semiconductor device using instantaneous single event upset self-recovery technology, characterized in that: The steps include: S1. Adding carbon nanotubes and a dispersant in a predetermined ratio into toluene, and dispersing them for a predetermined time at a power P using a disperser to obtain a dispersed solution; S2, centrifuging the dispersed solution at least twice under a centrifugal force G to obtain a carbon nanotube solution; S3, diluting the carbon nanotube solution with toluene by at least ten times, placing a substrate in the diluted carbon nanotube solution for soaking time t1, rinsing the soaked substrate with toluene for time t2, purging the rinsed substrate with nitrogen, and baking it in air at temperature C for time t3 to obtain a carbon nanotube film; S4. Based on a carbon nanotube film and a fast-frequency-response gate dielectric, a local bottom gate window is constructed using electron beam lithography. A diluted carbon nanotube solution is then deposited and etched to form the channel of a carbon nanotube field-effect transistor. An active channel region is constructed using electron beam lithography and then etched to form the active channel of the carbon nanotube field-effect transistor. A top gate window is constructed in the active channel; source and drain electrodes are patterned at both ends of the active channel to obtain P-type contacts of the source and drain electrodes; S5. Perform single particle irradiation and pulse laser irradiation on the carbon nanotube field effect transistor in sequence, use a microscope objective lens with a magnification of at least 100 times to focus the pulse laser beam, and form a charge spot on the carbon nanotube field effect transistor.

2. The method for manufacturing a semiconductor device using transient single event upset self-recovery technology according to claim 1, wherein: Step S2 is further as follows: S21, performing a first centrifugal operation on the dispersed solution under a centrifugal force G for a time of t to obtain a clear solution with a purity of at least 90%; S22, centrifuging the supernatant for a second time under a centrifugal force G for a time of t' to obtain a carbon nanotube solution with a purity of at least 90%; The centrifugal force G is 50000g, the first centrifugal operation time t is 0.5h, and the second centrifugal operation time t' is 2h.

3. The semiconductor device processing method using transient single event upset self-recovery technology according to claim 1, characterized in that: Step S3 further includes: The carbon nanotube film is annealed in a tube furnace at a temperature C1 with forming gas for at least 3 hours to remove polymers in the carbon nanotube film.

4. The method for manufacturing a semiconductor device using transient single event upset self-recovery technology according to claim 3, wherein: The forming gas is a mixture of argon and hydrogen in a ratio of 5:

1.

5. The method for manufacturing a semiconductor device using transient single event upset self-recovery technology according to claim 1, wherein: The substrate is a silicon substrate or a silicon dioxide substrate.

6. The method for manufacturing a semiconductor device using transient single event upset self-recovery technology according to claim 1, wherein: The purity of the nitrogen is not less than 99.999%, the carbon nanotubes are graphene, and the predetermined ratio is 1:

1.

7. The method for manufacturing a semiconductor device using transient single event upset self-recovery technology according to claim 1, wherein: Step S4 is further as follows: Based on the carbon nanotube film and the fast frequency response gate dielectric, electron beam lithography is used for patterning to construct a local bottom gate window of the carbon nanotube field effect transistor. Palladium with a thickness of h1 is evaporated on the local bottom gate window by atomic layer deposition and hafnium oxide with a thickness of h2 is grown. A diluted carbon nanotube solution is deposited on the local bottom gate window with the hafnium oxide grown. The deposited carbon nanotube solution is etched for a time t4 using oxygen plasma to form a channel of the carbon nanotube field effect transistor. The channel is patterned using electron beam lithography to construct an active channel region. The active channel region is etched for a time t5 using oxygen plasma to form an active channel of the carbon nanotube field effect transistor. The active channel is patterned using electron beam lithography to construct the top gate window of the carbon nanotube field-effect transistor. Hafnium oxide with a thickness of h3 is grown on the top gate window using atomic layer deposition, and palladium with a thickness of h4 is evaporated. The two ends of the active channel are patterned by electron beam lithography to form the source and drain of the carbon nanotube field effect transistor, and titanium with a thickness of h5 and palladium with a thickness of h6 are evaporated to obtain P-type contacts of the source and drain.

8. The method for manufacturing a semiconductor device using transient single event upset self-recovery technology according to claim 7, wherein: The palladium thickness h1 is 20 nm, the hafnium oxide thickness h2 is 10 nm, the hafnium oxide thickness h3 is 10 nm, the palladium thickness h4 is 20 nm, the titanium thickness h5 is 0.3 nm, and the palladium thickness h6 is 70 nm.

9. The method for manufacturing a semiconductor device using transient single event upset self-recovery technology according to claim 1, wherein: Also includes: S6. Use an oscilloscope to monitor the charge spot, record single event transient response data based on the monitoring results, and evaluate the single particle irradiation resistance of the carbon nanotube field effect transistor based on the response data.

10. A semiconductor device manufactured using the semiconductor device processing method using transient single event upset self-recovery technology according to any one of claims 1 to 9, characterized in that: include: Carbon nanotube film, used as channel material; The gate dielectric grown on the carbon nanotube film includes hafnium oxide.

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