Voltage regulator switch array

Abstract

A regulator circuit included in a computer system may employ a control circuit and a switch array including a plurality of switch circuits. Different groups of switching circuits, including respective groups of switching devices, are coupled between an input power supply node and a corresponding regulated power supply node. In order to maintain a desired respective voltage on the regulated power supply node, the control circuit compares the voltage of the regulated power supply node with a corresponding reference voltage and opens and closes the respective switching devices included in the switching circuits of the different groups based on the result of the comparison.

Description

Technical Field

[0001] The present disclosure relates to power management in computer systems, and more particularly to voltage regulator circuit operation. Background Art

[0002] Modern computer systems may include multiple circuit blocks designed to perform various functions. For example, such circuit blocks may include a processor and / or a processor core configured to execute software or program instructions. In addition, circuit blocks may include memory circuits, mixed signal or analog circuits, etc.

[0003] In some computer systems, circuit blocks may be designed to operate at different power supply voltage levels. Power management circuits may be included in such computer systems to generate and monitor varying power supply voltage levels for different circuit blocks.

[0004] The power management circuit generally includes one or more power converter circuits configured to generate a regulated voltage level for a corresponding power signal using the voltage level of the input power signal. Such a regulator circuit may employ a plurality of passive circuit elements, such as inductors, capacitors, etc. Summary of the invention

[0005] Various embodiments for generating a regulator power supply voltage level are disclosed. In general, the regulator circuit includes a plurality of switch circuits and a control circuit. The plurality of switch circuits include a first subset of switch circuits coupled between an input power node and a specific regulated power node. The number of switch circuits included in the first subset is based on a first target load current of the specific regulated power node. The plurality of switch circuits also include a second subset of switch circuits coupled between the input power node and a different regulated power node. The number of switch circuits included in the second subset is based on a second target load current of a different regulated power node. The control circuit is configured to close at least one switch device in a first plurality of switch devices included in the first subset using one or more control signals based on a comparison of a first reference voltage with a voltage level of a specific regulated power node. The control circuit is also configured to close at least one switch device in a second plurality of switch devices included in the second subset using one or more control signals based on a comparison of a second reference voltage with a voltage level of a different regulated power node. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of an embodiment of a voltage regulator circuit for a computer system.

[0007] Figure 2 is a block diagram of an implementation of a switching circuit.

[0008] Figure 3is a block diagram of another embodiment of a switching circuit.

[0009] Figure 4 are block diagrams of different implementations of switching circuits.

[0010] Figure 5 is a block diagram of an embodiment of a switch circuit including a multiplexing circuit for dynamic switch array programming.

[0011] Figure 6 is a block diagram of a control circuit for a voltage regulator circuit.

[0012] Figure 7 is a block diagram of a specific arrangement of a switch array for a voltage regulator circuit.

[0013] Figure 8 are block diagrams of different arrangements of switch arrays for voltage regulator circuits.

[0014] Fig. 9 is a block diagram of another arrangement of a switch array for a voltage regulator circuit.

[0015] Fig.10 is a flow chart of an embodiment of a method for operating a voltage regulator circuit.

[0016] Fig.11 is a flow chart of an embodiment of a method for programming a regulator switch array.

[0017] Fig.12 is a block diagram of one embodiment of a system on a chip including a voltage regulator circuit.

[0018] Fig.13 is a block diagram of various embodiments of a computer system that may include a power converter circuit.

[0019] Fig.14 An example of a non-transitory computer-readable storage medium storing circuit design information is illustrated. DETAILED DESCRIPTION

[0020] A computer system may include multiple circuit blocks configured to perform specific functions. Such circuit blocks may be fabricated on a common substrate and may employ different power supply voltage levels. A power management unit (commonly referred to as a "PMU") may include multiple regulator circuits configured to generate regulated voltage levels for various power supply signals. Such regulator circuits may employ both passive circuit elements (e.g., inductors, capacitors, etc.) and active circuit elements (e.g., transistors, diodes, etc.).

[0021] Different types of voltage regulator circuits may be employed based on the power requirements of the load circuit, available circuit area, etc. For example, a PMU may employ one or more power converter circuits that supply power to a regulated power supply node via an inductor. Other PMUs employ one or more low dropout ("LDO") voltage regulator circuits, where the additional passive devices associated with the power converter circuits are prohibitive in terms of cost and area.

[0022] During the design of an integrated circuit, load current estimates are determined for different regulated power supply nodes within the integrated circuit, and a voltage regulator circuit is designed based on the estimates. The design of such a voltage regulator circuit can be complex, requiring specialized high voltage transistors, custom mask designs, etc. In some cases, changes to the initial load current estimate during the design process can result in lengthy redesign of the voltage regulator circuit, thereby increasing the cost and schedule of the integrated circuit.

[0023] The embodiments illustrated in the accompanying drawings and described below can provide a technique for generating multiple regulated power supply signals from different input power supply signals by using a configurable switch array including multiple switch circuits having multiple switch devices. Different groups of switch circuits including multiple switch devices are coupled between different input power supply nodes and different regulated power supply nodes. By activating and deactivating various switch devices in different groups of switch circuits, the conductance between a given input power supply node and a given regulated power supply node can be adjusted to maintain the desired voltage level of a given regulated power supply node. By adopting such a configurable switch array, by changing the number of switch circuits coupled to a given regulated power supply node, the design of the regulator circuit can be easily adapted to accommodate last-minute changes in load current estimation. For example, if during the final stages of integrated circuit design, it is determined that the load current of a specific regulated power supply node exceeds the budget, an additional switch circuit of the regulator circuit can be coupled to the specific regulated power supply node to provide additional load current without having to redesign the regulator circuit. Alternatively, if the load current of a particular regulated power supply node is determined to be within the budget, one or more switch circuits of the regulator circuit can be decoupled from the particular regulated power supply node to improve the power efficiency of the regulator circuit without having to redesign the regulator circuit. In addition, by using high-speed transistors as switching devices, the use of expensive high-voltage transistors can be reduced, thereby reducing the cost of integrated circuits and making it easier to migrate the regulator circuit from one semiconductor process to another.

[0024] Figure 1 A block diagram depicting an embodiment of a voltage regulator circuit is illustrated in As illustrated, the voltage regulator circuit 100 includes a control circuit 101 and a switch array 104 .

[0025] Switch array 104 includes a plurality of switch circuits including switch circuits 102A and 102B. Switch circuit 102A includes a first subset of a plurality of switch circuits coupled between input power supply node 107 and regulated power supply node 108A. In various embodiments, the number of switch circuits included in switch circuit 102A may be based on a target load current of regulated power supply node 108A.

[0026] Switch circuit 102B includes a second subset of a plurality of switch circuits coupled between input power node 107 and regulated power node 108B. In various implementations, the number of switch circuits included in switch circuit 102B may be based on a target load current for regulated power node 108B.

[0027] As described below, a given switch circuit includes a plurality of switch devices coupled between power supply nodes to which the given switch circuit is coupled. For example, a given switch circuit in switch circuit 102A includes switch device 103A, and a given switch circuit in switch circuit 102B includes switch device 103B. In various embodiments, the switch devices may be implemented using various field effect transistors, including high speed thin oxide field effect transistors that are typically used to implement high speed logic circuits.

[0028] The control circuit 101 is configured to close at least one of the switch devices 103A based on a comparison of the reference voltage 106A with the voltage level of the regulated power supply node 108A using the control signal 105. The control circuit 101 is further configured to close at least one of the switch devices 103B based on a comparison of the reference voltage 106B with the voltage level of the regulated power supply node 108B using the control signal 105. By adjusting the number of activated switch devices within the various switch circuits included in the switch array 104, a desired voltage level can be maintained on the regulated power supply node.

[0029] Go to Figure 2 , depicting an embodiment of a switch circuit. In various embodiments, the switch circuit 200 may correspond to Figure 1 The depicted switching circuit 102A or 102B. As illustrated, the switching circuit 200 includes switching devices 201-203 and buffer circuits 204-206.

[0030] The switching devices 201-203 are coupled in parallel between the input power supply node 207 and the output power supply node 208 and are controlled by corresponding buffer signals of the buffer signals 213-215. In various embodiments, the input power supply node 207 may correspond to Figure 1 The input power node 107 of FIG. 10 and the output power node 208 may correspond to either the regulated power node 108A or 108B. Figure 2 Only three switch devices are depicted in the embodiment of FIG. , but in other embodiments, any suitable number of switch devices may be used.

[0031] Each of the switch devices 201-203 is configured to couple the output power node 208 to the input power node 207 in response to activation of a corresponding buffer signal of the buffer signals 213-215. For example, activation of the buffer signal 213 will cause the switch device 201 to activate, thereby allowing current to flow from the input power node 207 to the output power node 208 through the switch device 201. As more switch devices 201-203 are activated, the conductance between the input power node 207 and the output power node 208 decreases, thereby allowing more current to be supplied to the output power node 208, thereby increasing the voltage level of the output power node 208.

[0032] In various embodiments, the switch devices 201-203 may be implemented as p-channel metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (FINFETs), all-around gate field effect transistors (GAAFETs), or any other suitable transconductance devices. It is noted that the electrical characteristics of the switch devices 201-203 may be different from each other. In some cases, the respective widths of the switch devices 201-203 may be different to allow each of the switch devices 201-203 to have a different conductance between the input power supply node 207 and the output power supply node 208 when activated. For example, in some cases, the respective widths of the switch devices 201-203 may be binary weighted such that the width of the switch device 202 is twice the width of the switch device 201, and so on.

[0033] Buffer circuits 204-206 are coupled to input power supply node 207 and are configured to generate buffer signals 213-215 using corresponding ones of control signals 209-211. In various embodiments, control signals 209-211 may include a buffer signal generated by a controller such as Figure 1 The control circuit 101 depicted in FIG. 1 generates the control signal 105. Figure 2 In the embodiment of FIG. 3 , three buffer circuits are depicted, but in other embodiments employing a different number of switch devices, a corresponding number of buffer circuits may be used. In various embodiments, buffer circuits 204 - 206 may be implemented using any suitable combination of inverting circuits, non-inverting amplifier circuits, and the like.

[0034] It should be noted that the voltage level corresponding to the activation state of the buffered signals 213-215 may be based on the type of transconductance device used to implement the switching devices 201-203. For example, in the case where the switching devices 201-203 are implemented using p-channel MOSFETs, the voltage level corresponding to the activation state of the buffered signals 213-215 may be at or close to ground potential.

[0035] Go to Figure 3 , depicts another embodiment of the switch circuit. In various embodiments, the switch circuit 300 may correspond to Figure 1 Either of the depicted switching circuits 102A or 102B. As illustrated, the switching circuit 300 includes switching devices 301-303 and buffer circuits 304-306.

[0036] The switch devices 301-303 are coupled in parallel between the input power supply node 307 and the output power supply node 308 and are controlled by corresponding buffer signals of the buffer signals 313-315. In various embodiments, the input power supply node 307 may correspond to Figure 1 The input power node 107 of FIG. 10 and the output power node 308 may correspond to either the regulated power node 108A or 108B. Figure 3 Only three switch devices are depicted in the embodiment of FIG. , but in other embodiments, any suitable number of switch devices may be used.

[0037] Each of the switch devices 301-303 is configured to couple the output power node 308 to the input power node 307 in response to activation of a corresponding buffer signal of the buffer signals 313-315. For example, activation of the buffer signal 313 will cause the switch device 301 to activate, thereby allowing current to flow from the input power node 307 to the output power node 308 through the switch device 301. As more switch devices 301-303 are activated, the conductance between the input power node 307 and the output power node 308 decreases, thereby allowing more current to be supplied to the output power node 308, thereby increasing the voltage level of the output power node 308.

[0038] In various embodiments, the switch devices 301-303 may be implemented as n-channel MOSFETs, FINFETs, GAAFETs, or any other suitable transconductance devices. Note that the electrical characteristics of the switch devices 301-303 may be different from one another. In some cases, the respective widths of the switch devices 301-303 may be different to allow each of the switch devices 301-303 to have a different conductance between the input power node 307 and the output power node 308 when activated. For example, in some cases, the respective widths of the switch devices 301-303 may be binary weighted such that the width of the switch device 302 is twice the width of the switch device 301, and so on.

[0039] Buffer circuits 304-306 are coupled to boost supply node 316 and are configured to generate buffer signals 313-315 using corresponding ones of control signals 309-311. In various embodiments, control signals 309-311 may include signals generated by Figure 1 The control circuit 101 depicted in FIG. 1 generates the control signal 105. Figure 3 In the embodiment of FIG. 3 , three buffer circuits are depicted, but in other embodiments employing a different number of switch devices, a corresponding number of buffer circuits may be used. In various embodiments, buffer circuits 304 - 306 may be implemented using any suitable combination of inverting circuits, non-inverting amplifier circuits, and the like.

[0040] In some cases, the use of n-channel MOSFETs, FinFETs, GAAFETs, etc. may be preferred over p-channel devices for cost and performance reasons. In such cases, the gate-source voltage used to activate the switching devices 301-303 must be higher than the drain voltage of the switching devices 301-303 to achieve the highest conductance. In order to provide sufficient gate-source voltage to the switching devices 301-303, the activation state of the buffered signals 313-315 corresponds to a voltage level of the boosted power supply node 316 that is greater than the voltage level of the input power supply node 307. In various embodiments, the voltage level of the boosted power supply node 316 is greater than the voltage level of the input power supply node 307 by at least an amount corresponding to a threshold voltage associated with the switching devices 301-303.

[0041] Figure 2 and Figure 3 The depicted switching circuit implementation employs switching devices coupled in parallel between an input power supply node and a regulated power supply node. However, the switching circuit is not limited to using a parallel arrangement of switching devices. Figure 4 An embodiment of a switching circuit based on switching devices arranged in series is depicted in As illustrated, the switching circuit 400 includes switching devices 401-403 and snubber circuits 404-406.

[0042] The switching devices 401-403 are coupled in series between the input power supply node 407 and the output power supply node 408 and are controlled by corresponding buffer signals in the buffer signals 413-415. In various embodiments, the input power supply node 407 may correspond to Figure 1 The input power node 107 of FIG. 40 and the output power node 408 may correspond to either the regulated power node 108A or 108B. Figure 4 In the embodiment of FIG. 4 , only three switch devices are depicted, but in other embodiments, any suitable number of switch devices may be employed. By using switch devices coupled in series between the input power supply node 407 and the output power supply node 408, different conductances between the two power supply nodes may be achieved. In some embodiments, a switching circuit using series switch devices may be used in conjunction with a switching circuit using parallel switch devices to achieve a wider range of conductance values ​​between the input and output power supply nodes.

[0043] Each of the switch devices 401-403 is configured to couple its corresponding source terminal to its corresponding drain terminal in response to activation of a corresponding buffer signal in the buffer signals 413-415. For example, activation of the buffer signal 413 will cause the switch device 401 to be activated, thereby allowing current to flow from the input power node 407 through the switch device 401 to the source terminal of the switch device 402. When all of the switch devices 401-403 are activated, current can flow from the input power node 407 to the output power node 408, thereby increasing the voltage level of the output power node 408.

[0044] In various embodiments, the switch devices 401-403 may be implemented as p-channel MOSFETs, FINFETs, GAAFETs, or any other suitable transconductance devices. Note that the electrical characteristics of the switch devices 401-403 may be different from one another. In some cases, the respective widths of the switch devices 401-403 may be different to allow each of the switch devices 401-403 to have a different conductance between the input power supply node 407 and the output power supply node 408 when activated. For example, in some cases, the respective widths of the switch devices 401-403 may be binary weighted such that the width of the switch device 402 is twice the width of the switch device 401, and so on.

[0045] Buffer circuits 404-406 are coupled to input power supply node 407 and are configured to generate buffered signals 413-415 using corresponding ones of control signals 409-411. In various embodiments, control signals 409-411 may include a buffered signal generated by a controller such as Figure 1 The control circuit 101 depicted in FIG. 1 generates the control signal 105. Figure 4 In the embodiment of FIG. 4 , three buffer circuits are depicted, but in other embodiments employing a different number of switch devices, a corresponding number of buffer circuits may be used. In various embodiments, buffer circuits 404 - 406 may be implemented using any suitable combination of inverting circuits, non-inverting amplifier circuits, and the like.

[0046] Note that the voltage level corresponding to the activation state of the buffered signals 413-415 may be based on the type of transconductance device used to implement the switching devices 401-403. For example, if the switching devices 401-403 are implemented using p-channel MOSFETs, the voltage level corresponding to the activation state of the buffered signals 413-415 may be at or near ground potential.

[0047] In various embodiments, each of the switch circuits included in switch array 104 is coupled between an input power supply node and a regulated power supply node. The connection of a given switch circuit may be determined during the design phase of an integrated circuit employing regulator circuit 100 and then hardwired during fabrication of the integrated circuit.

[0048] However, in some cases, it may be desirable to have additional configurations available within the switch array 104 to account for variations in load current that were not accounted for during the design phase of the integrated circuit. To accommodate such variations in load current, a given switch circuit within the switch array 104 may be configured to use a different input power supply node and a different output power supply node. Figure 5 A block diagram of an embodiment of such a switch circuit is depicted in . As illustrated, switch circuit 500 includes switch devices 501-503, buffer circuits 504-506, and multiplexing circuits 516 and 517. Note that in various embodiments, switch circuit 500 may correspond to any of switch circuits 102A-102B.

[0049] Switching devices 501-503 are coupled in parallel between node 520 and node 519 and are controlled by corresponding buffer signals in buffer signals 513-515. Figure 5 Only three switch devices are depicted in the embodiment of FIG. , but in other embodiments, any suitable number of switch devices may be used.

[0050] In various embodiments, the switch devices 501-503 may be implemented as p-channel MOSFETs, FINFETs, GAAFETs, or any other suitable transconductance devices. Note that the electrical characteristics of the switch devices 501-503 may be different from one another. In some cases, the respective widths of the switch devices 501-503 may be different to allow each of the switch devices 501-503 to have a different conductance between the node 520 and the node 519 when activated. For example, in some cases, the respective widths of the switch devices 501-503 may be binary weighted such that the width of the switch device 502 is twice the width of the switch device 501, and so on.

[0051] Buffer circuits 504-506 are coupled to node 520 and are configured to generate buffered signals 513-515 using corresponding ones of control signals 509-511. In various embodiments, control signals 509-511 may include signals generated by Figure 1 The control circuit 101 depicted in FIG. 1 generates the control signal 105. Figure 5 In the embodiment of FIG. 5 , three buffer circuits are depicted, but in other embodiments employing a different number of switch devices, a corresponding number of buffer circuits may be used. In various embodiments, buffer circuits 504 - 506 may be implemented using any suitable combination of inverting circuits, non-inverting amplifier circuits, and the like.

[0052] Note that the voltage level corresponding to the activation state of the buffered signals 513-515 may be based on the type of transconductance device used to implement the switching devices 501-503. For example, if the switching devices 501-503 are implemented using p-channel MOSFETs, the voltage level corresponding to the activation state of the buffered signals 513-515 may be at or near ground potential.

[0053] Multiplexing circuit 516 is configured to selectively couple input power supply node 507B or input power supply node 507A to node 520 based on configuration data 518. Multiplexing circuit 517 is configured to selectively couple node 519 to either output power supply node 508A or 508B. In various embodiments, either input power supply node 507A or 507B may correspond to Figure 1 The input power supply node 107 of FIG. By adjusting the configuration data 518, the switch devices 501-503 can be coupled between different combinations of the input power supply nodes 507A-507B and the output power supply nodes 508A-508B. In various embodiments, the configuration data 518 can include a plurality of bits, the values ​​of which can be adjusted based on the load current drawn from the output power supply nodes 508A-508B or any other suitable criteria.

[0054] Multiplexing circuits 516 and 517 may be implemented using a plurality of transmission gate structures coupled together in a wired OR fashion or any other suitable circuit configured to perform a multiplexing function using analog voltage levels. Figure 5 In the embodiment of FIG. 5 , only two input power supply nodes and two output power supply nodes are depicted, but in other embodiments, multiplexing circuits 516 and 517 can be configured to use any suitable number of input power supply nodes and output power supply nodes.

[0055] Go to Figure 6 , depicts a block diagram of an embodiment of the control circuit 101. As illustrated, the control circuit 101 includes comparison circuits 601A-601B and a logic circuit 602.

[0056] Comparison circuit 601A is configured to generate comparison signal 603A using reference voltage 106A and the voltage level of regulated power supply node 108A, and comparison circuit 601B is configured to generate comparison signal 603B using reference voltage 106B and the voltage level of regulated power supply node 108B. To generate comparison signal 603A, comparison circuit 601A may be further configured to compare reference voltage 106A with the voltage level of regulated power supply node 108A, and quantize the result of the comparison to generate a plurality of bits included in comparison signal 603A. In a similar manner, to generate comparison signal 603B, comparison circuit 601B may be further configured to compare reference voltage 106B with the voltage level of regulated power supply node 108B, and quantize the result of the comparison to generate a plurality of bits included in comparison signal 603B.

[0057] In various embodiments, comparison circuit 601A and comparison circuit 601B may be implemented using a comparator circuit, such as a differential amplifier circuit, configured to generate an output signal whose signal amplitude is proportional to the difference between two input signals. In addition, comparison circuit 601A and comparison circuit 601B may be implemented using an analog-to-digital converter circuit configured to generate a plurality of bits whose values ​​correspond to the amplitudes of the input signals.

[0058] Logic circuit 602 is configured to generate control signal 105 using comparison signals 603A-603B and configuration data 518. In various embodiments, configuration data 518 may include a plurality of bits whose values ​​indicate which control signals 105 will be used to control the voltage level of regulated power supply node 108A and which control signals 105 will be used to control the voltage level of regulated power supply node 108B. In some embodiments, configuration data 518 may be static and stored in a one-time programmable memory circuit or other non-volatile memory circuit. Alternatively, configuration data 518 may be adjusted over time to account for changing load conditions on regulated power supply nodes 108A and 108B.

[0059] To generate control signal 105, logic circuit 602 may be further configured to activate different control signals in control signal 105 in response to determining that comparison signal 603A indicates that the voltage level of regulated power supply node 108A is less than reference voltage 106A. Alternatively, logic circuit 602 may be configured to deactivate other control signals in control signal 105 in response to determining that comparison signal 603A indicates that the voltage level of regulated power supply node 108A is greater than reference voltage 106A. In a similar manner, logic circuit 602 may be configured to activate and deactivate various control signals in control signal 105 based on the value of comparison signal 603B. In various embodiments, logic circuit 602 may be implemented as a microcontroller, a state machine, or a general purpose processor circuit configured to execute software or program instructions.

[0060] Please note that although Figure 6 In the embodiment of FIG. 1 , only two comparison circuits are depicted, but in other embodiments, additional comparison circuits may be employed if the switch array 104 is coupled to an additional regulated power supply node. In such a case, the logic circuit 602 may be further configured to generate the control signal 105 using additional comparison signals generated by the additional comparison circuits.

[0061] By coupling different switch circuits within the switch array 104 to different regulated power supply nodes and using separate control signals, the switch array 104 can be used to generate multiple regulated voltages. Figure 7 A block diagram of an embodiment of a switch array 104 configured to generate a plurality of regulated supply voltages is depicted in FIG. As illustrated, the switch array 104 includes switch circuits 701-709. In various embodiments, the switch circuits 701-709 may be implemented using any suitable combination of the switch circuits 200, 300, 400, and 500. Note that although Figure 7 In the embodiment of FIG. , only nine switching circuits are depicted, but in other embodiments, any suitable number of switching circuits may be used.

[0062] Switching circuits 701-703 are coupled between input power node 107 and regulated power node 710. In various implementations, switching circuits 701-703 are configured to generate a specific voltage level on regulated power node 710 using control signal 713 and the voltage level of input power node 107.

[0063] Switching circuits 704-706 are coupled between input power node 107 and regulated power node 711. In various implementations, switching circuits 704-706 are configured to generate a specific voltage level on regulated power node 711 using control signal 714 and the voltage level of input power node 107.

[0064] The switch circuits 707-709 are coupled between the input power node 107 and the regulated power node 712. In various embodiments, the switch circuits 707-709 are configured to generate a specific voltage level on the regulated power node 712 using the control signal 715 and the voltage level of the input power node 107. It should be noted that the control signals 713-715 may include Figure 1 In the control signal 105 depicted in .

[0065] exist Figure 7 In the illustrated embodiment, rows of switching circuits are coupled together to provide regulation for a given regulated power supply node. In other embodiments, different load current requirements of the regulated power supply node allow for different numbers of switching circuits to be used to regulate a given power supply node. Different numbers of switching circuits can be arranged in various topologies other than rows to provide voltage regulation. Figure 8 A block diagram of another embodiment of a switch array 104 having a different switch circuit arrangement is depicted in FIG. As illustrated, the switch array 104 includes switch circuits 801A-801D, 802A-802C, and 803A-803B. Note that although Figure 8 In the embodiment of FIG. , only nine switching circuits are depicted, but in other embodiments, any suitable number of switching circuits may be used.

[0066] The switch circuits 801A-801D are coupled between the input power node 107 and the regulated power node 804. In various embodiments, the switch circuits 801A-801D are configured to generate a specific voltage level on the regulated power node 804 using the voltage level of the input power node 107 and the control signal 807. Note that in some embodiments, the control signal 807 may include a Figure 1 The control signal 105 is depicted.

[0067] Switching circuits 802A-802C are coupled between input power node 107 and regulated power node 805. In various embodiments, switching circuits 802A-802C are configured to generate a specific voltage level on regulated power node 805 using the voltage level of input power node 107 and control signal 808. Note that in some embodiments, control signal 808 may include a Figure 1 The control signal 105 is depicted.

[0068] The switch circuits 803A-803B are coupled between the input power node 107 and the regulated power node 806. In various embodiments, the switch circuits 803A-803B are configured to generate a specific voltage level on the regulated power node 806 using the voltage level of the input power node 107 and the control signal 809. Note that in some embodiments, the control signal 809 may include a Figure 1 The control signal 105 is depicted.

[0069] In some cases, the voltage regulation function and the switching function of the switch circuits within the switch array may be used in combination. Fig. 9 , a block diagram of an embodiment of a switch array 104 that employs both voltage regulation and switching functions is depicted in FIG. As illustrated, the switch array 104 includes switch subsets 901-904. In various embodiments, each of the switch subsets 901-904 includes one or more of any suitable combination of switch circuits 200, 300, 400, or 500 arranged in series, in parallel, or in any suitable combination thereof. Note that control signals such as control signal 105 are omitted for clarity.

[0070] As illustrated, switch subset 901 is configured to generate a specific voltage level on regulated power node 909 using the voltage level of input power node 905. Switch subset 903 is configured to operate in a switching mode to generate gated power node 910 using input power node 906. For example, the switch circuit included in switch subset 903 is configured to selectively couple input power node 906 to gated power node 910 (or decouple from gated power node). By decoupling the two power nodes, gated power node 910 can be allowed to float to save power during power gating operation.

[0071] In some embodiments, switch subset 902 is configured to generate regulated voltage 908 using the voltage level of input power supply node 907. In various embodiments, different ones of the switch circuits included in switch subset 902 can be activated to adjust the voltage level of regulated voltage 908.

[0072] The switch subset 904 is also configured to operate in a switch mode to generate a voltage level on a gated regulated power supply node 911. In various embodiments, the switch subset 904 is configured to couple the output of the switch subset 902 to the gated regulated power supply node 911, thereby allowing the voltage level of the gated regulated power supply node 911 to become a regulated voltage 908. In response to a power gating operation or other suitable condition, the switch subset 904 is configured to decouple the gated power supply node 911 from the output of the switch subset 902, thereby allowing the gated regulated power supply node 911 to float. Power gating can also be achieved for regulated power supply nodes by using different subsets of switch circuits together.

[0073] Although Fig. 9 The illustrated embodiment of the switch array 104 depicts only four switch circuit subsets, but in other embodiments, any suitable number of switch circuit subsets may be employed.

[0074] Go to Fig.10 , illustrates a flow chart depicting an embodiment of a method for operating a voltage regulator circuit. The method, which may be applicable to various voltage regulator circuits, such as voltage regulator circuit 100 , begins at block 1001 .

[0075] The method includes performing a first comparison of a voltage of a first regulated power supply node with a first reference voltage (block 1002). In various embodiments, performing the first comparison may include generating a first differential voltage using the voltage level of the first regulated power supply node and the first reference voltage, and quantizing the first differential voltage to generate a first plurality of bits. In such cases, the method may further include generating a first plurality of control signals using the plurality of bits.

[0076] The method also includes activating a particular switching circuit of a first subset of a plurality of switching circuits based on a first result of the first comparison, wherein the first subset is coupled between an input power supply node and a first regulated power supply node, and wherein the number of switching circuits included in the first subset is based on a first target load current of the first regulated power supply node (block 1003).

[0077] In various embodiments, the particular switching circuit may include a plurality of switching devices coupled in series between the input power node and the first regulated power node. In such cases, activating the particular switching circuit based on the first result includes activating the plurality of switching devices using corresponding control signals in the first plurality of control signals.

[0078] In other embodiments, the particular switching circuit may include a plurality of switching devices coupled in parallel between the input power node and the first regulated power node. In such cases, activating the particular switching circuit based on the first result includes activating at least one switching device of the plurality of switching devices using the first plurality of control signals.

[0079] In some embodiments, the specific switch circuit may include a plurality of switch devices coupled between the input power node and the first regulated power node. In such cases, activating the specific switch circuit based on the first result may include buffering a subset of the first plurality of control signals using a boost power node to generate a plurality of buffered signals, and activating at least one switch device of the plurality of switch devices using the plurality of buffered signals. It should be noted that the voltage level of the boost power node is greater than the voltage level of the input power node.

[0080] The method further includes performing a second comparison of the voltage of the second regulated power supply node with the second reference voltage (block 1004). In various embodiments, performing the second comparison may include generating a second differential voltage using the voltage level of the second regulated power supply node and the second reference voltage, and quantizing the second differential voltage to generate a second plurality of bits. In such cases, the method may further include generating a second plurality of control signals using the second plurality of bits.

[0081] The method also includes adjusting conductance between the input power node and the second regulated power node by activating different switch circuits in a second subset of the plurality of switch circuits based on a second result of the second comparison, wherein the second subset is coupled between the input power node and the second regulated power node, and the number of switch circuits included in the second subset of the plurality of switch circuits is based on a second target load current of the second regulated power node (block 1005).

[0082] In some embodiments, adjusting the conductance between the input power node and the second regulated power node based on the second result may include: activating another switch circuit in the second subset of the plurality of switch circuits in response to determining that the voltage level of the second regulated power node is less than a threshold value than a second reference voltage.

[0083] In various embodiments, the different switching circuits include a plurality of switching devices coupled between the input power node and the second regulated power node. In such cases, adjusting the conductance between the input power node and the second regulated power node based on the second result may include activating a subset of the plurality of switching devices, wherein the number of switching devices included in the subset of the plurality of switching devices is based on a difference between a voltage level of the second regulated power node and a second reference voltage. The method ends at block 1006.

[0084] Go to Fig.11 , illustrates a flow chart depicting an embodiment of a method for programming a regulator switch array. The method, which may be applied to various switch arrays, such as the switch array 104 , begins at block 1101 .

[0085] The method includes receiving a plurality of target load currents for a corresponding plurality of regulated power supply nodes (block 1102). In various embodiments, the method may further include generating the plurality of target load currents by simulating load circuit performance under various manufacturing and operating conditions.

[0086] The method also includes determining a number of switch circuits to be coupled between the input power node and a given regulated power node in the corresponding plurality of regulated power nodes using a corresponding target load current in the plurality of target load currents (block 1103). In various embodiments, determining the number of switch circuits includes determining a range of conductance values ​​that support the corresponding target load current. In some embodiments, the method may further include determining a configuration of the switch device (parallel, series, or a combination thereof) and a type of the switch device based on the range of conductance values.

[0087] The method further includes programming a switch array of the regulator circuit using the number of switch circuits determined for a given regulated supply node (block 1104). In some embodiments, programming the switch array includes adjusting one or more mask layers used in fabrication of the integrated circuit to couple different switch circuits to different input supply nodes and different regulated supply nodes.

[0088] The method also includes storing configuration data associated with programming of the switch array (block 1105). In various embodiments, the configuration data may include information indicating a power supply node to which a given switch circuit is coupled. In some embodiments, storing the configuration data includes programming a one-time programmable memory circuit or other suitable non-volatile memory circuit using the configuration data. The method ends at block 1106.

[0089] exist Fig.12 1200. In the illustrated embodiment, SoC 1200 includes power management circuit 1201, processor circuit 1202, input / output circuit 1204, and memory circuit 1203, each of which is coupled to power supply node 1205. SoC 1200 also includes configuration data 518. In various embodiments, SoC 1200 can be configured for use in a desktop computer, a server, or in a mobile computing application (such as, for example, a tablet computer, a laptop computer, or a wearable computing device).

[0090] The power management circuit 1201 includes a voltage regulator circuit 100 configured to generate a regulated voltage level on a power supply node 1205 to provide power to a processor circuit 1202, an input / output circuit 1204, and a memory circuit 1203. In various embodiments, the arrangement of switches within the voltage regulator circuit 100 may be controlled by configuration data 518. In some embodiments, the configuration data 518 may be stored in a one-time programmable memory or other suitable non-volatile circuit. In some cases, the configuration data 518 may be updated based on changes in the load current of a power supply node, such as the power supply node 1205.

[0091] Although the power management circuit 1201 is depicted as including a single regulator circuit, in other embodiments, the power management circuit 1201 may include any suitable number of regulator circuits, each regulator circuit being configured to generate a regulated voltage level for a corresponding internal power signal among a plurality of internal power signals included in the SoC 1200.

[0092] In various embodiments, processor circuit 1202 may represent a general purpose processor that performs computing operations. For example, processor circuit 1202 may be a central processing unit (CPU) such as a microprocessor, microcontroller, application specific integrated circuit (ASIC), or field programmable gate array (FPGA).

[0093] In various embodiments, memory circuit 1203 may include any suitable type of memory, such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or non-volatile memory. Fig.12 A single memory circuit is illustrated in FIG. 1 , but in other embodiments, any suitable number of memory circuits may be employed.

[0094] Input / output circuitry 1204 may be configured to coordinate data transfers between SoC 1200 and one or more peripheral devices. Such peripheral devices may include, but are not limited to, storage devices (e.g., storage devices based on magnetic or optical media, including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral device. In some embodiments, input / output circuitry 1204 may be configured to implement a Universal Serial Bus (USB) protocol or IEEE 1394 (Firewire ® ) protocol version.

[0095] The input / output circuitry 1204 may also be configured to coordinate data transfers between the SoC 1200 and one or more devices (e.g., other computing systems or integrated circuits) coupled to the SoC 1200 via a network. In one embodiment, the input / output circuitry 1204 may be configured to perform data processing required to implement an Ethernet (IEEE 802.3) networking standard such as, for example, Gigabit Ethernet or 10 Gigabit Ethernet, but it is contemplated that any suitable networking standard may be implemented. In some embodiments, the input / output circuitry 1204 may be configured to implement multiple discrete network interface ports.

[0096] Now go to Fig.13 , illustrates various types of systems that may include any of the circuits, devices, or systems described above. The system or device 1300, which may incorporate or otherwise utilize one or more of the techniques described herein, may be used in a wide range of fields. For example, the system or device 1300 may be used as part of the hardware of a system such as a desktop computer 1310, a laptop computer 1320, a tablet computer 1330, a cellular or mobile phone 1340, or a television 1350 (or a set-top box coupled to a television).

[0097] Similarly, the disclosed elements can be used in a wearable device 1360, such as a smart watch or a health monitoring device. In many embodiments, a smart watch can implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. A wearable device can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also contemplated, including devices worn around the neck, devices implantable in the human body, glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0098] The system or device 1300 may also be used in a variety of other contexts. For example, the system or device 1300 may be used in the context of a server computer system (such as a dedicated server) or on shared hardware that implements a cloud-based service 1370. Further, the system or device 1300 may be implemented in a wide range of dedicated everyday devices, including devices 1380 commonly found in the home, such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the "Internet of Things" (IoT). Elements may also be implemented in various modes of transportation. For example, the system or device 1300 may be used in control systems, guidance systems, entertainment systems, etc., for various types of vehicles 1390.

[0099] Fig.13The applications illustrated in the examples are merely exemplary and are not intended to limit the potential future applications of the disclosed system or device. Other example applications include, but are not limited to: portable game devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0100] Fig.14 14 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 1420 is configured to process design information 1415 stored on a non-transitory computer-readable storage medium 1410 and to manufacture an integrated circuit 1430 based on the design information 1415.

[0101] The non-transitory computer-readable storage medium 1410 may include any of various suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1410 may be an installation medium, for example, a CD-ROM, a floppy disk, or a tape device; a computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, RambusRAM, etc.; a non-volatile memory, such as flash memory, magnetic media, etc., for example, a hard drive or optical storage device; a register or other similar type of memory element, etc. The non-transitory computer-readable storage medium 1410 may also include other types of non-transitory memories or combinations thereof. The non-transitory computer-readable storage medium 1410 may include two or more memory media that may reside in different locations, such as different computer systems connected by a network.

[0102] The design information 1415 may be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The design information 1415 may be capable of being used by the semiconductor manufacturing system 1420 to manufacture at least a portion of the integrated circuit 1430. The format of the design information 1415 may be recognizable by at least one semiconductor manufacturing system such as, for example, the semiconductor manufacturing system 1420. In some embodiments, the design information 1415 may include a netlist specifying elements of a cell library and their connectivity. One or more cell libraries used during logic synthesis of circuits included in the integrated circuit 1430 may also be included in the design information 1415. Such cell libraries may include information indicating a device or transistor level netlist, mask design data, characterization data, etc. of the cells included in the cell library.

[0103] In various embodiments, integrated circuit 1430 may include one or more custom macrocells, such as memory, analog or mixed signal circuits, etc. In such cases, design information 1415 may include information related to the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to a graphic data system (GDSII) or any other suitable format.

[0104] Semiconductor manufacturing system 1420 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 1420 may also be configured to perform various tests of the manufactured circuits for proper operation.

[0105] In various embodiments, the integrated circuit 1430 is configured to operate according to the circuit design specified by the design information 1415, which may include performing any of the functions described herein. For example, the integrated circuit 1430 may include any of the various elements shown or described herein. In addition, the integrated circuit 1430 may be configured to perform the various functions described herein in conjunction with other components. In addition, the functionality described herein may be performed by multiple connected integrated circuits.

[0106] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0107] ***

[0108] This disclosure includes references to "embodiments," which are non-limiting, specific implementations of the disclosed concepts. References to "an embodiment," "one embodiment," "a specific embodiment," "some embodiments," "various embodiments," etc., do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including the specific embodiments described in detail, as well as modifications or alternatives that fall within the spirit or scope of this disclosure. Not all of these embodiments will necessarily exhibit any or all of the potential advantages described herein.

[0109] Unless otherwise stated, the specific embodiments are not intended to limit the scope of the claims drafted based on the disclosure of the disclosed form, even if only a single example is described for a particular feature. Therefore, the disclosed embodiments are intended to be illustrative rather than restrictive, without any statement to the contrary. This patent application is intended to cover such alternatives, modifications, and equivalents, which will be obvious to those skilled in the art having the benefit of this disclosure.

[0110] The particular features, structures or characteristics may be combined in any suitable manner consistent with the present disclosure. Accordingly, the present disclosure is intended to include any feature or combination of features disclosed herein (explicitly or implicitly), or any generalization thereof. Accordingly, new claims may be made during the prosecution of the present application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features of the dependent claims may be combined with features of the independent claims, and features from the respective independent claims may be combined in any appropriate manner and not merely by the specific combinations listed in the appended claims.

[0111] For example, while the appended dependent claims are drafted so that each dependent claim is dependent on a single other claim, additional dependencies are also contemplated. It is also contemplated that a claim drafted in one legal type (e.g., apparatus) may inspire a corresponding claim of another legal type (e.g., method), where appropriate.

[0112] ***

[0113] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0114] Unless the context clearly dictates otherwise, references to singular forms such as “a,” “an,” and “the” are intended to mean “one or more.” Thus, reference to “an item” in a claim does not exclude additional instances of that item.

[0115] The word “may” is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0116] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0117] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," covering x but not y, y but not x, and both x and y. On the other hand, phrases such as "either, but not both, x or y" make it clear that "or" is used in an exclusive sense.

[0118] The expressions "w, x, y, or z, or any combination thereof" or "at least one of ... w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Thus, the phrase "at least one of ... w, x, y, and z" refers to at least one element of the elements in the set [w, x, y, z], thereby covering all possible combinations in the list of options. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0119] In this disclosure, various "labels" may precede a noun. Unless the context provides otherwise, different labels used for features (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. Unless otherwise specified, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to specific features.

[0120] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be considered to be "configured to" perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a memory storing executable program instructions, etc. The phrase is not used herein to refer to an intangible thing.

[0121] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function.

[0122] The recitation of a construct in the appended claims as “configured to” perform one or more tasks is expressly intended not to invoke 35 USC § 112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution, it will use the “means for [performing the function]” construct to recite the claim element.

[0123] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence a determination. That is, a determination may be based only on specified factors or on specified factors as well as other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0124] The phrase "in response to" describes one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect. That is, the effect may be responsive only to those factors, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "in response to B performing A." The phrase specifies that B is the factor that triggers the performance of A. The phrase does not exclude that performing A may also be responsive to some other factor, such as C. The phrase is also intended to cover embodiments in which A is performed only in response to B.

Claims

1. A device, comprising: A plurality of switch circuits, the plurality of switch circuits comprising: a first subset of the plurality of switch circuits, the first subset coupled between an input power node and a particular regulated power node, wherein a first number of switch circuits included in the first subset is based on a first target load current for the particular regulated power node; and a second subset of the plurality of switch circuits, the second subset coupled between the input power node and a different regulated power node, wherein a second number of switch circuits included in the second subset is based on a second target load current for the different regulated power node; and A control circuit, the control circuit being configured to: closing at least one switching device of a first plurality of switching devices included in the first subset using one or more control signals based on a comparison of a first reference voltage and a voltage level of the particular regulated power supply node; and Based on a comparison of a second reference voltage and a voltage level of the different regulated power supply node, at least one switching device of a second plurality of switching devices included in the second subset is closed using the one or more control signals.

2. The apparatus of claim 1 , wherein a given switch circuit of the first subset comprises: a plurality of buffer circuits configured to generate a corresponding plurality of buffered signals using a subset of the one or more control signals; and A plurality of devices are coupled between the input power node and the specific regulated power node and configured to couple the input power node to the specific regulated power node using corresponding buffered signals of the corresponding plurality of buffered signals.

3. The apparatus of claim 2 , wherein the plurality of buffer circuits are coupled to a boosted power supply node, a voltage of the boosted power supply node being greater than a voltage level of the input power supply node, and wherein an activation level of a given buffer signal of the corresponding plurality of buffer signals is greater than the voltage level of the input power supply node.

4. The apparatus of claim 1 , wherein a given switch circuit of the first subset comprises: a plurality of buffer circuits configured to generate a corresponding plurality of buffered signals using a subset of the one or more control signals; and A plurality of devices are coupled in series between the input power node and the specific regulated power node and configured to couple the input power node to the specific regulated power node in response to activation of the corresponding plurality of buffered signals.

5. An apparatus according to claim 1, wherein a given switching circuit of the first subset includes a plurality of devices, the plurality of devices are coupled between the input power node and the specific regulated power node, and the plurality of devices are configured to couple the input power node to the specific regulated power node using a corresponding control signal from the one or more control signals, and wherein the control circuit is further configured to activate a subset of the plurality of devices based on a target conductance between the input power node and the specific regulated power node. 6 . The apparatus of claim 1 , wherein the control circuit is further configured to quantify a comparison result of the first reference voltage and the voltage level of the particular regulated power supply node.

7. A method comprising: performing a first comparison of a voltage level of a first regulated power supply node with a first reference voltage; activating a particular switch circuit of a first subset of a plurality of switch circuits based on a first result of the first comparison, wherein the first subset is coupled between an input power supply node and the first regulated power supply node, and a first number of switch circuits included in the first subset is based on a target load current of the first regulated power supply node; performing a second comparison of the voltage level of the second regulated power supply node with a second reference voltage; as well as Based on a second result of the second comparison, the conductance between the input power node and the second regulated power node is adjusted by activating different switch circuits in a second subset of the plurality of switch circuits, wherein the second subset is coupled between the input power node and the second regulated power node, and a second number of switch circuits included in the second subset is based on a second target current of the second regulated power node.

8. The method of claim 7, wherein performing the first comparison comprises: generating a differential voltage using the voltage level of the first regulated power supply node and the first reference voltage; quantizing the differential voltage to generate a plurality of bits; as well as A plurality of control signals are generated using the plurality of bits.

9. The method of claim 8, wherein the specific switching circuit comprises a plurality of switching devices coupled in series between the input power node and the first regulated power node, and wherein activating the specific switching circuit based on the first result comprises activating the plurality of switching devices using corresponding control signals from among the plurality of control signals.

10. The method of claim 8, wherein the specific switching circuit comprises a plurality of switching devices coupled in parallel between the input power node and the first regulated power node, and wherein activating the specific switching circuit based on the first result comprises activating at least one of the plurality of switching devices using the plurality of control signals.

11. The method of claim 8, wherein the particular switching circuit comprises a plurality of switching devices coupled between the input power node and the first regulated power node, and wherein activating the particular switching circuit based on the first result comprises: buffering a subset of the plurality of control signals using a boosted power supply node to generate a plurality of buffered signals, wherein a voltage level of the boosted power supply node is greater than a voltage level of the input power supply node; as well as At least one switching device among the plurality of switching devices is activated using the plurality of buffered signals.

12. The method of claim 7, wherein adjusting the conductance between the input power node and the second regulated power node based on the second result comprises: In response to determining that the voltage level of the second regulated power supply node is less than the second reference voltage by a threshold value, another switch circuit in the second subset of the plurality of switch circuits is activated.

13. The method of claim 7 , wherein the different switching circuits include a plurality of switching devices coupled between the input power node and the second regulated power node, wherein adjusting the conductance between the input power node and the second regulated power node based on the second result includes activating a subset of the plurality of switching devices, and wherein the number of switching devices included in the subset of the plurality of switching devices is based on a difference between the voltage level of the second regulated power node and the second reference voltage.

14. A device, comprising: a first functional circuit block, the first functional circuit block being coupled to a first regulated power supply node; a second functional circuit block, the second functional circuit block being coupled to a second regulated power supply node; and A voltage regulator circuit, the voltage regulator circuit comprising a plurality of switch circuits, wherein the voltage regulator circuit is configured to: performing a first comparison of the voltage level of the first regulated power supply node with a first reference voltage; activating a particular switch circuit of a first subset of the plurality of switch circuits based on a first result of the first comparison, wherein the first subset is coupled between an input power supply node and the first regulated power supply node, and a first number of switch circuits included in the first subset is based on a target load current of the first regulated power supply node; performing a second comparison of the voltage level of the second regulated power supply node with a second reference voltage; as well as Based on a second result of the second comparison, the conductance between the input power node and the second regulated power node is adjusted by activating different switch circuits in a second subset of the plurality of switch circuits, wherein the second subset is coupled between the input power node and the second regulated power node, and a second number of switch circuits included in the second subset is based on a second target current of the second regulated power node.

15. The apparatus of claim 14, wherein to perform the first comparison, the voltage regulator circuit is further configured to: generating a differential voltage using the voltage level of the first regulated power supply node and the first reference voltage; quantizing the differential voltage to generate a plurality of bits; and A plurality of control signals are generated using the plurality of bits.

16. An apparatus according to claim 15, wherein the specific switching circuit includes a plurality of switching devices coupled in series between the input power node and the first regulated power node, and wherein in order to activate the specific switching circuit based on the first result, the regulator circuit is further configured to activate the plurality of switching devices using corresponding control signals among the plurality of control signals.

17. An apparatus according to claim 15, wherein the specific switching circuit includes a plurality of switching devices coupled in parallel between the input power node and the first regulated power node, and wherein in order to activate the specific switching circuit, the regulator circuit is further configured to activate at least one of the plurality of switching devices using the plurality of control signals based on the first result.

18. The apparatus of claim 15, wherein the specific switching circuit comprises a plurality of switching devices coupled between the input power node and the first regulated power node, and wherein to activate the specific switching circuit, the regulator circuit is further configured to, based on the first result: buffering the plurality of control signals using a boosted power supply node to generate a plurality of buffered signals, wherein a voltage level of the boosted power supply node is greater than a voltage level of the input power supply node; and At least one switching device among the plurality of switching devices is activated using the plurality of buffered signals.

19. The apparatus of claim 14, wherein in order to adjust the conductance between the input power node and the second regulated power node based on the second result, the regulator circuit is further configured to activate another switch circuit among the plurality of switch circuits in response to determining that the voltage level of the second regulated power node is less than a threshold value than the second reference voltage.

20. The apparatus of claim 14, wherein the different switching circuits comprise a plurality of switching devices coupled between the input power node and the second regulated power node, wherein in order to adjust the conductance between the input power node and the second regulated power node based on the second result, the regulator circuit is further configured to activate a subset of the plurality of switching devices, and the number of switching devices included in the subset of the plurality of switching devices is based on a difference between the voltage level of the second regulated power node and the second reference voltage.

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