Neural topology ordering

Abstract

A processor-implemented method for generating a topological order using an artificial neural network (ANN) includes receiving a set of tasks to be performed; representing the tasks in a graph comprising a plurality of nodes connected by edges, each node corresponding to a task in the task set; assigning a scheduling priority to each node in the graph; selecting a next one of the potential next nodes according to a probability of each of the potential next nodes based on the assigned scheduling priority and a topology of the graph; a topological order of the tasks is generated by repeating the selection of the next node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 18 / 103,757, filed on January 31, 2023, entitled “NEURAL TOPOLOGICAL ORDERING,” which claims the benefit of U.S. Provisional Patent Application No. 63 / 343,961, filed on May 19, 2022, entitled “NEURAL TOPOLOGICAL ORDERING,” the disclosures of which are expressly incorporated by reference in their entirety. Technical Field

[0003] Aspects of the present disclosure generally relate to neural topological ordering. Background Art

[0004] An artificial neural network may include an interconnected group of artificial neurons (e.g., a neuron model). An artificial neural network may be a computing device or represented as a method to be performed by a computing device. A convolutional neural network (CNN) is a feedforward artificial neural network. A convolutional neural network may include a collection of neurons, each of which has a receptive field and collectively spells out an input space. Convolutional neural networks, such as deep convolutional neural networks (DCNs), have numerous applications. Specifically, these neural network architectures are used in various technologies, such as image recognition, speech recognition, acoustic scene classification, keyword detection, autonomous driving, and other classification tasks.

[0005] Many problems in operations research involve performing a series of tasks while all obeying a set of precedence constraints between them and optimizing a cost metric of interest. Conventional methods approach such problems via heuristic strategies that are designed for general input distributions rather than being tailored to problem-specific input distributions. Some heuristic strategies are handcrafted for each instance, which is time-consuming and requires domain knowledge. Summary of the invention

[0006] The present disclosure is set out in the independent claims. Some aspects of the present disclosure are described in the dependent claims.

[0007] In one aspect of the present disclosure, a processor-implemented method includes: receiving a set of tasks to be performed. The processor-implemented method also includes: representing the set of tasks in a graph including a plurality of nodes connected by edges. Each node corresponds to a task in the set of tasks. The processor-implemented method further includes: assigning a scheduling priority to each node in the graph. The processor-implemented method also includes: selecting a next node among the potential next nodes based at least in part on the assigned scheduling priority and the topology of the graph according to the probability of each potential next node among the potential next nodes. The processor-implemented method also includes: generating a topological order of the tasks by repeating the selection of the next node.

[0008] Another aspect of the present disclosure relates to an apparatus comprising: a component for receiving a set of tasks to be performed. The apparatus also comprises: a component for representing the set of tasks in a graph comprising a plurality of nodes connected by edges. Each node corresponds to a task in the set of tasks. The apparatus further comprises: a component for assigning a scheduling priority to each node in the graph. The apparatus also comprises: a component for selecting a next node among the potential next nodes according to a probability of each potential next node among the potential next nodes based at least in part on the assigned scheduling priority and the topology of the graph. The apparatus also comprises: a component for generating a topological order of the tasks by repeating the selection of the next node.

[0009] In another aspect of the present disclosure, a non-transitory computer-readable medium having non-transitory program code recorded thereon is disclosed. The program code is executed by a processor and includes: program code for receiving a set of tasks to be performed. The program code also includes: program code for representing the set of tasks in a graph including a plurality of nodes connected by edges. Each node corresponds to a task in the set of tasks. The program code further includes: program code for assigning a scheduling priority to each node in the graph. The program code also includes: program code for selecting a next node among the potential next nodes according to the probability of each potential next node among the potential next nodes based at least in part on the assigned scheduling priority and the topology of the graph. The program code also includes: program code for generating a topological order of the tasks by repeating the selection of the next node.

[0010] Another aspect of the present disclosure relates to a device having a memory and one or more processors coupled to the memory. The processor is configured to receive a set of tasks to be performed. The processor is further configured to represent the set of tasks in a graph including a plurality of nodes connected by edges. Each node corresponds to a task in the set of tasks. The processor is further configured to assign a scheduling priority to each node in the graph. The processor is further configured to select a next node among the potential next nodes based at least in part on the assigned scheduling priority and the topology of the graph according to the probability of each potential next node in the potential next nodes. The processor is further configured to generate a topological order of the tasks by repeating the selection of the next node.

[0011] Additional features and advantages of the present disclosure will be described below. It will be appreciated by those skilled in the art that the present disclosure can be easily used as a basis for modifying or designing other structures for implementing the same purpose as the present disclosure. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features considered to be characteristic of the present disclosure, both in terms of its organization and method of operation, together with further objects and advantages, will be better understood when the following description is considered in conjunction with the accompanying drawings. However, it is to be expressly understood that each of the accompanying drawings is provided for illustration and description purposes only and is not intended as a definition of limitations of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The features, nature and advantages of the present disclosure will become more apparent when the detailed description set forth below is read in conjunction with the accompanying drawings, in which like reference numerals are correspondingly identified throughout.

[0013] Figure 1 An example implementation of a neural network using a system on a chip (SOC) including a general-purpose processor in accordance with certain aspects of the present disclosure is illustrated.

[0014] Figure 2A , Figure 2B and Figure 2C is a diagram illustrating a neural network according to aspects of the present disclosure.

[0015] Figure 2D is a diagram illustrating an exemplary deep convolutional network (DCN) according to aspects of the present disclosure.

[0016] Figure 3 is a block diagram illustrating an exemplary deep convolutional network (DCN) according to aspects of the present disclosure.

[0017] Figure 4 is a block diagram illustrating an exemplary software architecture that can modularize artificial intelligence (AI) functionality according to aspects of the present disclosure.

[0018] Figure 5 is a block diagram illustrating an example architecture for determining a topological order in accordance with aspects of the present disclosure.

[0019] Figure 6 is a diagram illustrating an example graph topology transformation according to aspects of the present disclosure.

[0020] Figure 7 is a flow chart illustrating a processor-implemented method for generating a topological order using an artificial neural network in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0021] The specific embodiments set forth below in conjunction with the accompanying drawings are intended as descriptions of various configurations and are not intended to represent the only configurations in which the described concepts may be practiced. In order to provide a comprehensive understanding of the various concepts, the specific embodiments include specific details. However, it is apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, in order to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0022] Based on the teachings, those skilled in the art will recognize that the scope of the present disclosure is intended to cover any aspect of the present disclosure, whether the aspect is implemented independently of any other aspect of the present disclosure or implemented in combination with any other aspect. For example, a device or a method may be implemented using any number of aspects stated. In addition, the scope of the present disclosure is intended to cover such a device or method that is practiced using other structures, functionality, or structures and functionality that are supplementary to or different from the various aspects of the present disclosure stated. It should be understood that any aspect of the present disclosure disclosed may be embodied by one or more elements of a claim.

[0023] The word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0024] Although specific aspects are described, numerous variations and permutations of these aspects fall within the scope of the present disclosure. Although some benefits and advantages of preferred aspects are mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses or purposes. On the contrary, various aspects of the present disclosure are intended to be widely applicable to different technologies, system configurations, networks and protocols, some of which are illustrated by way of example in the drawings and the following description of preferred aspects. The specific embodiments and drawings are merely illustrative of the present disclosure and are not limiting, and the scope of the present disclosure is defined by the appended claims and their equivalents.

[0025] Many problems in computer science may involve finding the best object sequence consistent with some priority constraints. Intuitive examples can be found in routing problems, where one goal is to find the shortest route between cities. Additionally, there may be warnings about the order in which cities should be visited (e.g., about the pickup and subsequent delivery of packages). Another example can be found in compiler pipelines, which involves finding the shortest duration for performing a set of operations. The operations to be performed (such as the cities in the previous example) may be subject to certain constraints. These constraints may come from data dependencies between operations, such as when the result of an operation is an operand in a subsequent operation. Therefore, the previous operation can be used as a priority constraint for dependent operations. In this example, the metric to be optimized may be, for example, the running time of the compiled program, the memory or other performance metrics designated as executing the program. A method for solving such problems involves formulating the problem in terms of the optimal topological order of a directed acyclic graph (DAG) that finds encoding priority constraints (e.g., execution order). However, doing so will cause a combinatorial optimization (CO) problem (e.g., np problem) that is usually computationally complex.

[0026] Conventional methods applied to CO problems may include heuristic methods, whose design involves extensive use of domain-specific and problem-specific knowledge developed across decades. Furthermore, it is time-consuming to handle such problems via heuristic strategies that are handcrafted or customized for each instance.

[0027] To address these and other challenges, aspects of the present disclosure relate to topological sorting using artificial neural networks. According to aspects of the present disclosure, an end-to-end machine learning-based method for topological sorting uses an encoder-decoder framework. The encoder can be configured as an attention-based graph neural network architecture that uses different topological transformations of a directed acyclic graph (DAG) for message passing. A DAG is a finite directed graph that does not have direct cycles. The graph may include a set of nodes connected by edges. Each node in the node may represent a task to be performed, and the edge may indicate the order in which the represented task is performed.

[0028] The node embeddings generated by the encoder of the attention-based graph neural network architecture can be converted into node priorities, which can be used by the decoder to generate a probability distribution over the topological order. In some aspects, the attention-based graph neural network architecture can be trained, for example, on a dataset of synthetically generated graphs called layered graphs.

[0029] Accordingly, attention-based graph neural networks can determine a topological order, and in some aspects, an optimal topological order. Therefore, aspects of the present disclosure can beneficially reduce memory and energy consumption. In addition, aspects of the present disclosure employ non-autoregressive techniques to parameterize the probability distribution of the topological order. That is, aspects of the present disclosure can utilize a single forward pass of a neural network to provide the topological order, rather than using an autoregressive approach in which each forward pass of the neural network is utilized to determine the topological order one node at a time. As a result, aspects of the present disclosure can improve performance (e.g., reduced memory consumption) with significantly lower runtime than autoregressive approaches.

[0030] Figure 1 An example implementation of a system on a chip (SOC) 100 is illustrated, which may include a central processing unit (CPU) 102 or a multi-core CPU configured to generate a topological order using an artificial neural network. Variables (e.g., neural signals and synaptic weights), system parameters associated with a computing device (e.g., a neural network with weights), delays, frequency bin information, and task information may be stored in a memory block associated with a neural processing unit (NPU) 108, a memory block associated with the CPU 102, a memory block associated with a graph processing unit (GPU) 104, a memory block associated with a digital signal processor (DSP) 106, a memory block 118, or may be distributed across multiple blocks. Instructions executed at the CPU 102 may be loaded from a program memory associated with the CPU 102, or may be loaded from the memory block 118.

[0031] The SOC 100 may also include additional processing blocks tailored for specific functions, such as a GPU 104, a DSP 106, a connectivity block 110 (which may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, etc.), and a multimedia processor 112 that may, for example, detect and recognize gestures. In one specific implementation, the NPU 108 is implemented in the CPU 102, the DSP 106, and / or the GPU 104. The SOC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, and / or a navigation module 120, which may include a global positioning system.

[0032] SOC 100 may be based on the ARM instruction set. In various aspects of the present disclosure, the instructions loaded into the general-purpose processor 102 may include a code for receiving a set of tasks to be performed. The general-purpose processor 102 may also include a code for representing a task in a graph including a plurality of nodes connected by edges. Each node corresponds to a task in the set of tasks. The general-purpose processor 102 may also include a code for assigning a scheduling priority to each node in the graph. The general-purpose processor 102 may also include a code for selecting a next node in a potential next node according to the probability of each potential next node in the potential next node based on the assigned scheduling priority and the topology of the graph. The general-purpose processor 102 may also include a code for generating a topological order of tasks by repeating the selection of the next node.

[0033] Deep learning architectures can perform object recognition tasks by learning to represent inputs at successively higher levels of abstraction in each layer, thereby building useful feature representations of the input data. In this way, deep learning solves a major bottleneck of traditional machine learning. Before the advent of deep learning, machine learning approaches to object recognition problems could rely heavily on human-designed features, possibly in conjunction with shallow classifiers. Shallow classifiers can be two-class linear classifiers, for example, where a weighted sum of feature vector components can be compared to a threshold to predict which class the input belongs to. Human-designed features can be templates or kernels customized for a specific problem domain by engineers with domain expertise. In contrast, while deep learning architectures can learn to represent features similar to those that human engineers might design, they do so through training. In addition, deep networks can learn to represent and recognize new types of features that humans may not have considered.

[0034] Deep learning architectures can learn hierarchies of features. For example, if presented with visual data, the first layer can learn to recognize relatively simple features in the input stream, such as edges. In another example, if presented with auditory data, the first layer can learn to recognize spectral power in specific frequencies. The second layer, taking the output of the first layer as input, can learn to recognize combinations of features, such as simple shapes for visual data or combinations of sounds for auditory data. For example, higher layers can learn to represent complex shapes in visual data or words in auditory data. Even higher layers can learn to recognize common visual objects or spoken phrases.

[0035] Deep learning architectures perform particularly well when applied to problems that have a natural hierarchical structure. For example, the classification of motorized vehicles can benefit from first learning to recognize wheels, windshields, and other features. These features can be combined in different ways at higher levels to recognize cars, trucks, and airplanes.

[0036] Neural networks can be designed to have various connectivity patterns. In a feedforward network, information is passed from a lower layer to a higher layer, where each neuron in a given layer communicates with a neuron in a higher layer. As described above, hierarchical representations can be constructed in successive layers of a feedforward network. Neural networks can also have cyclic connections or feedback (also known as top-down) connections. In a cyclic connection, the output from a neuron in a given layer can be communicated to another neuron in the same layer. The cyclic architecture can help identify patterns that span more than one input data block in the input data blocks that are delivered to the neural network in sequence. The connection from a neuron in a given layer to a neuron in a lower layer is called a feedback (or top-down) connection. When the recognition of a high-level concept can assist in discerning specific low-level features of the input, a network with many feedback connections may be helpful.

[0037] The connections between neural network layers can be fully connected or partially connected. Figure 2A An example of a fully connected neural network 202 is illustrated. In a fully connected neural network 202, a neuron in a first layer may communicate its output to each neuron in a second layer, such that each neuron in the second layer will receive input from each neuron in the first layer. Figure 2B An example of a locally connected neural network 204 is illustrated. In the locally connected neural network 204, neurons in a first layer may be connected to a limited number of neurons in a second layer. More generally, the locally connected layers of the locally connected neural network 204 may be configured such that each neuron in the layer will have the same or similar connectivity pattern, but the connection strengths may have different values ​​(e.g., 210, 212, 214, and 216). The locally connected connectivity patterns may produce spatially different receptive fields in higher layers because higher layer neurons in a given region may receive inputs that are tuned through training to properties of a limited portion of the total input to the network.

[0038] An example of a locally connected neural network is a convolutional neural network. Figure 2C An example of a convolutional neural network 206 is illustrated. The convolutional neural network 206 may be configured such that the connection strengths associated with the inputs of each neuron in the second layer are shared (e.g., 208). Convolutional neural networks may be well suited for problems where the spatial location of the inputs is meaningful.

[0039] One type of convolutional neural network is a deep convolutional network (DCN). Figure 2DA detailed example of a DCN 200 designed to recognize visual features from an image 226 input from an image capture device 230 (such as a vehicle-mounted camera) is illustrated. The DCN 200 of the current example can be trained to identify traffic signs and numbers provided on traffic signs. Of course, the DCN 200 can be trained for other tasks, such as identifying lane markings or identifying traffic lights.

[0040] The DCN 200 may be trained by supervised learning. During training, an image (such as an image 226 of a speed limit sign) may be presented to the DCN 200, and a forward pass may then be calculated to produce an output 222. The DCN 200 may include a feature extraction portion and a classification portion. Upon receiving the image 226, a convolutional layer 232 may apply a convolutional kernel (not shown) to the image 226 to generate a first set of feature maps 218. As an example, the convolutional kernel of the convolutional layer 232 may be a 5x5 kernel that generates a 28x28 feature map. In this example, because four different feature maps are generated in the first set of feature maps 218, four different convolutional kernels are applied to the image 226 at the convolutional layer 232. A convolutional kernel may also be referred to as a filter or a convolution filter.

[0041] The first feature map set 218 may be subsampled by a maximum pooling layer (not shown) to generate a second feature map set 220. The maximum pooling layer reduces the size of the first feature map set 218. That is, the size of the second feature map set 220 (such as 14x14) is smaller than the size of the first feature map set 218 (such as 28x28). The reduced size provides similar information to subsequent layers while reducing memory consumption. The second feature map set 220 may be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more sets of subsequent feature maps (not shown).

[0042] exist Figure 2D In the example of , the second feature map set 220 is convolved to generate a first feature vector 224. In addition, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature of the second feature vector 228 may include a number corresponding to a possible feature of the image 226, such as "sign", "60", and "100". A softmax function (not shown) may convert the numbers in the second feature vector 228 into probabilities. Therefore, the output 222 of the DCN 200 may be a probability that the image 226 includes one or more features.

[0043] In this example, the probability of "logo" and "60" in output 222 is higher than the probability of other numbers (such as "30", "40", "50", "70", "80", "90", and "100") in output 222. Before training, output 222 generated by DCN 200 may be incorrect. Therefore, the error between output 222 and the target output can be calculated. The target output is the ground truth value of image 226 (e.g., "logo" and "60"). The weights of DCN 200 can then be adjusted so that the output 222 of DCN 200 is closer to the target output.

[0044] To adjust the weights, the learning algorithm may calculate a gradient vector for the weights. The gradient may indicate the amount by which the error will increase or decrease when the weights are adjusted. At the top layer, the gradient may correspond directly to the value of the weights connecting the activated neurons in the penultimate layer and the neurons in the output layer. In the lower layers, the gradient may depend on the value of the weights and the calculated error gradients of the higher layers. The weights may then be adjusted to reduce the error. This way of adjusting weights may be referred to as "backward propagation" because it involves a "backward pass" through the neural network.

[0045] In practice, the error gradient of the weights may be calculated over a small number of examples so that the calculated gradient is close to the true error gradient. This approximation method may be referred to as stochastic gradient descent. Stochastic gradient descent may be repeated until the achievable error rate of the entire system stops decreasing or until the error rate reaches a target level. After learning, the DCN 200 may be presented with new images, and a forward pass through the DCN 200 may produce an output 222 that may be considered an inference or prediction of the DCN 200.

[0046] Deep belief network (DBN) is a probability model including multiple layers of hidden nodes. DBN can be used to extract hierarchical representations of training data sets. DBN can be obtained by stacking the layers of restricted Boltzmann machine (RBM). RBM is a type of artificial neural network that can learn probability distributions through input sets. Because RBM can learn probability distributions without information about the categories to which each input should be classified, RBM is generally used for unsupervised learning. Using unsupervised and supervised hybrid paradigms, the bottom RBM of DBN can be trained in an unsupervised manner and can be used as a feature extractor, while the top RBM can be trained in a supervised manner (on the joint distribution of the input and target class from the previous layer) and can be used as a classifier.

[0047] A DCN is a network of convolutional networks, configured with additional pooling and normalization layers. DCN has achieved state-of-the-art performance on many tasks. DCN can be trained using supervised learning, where both the input and output targets are known for many examples and are used to modify the weights of the network using a gradient descent method.

[0048] The DCN may be a feed-forward network. In addition, as described above, connections from neurons in the first layer of the DCN to a set of neurons in the next higher layer are shared across neurons in the first layer. The feed-forward and shared connections of the DCN may be used for fast processing. For example, the computational burden of the DCN may be much smaller than that of a similarly sized neural network that includes recurrent or feedback connections.

[0049] The processing of each layer of the convolutional network can be considered as a spatially invariant template or basis projection. If the input is first decomposed into multiple channels, such as the red, green and blue channels of a color image, the convolutional network trained on the input can be considered to be three-dimensional, with two spatial dimensions along the axis of the image and the third dimension capturing color information. The output of the convolutional connection can be considered to form a feature map in a subsequent layer, each element in which receives input from a certain range of neurons in the previous layer (e.g., feature map 218) and from each channel in the multiple channels. The values ​​in the feature map can be further processed with nonlinearity (such as correction, max(0,x)). The values ​​from adjacent neurons can be further pooled, which corresponds to downsampling and can provide additional local invariance and dimensionality reduction. Normalization corresponding to whitening can also be applied by lateral inhibition between neurons in the feature map.

[0050] The performance of deep learning architectures can increase as more labeled data points become available or as computing power increases. Modern deep neural networks are often trained with computing resources that are thousands of times greater than what was available to a typical researcher just fifteen years ago. New architectures and training paradigms can further improve the performance of deep learning. Rectified linear units can reduce the training problem known as vanishing gradients. New training techniques can reduce overfitting, allowing larger models to achieve better generalization. Encapsulation techniques can extract data within a given receptive field and further improve overall performance.

[0051] Figure 3 is a block diagram illustrating a DCN 350. Based on connectivity and weight sharing, the deep convolutional network 350 may include multiple different types of layers. Figure 3 As shown, the deep convolutional network 350 includes convolutional blocks 354A, 354B. Each of the convolutional blocks 354A, 354B may be configured with a convolutional layer (CONV) 356, a normalization layer (LNorm) 358, and a maximum pooling layer (MAX POOL) 360. Although only two convolutional blocks 354A, 354B are shown, the present disclosure is not limited thereto, but instead, any number of convolutional blocks 354A, 354B may be included in the deep convolutional network 350 according to design preferences.

[0052] The convolution layer 356 may include one or more convolution filters that may be applied to the input data to generate a feature map. The normalization layer 358 may normalize the output of the convolution filter. For example, the normalization layer 358 may provide whitening or lateral suppression. The maximum pooling layer 360 may provide spatial downsampling aggregation to achieve local invariance and dimensionality reduction.

[0053] For example, a parallel filter bank of a deep convolutional network may be loaded on SOC 100 (e.g., Figure 1 ) on the CPU 102 or GPU 104 of the SOC 100 to achieve high performance and low power consumption. In an alternative embodiment, the parallel filter bank can be loaded onto the DSP 106 or ISP 116 of the SOC 100. In addition, the deep convolutional network 350 can access other processing blocks that may exist on the SOC 100, such as the sensor processor 114 and the navigation module 120 dedicated to sensors and navigation, respectively.

[0054] The deep convolutional network 350 may also include one or more fully connected layers 362 (FC1 and FC2). The deep convolutional network 350 may also include a logistic regression (LR) layer 364. There are weights (not shown) to be updated between each layer 356, 358, 360, 362, 364 of the deep convolutional network 350. The output of each of these layers (e.g., 356, 358, 360, 362, 364) can be used as an input to a subsequent layer of these layers (e.g., 356, 358, 360, 362, 364) in the deep convolutional network 350 to learn a hierarchical feature representation from the input data 352 (e.g., image, audio, video, sensor data, and / or other input data) supplied at the first convolutional block 354A. The output of the deep convolutional network 350 is a classification score 366 for the input data 352. The classification score 366 can be a set of probabilities, where each probability is a probability that the input data includes a feature from a feature set.

[0055] Figure 4 400 is a block diagram illustrating an exemplary software architecture 400 that can modularize artificial intelligence (AI) functions. According to aspects of the present disclosure, using the architecture 400, a SOC 420 (which can be similar to Figure 1 Various processing blocks (e.g., CPU 422, DSP 424, GPU 426, and / or NPU 428) of SoC 100 support the application of neural topological sorting of AI application 402. Architecture 400 may be included in a computing device such as a smart phone, for example.

[0056] The AI ​​application 402 may be configured to call functions defined in the user space 404, which may, for example, provide detection and recognition of scenes indicating the location where the computing device (including the architecture 400) is currently operating. For example, the AI ​​application 402 may configure microphones and cameras differently depending on whether the identified scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. The AI ​​application 402 may make a request for compiled program code associated with a library defined in the AI ​​function application programming interface (API) 406. The request may ultimately rely on the output of a deep neural network configured to provide an inferred response based on, for example, video and positioning data.

[0057] The runtime engine 408, which may be compiled code of the runtime framework, may further be accessible to the AI ​​application 402. The AI ​​application 402 may cause the runtime engine 408 to request inference, for example, at a specific time interval or triggered by an event detected by a user interface of the AI ​​application 402. Upon causing the runtime engine 408 to provide an inference response, the runtime engine may then transmit a signal to an operating system (such as a kernel 412) in an operating system (OS) space 410 running on the SOC 420. In some examples, the kernel 412 may be a LINUX kernel. The operating system may then cause continuous quantization relaxation to be performed on a CPU 422, a DSP 424, a GPU 426, an NPU 428, or some combination thereof. The CPU 422 may be directly accessible by the operating system, while other processing blocks may be accessed through drivers, such as drivers 414, 416, or 418 for the DSP 424, the GPU 426, or the NPU 428, respectively. In an illustrative example, the deep neural network may be configured to run on a combination of processing blocks such as CPU 422 , DSP 424 , and GPU 426 , or may run on NPU 428 .

[0058] Application 402 (e.g., an AI application) can be configured to call functions defined in user space 404, which can, for example, provide detection and recognition of scenes indicating the current operating location of the device. For example, application 402 can configure microphones and cameras differently depending on whether the identified scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. Application 402 can make a request to compiled program code associated with a library defined in a scene detection application programming interface (API) 406 to provide an estimate of the current scene. The request can ultimately rely on the output of a differential neural network configured to provide scene estimates based on, for example, video and positioning data.

[0059] The runtime engine 408 (which can be the compiled code of the runtime framework) can be further accessible by the application 402. For example, the application 402 can cause the runtime engine to request scene estimation at specific time intervals or triggered by events detected by the user interface of the application. When causing the runtime engine to estimate a scene, the runtime engine can in turn transmit a signal to the operating system 410 (such as the Linux kernel 412) running on the SOC 420. The operating system 410 can in turn cause computations to be performed on the CPU 422, DSP 424, GPU 426, NPU 428, or some combination thereof. The CPU 422 can be directly accessed by the operating system, while the other processing blocks can be accessed through drivers (such as drivers 414 - 418 for the DSP 424, GPU 426, or NPU 428 respectively). In an exemplary example, the differential neural network can be configured to run on a combination of processing blocks (such as the CPU 422 and GPU 426), or can run on the NPU 428.

[0060] As described, aspects of the present disclosure relate to topological sorting using artificial neural networks. According to aspects of the present disclosure, precedence constraints of a task sequence can be represented, for example, via a graph such as a directed acyclic graph. A directed graph is a tuple G = (V, E), where V is a set of vertices, and is a set of edges between the vertices. A tuple is a finite ordered list or sequence of elements. A cycle is a sequence of edges i → … → i having at least one directed edge. Thus, a directed acyclic graph (DAG) is a finite directed graph that does not have a direct cycle. The graph can include a set of nodes connected by edges. Each of the nodes can represent a task to be executed, and the edges can indicate the order for executing the represented tasks.

[0061] A partial order is an irreflexive transitive relation < between certain pairs of the set V. The pairs (x, u) ∈ V × V related to < are called comparable, otherwise they are called incomparable. If there is a directed path from node x to node y, the DAG G = (V, E) can be mapped to a partially ordered set (V, <), where x < y. Multiple DAGs can be mapped to the same partial order. For example, DAGs with a vertex set {x, y, z} and edge sets E = {x → y, y → z} and E' = {x → y, y → z, x → z}, where s → t represents a directed edge from s to t, correspond to the same partial order x < y < z. The transitive closure (TC) of a DAG can be defined as the graph in which most edges have the same underlying partial order, such that there is a directed edge (x, y) whenever x < y. Conversely, the transitive reduction (TR) can be defined as the graph with the fewest edges that results in the same partial order. The order induced by a DAG is represented by < G represents.

[0062] The topological order or classification of a DAG G can be considered as a bijection σ∶V→{1,…,|V|}, such that whenever hour, The set of topological orders of G is a subset of the set of permutations of vertices that respects < G The total order of is consistent with that of (called a linear extension of the partial order).

[0063] Deciding on the scheduling of operations in a computational graph representing a neural network is a central problem in compilers. A DAG can be associated with a computational graph in a way that nodes represent operations (“ops”) and incoming / outgoing edges represent operands / results of these operations. Whenever an operation is executed, the input to that operation is stored in memory, and memory for the output must be allocated. Therefore, each node of the DAG carries a label The label specifies the memory to store the output of the operation. The first step in scheduling the DAG is to identify the topological order to execute the operations. A compiler for edge devices with limited memory may aim to choose a topological order that minimizes the peak memory footprint. In some aspects, the topological order may be determined to reduce the peak local memory usage. For example, this task can be formulated as the following combinatorial optimization problem with respect to the labeled DAG G = (V, E, m):

[0064]

[0065] where the definition

[0066]

[0067] where the memory usage at time t is determined by the memory usage of the outputs that have not been consumed by downstream operations at time t-1. t-1 Adding the memory usage of the output of operation σ(t) gives the value I t Then through It is obtained by subtracting the memory cost of nodes whose outgoing edges are only connected to already scheduled nodes (e.g., nodes whose outputs are only used by already scheduled operations). Naturally, I0=0,

[0068] Figure 55 is a block diagram illustrating an example architecture 500 for determining topological order according to aspects of the present disclosure. The architecture 500 includes an encoder 502 and a decoder 504. The encoder 502 can be configured as an attention-based graph neural network. The encoder 502 can include a set of multi-head attention layers that can be used to derive an embedding for each node of the graph G 516. For example, the graph G 516 can include a DAG. The node embeddings can be supplied to the decoder 504 and can be used to generate a distribution in a sequence space. For example, an inference method such as sampling inference, greedy inference, or beam search can be used to convert the distribution to a sequence.

[0069] Graph neural networks (GNNs) can encode scheduling problems via embeddings of the nodes of a graph G. GNN architectures can operate by updating these embeddings via aggregation of “messages” transmitted from other nodes, typically in the form of some function of their own embeddings.

[0070] According to various aspects of the present disclosure, the encoder 502 obtains a vector of input features And through the node-by-node linear transformation Generate an initial node embedding h(0). Subsequently, a series of L attention layers, each of which includes a multi-head attention (MHA) sublayer, are followed by a node-based multilayer perceptron (MLP) 506 that updates these embeddings. A topology-inductive bias can be applied to the embedding updates by having separate groups of one or more attention heads (e.g., 508a-508g) be masked by each of the following graphs induced by the original graph G (516). For example, Figure 5 As shown in the example of , MHAs 508a-508d are shaded to indicate how the MHAs can operate on forward versions of topological transformations 510a-d, respectively, of graph G. On the other hand, MHAs 508e-508g are not shaded to indicate how the MHAs can operate on reverse versions of topological transformations 510a-510c, respectively, of graph G.

[0071] In doing so, the encoder 502 may generate node embeddings to convey information about different topological transformations of the graph G (e.g., 516). The topological transformation may include an initial graph G (e.g., 516), transitive reductions (e.g., 510a), transitive closures (e.g., 510c), and incomparable node pairs (e.g., 510d). A transitive reduction (TR) may be performed to produce a directed graph (e.g., 510c) obtained by removing TR edges. The resulting directed graph (e.g., 510c) may be generated by removing as many edges as possible without affecting the reachability relationships (e.g., partial order) between nodes from the graph G: G\E TR(G). The transitive closure transformation aims to add as many edges as possible without affecting the reachability relations (e.g., partial order) between nodes. Applying the transitive closure (TC) transformation produces a directed graph obtained by removing the edges of graph G from its TC: TC(G)\E. The incomparable node pair transformation retains all nodes that do not have precedence relations. Applying the incomparable node pair transformation, an undirected graph can be obtained by connecting all incomparable node pairs.

[0072] Additionally, the topological transformation may include the inversion of each of the graphs resulting from the TR transformation and the TC transformation. The inverted or reversed versions of the graphs (510a-510c) may be obtained by flipping the edges (eg, the direction of the arrows connecting the nodes) of each graph 510a-510c.

[0073] By adding these topology transformation graphs (e.g., 510a-510d) and the inverse of the topology transformation graphs 520a-520c, a fully connected graph with respect to the node set V can be obtained, in which all nodes are connected to all nodes. Then, effectively, the propagation rule of the encoder 502 can be such that

[0074]

[0075] Among them, M j is a mask that ensures that head j (e.g., MHA 508a-508g) is connected only to the graph to which it is assigned (e.g., topology transformation graph 510a-d). Layer normalization can be applied to MHA (e.g., 508a-508g) and MLP (e.g., 506a-506b) inputs. The number of attention heads (e.g., MHA 508a-508g) assigned to each topology transformation graph 510a-d can be chosen independently (e.g., setting it to zero means not passing messages along the edges of the corresponding graph), or the parameters can be tied or shared between different MHAs (e.g., 508a-508g). Each of the nodes may affect the representation of each other, while also injecting strong inductive biases based on the structure of the graph G (e.g., 516).

[0076] The decoder 504 may derive a random policy p(σ|G) on a valid topological order of the graph G. For example, the random policy p(σ|G) may be given by:

[0077]

[0078] The complete sequence can be sampled by autoregressively picking new nodes at each step. However, this is very time-consuming because when a neural network (NN) is used as p θ When using a function approximator for , it also requires performing |V| calls to the NN, which limits its feasibility to relatively small graphs due to the amount of computation employed.

[0079] Accordingly, to scale to large graphs, a non-autoregressive (NAR) approach can be employed that decouples the number of NN calls from the graph size. Instead, a non-scheduling probability may be assigned to a node. The priority of node i may be derived by passing its final embedding through the MLP 506:

[0080]

[0081] For example, Figure 5 As shown, the outputs of MHAs 508a-508g may be supplied to MLP 506a. MLP 506a may process the outputs according to a propagation rule (e.g., as shown in Equations 4 and 5) to generate encoder outputs Encoder output MLP 506b may be used to process to determine the scheduling priority assigned to each node of graph G. For example, graph 512 has bars representing the scalar ordering priority of each node. The size of the bar may indicate the relative scheduling priority of each node. Decoder 504 processes the scalar scheduling priority of each node to determine sequence 514.

[0082] Advantageously, these priorities can be assigned using a single NN inference. A sequence or topological order can be constructed by adding new nodes at each step. Given a partial sequence σ 1:i-1 , due to both the graph topology and the choices made earlier in the sequence, the next node can only be selected from a subset S of schedulable nodes (σ 1:i-1 , G). Then, the distribution of the next node to be added in step i is given as follows:

[0083]

[0084] From the distribution p(σ t |σ 1:t-1 ,h,G) in the partial sequence) can be determined using the following formula, for example:

[0085] 1. Greedy search: At each step t, select the one with the highest probability (e.g. ) node.

[0086] 2. Sampling inference: At each step t, from the next node distribution (e.g., σ t ~p(·|σ 1:t-1 ,h,G)) sampling.

[0087] 3. Beam search with state folding: The partial sequences are extended by using a beam search method where the score function is the total probability of the partial sequences. The beam search method can be enhanced using the following observation: given two partial sequences under consideration, namely σ 1:tand such that both have so far scheduled the same set of nodes (e.g., but in different orders), and Then, some sequences can be ignored and only part of the sequence σ is used in the beam search 1:t This is because both partial sequences schedule the same set of remaining nodes, and hence the set of future memory costs for σ 1:t and Both are the same, but the current peak memory cost is So, in terms of the minimum achievable peak memory usage, σ 1:t Better than

[0088] The architecture 500 may induce a distribution p of a set of topological orders for a given DAG G. θ (σ|G). The expected cost incurred can be given by Given. Architecture 500 can be implemented by minimizing the cost via gradient descent using the REINFORCE gradient estimator To train, as follows:

[0089]

[0090] where b(G) is a baseline that aims to reduce the variance of the estimator. The baseline b(G) can be set equal to the cost of the greedy rollout of the baseline policy on the graph G:

[0091]

[0092] Figure 6 is a diagram illustrating an example graph topology transformation according to aspects of the present disclosure. Figure 6 , a fully connected graph 602 is shown. The fully connected graph 602 includes a set of 8 nodes connected in an all-to-all manner. For example, each of these nodes may represent a task (e.g., an operation) to be performed. The edges connecting the nodes of the fully connected graph 602 may indicate the relationship between the nodes (e.g., order). As described, information about the graph topology may be included in the encoder (e.g., Figure 5 502). The fully connected graph 602 can be decomposed into subgraphs (e.g., graphs including a subset of the edges of the fully connected graph 602) via topological transformations 604a-604g. Each of the subgraphs can capture a different type of node-level interaction. Conversely, the subgraphs obtained from the transformations 604a-604g can be summed to produce the fully connected graph 602.

[0093] In some aspects, the transformer architecture can operate on each subgraph. Figure 5As shown, an MHA (eg, 508e-508g) may be assigned to each subgraph (eg, topology transformation graphs 510a-510d). Each transformer may be independent. In some aspects, transformers may share parameters.

[0094] The subgraph formed by applying topological transformations 604a-604g may be used to determine nodes of the execution graph (e.g., see Figure 5 The priority of node 512).

[0095] Figure 7 is a flow chart illustrating a processor-implemented method 700 for generating a topological order using an artificial neural network (ANN) according to aspects of the present disclosure. In some aspects, for example, the processor-implemented method 700 may be executed by a processor such as the CPU 102 or the NPU 108. Figure 7 As shown, at block 702, a processor receives a set of tasks to be performed. In some aspects, these tasks may include, for example, operations in a computer program. For example, the tasks may be performed by a compiler.

[0096] At block 704, the processor represents the task set in a graph comprising a plurality of nodes connected by edges. Each node corresponds to a task in the task set. For example, as shown in FIG. Figure 6 As described above, a set of tasks may be represented in a graph (e.g., graph 602a). Graph 602 may be, for example, a DAG. Graph 602 may include a plurality of nodes connected by edges.

[0097] At block 706, the processor assigns a scheduling priority to each node in the graph. Figure 5 As mentioned above, scheduling priority The non-scheduling probability may be assigned to the node (eg, 512). In addition, the assigned scheduling priority may be based on the subgraph formed by applying the topological transformation (eg, see Figure 5 In some aspects, the scheduling priorities of the nodes of the graph may be assigned in a single inference.

[0098] At block 708, the processor selects a next node among the potential next nodes based at least in part on the assigned scheduling priority and the topology of the graph according to the probability of each of the potential next nodes. Figure 5 As described, the next node (eg, node 514) may be selected based on a greedy search of a probability distribution of potential next nodes, sampling from a probability distribution of potential next nodes, or a beam search process.

[0099] At block 710, the processor generates a topological order of tasks by repeating the selection of the next node. Figure 5As described, the nodes of the graph may be ranked based on the assigned priorities to generate a topological order.

[0100] Example aspects

[0101] Aspect 1: A processor-implemented method comprising: receiving a set of tasks to be executed; representing the set of tasks in a graph comprising a plurality of nodes connected by edges, each node corresponding to a task in the set of tasks; assigning a scheduling priority to each node in the graph; selecting a next node among the potential next nodes based at least in part on the assigned scheduling priority and the topology of the graph according to the probability of each potential next node among the potential next nodes; and generating a topological order of the tasks by repeating the selection of the next node.

[0102] Aspect 2: The processor-implemented method according to aspect 1, wherein the set of tasks comprises a set of operations to be processed by a compiler.

[0103] Aspect 3: The processor-implemented method according to Aspect 1 or 2 further includes: selecting the next node based on one of the following: a greedy search of the probability distribution of the potential next node, sampling from the probability distribution of the potential next node, or a beam search process.

[0104] Aspect 4: The processor-implemented method according to any one of Aspects 1 to 3, further comprising: assigning the scheduling priorities to the plurality of nodes via an artificial neural network (ANN) using a single inference.

[0105] Aspect 5: The processor-implemented method according to any one of aspects 1 to 4, wherein the graph comprises a directed acyclic graph.

[0106] Aspect 6: The processor-implemented method according to any one of aspects 1 to 5, wherein the scheduling priority is assigned based on one or more topology changes.

[0107] Aspect 7: The processor-implemented method according to any one of Aspects 1 to 6, further comprising: executing the set of tasks according to the topological order.

[0108] Aspect 8: A device comprising: a memory; and at least one processor coupled to the memory, the at least one processor being configured to: receive a set of tasks to be executed; represent the tasks in a graph comprising a plurality of nodes connected by edges, each node corresponding to a task in the set of tasks; assign a scheduling priority to each node in the graph; select a next node among the potential next nodes based at least in part on the assigned scheduling priority and the topology of the graph according to the probability of each potential next node among the potential next nodes; and generate a topological order of the tasks by repeating the selection of the next node.

[0109] Aspect 9: The apparatus according to Aspect 8, wherein the task comprises a set of operations to be processed by a compiler.

[0110] Aspect 10: An apparatus according to Aspect 8 or 9, wherein the at least one processor is further configured to: select the next node based on one of: a greedy search of the probability distribution of the potential next node, sampling from the probability distribution of the potential next node, or a beam search process.

[0111] Aspect 11: The apparatus according to any one of aspects 8 to 10, wherein the at least one processor is further configured to: assign the scheduling priorities to the plurality of nodes using a single inference.

[0112] Aspect 12: The apparatus according to any one of aspects 8 to 11, wherein the graph comprises a directed acyclic graph.

[0113] Aspect 13: The apparatus according to any one of aspects 8 to 12, wherein the at least one processor is further configured to: assign the scheduling priorities to the plurality of nodes based on one or more topology changes.

[0114] Aspect 14: The apparatus according to any one of aspects 8 to 13, wherein the at least one processor is further configured to: execute the set of tasks according to the topological order.

[0115] Aspect 15: A non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising: program code for receiving a set of tasks to be executed; program code for representing the tasks in a graph comprising a plurality of nodes connected by edges, each node corresponding to a task in the set of tasks; program code for assigning a scheduling priority to each node in the graph; program code for selecting a next node among the potential next nodes based at least in part on the assigned scheduling priority and the topology of the graph according to the probability of each potential next node among the potential next nodes; and program code for generating a topological order of the tasks by repeating the selection of the next node.

[0116] Aspect 16: The non-transitory computer-readable medium of aspect 15, wherein the task comprises a set of operations to be processed by a compiler.

[0117] Aspect 17: The non-transitory computer-readable medium according to Aspect 15 or 16 further includes: program code for selecting the next node via an artificial neural network (ANN) based on one of the following: a greedy search of the probability distribution of the potential next node, sampling the probability distribution of the potential next node, or a beam search process.

[0118] Aspect 18: The non-transitory computer-readable medium according to any one of aspects 15 to 17, further comprising: program code for assigning the scheduling priorities to the plurality of nodes via an artificial neural network (ANN) using a single inference.

[0119] Aspect 19: The non-transitory computer-readable medium of any one of Aspects 15 to 18, wherein the graph comprises a directed acyclic graph.

[0120] Aspect 20: The non-transitory computer-readable medium according to any one of aspects 15 to 19, further comprising: program code for assigning the scheduling priorities to the plurality of nodes based on one or more topology changes.

[0121] Aspect 21: The non-transitory computer-readable medium according to any one of Aspects 15 to 20, further comprising: program code for executing the set of tasks according to the topological order.

[0122] Aspect 22: A device comprising: a component for receiving a set of tasks to be executed; a component for representing the tasks in a graph including a plurality of nodes connected by edges, each node corresponding to a task in the set of tasks; a component for assigning a scheduling priority to each node in the graph; a component for selecting a topological order of the tasks by repeating the selection of a next node; and a component for generating the topological order of the tasks by repeating the selection of the next node.

[0123] Aspect 23: The apparatus according to Aspect 22, wherein the task comprises a set of operations to be processed by a compiler.

[0124] Aspect 24: The apparatus according to Aspect 22 or 23 further includes: a component for selecting the next node via an artificial neural network (ANN) based on one of the following: a greedy search of the probability distribution of the potential next node, sampling from the probability distribution of the potential next node, or a beam search process.

[0125] Aspect 25: The apparatus according to any one of Aspects 22 to 24, further comprising: a component for assigning the scheduling priorities to the plurality of nodes using a single inference.

[0126] Aspect 26: The apparatus according to any one of Aspects 22 to 25, wherein the graph comprises a directed acyclic graph.

[0127] Aspect 27: The apparatus according to any one of Aspects 22 to 26, further comprising: a component for assigning the scheduling priorities to the plurality of nodes based on one or more topology changes.

[0128] Aspect 28: The apparatus according to any one of Aspects 22 to 27, further comprising: a component for executing the set of tasks according to the topological order.

[0129] In one aspect, the receiving means, indicating means, assigning means, selecting means, generating means, executing means, and / or determining means may be the GPU 104, a program memory associated with the GPU 104, the fully connected layer 362, the NPU 428, and / or the routing connection processing unit 216 configured to perform the recited functions. In another configuration, the aforementioned means may be any module or any device configured to perform the functions recited by the aforementioned means.

[0130] The various operations of the above methods may be performed by any suitable components capable of performing the corresponding functions. These components may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. In general, where operations are illustrated in the accompanying drawings, these operations may have corresponding paired components plus functional components with similar numbers.

[0131] As used, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, database, or another data structure), ascertaining, etc. Additionally, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. Furthermore, "determining" may include resolving, selecting, choosing, establishing, etc.

[0132] As used, a phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc.

[0133] The various illustrative logical blocks, modules, and circuits described in conjunction with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described. A general purpose processor may be a microprocessor, but in an alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0134] The steps or algorithms of the methods described in conjunction with the present disclosure may be directly embodied in hardware, software modules executed by a processor, or a combination of the two. The software module may be located in any form of storage medium known in the art. Some examples of usable storage media include random access memory (RAM), read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs, and the like. The software module may include a single instruction, perhaps multiple instructions, and may be distributed over several different code segments, distributed between different programs, and distributed across multiple storage media. The storage medium may be coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative solution, the storage medium may be integral with the processor.

[0135] The disclosed methods include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0136] The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may include a processing system in a device. The processing system may be implemented using a bus architecture. Depending on the specific application and overall design constraints of the processing system, the bus may include any number of interconnecting buses and bridges. The bus may link various circuits together, including a processor, a machine-readable medium, and a bus interface. The bus interface may be used to connect a network adapter, etc., to the processing system via the bus. The network adapter may be used to implement signal processing functions. For some aspects, a user interface (e.g., a keypad, a display, a mouse, a joystick, etc.) may also be connected to the bus. The bus may also link various other circuits, such as timing sources, peripheral devices, voltage regulators, power management circuits, etc., which are well known in the art and will not be described further.

[0137] The processor may be responsible for managing the bus and general processing, including executing software stored on the machine-readable medium. The processor may be implemented using one or more general-purpose processors and / or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuits that can execute software. Software should be broadly interpreted as meaning instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or other. By way of example, a machine-readable medium may include a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a disk, an optical disk, a hard disk drive, or any other suitable storage medium, or any combination thereof. The machine-readable medium may be embodied in a computer program product. The computer program product may include packaging materials.

[0138] In hardware implementation, machine-readable media can be a part of a processing system separated from a processor. However, as will be readily appreciated by those skilled in the art, machine-readable media or any part thereof can be outside a processing system. By way of example, machine-readable media can include a transmission line, a carrier wave modulated by data, and / or a computer product separated from a device, all of which can be accessed by a processor through a bus interface. Alternatively or in addition thereto, machine-readable media or any part thereof can be integrated into a processor, such as with a cache and / or a general register stack. Although the various components discussed can be described as having specific locations, such as local components, they can also be configured in various ways, such as certain components being configured as a part of a distributed computing system.

[0139] The processing system can be configured as a general processing system having one or more microprocessors providing processor functionality and an external memory providing at least a portion of a machine-readable medium, all of which are linked together with other supporting circuit systems through an external bus architecture. Alternatively, the processing system may include one or more neuromorphic processors for implementing the described neuron model and neural system model. As another alternative, the processing system may be implemented with an application specific integrated circuit (ASIC) having a processor, a bus interface, a user interface, support circuits, and at least a portion of a machine-readable medium integrated in a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuits, or circuits capable of performing the various functionalities described throughout this disclosure. Those skilled in the art will recognize how to best implement the functionality of the processing system depending on the specific application and the overall design constraints imposed on the entire system.

[0140] The machine-readable medium may include multiple software modules. These software modules include instructions that cause the processing system to perform various functions when executed by the processor. The software modules may include a sending module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, when a triggering event occurs, the software module may be loaded from a hard drive into a RAM. During the execution of the software module, the processor may load some of the instructions into a cache to increase access speed. Then one or more cache lines may be loaded into a general register stack for execution by the processor. When the functionality of a software module is mentioned below, it will be understood that such functionality is implemented by the processor when executing instructions from the software module. In addition, it should be understood that various aspects of the present disclosure produce improvements in the functionality of a processor, a computer, a machine, or other systems that implement such aspects.

[0141] If implemented in software, each function can be stored on or sent by a computer-readable medium as one or more instructions or codes.Computer-readable media includes both computer storage media and communication media, including any medium that promotes the transfer of computer programs from one place to another.Storage media can be any available medium that can be accessed by a computer.By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of an instruction or data structure and can be accessed by a computer.Additionally, any connection is also appropriately referred to as a computer-readable medium.For example, if software is sent from a website, a server, or other remote sources using a coaxial cable, an optical cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwaves, the coaxial cable, the optical cable, the twisted pair, the DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Optical disks, where magnetic disks typically reproduce data magnetically, and optical disks reproduce data optically with lasers. Thus, in some aspects, computer-readable media may include non-transitory computer-readable media (e.g., tangible media). Additionally, for other aspects, computer-readable media may include transient computer-readable media (e.g., signals). Combinations of the above should also be included within the scope of computer-readable media.

[0142] Thus, some aspects may include a computer program product for performing the operations presented. For example, such a computer program product may include a computer-readable medium having stored (and / or encoded) thereon instructions that can be executed by one or more processors to perform the described operations. For some aspects, the computer program product may include packaging materials.

[0143] In addition, it should be understood that the modules and / or other appropriate components for performing the described methods and techniques can be downloaded and / or otherwise obtained by the user terminal and / or base station when applicable. For example, such a device can be coupled to a server to facilitate the transfer of components for performing the described methods. Alternatively, the various methods described can be provided via a storage component (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or a floppy disk, etc.) so that once the storage device is coupled to or provided to the user terminal and / or base station, the device can obtain the various methods. In addition, any other suitable technology suitable for providing the described methods and techniques to the device can be used.

[0144] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A processor-implemented method, comprising: Receive a collection of tasks to be performed; representing the set of tasks in a graph comprising a plurality of nodes connected by edges, each node corresponding to a task in the set of tasks; assigning a scheduling priority to each node in the graph; selecting a next node among the potential next nodes based at least in part on the assigned scheduling priority and a topology of the graph according to a probability of each of the potential next nodes; as well as A topological order of the tasks is generated by repeating the selection of the next node. 2 . The processor-implemented method of claim 1 , wherein the set of tasks comprises a set of operations to be processed by a compiler.

3. The processor-implemented method of claim 1 , further comprising: The next node is selected based on one of: a greedy search of a probability distribution of the potential next nodes, sampling from the probability distribution of the potential next nodes, or a beam search process.

4. The processor-implemented method of claim 1 , further comprising: The scheduling priorities are assigned to the plurality of nodes via an artificial neural network (ANN) using a single inference.

5. The processor-implemented method of claim 1, wherein the graph comprises a directed acyclic graph. 6 . The processor-implemented method of claim 1 , wherein the scheduling priority is assigned based on one or more topology changes.

7. The processor-implemented method of claim 1 , further comprising: The set of tasks is executed according to the topological order.

8. An apparatus comprising: Memory; and at least one processor, the at least one processor coupled to the memory, the at least one processor configured to: Receive a collection of tasks to be performed; representing the tasks in a graph comprising a plurality of nodes connected by edges, each node corresponding to a task in the set of tasks; assigning a scheduling priority to each node in the graph; selecting a next node among the potential next nodes based at least in part on the assigned scheduling priority and a topology of the graph according to a probability of each of the potential next nodes; as well as A topological order of the tasks is generated by repeating the selection of the next node.

9. The apparatus of claim 8, wherein the task comprises a set of operations to be processed by a compiler.

10. The apparatus of claim 8, wherein the at least one processor is further configured to select the next node based on one of: a greedy search of a probability distribution of the potential next nodes, sampling from the probability distribution of the potential next nodes, or a beam search process.

11. The apparatus of claim 8, wherein the at least one processor is further configured to assign the scheduling priorities to the plurality of nodes using a single inference.

12. The apparatus of claim 8, wherein the graph comprises a directed acyclic graph.

13. The apparatus of claim 8, wherein the at least one processor is further configured to assign the scheduling priorities to the plurality of nodes based on one or more topology changes.

14. The apparatus of claim 8, wherein the at least one processor is further configured to: execute the set of tasks according to the topological order.

15. A non-transitory computer readable medium having program code recorded thereon, the program code being executed by a processor and comprising: Program code for receiving a set of tasks to be performed; program code for representing the tasks in a graph comprising a plurality of nodes connected by edges, each node corresponding to a task in the set of tasks; program code for assigning a scheduling priority to each node in said graph; program code for selecting a next node among the potential next nodes based at least in part on the assigned scheduling priority and a topology of the graph according to a probability of each of the potential next nodes; and Program code for generating a topological order of the tasks by repeating the selecting of the next node.

16. The non-transitory computer readable medium of claim 15, wherein the task comprises a set of operations to be processed by a compiler.

17. The non-transitory computer readable medium of claim 15, further comprising: Program code for selecting the next node via an artificial neural network (ANN) based on one of: a greedy search of a probability distribution of the potential next nodes, sampling the probability distribution of the potential next nodes, or a beam search process.

18. The non-transitory computer readable medium of claim 15, further comprising: Program code for assigning the scheduling priorities to the plurality of nodes via an artificial neural network (ANN) utilizing a single inference.

19. The non-transitory computer-readable medium of claim 15, wherein the graph comprises a directed acyclic graph.

20. The non-transitory computer readable medium of claim 15, further comprising: Program code for assigning the scheduling priorities to the plurality of nodes based on one or more topology changes.

21. The non-transitory computer readable medium of claim 15, further comprising: Program code for executing the set of tasks according to the topological order.

22. An apparatus comprising: A component for receiving a collection of tasks to be performed; means for representing the tasks in a graph comprising a plurality of nodes connected by edges, each node corresponding to a task in the set of tasks; means for assigning a scheduling priority to each node in said graph; means for selecting a topological order of said tasks by repeating the selection of a next node; and Means for generating the topological order of the tasks by repeating the selecting of the next node.

23. The apparatus of claim 22, wherein the task comprises a set of operations to be processed by a compiler.

24. The apparatus of claim 22, further comprising: Means for selecting the next node via an artificial neural network (ANN) based on one of: a greedy search of a probability distribution of the potential next nodes, sampling from the probability distribution of the potential next nodes, or a beam search process.

25. The apparatus of claim 22, further comprising: Means for assigning the scheduling priorities to the plurality of nodes using a single inference.

26. The apparatus of claim 22, wherein the graph comprises a directed acyclic graph.

27. The apparatus of claim 22, further comprising: Means for assigning the scheduling priorities to the plurality of nodes based on one or more topology changes.

28. The apparatus of claim 22, further comprising: Means for executing said set of tasks according to said topological order.

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