Multilayer ceramic capacitor with ultra wide band performance

Abstract

A broadband multilayer ceramic capacitor may include a first external terminal and a second external terminal. The first portion of the first external terminal may be spaced apart from the first portion of the second external terminal by a first external terminal spacing distance. The first active electrode layer may include a rectangular first active electrode connected with a first external terminal. The second active electrode layer may include a rectangular second active electrode connected with a second external terminal. An outermost active electrode layer closest to an outer surface of the capacitor may be spaced apart from the outer surface by an outermost active-to-surface distance. The ratio of the capacitor thickness in the Z-direction to the outermost layer active-to-surface distance may be 1.1 or more. The ratio of the capacitor length in the longitudinal direction to the first external terminal spacing distance may be 15 or more.

Description

[0001] Related Applications

[0002] This application is based on and claims priority to the U.S. Provisional Patent Application Serial No. 63 / 341,000, filed on May 12, 2022, which is incorporated herein by reference. Background Art

[0003] The diversity of modern technology applications has created a demand for efficient electronic components and integrated circuits used therein. Capacitors are essential components for filtering, coupling, bypassing, and other aspects of such modern applications, which can include wireless communications, alarm systems, radar systems, circuit switching, matching networks, and many other applications. The rapid increase in speed and packaging density of integrated circuits has particularly required advances in coupling capacitor technology. When high-capacitance coupling capacitors are subjected to the high frequencies of many current applications, performance characteristics become increasingly important. Since capacitors are essential for such a wide range of applications, the accuracy and efficiency of capacitors are extremely important. Therefore, many specific aspects of capacitor design have become the focus of improving their performance characteristics. Summary of the invention

[0004] According to one embodiment of the present invention, a broadband multilayer ceramic capacitor may include: a monolithic body including a plurality of dielectric layers stacked in a Z direction, and the monolithic body may have a first end, the first end being opposite to the second end. A first external terminal may be disposed along the first end of the monolithic body. The first external terminal may include a first portion extending along an outer surface of the monolithic body. The second external terminal may be disposed along the second end of the monolithic body. The second external terminal may include a first portion extending along the outer surface of the monolithic body. The first portion of the first external terminal may be spaced apart from the first portion of the second external terminal by a first external terminal spacing distance. An active electrode region may include a plurality of first active electrode layers and a plurality of second active electrode layers. The plurality of first active electrode layers may include at least one active electrode having a rectangular shape. The plurality of second active electrode layers may include at least one second active electrode having a rectangular shape. The plurality of first active electrode layers may be connected to the first external terminal. The plurality of second active electrode layers may be connected to the second external terminal. The active electrode region may include an outermost active electrode layer. The outermost active electrode layer may be spaced apart from the outer surface by an outermost active-to-surface distance. The monolithic body may have a thickness along the Z direction. The ratio of the thickness to the outermost active-to-surface distance may be 1.1 or greater. The capacitor may have a capacitor length extending along the longitudinal direction. The ratio of the capacitor length to the first external terminal spacing distance may be 15 or greater.

[0005] According to another embodiment of the present invention, a device may include: a mounting surface and a broadband multilayer ceramic capacitor. The broadband multilayer ceramic capacitor may include: a monolithic body, the monolithic body including a plurality of dielectric layers stacked in the Z direction, and the monolithic body may have a first end, the first end being opposite to the second end. A first external terminal may be arranged along the first end of the monolithic body. The first external terminal may include a first portion extending along the outer surface of the monolithic body. The second external terminal may be arranged along the second end of the monolithic body. The second external terminal may include a first portion extending along the outer surface of the monolithic body. The first portion of the first external terminal may be spaced apart from the first portion of the second external terminal by a first external terminal spacing distance. An active electrode region may include a plurality of first active electrode layers and a plurality of second active electrode layers. The plurality of first active electrode layers may include at least one active electrode having a rectangular shape. The plurality of second active electrode layers may include at least one second active electrode having a rectangular shape. The plurality of first active electrode layers may be connected to the first external terminal. The plurality of second active electrode layers may be connected to the second external terminal. The active electrode region may include an outermost active electrode layer. The outermost active electrode layer may be spaced apart from the outer surface by an outermost active-to-surface distance. The monolithic body may have a thickness along the Z direction. A ratio of the thickness to the outermost active-to-surface distance may be 1.1 or greater. The capacitor may have a capacitor length extending along the longitudinal direction. A ratio of the capacitor length to the first external terminal spacing distance may be 15 or greater.

[0006] According to yet another embodiment of the present invention, a method of forming a broadband multilayer ceramic capacitor may include: forming a plurality of active electrodes on a plurality of active electrode layers. At least one first active electrode layer of the plurality of active electrode layers may include a first active electrode. At least one second active electrode layer of the plurality of active electrode layers may include a second active electrode. The method may also include: stacking the plurality of active electrode layers and a plurality of dielectric layers to form a monolithic body having an outer surface. The plurality of active electrode layers may include an outermost active electrode layer, the outermost active electrode layer being disposed closest to the outer surface of the monolithic body among the plurality of active electrode layers. The method may also include: depositing a first external terminal along a first end of the capacitor. The first external terminal may be connected to the first active electrode layer. The first external terminal may include a first portion extending along the outer surface of the capacitor. The method may also include: depositing a second external terminal along a second end of the capacitor, the second end being opposite to the first end. The second external terminal may be connected to the second active electrode layer. The second external terminal may include a first portion extending along the outer surface of the capacitor. The outermost active electrode layer may be spaced apart from the outer surface by an outermost active-to-surface distance. The monolithic body may have a thickness along the Z direction. The ratio of the thickness to the outermost active-to-surface distance may be 1.1 or greater. The capacitor may have a capacitor length extending along the longitudinal direction. The ratio of the capacitor length to the first external terminal spacing distance may be 15 or greater. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] A full and enabling disclosure of the invention, including the best mode thereof, to one skilled in the art, is more particularly set forth in the remainder of the specification, including with reference to the accompanying drawings, in which:

[0008] Figure 1A shows a side cross-sectional view of one embodiment of a capacitor according to aspects of the present disclosure;

[0009] Figure 1B According to various aspects of the present disclosure Figure 1A An exploded side view of one embodiment of an adjacent active electrode layer of a capacitor in FIG.

[0010] Figure 2 According to various aspects of the present disclosure Figure 1A A circuit diagram of an embodiment of the capacitor shown;

[0011] Figure 3A shows a shielding electrode layer that may be included in a shielding electrode region of various embodiments of a capacitor according to aspects of the present disclosure;

[0012] Figure 3BAnother embodiment of a shield electrode layer is shown, which can be included in the shield electrode region of various embodiments of capacitors according to aspects of the present disclosure;

[0013] Figure 4 shows a side cross-sectional view of another embodiment of a capacitor according to aspects of the present disclosure;

[0014] FIG. 5A to FIG. 5C The present invention shows various embodiments of the present invention. Figure 4 A top view of an anchor electrode of a capacitor in FIG.

[0015] Figure 6 shows a side cross-sectional view of another embodiment of a capacitor according to aspects of the present disclosure;

[0016] Figure 7 shows a side cross-sectional view of yet another embodiment of a capacitor according to aspects of the present disclosure;

[0017] Fig. 8A According to various aspects of the present disclosure Figure 7 An exploded side view of one embodiment of an adjacent active electrode layer of a capacitor in FIG.

[0018] Figure 8B According to various aspects of the present disclosure Fig. 8A a capacitor region of the first active electrode layer;

[0019] Figure 8C According to various aspects of the present disclosure Fig. 8A A capacitor region of a second active electrode layer;

[0020] Fig. 9 shows a side cross-sectional view of yet another embodiment of a capacitor according to aspects of the present disclosure;

[0021] Fig.10 According to various aspects of the present disclosure Figure 1A Multiple insertion loss curves for multiple capacitors in;

[0022] Fig.11 According to various aspects of the present disclosure Figure 1A a plurality of insertion loss curves for a plurality of capacitors in; and

[0023] Fig.12 According to various aspects of the present disclosure Figure 1A Multiple insertion loss curves for multiple capacitors in . DETAILED DESCRIPTION

[0024] Those skilled in the art will appreciate that this discussion is merely a description of exemplary embodiments and is not intended to limit the broader aspects of the invention.

[0025] In general, the present subject matter relates to capacitors such as for broadband applications and / or ultra-broadband applications. The capacitor includes alternating dielectric and electrode layers that may form at least a portion of a monolithic body of the capacitor. By arranging the dielectric and electrode layers in a stacked or laminar configuration, the capacitor may be referred to as a multilayer capacitor, and particularly, for example, as a multilayer ceramic capacitor when the dielectric layers include ceramics.

[0026] The capacitor may include a monolithic body including a plurality of dielectric layers stacked in a Z direction. A first external terminal may be disposed along a first end of the capacitor. The first external terminal may include a first portion extending along an outer surface of the monolithic body of the capacitor. A second external terminal may be disposed along a second end of the capacitor, the second end being opposite to the first end in a longitudinal direction. The second external terminal may include a first portion extending along an outer surface of the monolithic body. The first portion of the first external terminal may be spaced apart from the first portion of the second external terminal by a first external terminal spacing distance in a longitudinal direction.

[0027] The outer surface may be the top surface of the monolithic body of the capacitor or the bottom surface of the monolithic body of the capacitor. The top surface and the bottom surface of the monolithic body are opposite to each other along the Z direction. In some embodiments, the first external terminal and the second external terminal may each include a first portion extending along the first external surface of the monolithic body, a second portion extending along the second external surface of the monolithic body, etc., so that the first external terminal and the second external terminal extend along more than one external surface of the monolithic body of the capacitor. For example, in some embodiments, the first external terminal may include a second portion extending along the second external surface of the monolithic body, and the second external terminal may include a second portion extending along the second external surface of the monolithic body. The second portion of the first external terminal may be spaced apart from the second portion of the second external terminal in the longitudinal direction by a second external terminal spacing distance. In an embodiment in which the capacitor includes a first portion of the first external terminal, a first portion of the second external terminal, a second portion of the first external terminal, and a second portion of the second external terminal, the first portion of each of the first external terminal and the second external terminal may extend along one of the top surface and the bottom surface of the monolithic body, and the second portion of each of the first external terminal and the second external terminal may extend along the other of the top surface and the bottom surface of the monolithic body.

[0028] The first external terminal spacing distance and / or the second external terminal spacing distance can be relatively small, so that a fringe effect capacitance is generated between the external terminals. This fringe effect capacitance can contribute to the good high frequency performance of the capacitor. For example, the capacitor can have a capacitor length in the longitudinal direction, between the first end and the second end. The ratio of the capacitor length to the first external terminal spacing distance can be greater than about 2, greater than about 3 in some embodiments, greater than about 5 in some embodiments, greater than about 7 in some embodiments, greater than about 10 in some embodiments, greater than about 20 in some embodiments, greater than about 30 in some embodiments, and greater than about 35 in some embodiments. In addition, the ratio of the capacitor length to the second external terminal spacing distance can be greater than about 2, greater than about 3 in some embodiments, greater than about 5 in some embodiments, greater than about 7 in some embodiments, greater than about 10 in some embodiments, greater than about 20 in some embodiments, greater than about 30 in some embodiments, and greater than about 35 in some embodiments.

[0029] In some embodiments, the first external terminals can be spaced apart by a distance less than about 250 microns, in some embodiments less than about 200 microns, in some embodiments less than about 175 microns, in some embodiments less than about 150 microns, in some embodiments less than about 100 microns, in some embodiments less than about 75 microns, in some embodiments less than about 50 microns, in some embodiments less than about 40 microns, in some embodiments less than about 30 microns, and in some embodiments less than about 20 microns. Similarly, in some embodiments, the second external terminals can be spaced apart by a distance less than about 250 microns, in some embodiments less than about 200 microns, in some embodiments less than about 175 microns, in some embodiments less than about 150 microns, in some embodiments less than about 100 microns, in some embodiments less than about 75 microns, in some embodiments less than about 50 microns, in some embodiments less than about 40 microns, in some embodiments less than about 30 microns, and in some embodiments less than about 20 microns. For example, in some embodiments, the first external terminal spacing distance and / or the second external terminal spacing distance can be in the range of about 1 micron to about 250 microns, in some embodiments about 5 microns to about 200 microns, in some embodiments about 10 microns to about 150 microns, and in some embodiments about 15 microns to about 100 microns.

[0030] The capacitor may include an active electrode region having a plurality of active electrode layers. In some embodiments, the plurality of active electrode layers may include a first active electrode layer connected to a first external terminal and a second active electrode layer connected to a second external terminal. For example, the first active electrode layer may include a first active electrode connected to the first external terminal, and the second active electrode layer may include a second active electrode connected to the second external terminal. The first active electrode layer may overlap with the second active electrode layer in a longitudinal direction. The overlap between the first active electrode layer and the second active electrode layer may provide capacitance between the first external terminal and the second external terminal. The first active electrode layer may overlap with the second active electrode layer along an overlap distance. The overlap distance may be a significant portion of the capacitor length. The ratio of the overlap distance to the capacitor length may be greater than about 0.4, greater than about 0.5 in some embodiments, and greater than about 0.6 in some embodiments. For example, the overlap distance may be in the range of from about 0.4 to about 0.98, from about 0.5 to about 0.95 in some embodiments, and from about 0.6 to about 0.9 in some embodiments.

[0031] In some embodiments, the active electrode region includes an outermost active electrode layer, which can be the active electrode layer closest to the outer surface of the monolithic body. The outermost active electrode layer can be spaced apart from the outer surface by an outermost active-to-surface distance. The outermost active-to-surface distance can be relatively small so that edge effect capacitance is generated between the active electrode and the external terminal. This edge effect capacitance can contribute to the good performance of the capacitor, particularly at lower frequencies of the frequency range of the capacitor.

[0032] The monolithic body or capacitor can have a thickness along the Z direction, and in some embodiments, the ratio of the thickness to the outermost active-to-surface distance is 1.1 or greater, in some embodiments, 2 or greater, in some embodiments, 3 or greater, in some embodiments, 5 or greater, in some embodiments, 10 or greater, in some embodiments, 20 or greater, in some embodiments, 30 or greater, in some embodiments, 40 or greater, and in some embodiments, 50 or greater.

[0033] In some embodiments, the outermost active-to-surface distance can be 150 microns or less, in some embodiments 125 microns or less, in some embodiments 100 microns or less, in some embodiments 90 microns or less, in some embodiments 75 microns or less, in some embodiments 60 microns or less, in some embodiments 40 microns or less, in some embodiments 25 microns or less, in some embodiments 15 microns or less, in some embodiments 10 microns or less, and in some embodiments 5 microns or less. As an example, the outermost active-to-surface distance can be in the range of from about 1 micron to about 150 microns, in some embodiments from about 5 microns to about 100 microns, in some embodiments from about 10 microns to about 90 microns, and in some embodiments from about 15 microns to about 50 microns.

[0034] The active electrode region may have an active electrode region thickness in the Z direction. The active electrode region thickness may be defined between the lowest active electrode layer and the highest active electrode layer. The ratio of the capacitor thickness to the active electrode region thickness may be in the range of from about 1.1 to about 20, in some embodiments from about 1.5 to about 10, and in some embodiments from about 1.7 to about 5.

[0035] In some embodiments, the first active electrode layer in the plurality of active electrode layers may include a first active electrode and a second active electrode, the first active electrode being connected to the first external terminal, and the second active electrode being connected to the second external terminal. The second electrode may be coplanar with the first electrode. The second active electrode layer in the plurality of active electrode layers may include a third active electrode and a fourth active electrode, the third active electrode being connected to the first external terminal, and the fourth active electrode being connected to the second external terminal. The third active electrode may be coplanar with the fourth active electrode. The first active electrode may overlap with the fourth active electrode in the longitudinal direction. The overlap between the first active electrode and the fourth active electrode may provide capacitance between the first external terminal and the second external terminal. The first active electrode may overlap with the fourth active electrode along an overlap distance. The overlap distance may be a significant portion of the capacitor length. The ratio of the overlap distance to the capacitor length may be greater than about 0.4, greater than about 0.5 in some embodiments, and greater than about 0.6 in some embodiments. For example, the overlap distance may range from about 0.4 to about 0.98, in some embodiments from about 0.5 to about 0.95, and in some embodiments from about 0.6 to about 0.9.

[0036] The active electrodes may have a configuration that provides edge effect capacitance between coplanar electrodes. This edge effect capacitance may also contribute to good high frequency performance of the device. For example, the first active electrode and the second active electrode may form a relatively small end gap that may provide edge effect capacitance between the active electrodes. For example, an end gap distance may be formed in the longitudinal direction between the first active electrode and the second active electrode. In some embodiments, the end gap may be less than about 250 microns, in some embodiments less than about 150 microns, in some embodiments less than about 120 microns, and in some embodiments less than about 100 microns, and in some embodiments less than about 80 microns.

[0037] In some embodiments, the capacitor may include one or more shield electrode layers. The one or more shield electrode layers may have a variety of shapes and configurations. As an example, each shield electrode layer may include a pair of opposing, coplanar shield electrodes. In some embodiments, the shield electrodes may be substantially square or rectangular. In other embodiments, the shield electrodes may have steps or grooves.

[0038] The one or more shielding electrode layers may be located within the monolithic body. The shielding electrode may be located between the active electrode region and an outer surface of the monolithic body, such as a bottom surface of the monolithic body or a top surface of the monolithic body. In some embodiments, the broadband multilayer ceramic capacitor may not have a shielding electrode that is higher than the plurality of active electrode layers in the Z direction. In some embodiments, the broadband multilayer ceramic capacitor may not have a shielding electrode that is higher than the lowest electrode layer in the plurality of active electrode layers in the Z direction.

[0039] The shielding electrode is generally spaced apart from the active electrode by a shielding-to-active distance, so that the shielding electrode area is spaced apart and / or distinguished from the active electrode area. Each of the multiple active electrode layers can be evenly spaced apart from each other in the Z direction by an active electrode spacing distance, which is sometimes referred to as a "drop". The shielding-to-active distance can be greater than the active electrode spacing distance. For example, the shielding-to-active distance can be 2 times or more of the active electrode spacing distance, in some embodiments 3 times or more, in some embodiments 4 times or more, in some embodiments 5 times or more, and in some embodiments 10 times or more.

[0040] As an example, the active electrode spacing distance can be in the range of from about 0.1 microns to about 2 microns, and in some embodiments from about 0.2 microns to about 0.5 microns. The shield-to-active distance can be in the range of from 5 microns to about 80 microns, in some embodiments from about 10 microns to about 70 microns, in some embodiments from about 20 microns to about 60 microns, and in some embodiments from about 30 microns to about 50 microns.

[0041] The shield electrode region may include an outermost shield electrode layer, which may be the shield electrode layer closest to the outer surface of the monolithic body. The outermost shield electrode layer may be spaced apart from the outer surface by an outermost shield-to-surface distance. The monolithic body or capacitor may have a thickness along the Z direction, and in some embodiments, the ratio of the thickness to the outermost shield-to-surface distance is 1.1 or greater, in some embodiments, 2 or greater, in some embodiments, 3 or greater, in some embodiments, 5 or greater, in some embodiments, 10 or greater, and in some embodiments, 20 or greater.

[0042] The shielding electrode region may have a shielding electrode region thickness in the Z direction. The shielding electrode region thickness may be defined between an outermost shielding electrode of the shielding electrode region with respect to the Z direction and an innermost shielding electrode of the shielding electrode region with respect to the Z direction. The ratio of the capacitor thickness to the shielding electrode region thickness may be in the range of from about 1.1 to about 20, in some embodiments from about 1.5 to about 10, and in some embodiments from about 1.7 to about 5.

[0043] In some embodiments, the capacitor may include a dielectric region between the active electrode region and the top of the capacitor and / or between the active electrode region and the bottom of the capacitor. For example, the first dielectric region may extend from the active electrode region to the first outer surface of the broadband multilayer ceramic capacitor (e.g., the top surface or the bottom surface of the capacitor), and the second dielectric region may extend from the active electrode region to the second outer surface of the capacitor (e.g., the other of the top surface or the bottom surface of the capacitor). As another example, the active electrode region may be located between the dielectric region and the shielding electrode region in the Z direction. As yet another example, the first dielectric region may extend from the active electrode region to the outer surface of the broadband multilayer ceramic capacitor, and the second dielectric region may extend from the active electrode region to the shielding electrode region.

[0044] One or more dielectric regions may not have active electrodes and / or shield electrodes. For example, in some embodiments, the one or more dielectric regions may include one or more floating electrodes and / or dummy electrode tabs. For example, the dielectric region between the active electrode region and the shield electrode region may include one or more dummy electrode tabs, which may contribute to forming external terminals. These dummy electrode tabs generally extend less than about 40% of the length of the capacitor from the respective ends of the capacitor. For example, a first plurality of dummy electrode tabs may be connected to a first external terminal, and a second plurality of dummy electrode tabs may be connected to a second external terminal.

[0045] In some embodiments, the one or more dielectric regions may not have an electrode layer extending more than 40% of the length of the capacitor, in some embodiments more than 30% of the length of the capacitor, in some embodiments more than 20% of the length of the capacitor, in some embodiments more than 15% of the length of the capacitor, in some embodiments more than 10% of the length of the capacitor, in some embodiments more than 5% of the length of the capacitor, and in some embodiments more than 2% of the length of the capacitor. However, in other embodiments, the one or more dielectric regions may not have all electrode layers.

[0046] The broadband multilayer ceramic capacitor may have a capacitor thickness in the Z direction between the top surface and the bottom surface. The dielectric region may have a dielectric region thickness in the Z direction. The ratio of the capacitor thickness to the dielectric region thickness may be about 1.1 or greater, in some embodiments about 2 or greater, in some embodiments about 5 or greater, in some embodiments about 10 or greater, in some embodiments about 20 or greater, in some embodiments about 30 or greater, in some embodiments about 40 or greater, and in some embodiments about 50 or greater. In some embodiments, the dielectric region extends between the outermost active electrode layer and the outer surface of the broadband multilayer ceramic capacitor such that the dielectric region thickness is the same as the outermost active-to-surface distance.

[0047] Broadband multilayer ceramic capacitors can be part of, assembled with, and / or integrated into a device, such as a device that operates over a wide frequency range. The capacitor can be configured to be mounted to a mounting surface of the device. More specifically, the capacitor can be mounted to the mounting surface so that each of the multiple active electrode layers of the capacitor extends parallel to the mounting surface. Capacitors mounted in this horizontal orientation (horizontal orientation) (wherein the active electrodes extend parallel to the mounting surface of the device) can have better performance than capacitors configured as described herein and mounted in a vertical electrode orientation. For example, a broadband multilayer ceramic capacitor mounted in a horizontal orientation can exhibit lower insertion loss than a broadband multilayer ceramic capacitor mounted in a vertical orientation over a frequency range. For example, a broadband multilayer ceramic capacitor mounted in a horizontal orientation may exhibit an insertion loss in a range of about 0.0 decibels (dB) to about -0.8 dB over a frequency range of about 5 gigahertz (GHz) to about 67 GHz, but a broadband multilayer ceramic capacitor mounted in a vertical orientation may exhibit an insertion loss in a range of about -1.5 dB to about -2.0 dB over a frequency range of about 5 GHz to about 67 GHz.

[0048] The size and spacing of the external terminals can be selectively configured in conjunction with the spacing of the active electrode area to the outer surface of the capacitor and / or the size of the capacitor to provide improved inductance and capacitance over a larger frequency range than previous capacitors. For example, the first external terminal spacing distance and / or the second external terminal spacing distance can be selected to provide an inductive loop that improves the response characteristics of the capacitor over a first frequency range. The active electrode area configuration (e.g., the outermost active-to-surface distance) can be selected to provide an edge effect capacitance that improves the response of the capacitor over a second frequency range that extends higher or lower than the first frequency range, or is the same as or completely different from the first frequency range. In addition, the outermost active-to-surface distance can be selected to provide an inductive loop that improves the response of the capacitor over a third frequency range that extends higher or lower than the first frequency range, or is the same as or completely different from the first frequency range; the third frequency range can be the same as or different from the second frequency range. For example, a smaller first external terminal spacing distance can improve performance in a higher first frequency range, and a secondary capacitor can be formed between the outermost active electrode and a terminal extending along the outer surface of the monolithic body, which together with the smaller outermost active-to-surface distance improves performance in a lower second frequency range.

[0049] The outermost active-to-surface distance can define a cover layer between the electrode and the outer surface of the capacitor, which in some embodiments can be minimized to form a relatively thin cover layer, which can improve inductance and capacitance in the first frequency range and the second frequency range (e.g., over all operating frequency ranges of the capacitor). The external terminal spacing distance (e.g., the first external terminal spacing distance and / or the second external terminal spacing distance) can be minimized to improve inductance at higher frequencies within the operating frequency range of the capacitor. In at least some embodiments, the minimum external terminal spacing distance combined with the relatively small outermost active-to-surface distance can provide better high frequency performance of the capacitor than either feature alone, and / or can improve the performance of the capacitor over a wider frequency range than either feature alone. Therefore, one or more features as described herein can improve capacitor performance over at least a segment of the frequency band of the capacitor, and the combination of one or more features as described herein can provide better capacitor performance over the entire frequency band than any one of the one or more features alone.

[0050] Broadband multilayer ceramic capacitors as described herein can exhibit lower insertion loss over a wider frequency range. Typically, insertion loss is the power loss through the capacitor, and insertion loss can be measured using any method known in the art. For example, a capacitor can exhibit an insertion loss of greater than about -1.20 dB from about 1 GHz to about 67 GHz, greater than about -1.10 dB in some embodiments, greater than about -0.90 dB in some embodiments, and greater than about -0.80 dB in some embodiments. In some embodiments, a capacitor can exhibit an insertion loss of greater than about -0.60 dB from about 1 GHz to about 40 GHz, greater than about -0.50 dB in some embodiments, greater than about -0.45 dB in some embodiments, and greater than about -0.40 dB in some embodiments.

[0051] In some embodiments, the capacitor may exhibit an insertion loss greater than about -0.30 dB at about 10 GHz, greater than about -0.25 dB at about 10 GHz, and greater than about -0.20 dB at about 10 GHz in some embodiments. The capacitor may exhibit an insertion loss greater than about -0.60 dB at about 20 GHz, greater than about -0.50 dB at about 20 GHz in some embodiments, greater than about -0.40 dB at about 20 GHz, and greater than about -0.30 dB in some embodiments. The capacitor may exhibit an insertion loss greater than about -0.40 dB at about 30 GHz, greater than about -0.35 dB at about 30 GHz, greater than about -0.30 dB at about 30 GHz, greater than about -0.25 dB at about 30 GHz, and greater than about -0.20 dB at about 30 GHz in some embodiments. The capacitor may exhibit an insertion loss greater than about -0.60 dB at about 40 GHz, greater than about -0.50 dB at about 40 GHz in some embodiments, greater than about -0.40 dB at about 40 GHz in some embodiments, and greater than about -0.30 dB at about 40 GHz in some embodiments. The capacitor may exhibit an insertion loss greater than about -1.20 dB at about 50 GHz, greater than about -0.90 dB at about 50 GHz in some embodiments, greater than about -0.80 dB at about 50 GHz in some embodiments, and greater than about -0.50 dB at about 50 GHz in some embodiments. The capacitor may exhibit an insertion loss greater than about -1.10 dB at about 60 GHz, in some embodiments greater than about -0.90 dB at about 60 GHz, in some embodiments greater than about -0.80 dB at about 60 GHz, and in some embodiments greater than about -0.60 dB at about 60 GHz.

[0052] In some embodiments, the broadband multilayer ceramic capacitor can exhibit an insertion loss in the range of about -0.05 dB to about -0.40 dB at about 5 GHz to about 20 GHz, in some embodiments in the range of about -0.10 dB to about -0.40 dB at from about 10 GHz to about 20 GHz, in some embodiments in the range of about -0.05 dB to about -0.40 dB at from about 20 GHz to about 30 GHz, and in some embodiments in the range of about -0.05 dB to about -0.40 dB at from about 30 GHz to about 40 GHz. In some embodiments, the range is about -0.05 dB to about -1.20 dB from about 50 GHz to about 60 GHz, and in some embodiments, the range is about -0.05 dB to about -1.20 dB from about 60 GHz to about 70 GHz, and in some embodiments, the range is about -0.05 dB to about -1.10 dB from about 60 GHz to about 77 GHz.

[0053] I. Example Embodiments

[0054] Go to Figure 1A , an embodiment of a broadband multilayer ceramic capacitor 100 is disclosed. Figure 1A A schematic side cross-sectional view of one embodiment of a capacitor 100 according to aspects of the present disclosure is shown. Figure 1A The multilayer capacitor 100 shown in the embodiment of has a monolithic body 98 that includes a plurality of dielectric layers stacked in the Z-direction 136 and extending in the longitudinal direction 132 between a first end 19 and an opposite second end 21. A first external terminal 118 is disposed along the first end 19, and a second external terminal 120 is disposed along the second end 21. The first external terminal 118 includes a first portion 140 extending along an outer surface (e.g., bottom surface 20) of the monolithic body, and similarly, the second external terminal 120 includes a first portion 144 extending along an outer surface (e.g., bottom surface 20) of the monolithic body. The first portion 140 of the first external terminal 118 is spaced apart from the first portion 144 of the second external terminal 120 by a first external terminal spacing distance 142.

[0055] Likewise, in some embodiments, the first external terminal 118 includes a second portion 146 extending along another external surface of the monolithic body (e.g., top surface 18), and the second external terminal 120 includes a second portion 150 extending along another external surface of the monolithic body (e.g., top surface 18). The second portion 146 of the first external terminal 118 is spaced apart from the second portion 150 of the second external terminal 120 by a second external terminal spacing distance 148. The top surface 18 of the monolithic body 98 can be opposite the bottom surface 20 along the Z-direction 136.

[0056] In some embodiments, the first external terminal spacing distance 142 is the same as the second external terminal spacing distance 148. In other embodiments, the first external terminal spacing distance 142 and the second external terminal spacing distance 148 are not equal to each other. For example, in some embodiments, the first external terminal spacing distance 142 is greater than the second external terminal spacing distance 148, and in other embodiments, the first external terminal spacing distance 142 is less than the second external terminal spacing distance 148.

[0057] In some embodiments, the first external terminal spacing distance 142 is less than about 250 microns, in some embodiments less than about 200 microns, in some embodiments less than about 175 microns, in some embodiments less than about 150 microns, in some embodiments less than about 100 microns, in some embodiments less than about 75 microns, in some embodiments less than about 50 microns, in some embodiments less than about 40 microns, in some embodiments less than about 30 microns, and in some embodiments less than about 20 microns. In some embodiments, the second external terminal spacing distance 148 is less than about 250 microns, in some embodiments less than about 200 microns, in some embodiments less than about 175 microns, in some embodiments less than about 150 microns, in some embodiments less than about 100 microns, in some embodiments less than about 75 microns, in some embodiments less than about 50 microns, in some embodiments less than about 40 microns, in some embodiments less than about 30 microns, and in some embodiments less than about 20 microns. For example, in some embodiments, the first external terminal spacing distance 142 and / or the second external terminal spacing distance 148 is in the range of about 1 micron to about 250 microns, in some embodiments about 5 microns to about 200 microns, in some embodiments about 10 microns to about 150 microns, and in some embodiments about 15 microns to about 100 microns.

[0058] In addition, the capacitor can have a capacitor length 17 extending between the first end 19 and the second end 21 in the longitudinal direction 132. The ratio of the capacitor length 17 to the first external terminal spacing distance 142 and / or the ratio of the capacitor length 17 to the second external terminal spacing distance 148 can be 2 or greater, such as about 3 or greater, about 5 or greater, about 7 or greater, about 10 or greater, about 20 or greater, about 30 or greater, or about 35 or greater.

[0059] like Figure 1AAs shown, the multilayer capacitor 100 may include a plurality of electrode regions 10 stacked in a Z direction 136. The plurality of electrode regions 10 may include a dielectric region 12, an active electrode region 14, a shielding electrode region 16, and a second or additional dielectric region 115. The active electrode region 14 may be located between the dielectric region 12 and the shielding electrode region 16 in the Z direction 136. The dielectric region 12 may extend from the active electrode region 14 to a top surface 18 of the broadband multilayer ceramic capacitor 100. The second or additional dielectric region 115 may extend from the active electrode region 14 to the shielding electrode region 16.

[0060] A plurality of electrode regions 10 may include a plurality of dielectric layers. Some dielectric layers may include electrode layers formed thereon. In general, the thickness of the dielectric layer and the electrode layer is not limited and may be any thickness desired, depending on the performance characteristics of the capacitor. For example, the thickness of the electrode layer may be, but is not limited to, about 500 nanometers (nm) or greater (e.g., about 1 micrometer (μm) or greater, such as about 2 μm or greater, such as about 3 μm or greater, such as about 4 μm or greater) to about 10 μm or less (e.g., about 5 μm or less, such as about 4 μm or less, such as about 3 μm or less, such as about 2 μm or less). For example, the electrode layer may have a thickness from about 1 μm to about 2 μm. In addition, in one embodiment, the thickness of the dielectric layer may be defined according to the thickness of the above-mentioned electrode layer. In addition, it should be understood that when there is a thickness of a dielectric layer as defined herein, the thickness of such a dielectric layer may also be applied to any layer between active electrode layers and / or between shielding electrode layers.

[0061] Generally, the present invention provides a multilayer capacitor having a unique electrode arrangement and configuration that provides various benefits and advantages. In this regard, it should be understood that the material used to construct the capacitor may not be limited and may be any material commonly used in the art and may be formed using any method commonly used in the art.

[0062] Typically, the dielectric layer is typically formed of a material having a relatively high dielectric constant (K), such as from about 10 to about 40,000, in some embodiments from about 50 to about 30,000, and in some embodiments from about 100 to about 20,000.

[0063] In this regard, the dielectric material may be a ceramic. The ceramic may be provided in a variety of forms such as, for example, a wafer (eg, pre-fired) or a co-fired dielectric material within the device itself.

[0064] Specific embodiments of types of high dielectric materials include, for example, NPO (COG) (up to about 100), X7R (from about 3,000 to about 7,000), X7S, Z5U and / or Y5V materials. It should be understood that the above materials are described by their industry-recognized definitions, some of which are standard classifications established by the Electronic Industries Alliance (EIA), and therefore should be recognized by those of ordinary skill in the art. For example, such materials may include ceramics. These materials may include perovskites, such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lanthanum lead zirconate titanate), sodium bismuth titanate, etc. In a specific embodiment, for example, the formula Ba x Sr 1-x TiO 3 Barium strontium titanate (BSTO), wherein x is from 0 to 1, in some embodiments x is from about 0.15 to about 0.65, and in some embodiments x is from about 0.25 to about 0.6. Other suitable perovskites may include, for example: Ba x Ca 1-x TiO 3 (wherein x is from about 0.2 to about 0.8, and in some embodiments x is from about 0.4 to about 0.6), Pb x Zr 1-x TiO 3 ("PZT") (wherein x is in the range of about 0.05 to about 0.4), lead lanthanum zirconium titanate ("PLZT"), lead titanate (PbTiO 3 ), barium calcium zirconium titanate (BaCaZrTiO 3 ), sodium nitrate (NaNO 3 ), potassium niobate (KNbO 3 ), lithium niobate (LiNbO 3 ), lithium tantalate (LiTaO 3 ), lead metaniobate (PbNb 2 O 6 ), lead tantalate (PbTa 2 O 6 )KSr(NbO 3 ) and NaBa 2 (NbO 3 )5 HkDJ 2 PO 4 There are additional composite perovskites including A[B1 1 / 3 B2 2 / 3 ]O 3 Materials, wherein A is Ba x Sr 1-x (x can be a value from 0 to 1); B1 is Mg y Zn 1-y (y can be a value from 0 to 1); B2 is Ta z Nb 1-z (z may have a value from 0 to 1.) In one particular embodiment, the dielectric layer may include titanate.

[0065] The electrode layer can be formed of any of a variety of different metals known in the art. The electrode layer can be made of a metal (e.g., a conductive metal). The material can include precious metals (e.g., silver, gold, palladium, platinum, etc.) and basic metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), etc., and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, and respective sputtered layers of chromium, nickel, and gold may also be suitable. The electrode can also be made of a low resistance material (e.g., silver, copper, gold, aluminum, palladium, etc.). In a specific embodiment, the electrode layer can include nickel or its alloys.

[0066] A plurality of first active electrode layers 102 and a plurality of second active electrode layers 104 may be arranged in the active electrode region 14 of the capacitor 100. More specifically, as Figure 1A As shown, the active electrode region 14 may include an alternating arrangement of first electrode layers 102 and second electrode layers 104. For example, a plurality of first electrode layers 102 and a plurality of second electrode layers 104 may be arranged in an alternating mirror configuration. Figure 1A As further shown, the first active electrode layer 102 may be connected to the first external terminal 118 , and the second active electrode layer 104 may be connected to the second external terminal 120 .

[0067] Furthermore, the first active electrode layer 102 may overlap the second active electrode layer along an overlapping distance 122. Figure 1A The side cross-sectional view of FIG. 1 shows a capacitor 100 having a total of four first electrode layers 102 and three second electrode layers 104. However, it should be understood that any number of electrode layers 102, 104 may be employed to obtain a desired capacitance for a desired application.

[0068] refer to Figure 1B , each active electrode layer 102, 104 may have an electrode width 126. More specifically, Figure 1BIn the illustrated embodiment, each first active electrode layer 102 has an electrode width 126, and each second active electrode layer 104 has an electrode width 126. The electrode width 126 may affect, for example, the capacitance between the outermost active electrode layer and the first portion 140 of the first external terminal 118 and the first portion 144 of the second external terminal 120, and / or between the outermost active electrode layer and the second portion 146 of the first external terminal 118 and the second portion 150 of the second external terminal 120.

[0069] like Figure 1A As further shown, the capacitor 100 may include one or more shielding electrode layers 15 in the shielding electrode region 16. The shielding electrode layer 15 may have a variety of configurations, such as the following reference Figure 3A and Figure 3B ( Figure 3A and Figure 3B The configuration described above shows that the shielding electrode layer 15 may include a first shielding electrode 22 and a second shielding electrode 24 .

[0070] The shield electrode region 16 can be located within the capacitor 100, between the active electrode region 14 and the outer surface of the monolithic body 98, such as between the active electrode region 14 and the top surface 18 and / or between the active electrode region 14 and the bottom surface 20. The shield electrode layer 15 is typically spaced apart from the active electrode layers 102, 104 by a shield-to-active distance 67, such that the first shield electrode 22 and the second shield electrode 24 are separated from the active electrode region. For example, each active electrode layer 102, 104 can be uniformly spaced apart from each other in the Z direction 136 by an active electrode spacing distance 105, which is sometimes referred to as a "drop". The shield-to-active distance 67 can be greater than the active electrode spacing distance 105. For example, the shield-to-active distance 67 can be twice or more than the active electrode spacing distance 105. As an example, the active electrode spacing distance 105 can be in the range of about 0.5 microns to about 5 microns. The shield-to-active distance 67 may be greater than about 5 microns, in some embodiments greater than about 10 microns, in some embodiments greater than about 20 microns, and in some embodiments greater than about 30 microns.

[0071] As shown, for example, in Figure 1A In some embodiments, the capacitor 100 may not have active electrode layers 102, 104 in the additional dielectric region 115 (e.g., the second dielectric region) between the active electrode region 14 and the shielding electrode region 16 in the Z direction 136. However, in other embodiments, the dielectric region 115 between the active electrode region 14 and the shielding electrode region 16 may include one or a virtual electrode tab (e.g., as shown in FIG. Figure 6 as shown), which can help form external terminals.

[0072] refer to Figure 1A In some embodiments, broadband multilayer ceramic capacitor 100 can have a capacitor thickness 56 in Z-direction 136 between top surface 18 and bottom surface 20. Dielectric region 12 can have a dielectric region thickness 58 in Z-direction 136. In some embodiments, a ratio of capacitor thickness 56 to dielectric region thickness 58 can be about 10 or greater.

[0073] The active electrode region 14 may have an active electrode region thickness 59 in the Z direction 136. The active electrode region 14 may not have shield electrodes 22, 24 and / or may include only overlapping electrodes. The active electrode region thickness 59 may be defined between the lowest active electrode layer 101 and the highest active electrode layer 103 with respect to the Z direction 136. The ratio of the capacitor thickness 56 to the active electrode region thickness 59 may be in the range of about 1.1 to about 20.

[0074] In addition, the area between the active electrodes 102, 104 and the bottom surface 20 of the capacitor 100 (the area is formed by Figure 1A The second or additional dielectric region 115 and the shield electrode region 16 in the embodiment of the present invention can be relatively thin. More specifically, the outermost active electrode layer and the outer surface of the monolithic body 98 (e.g., Figure 1AThe outermost active-to-surface distance 60 (between the lowest active electrode layer 101 shown and the bottom surface 20) is relatively small or can be minimized to form a relatively thin cover layer between the active electrodes 102, 104 and the outer surface of the monolithic body 98. For example, the ratio of the capacitor thickness 56 to the outermost active-to-surface distance 60 can be greater than about 2. For example, in some embodiments, the ratio of the capacitor thickness 56 to the outermost active-to-surface distance 60 can be 1.1 or greater, in some embodiments, 2 or greater, in some embodiments, 3 or greater, in some embodiments, 5 or greater, in some embodiments, 10 or greater, in some embodiments, 20 or greater, in some embodiments, 30 or greater, in some embodiments, 40 or greater, and in some embodiments, 50 or greater. In addition, in some embodiments, the outermost active-to-surface distance 60 can be 150 microns or less, in some embodiments, 125 microns or less, in some embodiments, 100 microns or less, in some embodiments, 90 microns or less, in some embodiments, 75 microns or less, in some embodiments, 60 microns or less, in some embodiments, 40 microns or less, in some embodiments, 25 microns or less, in some embodiments, 15 microns or less, in some embodiments, 10 microns or less, and in some embodiments, 5 microns or less. As an example, the outermost active-to-surface distance 60 can be in the range of from about 1 micron to about 150 microns, in some embodiments from about 5 microns to about 100 microns, in some embodiments from about 10 microns to about 90 microns, and in some embodiments from about 15 microns to about 50 microns.

[0075] like Figure 1A As shown in the embodiment of FIG. 1 , the cover layer or outermost active-to-surface distance 60 includes the shield electrode region 16 and the second or additional dielectric region 115. In some embodiments, the dielectric region 12 extends between the outermost active electrode layer and the outer surface of the broadband multilayer ceramic capacitor, so that the dielectric region 12 defines the cover layer and the dielectric region thickness 58 is the same as the outermost active-to-surface distance 60. For example, referring to Fig. 9 The broadband multilayer ceramic capacitor 900 shown includes a first dielectric region 12 extending from an active electrode region 14 to a top surface 18 and a second dielectric region 12 extending from the active electrode region 14 to a bottom surface 20, wherein a dielectric region thickness 58 of the second dielectric region 12 is the same as an outermost active-to-surface distance 60.

[0076] In some embodiments, the outermost shield-to-surface distance 63 may be defined as the distance between the shield electrodes 22, 24 and the outer surface of the capacitor 100, such as Figure 1AThe bottom surface 20 of the capacitor 100 is shown. If multiple shield electrode layers 15 are included, the outermost shield to surface distance 63 can be defined as the outermost shield electrode layer 137 ( Figure 4 ) and an outer surface, which may be, for example, top surface 18 for shield electrode region 16 between top surface 18 and active electrode region 14, or bottom surface 20 for shield electrode region 16 between active electrode region 14 and bottom surface 20. The ratio of capacitor thickness 56 to outermost shield-to-surface distance 63 may be greater than about 2. For example, in some embodiments, the ratio of capacitor thickness 56 to outermost shield-to-surface distance 63 may be 1.1 or greater, in some embodiments 2 or greater, in some embodiments 3 or greater, in some embodiments 5 or greater, in some embodiments 10 or greater, and in some embodiments 20 or greater.

[0077] As previously described, the shield electrodes 22, 24 may be spaced apart from the active electrodes 102, 104 by a shield-to-active distance 67. Figure 1A In the embodiment of , the shield-to-active distance 67 is defined between the lowest active electrode 101 and the shield electrode layer 15 closest to the lowest active electrode 101 in the Z direction 136. In the embodiment including more than one shield electrode layer 15, for example Figure 4 As shown, the shield-to-active distance 67 is defined between the innermost shield electrode layer 138 and the active electrode layers 102, 104 closest to the innermost shield electrode layer 138. The ratio of the shield-to-active distance 67 to the outermost shield-to-surface distance 63 can be in the range of from about 1 to about 20, in some embodiments from about 2 to about 10, and in some embodiments from about 3 to about 5.

[0078] In general, with respect to the embodiments discussed herein, the first external terminal 118 and the second external terminal 120 can be formed of any of a variety of different materials known in the art. For example, the external terminals 118, 120 can be made of metal (e.g., conductive metal). The external terminal materials can include precious metals (e.g., silver, gold, palladium, platinum, etc.) and basic metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. In a specific embodiment, the external terminals 118, 120 can include copper or its alloys.

[0079] The external terminals 118, 120 may be formed using any method known in the art. The external terminals 118, 120 may be formed using techniques such as sputtering, painting, printing, chemical plating or fine copper terminal (FCT), electroplating, plasma deposition, propellant spraying / air brushing, and the like.

[0080] In one embodiment, the external terminals 118, 120 can be formed so that the external terminals 118, 120 are relatively thick. For example, the external terminals 118, 120 can be formed by applying a thick film strip of metal to the exposed portion of the electrode layer (e.g., by immersing the capacitor in a liquid external terminal material). This metal can be in a glass matrix and can include silver or copper. As an example, this strip can be printed and fired onto the capacitor. Thereafter, an additional metal (e.g., nickel, tin, solder, etc.) plating can be formed over the terminal strip so that the capacitor can be soldered to the substrate. This application of the thick film strip can be performed using any method known in the art (e.g., by a termination machine and printing wheel for transferring a paste of the loaded metal over the exposed electrode layer).

[0081] Thick plated external terminals 118, 120 can have an average thickness of about 150 microns or less, such as about 125 microns or less, such as about 100 microns or less, such as about 80 microns or less. Thick plated external terminals 118, 120 can have an average thickness of about 25 microns or more, such as about 35 microns or more, such as about 50 microns or more, such as about 75 or more microns. For example, thick plated external terminals 118, 120 can have an average thickness of about 25 microns to about 150 microns, such as about 35 microns to about 125 microns, such as about 50 microns to about 100 microns.

[0082] In another embodiment, the external terminals 118, 120 can be formed so that each external terminal is a thin film coating of a metal. Such a thin film coating can be formed by depositing a conductive material (e.g., a conductive metal) on an exposed portion of the electrode layer. For example, the front edge of the electrode layer can be exposed so that the front edge can allow the formation of a plated terminal.

[0083] The thin plated external terminals 118, 120 can have an average thickness of about 50 microns or less, such as about 40 microns or less, such as about 30 microns or less, such as about 25 microns or less. The thin plated external terminals 118, 120 can have an average thickness of about 5 microns or more, such as about 10 microns or more, such as about 15 microns or more. For example, the external terminals 118, 120 can have an average thickness of about 5 microns to about 50 microns, such as about 10 microns to about 40 microns, such as about 15 microns to about 30 microns, such as about 15 microns to about 25 microns.

[0084] Typically, the external terminals 118, 120 may include plated terminals. For example, the external terminals 118, 120 may include electroplated terminals, electroless plated terminals, or a combination thereof. For example, the electroplated terminals may be formed by electroplating. The electroless plated terminals may be formed by chemical plating.

[0085] When multiple layers constitute the external terminal, the external terminal can include an electroplated terminal and an electroless plating terminal. For example, an initial material layer can be deposited first using electroless plating. The plating technique can then be switched to an electrochemical plating system, which can allow for faster material deposition.

[0086] When forming the plated terminations 118, 120 using either plating method, the leading edges of the lead tabs of the electrode layers exposed from the capacitor body are subjected to the plating solution (eg, by immersing the capacitor in the plating solution).

[0087] The plating solution contains a conductive material (e.g., a conductive metal) to form the plated terminal, that is, the plated terminal is formed using a conductive material. This conductive material can be any of the above materials or any material known in the art. For example, the plating solution can be a nickel sulfamate bath solution or other nickel solution, so that the coating and the external terminal include nickel. Alternatively, the plating solution can be a cupric acid bath or other suitable copper solution, so that the coating and the external terminal include copper.

[0088] In addition, it should be understood that the plating solution may include other additives known in the art. For example, the additives may include other organic additives and mediators that may aid in the plating process. In addition, additives may be used to use the plating solution at a desired pH. In one embodiment, a drag reducing additive may be used in the solution to assist in complete coating coverage and bonding of the plating material to the exposed front edges of the capacitor and lead tabs.

[0089] The capacitor may be exposed, submerged or immersed in the plating solution for a predetermined amount of time. Such exposure time is not necessarily limited, but may be an amount of time sufficient to allow sufficient deposition of plating material to form plated terminals. In this regard, the time should be sufficient to allow a continuous connection to be formed between the desired exposed adjacent leading edges of lead tabs of a given polarity of each electrode layer within a set of alternating dielectric and electrode layers.

[0090] Generally, the difference between electroplating and chemical plating is that electroplating uses an electrical bias, such as by using an external power supply. Typically, electrolytic plating solutions can be subjected to high current density ranges, for example, ten to fifteen amps per square foot (amp / ft 2) (rated voltage is 9.4 volts). The following connections can be made in the same plating bath: a negative connection to the capacitor that needs to form a plated terminal, and a positive connection to a solid material (e.g., copper in a copper plating bath). That is, the capacitor is biased to a polarity opposite to the polarity of the plating bath. Using this method, the conductive material of the plating bath is attracted to the metal of the exposed front edge of the lead tab of the electrode layer.

[0091] Before the capacitor is immersed in or subjected to the plating solution, various pretreatment steps may be employed. These steps may be performed for a variety of purposes including catalyzing, accelerating and / or improving the adhesion of the plating material to the leading edge of the lead tab.

[0092] In addition, an initial cleaning step may be employed prior to plating or any other pretreatment step. This step may be employed to remove any oxide buildup formed on the exposed lead tabs of the electrode layer. When the internal electrodes or other conductive elements are formed of nickel, this cleaning step may be particularly helpful in assisting in removing any buildup of nickel oxide. Part cleaning may be achieved by complete immersion in a pre-cleaning bath (e.g., a bath comprising an acidic cleaner). In one embodiment, exposure may last for a predetermined time, such as on the order of about 10 minutes. Cleaning may also alternatively be achieved by chemical polishing or harperizing steps.

[0093] In addition, the step of the exposed metal front edge of the lead terminal tab of the activation electrode layer can be performed to promote the deposition of conductive material. Activation can be achieved by immersing palladium salts, photopatterned palladium organometallic precursors (by mask or laser), screen printing or inkjet deposition palladium compounds or electrophoretic palladium deposition. It should be understood that activation based on palladium is currently only disclosed as an embodiment of an activation solution, which usually works well with the activation of the exposed terminal tab portion formed by nickel or its alloy. However, it should be understood that other activation solutions may also be used.

[0094] In addition, as an alternative to or in addition to the above-mentioned activation step, an activating dopant may be introduced into the conductive material when forming the electrode layer of the capacitor. For example, when the electrode layer comprises nickel and the activating dopant comprises palladium, the palladium dopant may be introduced into the nickel ink or composition that forms the electrode layer. This may eliminate the palladium activation step. It should be further understood that some of the above-mentioned activation methods (e.g., organometallic precursors) also contribute to the co-deposition of the glass former itself to increase adhesion to the general ceramic body of the capacitor. When the activation step is used as described above, trace amounts of activator material may generally remain at the exposed conductive portion before and after termination plating.

[0095] In addition, a post-treatment step after plating can also be used. This step can be performed for a variety of purposes, including enhancing and / or improving the adhesion of the material. For example, a heating (or annealing) step can be used after performing the plating step. This heating can be performed by baking, subjecting to laser, ultraviolet (UV) exposure, microwave exposure, arc welding, etc.

[0096] As indicated herein, the external terminal may include at least one plating layer. In one embodiment, the external terminal may include only one plating layer. However, it should be understood that the external terminal may include multiple plating layers. For example, the external terminal may include a first plating layer and a second plating layer. In addition, the external terminal may also include a third plating layer. The materials of these plating layers may be any of the above and known in the art.

[0097] For example, one plating layer (e.g., the first plating layer) may include copper or its alloy. Another plating layer (e.g., the second plating layer) may include nickel or its alloy. Another plating layer (e.g., the third plating layer) may include tin, lead, gold, or a combination of materials (e.g., alloy). Alternatively, the initial plating layer may include nickel, followed by a plating layer of tin or gold. In another embodiment, an initial plating layer of copper may be formed, followed by a nickel layer.

[0098] In one embodiment, the initial or first plating layer may be a conductive metal (e.g., copper). The area may then be covered with a second layer comprising a resistive polymeric material for sealing. The area may then be polished to selectively remove the resistive polymeric material and then plated again with a third layer comprising a conductive metal material (e.g., copper).

[0099] The second layer above the initial plating layer may correspond to a solder barrier layer, such as a nickel solder barrier layer. In some embodiments, the layer may be formed by electroplating an additional metal (e.g., nickel) layer on top of an initial chemical plating layer or electrolytic plating layer (e.g., copper plating). Other exemplary materials for the solder barrier layer include nickel-phosphorus, gold, and silver. In some embodiments, the third layer on the solder barrier layer may correspond to a conductive layer, such as plated nickel (Ni), nickel / chromium (Ni / Cr), silver (Ag), palladium (Pd), tin (Sn), lead / tin (Pb / Sn), or other suitable plated solder.

[0100] Additionally, a metal coating may be formed and then an electroplating step may be performed to provide a resistive alloy or a higher resistive metal alloy coating over such metal coating, such as an electroless nickel-phosphorus (Ni-P) alloy. However, it should be understood that any metal coating may be included, as will be appreciated by one of ordinary skill in the art from the full disclosure herein.

[0101] It should be understood that any of the above steps can occur as a batch process, such as a barrel plating process, a fluidized bed plating process, and / or a flow-through plating terminal process, all of which are well known in the art. Such a batch process can process multiple components simultaneously, thereby providing an efficient and fast termination process. This is a particular advantage over conventional termination methods (e.g., printing of thick film terminals that require individual component processing).

[0102] In some embodiments, a combination of external terminal configurations may be used for the first external terminal 118 and / or the second external terminal 120. For example, in some embodiments, the first external terminal 118 and the second external terminal 120 may be a combination of FCT (pure copper termination) and thick film termination. For example, FCT may be applied at each end of the monolithic body 98, and a thick film terminal may be applied to each FCT terminal. Other combinations of terminal forming techniques and / or terminal forming configurations may also be used.

[0103] As described herein, the formation of external terminals is usually guided by the position of the exposed front edge of the lead tab of the electrode layer. This phenomenon can be referred to as "self-determining", because the formation of external plated terminals is determined by the configuration of the exposed conductive metal of the electrode layer at the peripheral position selected on the capacitor. In some embodiments, the capacitor may include a "virtual tab" to provide exposed conductive metal along the monolithic body of the capacitor, not including other electrodes (e.g., active electrodes or shielding electrodes). In some embodiments, one or more "virtual tabs", "virtual electrodes", anchor tabs and / or anchor electrodes, for example, may be added for the features of the nucleation function (nucleate function) that occurs in, for example, FCT (pure copper termination, chemical plating) processes. In the FCT process, such virtual tabs or electrodes, or anchor tabs or electrodes may be positioned inside or outside relative to the monolithic component to nucleate the metallized plating material, thereby forming external plated terminals.

[0104] It should be understood that additional techniques for forming capacitor terminals may also be within the scope of the present technology. Exemplary alternatives include, but are not limited to, forming terminals by plating, magnetic, mask, electrophoresis / electrostatic, sputtering, vacuum deposition, printing, or other techniques for forming thick or thin film conductive layers.

[0105] Figure 2 Shows Figure 1A. It will be appreciated that various capacitive elements may be defined within capacitor 100, and the sizes of various gaps and / or spacing distances may be selectively designed to achieve desired corresponding capacitance values ​​for the capacitive elements of capacitor 100. More specifically, the configuration and various parameters of the capacitor (e.g., the number of electrode layers, the surface area of ​​the overlapping center portion of the electrode pairs, the distance separating the electrodes, the dielectric constant of the dielectric material, etc.) may be selected to achieve the desired capacitance value. However, the capacitors disclosed herein may include arrays of combined series capacitors and parallel capacitors to provide effective broadband performance.

[0106] exist Figure 2 In an exemplary ultra-wideband capacitor embodiment shown, the primary capacitor P generally corresponds to a relatively large capacitance that is suitable for operation in a generally lower frequency range (e.g., on the order of about several kilohertz (kHz) to about 200 megahertz (MHz)), while the secondary capacitors D1 and D2 generally may correspond to relatively small value capacitors that are configured to operate in a relatively higher frequency range (e.g., on the order of about 200 megahertz (MHz) to several gigahertz (GHz)). For example, the secondary capacitor D1 may correspond to a capacitor of a smaller value than the primary capacitor P and may be configured to operate at a higher frequency than the primary capacitor P; and the secondary capacitor D2 may correspond to a capacitor of a smaller value than the secondary capacitor D1 and may be configured to operate at a higher frequency than the secondary capacitor D1. As described above, the primary capacitor P, the secondary capacitor D1, and the secondary capacitor D2 may all be formed by a capacitive element defined by the capacitor 100 (or the various embodiment multilayer capacitors described herein), wherein the capacitance value of each capacitor P, D1, D2 is determined based on the selected value of one or more dimensions described herein. For example, a thinner cover layer or outermost active-to-surface distance 60 may be selected to provide a capacitance value to improve the low frequency performance of the capacitor, while a smaller first external terminal separation distance 142 may be selected to provide a capacitance value to improve the high frequency performance of the capacitor.

[0107] Figure 3A Shield electrode layer 26 is shown, which may be included in shield electrode region 16 (at Figure 1A As indicated above, the first shield electrode 22 may be parallel to the longitudinal direction 132 (eg, Figure 1A The first shield electrode 22 may have a first longitudinal edge 28 that is aligned with the lateral direction 134 and faces away from the first external terminal 118 (in FIG. Figure 1A) and a first end 19. The first shield electrode 22 may have a second longitudinal edge 30 that is aligned with the transverse direction 134 and faces away from the first external terminal 118 (at Figure 1A ) and the first end 19. The second longitudinal edge 30 can be offset from the first longitudinal edge 28 in the longitudinal direction 132 by a shield electrode offset distance 32 to define a step 25.

[0108] The second shielding electrode 24 may be connected to the second external terminal 120 (at Figure 1A The second shielding electrode 24 can be connected to the second end 21 in the Z direction 136 (in Figure 1A 1 and 12. The second shield electrode 24 may have a similar configuration to the first shield electrode 22. For example, the second shield electrode 24 may have a first longitudinal edge 28 that is aligned with the transverse direction 134 and faces away from the second external terminal 120 (in FIG. Figure 1A The second shield electrode 24 may have a second longitudinal edge 30 that is aligned with the transverse direction 134 and faces away from the second external terminal 120 (in Figure 1A 2 and 3. The second longitudinal edge 30 of the second shield electrode 24 can be offset from the first longitudinal edge 28 of the second shield electrode 24 in the longitudinal direction 132 by a shield electrode offset distance 32 to define a step 25.

[0109] A first shield capacitance region 34 may be formed between a first longitudinal edge 28 of the first shield electrode 22 and a first longitudinal edge 28 of the second shield electrode 24. A second shield capacitance region 36 may be formed between a second longitudinal edge 30 of the first shield electrode 22 and a second longitudinal edge 30 of the second shield electrode 24. In some embodiments, a width 38 of the first longitudinal edge 28 in the lateral direction 134 may be less than a width 40 of the first shield electrode 22 in the lateral direction 134.

[0110] A first shield gap distance 42 may be formed between a first longitudinal edge 28 of the first shield electrode 22 and a first longitudinal edge 28 of the second shield electrode 24 in the longitudinal direction 132. A second shield gap distance 44 may be formed between a second lateral edge 30 of the first shield electrode 22 and a second lateral edge 30 of the second shield electrode 22 in the longitudinal direction 132.

[0111] In some embodiments, a third shield gap distance 46 can be formed between a third longitudinal edge 48 of the first shield electrode 22 and a third longitudinal edge 48 of the second shield electrode 24. A third shield capacitance region 51 can be formed between the third longitudinal edge 48 of the first shield electrode 22 and the third longitudinal edge 48 of the second shield electrode 24. In some embodiments, the third shield gap distance 46 can be substantially equal to the second shield gap distance 44, so that the third shield capacitance region 51 can be substantially similar in size and shape to the second shield capacitance region 36. For example, in some embodiments, the first shield electrode 22 and / or the second shield electrode 24 can be symmetrical about a longitudinal centerline 50 extending in the longitudinal direction 132.

[0112] However, in other embodiments, the third shield gap distance 46 may be greater than or less than the second shield gap distance 44, such that the size and / or shape of the third shield capacitance region 51 is different from the second shield capacitance region 36, and the third shield capacitance region produces a capacitance different from the second capacitance region.

[0113] It should be understood that in some embodiments, one or more of the shield electrodes 22, 24 can be rectangular. In other words, the shield electrode offset distance 32 can be zero or substantially zero so that the first longitudinal edge 28 and the second longitudinal edge 30 are aligned or substantially aligned.

[0114] Figure 3B Another embodiment of a shield electrode layer 26 is shown, which may be included in a shield electrode region 16 (at the top) within the monolithic body of capacitor 100. Figure 1A The first shield electrode 22 may be parallel to the longitudinal direction 132 (eg, Figure 1A The first shield electrode 22 may be parallel to the first external terminal 118 (in Figure 1A The first shielding electrode 22 may have a substantially square or rectangular shape. The second shielding electrode 24 may be connected to the second external terminal 120 (shown in FIG. 1 ). Figure 1A The second shielding electrode 24 can be connected to the second end 21 in the Z direction 136 (in Figure 1A The second shield electrode 24 may be substantially aligned with the first shield electrode 22.

[0115] A single shielding capacitance region 34 may be formed between the first shielding electrode 22 and the second shielding electrode 24. More specifically, Figure 3B In the embodiment of the present invention, the first shield electrode 22 has a longitudinal edge 28, which is aligned with the transverse direction 134 and faces away from the first external terminal 118 (at Figure 1ASimilarly, the second shield electrode 24 has a longitudinal edge 28 that is aligned with the transverse direction 134 and faces away from the second external terminal 120 (shown in FIG. Figure 1A ) and the second end 21. A shield gap distance 42 may be formed between the longitudinal edge 28 of the first shield electrode 22 and the longitudinal edge 28 of the second shield electrode 24 in the longitudinal direction 132. Figure 3B As shown, the capacitive region 34 is formed in a gap between the longitudinal edge 28 of the first shield electrode 22 and the longitudinal edge 28 of the second shield electrode 24 .

[0116] Return to reference Figure 1A , the capacitor 100 may be part of a device 1 that includes a mounting surface 5. Figure 1A As shown, in some embodiments, capacitor 100 is configured to be mounted to mounting surface 5, which can be any surface known in the art on which a capacitor can be mounted or coupled. Figure 1A As further shown, the capacitor 100 is mounted to the mounting surface 5 such that each of the plurality of active electrode layers 102, 104 of the capacitor 100 extends parallel to the mounting surface. As described elsewhere herein, the capacitor 100 in a horizontal orientation as shown in the figures (where the active electrodes extend parallel to the mounting surface 5) may perform better than a capacitor mounted in a vertical electrode orientation configured as described herein.

[0117] refer to Figure 4 , a schematic side cross-sectional view of another embodiment of a broadband multilayer capacitor is provided. Figure 1A Similar to the capacitor 100 shown in FIG. Figure 4 The multilayer capacitor 400 shown in the embodiment includes a first external terminal 118 disposed along a first end 19 and a second external terminal 120 disposed along a second end 21, which is opposite to the first end 19 in the longitudinal direction 132. In addition, as described with reference to capacitor 100, capacitor 400 may include a plurality of dielectric layers and a plurality of electrode layers, wherein the electrode layers are interlaced in an opposing and spaced relationship, and a dielectric layer is located between each adjacent electrode layer.

[0118] More specifically, in Figure 4In some embodiments, the capacitor 400 has a monolithic body 98 including a plurality of dielectric layers stacked in the Z-direction 136 and extending between a first end 19 and an opposite second end 21, wherein a first external terminal 118 is disposed along the first end 19 and a second external terminal 120 is disposed along the second end 21. The first external terminal 118 includes a first portion 140 extending along an outer surface (e.g., bottom surface 20) of the monolithic body, and similarly, the second external terminal 120 includes a first portion 144 extending along an outer surface (e.g., bottom surface 20) of the monolithic body. The first portion 140 of the first external terminal 118 is spaced apart from the first portion 144 of the second external terminal 120 by a first external terminal spacing distance 142. Likewise, in some embodiments, the first external terminal 118 includes a second portion 146 extending along another outer surface (e.g., top surface 18) of the monolithic body, and the second external terminal 120 includes a second portion 150 extending along another outer surface (e.g., top surface 18) of the monolithic body. The second portion 146 of the first external terminal 118 is spaced apart from the second portion 150 of the second external terminal 120 by a second external terminal spacing distance 148. The first external terminal spacing distance 142 and / or the second external terminal spacing distance 148 may be as described with reference to Figure 1A 1. The capacitor 100 shown in FIG. 1 may be configured as described, for example, the first external terminal separation distance 142 may be the same as or different from the second external terminal separation distance 148, and / or may be within one of the specified ranges.

[0119] Additionally, as described above, capacitor 400 may include a shielding electrode. Figure 4 As shown, the multilayer capacitor 400 may include a first shielding region 210 and a second shielding region 212, and each of the shielding regions 210, 212 may include (for example, as described above with reference to Figure 3A and Figure 3B ) one or more shield electrode layers 26. In some embodiments, the shielding regions 210, 212 may be separated from the active electrode region 14 by a dielectric region (eg, a dielectric region that does not include any electrode layers).

[0120] A shield electrode region thickness 61 may be defined in the Z direction 136. The shield electrode region thickness 61 may be defined on an outer surface of the capacitor 100 (eg, Figure 4 The top surface 18 shown in FIG. 1 is connected to the outermost electrode layer (e.g., Figure 4 The ratio of the capacitor thickness 56 to the shielding electrode region thickness 61 may be in the range of about 1.1 to about 20.

[0121] The shield electrode layer 26 may have a first shield electrode configuration, wherein (eg, as shown in FIG. 1 ) Figure 3BEach shield electrode 22, 24 is generally rectangular. In other embodiments, the shield electrode layer 26 may have a second shield electrode configuration, wherein (for example, as described above with reference to Figure 3A The shielding electrodes 22 , 24 (as explained above) include a step 25 .

[0122] As mentioned above, the active electrode region 14 may be disposed between the first shielding region 210 and the second shielding region 212. The active electrode region 14 may include a plurality of alternating active electrode layers 102, 104, which may be, for example, as described in reference Figure 1A As explained or in other embodiments as reference FIG. 8A to FIG. 8C Additionally, a pair of ceramic caps 214 may be disposed along the top surface and / or the bottom surface of the capacitor 400. The ceramic caps 214 may include a dielectric material that is the same as or similar to the dielectric material of the plurality of dielectric layers.

[0123] Still reference Figure 4 In some embodiments, the multilayer capacitor 400 may further include anchoring electrode regions 402, 404, 406, and / or 408. For example, the multilayer capacitor 400 may include a first anchoring electrode region 404 on top of the active electrode region 14. In addition, the first shielding electrode region 210 including the shielding electrode layer 26 may be located above the first anchoring electrode region 404, for example, on top of the first anchoring electrode region. In addition, the second anchoring electrode region 402 may be located above the first shielding electrode region 210, for example, on top of the first shielding electrode region. Similarly, the multilayer capacitor 400 may include a third anchoring electrode region 406 below the active electrode region 14 (e.g., immediately below the active electrode region 14). In addition, the second shielding electrode region 212 including the shielding electrode layer 26 may be located below the third anchoring electrode region 406, for example, immediately below the third anchoring electrode region 406. In addition, the fourth anchoring electrode region 408 may be located below the second shielding electrode region 212, for example, immediately below the second shielding electrode region. In this regard, for example, the active electrode region 14 may be disposed between the first anchor electrode region 404 and the third anchor electrode region 406. The active electrode region 14 may be as described above with reference to FIG. Figure 2 A. Figure 2 B and Figure 2 C as described.

[0124] refer to Figure 5A, the anchor electrode regions 402, 404, 406, and / or 408 may include a plurality of anchor electrode layers 410, each having a pair of anchor electrodes 412. The anchor electrodes 412 may include a pair of electrode arms 414. Each electrode arm 414 of the anchor electrodes 412 may include a main portion 428 and a step portion 430. More specifically, the electrode arm 414 of the first anchor electrode 412 may include a first longitudinal edge 416 that extends in the transverse direction 134 and may define an edge of the step portion 430. The second longitudinal edge 418 may extend in the transverse direction 134 and may define an edge of the main portion 428 of the arm 414. The first longitudinal edge 416 may be offset from the second longitudinal edge 418 in the longitudinal direction 132 by an arm offset distance 420. As such, the electrode arms 414 of the anchor electrodes 412 may include a step 426 that is offset inwardly from the outer lateral edge 425 of the anchor electrode 412.

[0125] One or both electrode arms 414 of the first anchor electrode 412 and / or the second anchor electrode 412 may include respective main portions 428 and step portions 430. For example, the two arms 414 of the two electrodes 412 may include respective main portions 428 and step portions 430, such as Figure 5A As shown. A step arm gap 422 may be formed between the step portions 430 of the aligned arms 414. A main arm gap 424 may be formed between the main portions 428 of the aligned arms 414.

[0126] refer to Figure 5B and Figure 5C , the anchor electrode 412 can have various configurations. For example, referring to Figure 5B In some embodiments, the electrode arm 414 of the anchor electrode 412 may not include a step. For example, such an electrode may have a C-shaped configuration without a step. Figure 5C , the step 426 can be offset from the inner lateral edge 427 of the arm 414 of the anchor electrode 412. However, other configurations are possible. For example, in some embodiments, the step 426 can be offset from both the outer lateral edge 425 and the inner lateral edge 427.

[0127] refer to Figure 6 , a schematic side cross-sectional view of another embodiment of a broadband multilayer capacitor is provided. Figure 1A Similar to the capacitor 100 shown in FIG. Figure 6The multilayer capacitor 600 shown in the embodiment of has a monolithic body 98 that includes a plurality of dielectric layers stacked in the Z direction 136 and extending between a first end 19 and an opposite second end 21. A first external terminal 118 is disposed along the first end 19, and a second external terminal 21 is disposed along the second end 21. The first external terminal 118 includes a first portion 140 extending along an outer surface (e.g., bottom surface 20) of the monolithic body, and similarly, the second external terminal 120 includes a first portion 144 extending along an outer surface (e.g., bottom surface 20) of the monolithic body. The first portion 140 of the first external terminal 118 is spaced apart from the first portion 144 of the second external terminal 120 by a first external terminal spacing distance 142. Likewise, in some embodiments, the first external terminal 118 includes a second portion 146 extending along another outer surface (e.g., top surface 18) of the monolithic body, and the second external terminal 120 includes a second portion 150 extending along another outer surface (e.g., top surface 18) of the monolithic body. The second portion 146 of the first external terminal 118 is spaced apart from the second portion 150 of the second external terminal 120 by a second external terminal spacing distance 148. The first external terminal spacing distance 142 and / or the second external terminal spacing distance 148 may be as described with reference to Figure 1A 1. The capacitor 100 shown in FIG. 1 may be configured as described, for example, the first external terminal separation distance 142 may be the same as or different from the second external terminal separation distance 148, and / or may be within one of the specified ranges.

[0128] like Figure 6 As depicted, in some embodiments, the dielectric region 12 and / or the additional dielectric region 115 may not have an electrode layer that extends from the first end 19 or the second end 21 of the capacitor 100 more than about 40% of the length 17 of the capacitor 600. For example, in such embodiments, the dielectric region 12 and / or the additional dielectric region 115 may include one or more floating electrodes and / or dummy electrode tabs. However, in other embodiments, such as those described above with reference to Figure 1A As described, the dielectric region 12 and / or the additional dielectric region 115 may not have all electrode layers.

[0129] In some embodiments, the broadband multilayer ceramic capacitor 600 may not have the shielding electrodes 22, 24 above the plurality of active electrode layers 102, 104 in the Z-direction 136. For example, in some embodiments, the broadband multilayer ceramic capacitor 600 may not have the shielding electrodes 22, 24 above the lowest active electrode layer 101 among the plurality of active electrode layers 102, 104 in the Z-direction 136. In addition, in some embodiments, the capacitor 400 may not have the shielding electrodes 22, 24 below the plurality of active electrode layers 102, 104 in the Z-direction 136. For example, in some embodiments, the capacitor 600 may not have the shielding electrodes 22, 24 below the highest active electrode layer 103 among the plurality of active electrode layers 102, 104 in the Z-direction 136.

[0130] As previously described, in some embodiments, capacitor 600 includes dummy tab electrodes 52, 54 that can facilitate, for example, depositing and / or forming terminals 118, 120 using a pure copper termination process. Dummy tab electrodes 52, 54 can extend from first end 19 or second end 21 by less than about 40% of capacitor length 17. For example, in some embodiments, dummy tab electrodes 52, 54 can extend by less than about 40% of capacitor length 17, in some embodiments less than about 30% of the capacitor length, in some embodiments less than about 25% of the capacitor length, in some embodiments less than about 20% of the capacitor length, in some embodiments less than about 15% of the capacitor length, and in some embodiments less than about 10% of the capacitor length. Additionally, in some embodiments, region 115 between shield electrode region 16 and active electrode region 14 can include dummy tab electrodes 55, 57 that can be configured similarly to dummy tab electrodes 52, 54.

[0131] In some embodiments, capacitor 100 may include one or more floating electrodes. Figure 6In the embodiment of the present invention, the floating electrode 152 is located in the dielectric region 12. However, in other embodiments, one or more floating electrodes 152 may be located in the active electrode region 14. Typically, such floating electrodes 152 are not directly connected to the external terminals 118, 120. The one or more floating electrodes 152 may be positioned and configured according to any method known in the art. For example, one or more floating electrodes may be provided so that the one or more floating electrodes overlap at least a portion (e.g., a central portion) of the first active electrode and / or the second active electrode of the active electrode layer. In this regard, the floating electrode layer is alternately stacked and arranged with the first electrode layer and the second electrode layer; in this regard, the layers may be separated by a dielectric layer. In addition, such floating electrodes may have any shape known in the art. For example, in one embodiment, the floating electrode layer may include at least one floating electrode having a dagger-shaped configuration. In another embodiment, the floating electrode may be similar to the configuration and shape of the first active electrode layer 102 as described herein.

[0132] Figure 7 Another example embodiment of a capacitor 700 according to aspects of the present disclosure is shown. The capacitor 700 may be generally similar to Figure 1A The capacitor 100 is just Figure 7 The capacitor 700 in FIG. 1 may include an additional shielding electrode region 166 and as shown in FIG. FIG. 8A to FIG. 8C As further described, capacitor 700 can include a first active electrode layer 102 having two active electrodes 106, 108 and a second active electrode layer 104 having two active electrodes 107, 109. Capacitor 700 can be generally symmetrical about longitudinal centerline 165. Additional shielding electrode region 166 can be generally configured similarly to shielding electrode region 16. Dielectric region 168 between active electrode region 14 and additional shielding electrode region 166 can generally have no electrode layer or no electrode layer extending more than 40% of length 17 of capacitor 700 (e.g., in some embodiments, region 168 can include a dummy electrode). As shown in FIG. Figure 7 As shown and as referenced Figure 1A As described in more detail, capacitor 700 may be mounted to mounting surface 5 of device 1 .

[0133] As previously mentioned, in some embodiments of the capacitor as described herein, each active electrode layer 102, 104 may include one or more active electrodes, such as those described in reference Figure 7 As shown in capacitor 700. Fig. 8A FIG. 1 shows an exploded perspective view of one embodiment of an active electrode pattern of one or more electrodes in the active electrode region 14 according to aspects of the present disclosure. Fig. 8AAs shown in the embodiment of FIG. 1 , the first electrode layer 102 includes a first active electrode 106 and a second active electrode 108. The first active electrode 106 can be connected to the first external terminal 118 ( Figure 7 ) is connected, and the second active electrode 108 can be connected to the second external terminal 120 ( Figure 7 The dielectric material 124 separates the first active electrode 106 from the second active electrode 108 in the first active electrode layer 102 .

[0134] like Fig. 8A As further shown, the second electrode layer 104 can be configured similarly to the first electrode layer 102 of the depicted capacitor 700. In the illustrated embodiment, the second electrode layer 104 shown includes a third active electrode 107 and a fourth active electrode 109. The third active electrode 107 can be connected to the first external terminal 118 ( Figure 7 ) is connected, and the fourth active electrode 109 can be connected to the second external terminal 120 ( Figure 7 The dielectric material 124 separates the third active electrode 107 from the fourth active electrode 109 in the second active electrode layer 104 .

[0135] like Fig. 8A As further shown, the first active electrode 106 can be coplanar with the second active electrode 108. Similarly, the third active electrode 107 can be coplanar with the fourth active electrode 109. In addition, the first active electrode 106 can overlap with the fourth active electrode 109 in the longitudinal direction 132. The first active electrode 106 can be overlapped along the overlap distance 122 ( Figure 7 ) overlaps with the fourth active electrode. Figure 7 and Fig. 8A As shown, in at least some embodiments, the multilayer capacitor 700 may include alternating first active electrode layers 102 and second active electrode layers 104 . Figure 7 The side cross-sectional view of FIG. 7 shows a capacitor 700 having a total of four first electrode layers 102 and three second electrode layers 104. However, it should be understood that any number of electrode layers 102, 104 may be employed to obtain a desired capacitance for a desired application.

[0136] refer to Figure 8B and Figure 8C , a capacitance region may be formed between the first active electrode 106 and the second active electrode 108 of the first electrode layer 102, and a capacitance region may be formed between the third active electrode 107 and the fourth active electrode 109 of the second electrode layer 104. More specifically, Figure 8B and Figure 8CIn the illustrated embodiment, an end gap distance 110 is defined between an end 112 of the first active electrode 106 and an end 114 of the second active electrode 108, and an end gap distance 111 is defined between an end 113 of the third active electrode 107 and an end 117 of the fourth active electrode 109. Figure 8B As shown in the embodiment of FIG. 1 , a capacitor region 116 may be formed between the end 112 of the first active electrode 106 and the end 114 of the second active electrode 108. Figure 8C As shown in the embodiment of FIG. 1 , a capacitor region 119 may be formed between the end portion 113 of the third active electrode 107 and the end portion 117 of the fourth active electrode 109 .

[0137] refer to Fig. 9 , a side cross-sectional schematic diagram of another embodiment of a capacitor 900 is provided. It will be understood that the capacitor 900 can be similar to the above reference Figure 1A The capacitor 100 is described. However, with Figure 1A Compared to the embodiment shown, Fig. 9 The capacitor 900 shown in FIG. 1 lacks the shield electrode region 16 and includes more active electrode layers 102, 104. Thus, as previously described, some embodiments of multilayer ceramic capacitors without shield electrodes and with any suitable number of active electrode layers may be provided. Fig. 9 Also shown, capacitor 900 may be as Fig. 9 As shown and as reference Figure 1A Mounted in the apparatus 1, mounted to the mounting surface 5 as described in more detail.

[0138] In addition, the dielectric region 12 between the active electrodes 102, 104 and the top surface 18 and the bottom surface 20 of the capacitor 900 is relatively thin, for example, so that there is little dielectric between the outermost active electrode layer and the outer surface (e.g., Fig. 9The outermost active-to-surface distance 60 (between the lowest active electrode layer 101 shown and the bottom surface 20) is relatively small. For example, the ratio of the capacitor thickness 56 to the outermost active-to-surface distance 60 can be greater than about 2. For example, in some embodiments, the ratio of the capacitor thickness 56 to the outermost active-to-surface distance 60 can be 1.1 or greater, in some embodiments 2 or greater, in some embodiments 3 or greater, in some embodiments 5 or greater, in some embodiments 10 or greater, in some embodiments 20 or greater, in some embodiments 30 or greater, in some embodiments 40 or greater, and in some embodiments 50 or greater. In addition, in some embodiments, the outermost active-to-surface distance 60 can be 150 microns or less, in some embodiments, 125 microns or less, in some embodiments, 100 microns or less, in some embodiments, 90 microns or less, in some embodiments, 75 microns or less, in some embodiments, 60 microns or less, in some embodiments, 40 microns or less, in some embodiments, 25 microns or less, in some embodiments, 15 microns or less, in some embodiments, 10 microns or less, and in some embodiments, 5 microns or less.

[0139] II. Test Method

[0140] According to aspects of the present disclosure, a test assembly can be used to test performance characteristics of a capacitor, such as insertion loss and return loss. For example, the capacitor can be mounted to a test board. Both input and output lines can be connected to the test board. The test board can include microstrip lines that electrically connect the input and output lines to corresponding external terminals of the capacitor.

[0141] An input signal can be applied to the input line using a source signal generator (e.g., 1806 Keithley 2400 Series Source Measure Unit (SMU), such as Keithley 2410-C SMU), and the resulting output signal of the capacitor can be measured at the output line (e.g., using a source signal generator). This process is repeated for various configurations of capacitors to produce insertion loss curves such as those described below with reference to Examples 1 to 3.

[0142] III. Examples

[0143] Example 1

[0144] Fig.10 Shows multiple Figure 1A Multiple insertion loss response curves 1000 (S 21), these broadband multilayer ceramic capacitors have a 0201 case size and a capacitance of 220 nanofarads (nF). The plurality of capacitors 100 have an outermost active-to-surface distance 60 of about 1.2 mils or 30.5 microns. Each capacitor 100 of the plurality of capacitors 100 is mounted to a test board in a horizontal orientation, with each electrode of the capacitor 100 extending parallel to the test board.

[0145] As shown in response curve 1000, within the frequency ranges from about 1 GHz to about 12 GHz and from about 22 GHz to about 32 GHz, the insertion loss of the capacitor is greater than -0.20 dB. Within the frequency ranges from about 12 GHz to about 22 GHz and from about 32 GHz to about 37 GHz, the insertion loss of the capacitor is greater than -0.30 dB. Within the frequency range from about 37 GHz to about 47 GHz, the insertion loss of the capacitor is greater than -0.60 dB. Within the frequency range from about 47 GHz to about 60 GHz, the insertion loss of the capacitor is greater than -0.80 dB; and within the frequency range from about 60 GHz to about 67 GHz, the insertion loss of the capacitor is greater than about -0.90 dB.

[0146] Example 2

[0147] Fig.11 A plurality of insertion loss response curves 1100 (S) of a plurality of broadband multilayer ceramic capacitors 100 are shown. 21 ), the plurality of broadband multilayer ceramic capacitors having a 0201 case size, a capacitance of 220 nF, and a first external terminal separation distance 142 of about 10 mil or about 250 microns. The plurality of capacitors 100 have an outermost active-to-surface distance 60 of about 1.2 mil or 30.5 microns. Each capacitor 100 of the plurality of capacitors 100 is mounted to a test board in a horizontal orientation, with each electrode of the capacitor 100 extending parallel to the test board.

[0148] As shown in response curve 1100, within the frequency range from about 1 GHz to about 15 GHz and from about 25 GHz to about 37 GHz, the insertion loss of the capacitor is greater than -0.25 dB. Within the frequency range from about 15 GHz to about 25 GHz and from about 37 GHz to about 60 GHz, the insertion loss of the capacitor is greater than -0.50 dB. Within the frequency range from about 60 GHz to about 67 GHz, the insertion loss of the capacitor is greater than -0.60 dB.

[0149] Example 3

[0150] Fig.12 A plurality of insertion loss response curves 1200 (S) of a plurality of broadband multilayer ceramic capacitors 100 are shown.21 ), the plurality of broadband multilayer ceramic capacitors having a 0201 case size, a capacitance of 100 nF, an outermost active-to-surface distance 60 of approximately 1.4 mil or 35.6 microns, and a capacitor thickness 56 of 22 millimeters (mm). Each capacitor 100 of the plurality of capacitors 100 is mounted to a test board in a horizontal orientation, with electrodes of the capacitor 100 extending parallel to the test board.

[0151] Fig.12 Also shown are multiple insertion loss response curves 1250 (S 21 ), the plurality of multilayer capacitors having a 0201 case size, a capacitance of 100 nF, an outermost active-to-surface distance 60 of approximately 1.2 mil or 30.5 microns, and a capacitor thickness 56 of 15 mm. Each capacitor 100 of the plurality of capacitors 100 is mounted to a test board in a horizontal orientation, with electrodes of the capacitor 100 extending parallel to the test board.

[0152] like Fig.12 As shown in curve 1200 in , the insertion loss of the 22 mm thick capacitor is greater than -0.50 dB in the frequency range from about 1 GHz to about 43 GHz, greater than -1.00 dB in the frequency range from about 43 GHz to about 60 GHz, and greater than -1.20 dB in the frequency range from about 60 GHz to about 67 GHz.

[0153] like Fig.12 As shown in curve 1250 in , the insertion loss of the 15 mm thick capacitor is greater than -0.50 dB in the frequency range from about 1 GHz to about 37 GHz, greater than -1.00 dB in the frequency ranges from about 37 GHz to about 48 GHz and from about 53 GHz to about 67 GHz, and greater than -1.20 dB in the frequency range from about 48 GHz to about 53 GHz.

[0154] Those of ordinary skill in the art can practice these and other modifications and variations of the present invention without departing from the spirit and scope of the present invention. In addition, it should be understood that the aspects of the various embodiments can be interchanged in whole or in part. In addition, those of ordinary skill in the art will understand that the foregoing description is only as an example and is not intended to limit the present invention further described in the appended claims.

Claims

1. A broadband multilayer ceramic capacitor comprising: a monolithic body comprising a plurality of dielectric layers stacked in the Z direction, the monolithic body having a first end, the first end being opposite to the second end; a first external terminal disposed along the first end of the monolithic body, the first external terminal including a first portion extending along an outer surface of the monolithic body; a second external terminal disposed along the second end of the monolithic body, the second external terminal comprising a first portion extending along the outer surface of the monolithic body, the first portion of the first external terminal being spaced apart from the first portion of the second external terminal by a first external terminal spacing distance; as well as an active electrode region, the active electrode region comprising a plurality of first active electrode layers and a plurality of second active electrode layers, the plurality of first active electrode layers comprising at least one active electrode having a rectangular shape, and the plurality of second active electrode layers comprising at least one second active electrode having a rectangular shape, the plurality of first active electrode layers being connected to the first external terminal, and the plurality of second active electrode layers being connected to the second external terminal, The active electrode region includes an outermost active electrode layer, and the outermost active electrode layer is spaced apart from the outer surface by an outermost active-to-surface distance. wherein the single-piece body has a thickness along the Z direction, wherein the ratio of the thickness to the outermost active-to-surface distance is 1.1 or greater, wherein the capacitor has a capacitor length extending in a longitudinal direction, and Wherein, a ratio of the capacitor length to the first external terminal spacing distance is 15 or greater.

2. The broadband multilayer ceramic capacitor according to claim 1, wherein: The outermost active-to-surface distance is 150 microns or less.

3. The broadband multilayer ceramic capacitor according to claim 1, wherein: The first external terminals are spaced apart by a distance of 250 micrometers or less.

4. The broadband multilayer ceramic capacitor according to claim 1, wherein: The broadband multilayer ceramic capacitor is configured for mounting to a mounting surface, wherein each first active electrode layer of the plurality of first active electrode layers and each second active electrode layer of the plurality of second active electrode layers extends parallel to the mounting surface.

5. The broadband multilayer ceramic capacitor according to claim 4, wherein: The broadband multilayer ceramic capacitor exhibits an insertion loss greater than about -1.2 dB from about 5 GHz to about 67 GHz.

6. The broadband multilayer ceramic capacitor of claim 1, wherein: The outer surface is a bottom surface of the monolithic body.

7. The broadband multilayer ceramic capacitor of claim 1, wherein: The outer surface is the top surface of the monolithic body.

8. The broadband multilayer ceramic capacitor of claim 1, further comprising: A shielding electrode region is located between the active electrode region and the outer surface.

9. The broadband multilayer ceramic capacitor of claim 1, further comprising: A dielectric region is located between the active electrode region and the second outer surface of the monolithic body in the Z direction.

10. The broadband multilayer ceramic capacitor of claim 9, wherein: The second outer surface is opposite to the outer surface along the Z direction.

11. The broadband multilayer ceramic capacitor of claim 9, wherein: The dielectric region has no electrode layer extending from the first end of the monolithic body or the second end of the monolithic body more than 40% of the length of the capacitor.

12. The broadband multilayer ceramic capacitor of claim 9, wherein: The dielectric region has no electrode layer.

13. The broadband multilayer ceramic capacitor of claim 1 further comprising: At least one floating electrode, the at least one floating electrode is not connected to the first external terminal or the second external terminal; wherein the at least one floating electrode is disposed in a dielectric region, the dielectric region being located between the shielding electrode region and a top surface of the capacitor in the Z direction.

14. The broadband multilayer ceramic capacitor of claim 1, wherein: The broadband multilayer ceramic capacitor exhibits an insertion loss greater than about -1.0 dB at about 67 GHz.

15. The broadband multilayer ceramic capacitor of claim 1, wherein: The broadband multilayer ceramic capacitor exhibits an insertion loss greater than about -0.6 dB at about 40 GHz.

16. The broadband multilayer ceramic capacitor of claim 1, wherein: The broadband multilayer ceramic capacitor exhibits an insertion loss greater than about -0.2 dB at about 10 GHz.

17. The broadband multilayer ceramic capacitor of claim 1, wherein: The broadband multilayer ceramic capacitor exhibits an insertion loss greater than about -0.5 dB from about 5 GHz to about 20 GHz.

18. The broadband multilayer ceramic capacitor of claim 1, wherein: The broadband multilayer ceramic capacitor exhibits an insertion loss greater than about -0.6 dB from about 20 GHz to about 40 GHz.

19. The broadband multilayer ceramic capacitor of claim 1, wherein: The broadband multilayer ceramic capacitor exhibits an insertion loss greater than about -1.0 dB from about 40 GHz to about 50 GHz.

20. The broadband multilayer ceramic capacitor of claim 1, wherein: The broadband multilayer ceramic capacitor exhibits an insertion loss greater than about -1.2 dB from about 50 GHz to about 60 GHz.

21. The broadband multilayer ceramic capacitor of claim 1, wherein: The broadband multilayer ceramic capacitor exhibits an insertion loss greater than about -1.2 dB from about 60 GHz to about 67 GHz.

22. A device comprising: Mounting surface; as well as Wideband Multilayer Ceramic Capacitors, including: a monolithic body comprising a plurality of dielectric layers stacked in the Z direction, the monolithic body having a first end, the first end being opposite to the second end; a first external terminal disposed along the first end of the monolithic body, the first external terminal including a first portion extending along an outer surface of the monolithic body; a second external terminal disposed along the second end of the monolithic body, the second external terminal including a first portion extending along the outer surface of the monolithic body, the first portion of the first external terminal being spaced apart from the first portion of the second external terminal by a first external terminal spacing distance; and an active electrode region, the active electrode region comprising a plurality of first active electrode layers and a plurality of second active electrode layers, the plurality of first active electrode layers comprising at least one active electrode having a rectangular shape, and the plurality of second active electrode layers comprising at least one second active electrode having a rectangular shape, the plurality of first active electrode layers being connected to the first external terminal, and the plurality of second active electrode layers being connected to the second external terminal, wherein the active electrode region comprises an outermost active electrode layer, the outermost active electrode layer being spaced apart from the outer surface by an outermost active-to-surface distance; wherein the monolithic body has a thickness along the Z direction; wherein a ratio of the thickness to the outermost active-to-surface distance is 1.1 or greater; wherein the capacitor has a capacitor length extending along a longitudinal direction; and wherein a ratio of the capacitor length to the first external terminal spacing distance is 15 or greater, wherein the broadband multilayer ceramic capacitor is mounted to the mounting surface in a horizontal orientation such that each of a plurality of active electrode layers extends parallel to the mounting surface.

23. The apparatus of claim 22, wherein: Each of the plurality of first active electrode layers includes at least one active electrode having a rectangular shape.

24. The apparatus of claim 22, wherein: Each of the plurality of second active electrode layers includes at least one active electrode having a rectangular shape.

25. The apparatus of claim 22, wherein: The outermost active-to-surface distance is 100 microns or less, and the first external terminal spacing distance is 75 microns or less.

26. A method of forming a broadband multilayer ceramic capacitor, the method comprising: forming a plurality of active electrodes on the plurality of active electrode layers, wherein at least one first active electrode layer among the plurality of active electrode layers comprises a first active electrode, and at least one second active electrode layer among the plurality of active electrode layers comprises a second active electrode; stacking the plurality of active electrode layers and the plurality of dielectric layers to form a monolithic body having an outer surface, the plurality of active electrode layers including an outermost active electrode layer disposed closest to the outer surface of the monolithic body among the plurality of active electrode layers; depositing a first external terminal along a first end of the capacitor, the first external terminal being connected to the first active electrode layer, the first external terminal comprising a first portion extending along the outer surface of the capacitor; and depositing a second external terminal along a second end of the capacitor, the second end being opposite to the first end, the second external terminal being connected to the second active electrode layer, the second external terminal comprising a first portion extending along the outer surface of the capacitor, wherein the outermost active electrode layer is spaced from the outer surface by an outermost active-to-surface distance, wherein the single-piece body has a thickness along the Z direction, wherein the ratio of the thickness to the outermost active-to-surface distance is 1.1 or greater, wherein the capacitor has a capacitor length extending in a longitudinal direction, and Wherein, a ratio of the capacitor length to the first external terminal spacing distance is 15 or greater.

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