Method for transferring layer from source substrate to target substrate

Abstract

The present specification relates to a method of transferring a layer (15) from a source substrate (13) to a target substrate (17), comprising the steps of: a) arranging a masking disc on a central portion of a bonding surface of the layer and / or on a central portion of a bonding surface of the target substrate (17); b) performing an ion etching to form a step (29, 30) opposite the bonding surface of the layer (15) and / or the peripheral portion of the bonding surface of the target substrate (17) that is not covered by the masking disc; c) removing the masking disc; d) activating the bonding surface of the layer and the bonding surface of the target substrate (17); and e) contacting the bonding surface of the layer with the bonding surface of the target substrate (17).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the priority of French patent application No. 2204713 filed on May 18, 2022 and entitled “Method for transferring a layer from a source substrate to a target substrate”, which application is considered to be an integral part of this description to the extent provided by law. Technical Field

[0003] The present disclosure generally relates to methods of manufacturing microelectronic components based on semiconductor materials. More specifically, it is intended to relate to a method of transferring a semiconductor layer from a source substrate to a target substrate. Background Art

[0004] In microelectronic component manufacturing methods, layer transfer is currently used to transfer relatively thin semiconductor layers of high crystal quality onto thicker target substrates of lower crystal quality or made of cheaper materials.

[0005] After transfer, the transferred layer can be used as a substrate for an epitaxial step. Microelectronic components can then be formed within and on top of the epitaxial layer.

[0006] It would be desirable to at least partially overcome certain disadvantages of known methods for transferring a semiconductor layer from a source substrate to a target substrate.

[0007] More particularly, improvement of the quality of the edges of the transferred layer is contemplated herein. Summary of the invention

[0008] One embodiment provides a method of transferring a layer from a source substrate to a target substrate, the method comprising the steps of:

[0009] a) arranging a masking disk on a central portion of the bonding surface of the layer and / or the target substrate;

[0010] b) performing ion etching to form a step in front of a peripheral portion of the bonding surface of the layer and / or the target substrate that is not covered by the masking disk;

[0011] c) removing the masking disk;

[0012] d) activating the bonding surface of the layer and the bonding surface of the target substrate by ion etching or ion deposition of a bonding material; and

[0013] e) after step d), placing the bonding surface of the layer in contact with a bonding surface of a target substrate, wherein steps b) and d) are performed sequentially in the same ion processing chamber; and

[0014] Wherein, steps d) and e) are carried out under vacuum without breaking the vacuum between the two steps.

[0015] According to one embodiment, the target substrate and / or the source substrate has tapered edges across the first width.

[0016] According to one embodiment, after step b), the step extends from an edge of the layer and / or from an edge of the target substrate over a width greater than or equal to the first width.

[0017] According to one embodiment, the diameter of the disk is smaller than the diameter of the source substrate and / or smaller than the diameter of the target substrate.

[0018] According to one embodiment, the method comprises a step f) of removing the source matrix after step e).

[0019] According to one embodiment, step f) comprises an annealing step which causes the assembly obtained at the end of step e) to break in the plane of the implanted buried layer separating said layer from the source matrix.

[0020] According to an embodiment, the layer is a semiconductor layer.

[0021] According to one embodiment, the method comprises, after step f), a step of epitaxy on top of and in contact with the surface of said layer opposite to the target substrate.

[0022] According to one embodiment, after step b), the step extends from the bonding surface of the layer and / or the bonding surface of the target substrate down to a depth of more than 700 nm.

[0023] According to one embodiment, step d) comprises depositing a bonding layer on the bonding surface of the layer and / or on the surface of the target substrate.

[0024] According to an embodiment, the thickness of the bonding layer is in the range of 0.2 nm to 100 nm, for example in the range of 1 nm to 20 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0026] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1F is a cross-sectional view partially and schematically showing sequential steps of an example of a method of transferring a semiconductor layer from a source substrate to a target substrate according to a first embodiment; and

[0027] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E and Figure 2F is a cross-sectional view partially and schematically illustrating consecutive steps of an example of a method of transferring a semiconductor layer from a source substrate to a target substrate according to a second embodiment. DETAILED DESCRIPTION

[0028] In the various drawings, the same features are represented by the same reference numerals. In particular, in various embodiments, common structural features and / or functional features may have the same reference numerals, and the same structural characteristics, dimensional characteristics, and material characteristics may be provided.

[0029] For the sake of clarity, only the steps and elements that are helpful for understanding the embodiments described herein are described and shown in detail. In particular, the method of manufacturing microelectronic components based on transferred semiconductor layers is not described in detail, the described transfer method is compatible with all or most commonly used microelectronic component manufacturing methods.

[0030] In the following disclosure, when referring to absolute position qualifiers (such as terms "front", "back", "top", "bottom", "left", "right", etc.) or relative position qualifiers (such as terms "above", "below", "upper", "lower", etc.) or orientation qualifiers (such as "horizontal", "vertical", etc.), unless otherwise stated, the orientation of the figure should be referred to.

[0031] Unless otherwise indicated, the expressions "about", "approximately", "substantially" and "approximately" mean within 10%, preferably within 5%.

[0032] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1F is a cross-sectional view partially and schematically illustrating consecutive steps of an example of a method of transferring a semiconductor layer from a source substrate to a target substrate according to a first embodiment.

[0033] Figure 1A A structure 110 is shown on its left part, which includes a source substrate 13 and a semiconductor layer 15 to be transferred, and a target substrate 17 is shown on its right part.

[0034] The semiconductor layer 15 to be transferred is arranged on the upper surface of the substrate 13 and, for example, in contact with it. For example, the semiconductor layer 15 extends continuously across the entire upper surface of the substrate 13 with a substantially uniform thickness. The semiconductor layer 15 is, for example, a single crystal layer. As an example, the semiconductor layer 15 is a silicon carbide (SiC) layer, for example, a single crystal of the 4H-SiC type. As a variation, the semiconductor layer 15 is made of germanium (Ge), for example, a single crystal. The described embodiments are not limited to these specific examples.

[0035] The source matrix 13 is made of, for example, a semiconductor material. For example, the source matrix 13 is made of the same material as the layer 15. However, the described embodiments are not limited to this particular case.

[0036] For example, the thickness of the layer 15 to be transferred is in the range from 100 nm to 10 μm, for example in the range from 300 nm to 2 μm.

[0037] For example, the thickness of the source matrix 13 is in the range from 100 μm to 1 mm, for example in the range from 250 μm to 800 μm, for example approximately 350 μm.

[0038] The target substrate 17 can be made of a semiconductor material or of a dielectric material. The target substrate 17 is, for example, a semiconductor wafer, for example made of silicon or of carbide polysilicon, for example of the 3C-SiC type.

[0039] For example, the target substrate 17 and the source substrate 13 have substantially the same shape and the same size in a top view. For example, in a top view, the target substrate 17 and the source substrate 13 are both circular in shape and have, for example, the same diameter.

[0040] In order to limit the risk of breakage, the target substrate 17 and / or the source substrate 13 preferably has a tapered or rounded edge and lip region, for example, across a peripheral annular band with a width ranging from 0.1 mm to 5 mm, for example, from 0.2 mm to 3 mm. In other words, the target substrate 17 and / or the source substrate 13 has at its periphery a thickness that decreases as the distance from the center of the substrate increases, for example, across a peripheral annular band with a width ranging from 0.1 mm to 5 mm, for example, from 0.2 to 3 mm.

[0041] During bonding of the layer 15 to be transferred to the target substrate 17, the layer 15 to be transferred is placed in Figure 1A In the orientation, the upper surface of the target substrate 17 is contacted by its upper surface.

[0042] In practice, and more specifically in the case of target substrate 17 and / or source substrate 13 with tapered edges, it can be observed that the bonding of layer 15 to target substrate 17 is not complete at the periphery of the assembly. In fact, when bonding layer 15 to substrate 17, while layer 15 and substrate 17 are in good contact in the center of the assembly, they are not in contact or only partially in contact at the edges of the assembly, in particular due to the peripheral tapering of the substrate and / or possible surface irregularities of the substrate.

[0043] At the end of the step of removing the source substrate 13, the peripheral portions of the layer 15 which are not bonded or poorly bonded to the target substrate 17 are broken off. Thus, a peripheral annular zone of the target substrate 17 is not covered by the layer 15 or is only partially covered by it.

[0044] In the absence of specific precautions, after the transfer, the edge of the layer 15 at the periphery of the assembly is irregular. In fact, this is due to the fact that the bonding limit between the layer 15 and the target substrate 17 is irregular. This irregularity of the edge of the layer 15 may make it possible for defects to propagate towards the center of the layer 15 during subsequent microelectronic component manufacturing steps, for example during the step of epitaxy from the upper surface of the layer 15. Defects are particularly likely to propagate in the epitaxial layer on the layer 15.

[0045] It is desirable herein to improve the regularity or flatness of the edges of the layer 15 at the end of the transfer.

[0046] Figure 1B The steps of etching a step 29 at the periphery of the upper surface of the layer 15 (referred to as the bonding surface) and etching a step 30 at the periphery of the upper surface of the target substrate 17 (referred to as the bonding surface) are shown.

[0047] The step 29 extends from the upper surface of the layer 15, for example in a portion of the layer 15. As a variant, the step 29 extends from the upper surface of the layer 15, for example in a portion of the layer 13, and for example in a portion of the matrix 13.

[0048] The steps 29 and 30 are carried out by an etching or ion milling method, which comprises sending an ion beam 19 or an atom beam, such as a neutral beam, onto the area to be etched. This step is carried out under vacuum, that is to say under a pressure lower than atmospheric pressure, such as under an ultra-high vacuum, for example at a pressure lower than 10 -7 mbar (e.g. below 10 -8 mbar).

[0049] During the etching step, only the free parts of the upper surface of the target substrate 17 and of the layer 15 are etched (that is, the parts of the upper surface of the target substrate 17 and of the layer 15 that are not covered by the mask).

[0050] exist Figure 1B In the example of , the central portions of the bonding surfaces are each covered with a masking disk in order to form the step 29 only at the periphery of the bonding surface of the layer 15 and the step 30 only at the periphery of the bonding surface of the target substrate 17. Thus, during the etching step, the masking disk 31 covers the central portion of the bonding surface of the layer 15 and the masking disk 33 covers the central portion of the bonding surface of the target substrate 17.

[0051] By way of example, in vertical projection, the center of the masking disk 31 coincides with the center of the source substrate 13, and the center of the masking disk 33 coincides with the center of the target substrate 17. For example, the diameter of the masking disk 31 is smaller than the diameter of the source substrate 13, and the diameter of the masking disk 33 is smaller than the diameter of the target substrate 17. The difference between the diameter of the source substrate 13 and the diameter of the masking disk 31 is, for example, in the range of 0.1 mm to 5 mm, such as in the range of 0.5 mm to 3 mm, such as approximately 1 mm. The difference between the diameter of the target substrate 17 and the diameter of the masking disk 33 is, for example, in the range of 0.1 mm to 5 mm, such as in the range of 0.5 mm to 3 mm, such as approximately 1 mm. By way of example, the masking disks 31 and 33 are identical in the manufacturing dispersion.

[0052] The masking disks 31 and 33 are, for example, metallic and / or made of a semiconductor or insulating material. As an example, during the steps of etching steps 29 and 30, the masking disk 31 is arranged on top of the upper surface of the semiconductor layer 15 and is arranged in contact with the upper surface of the semiconductor, and the masking disk 33 is arranged on top of the upper surface of the target substrate 17 and is arranged in contact with the upper surface of the target substrate.

[0053] In the example shown, etching of the step 29 in the layer 15 and etching of the step 30 in the target substrate 17 are performed simultaneously. As a variant, etching of the step 29 in the layer 15 and etching of the step 30 in the target substrate 17 are performed consecutively.

[0054] As an example, the depth of step 29 from the upper surface of layer 15 is greater than approximately 700 nm, such as greater than approximately 1 μm. As an example, the depth of step 30 from the upper surface of substrate 17 is greater than approximately 700 nm, such as greater than approximately 1 μm. For example, due to the different properties of layer 15 and substrate 17, step 29 and step 30 do not have the same depth.

[0055] At the end of this step, the masking disks 31 and 33 are removed.

[0056] Figure 1C The step of activating the bonding surface of the target substrate 17 and the bonding surface of the layer 15 is shown.

[0057] The method implemented during this step is an etching or ion milling method similar to the method implemented during the formation of steps 29 and 30. In particular, according to Figures 1A to 1F In one aspect of the embodiment of the present invention, activating the bonding surface by etching or ion milling is performed in the same ion processing chamber as etching steps 29, 30. However, the etching energy and / or etching time is lower than the etching energy and / or etching time implemented when forming steps 29 and 30 to activate the exposed surface without etching a significant thickness of layer 15 and a significant thickness of substrate 17.

[0058] During this step, an ion beam 19 or an atomic beam (preferably a neutral beam) sent onto the surface to be activated makes it possible to remove possible oxides present at the surface of the surface to be activated, while leaving dangling bonds that will be used to form covalent bonds in a subsequent step during the process of contacting the activated surfaces. This type of bonding method allows a bonding generally referred to as surface activated bonding or SAB. As an example, during this step, the material removed from the surface to be activated is less than a few nanometers, for example less than 5 nm. In any case, the thickness of the material removed during this activation step is less than the thickness removed during the formation of steps 29 and 30.

[0059] As an example, relative to Figure 1B The steps shown in Figure 1C During the steps shown, the surface exposure time is, for example, reduced and / or the power of the ion beam 19 is, for example, lowered.

[0060] In the example shown, the activation of the bonding surface of the layer 15 and the activation of the bonding substrate of the target layer 17 are performed simultaneously. The activation of the bonding surface of the layer 15 and the activation of the bonding surface of the target substrate 17 are performed consecutively without breaking the vacuum.

[0061] For example, during this step, the entire surface of the bonding surface of the substrate 17 and the entire surface of the bonding surface of the layer 15 are activated.

[0062] Figure 1D The structure 110 and the target substrate 17 are shown at the end of the step of activating the upper surface of the layer 15 and the upper surface of the target substrate 17 .

[0063] At this stage, the surface 15′ corresponding to the bonding surface of the layer 15 extending further in the step 29 and the surface 17′ corresponding to the bonding surface of the target substrate 17 extending further in the step 30 are activated in the same manner as the central part of the layer 15 and the central part of the substrate 17.

[0064] Figure 1EThe step of bonding the structure 110 to the target substrate 17 is shown. During this step, the bonding surface 15' of the layer 15 is placed in contact with the bonding surface 17' of the target substrate 17. Due to the geometry of the structure 110 and the substrate 17, only the central area of ​​the bonding surface of the layer 15, which is bounded by the step 29, is placed in contact with the central area of ​​the bonding surface of the substrate 17, which is bounded by the step 30, during this step.

[0065] When the dangling bonds formed on the bonding surface of the layer 15 and the dangling bonds formed on the bonding surface of the substrate 17 are placed in contact, they form covalent bonds to ensure that the layer 15 is bonded to the substrate 17. The depths of the steps 29, 30 are large enough that although the dangling bonds formed in the step 29 at the periphery of the layer 15 and the dangling bonds formed in the step 30 at the periphery of the substrate 15 are placed in front of each other, they do not form covalent bonds.

[0066] As an example, the bonding step is performed at a temperature ranging from 10° C. to 400° C., such as from 10° C. to 40° C., such as at room temperature.

[0067] Figure 1F Shown in the removal Figure 1E The source matrix 13 is shown together with the structure obtained at the end of the step of removing the structure.

[0068] For example, the substrate 13 is made of the same semiconductor material as the layer 15 and is implanted with a buried layer (not visible in the figure) of, for example, hydrogen ions (H+) to separate the layer 15 from the source substrate 13. As an example, the structure 110 is initially a single crystalline semiconductor wafer, which is implanted with, for example, hydrogen ions from its upper surface to form a buried implant layer that separates the layer 15 to be transferred from the source substrate 13. As an example, the removal of the source substrate 13 may include a step of thermal annealing so that the structure 110 is broken in the plane of the buried implant layer to enable the removal of the source substrate 13 and to leave only the layer 15 on the target substrate 17.

[0069] More generally, removing the substrate 13 may be performed by any other known method for removing a source substrate during the transfer of a semiconductor layer from a source substrate to a target substrate, for example by grinding or by a laser lift-off method.

[0070] During the removal of the source substrate 13, only the central area of ​​the layer 15 to be transferred, which is not located in front of the steps 29 and 31, remains bonded to the target substrate 17. However, the peripheral part of the target substrate 17 located in front of the steps 29 and 30 remains free, that is, not covered by the layer 15.

[0071] Therefore, in Figures 1A to 1FAt the end of the method shown, the transferred layer 15 has flat and regular edges which correspond substantially to the edges of the steps 29 and / or 30 .

[0072] Activation step of bonding surface ( Figure 1C ) and bonding steps ( Figure 1E ) is carried out without breaking the vacuum, for example in the same apparatus (for example including the implementation Figure 1B The etching steps and Figure 1C The activation chamber and the activation step of Figure 1E The bonding step is carried out in a bonding chamber).

[0073] In practice, during the bonding step ( Figure 1E ), it is desirable to align the structure so that the central area of ​​the bonding surface of layer 15, defined by step 29, and the bonding surface of substrate 17, defined by step 30, coincide. However, even if the alignment is not perfect, the solution provided enables a smooth edge of the transferred layer to be obtained, since only the portions of the bonding surface that are placed in contact will adhere to each other.

[0074] exist Figure 1B In the example shown, etching of the layer 15 is performed through the masking disk 31 to form the step 29 in the layer 15, and etching of the target substrate 17 is performed through the masking disk 33 to form the step 30 in the target substrate 17. As a variant, the masking disk can be provided only on the layer 15 or only on the target substrate 17 to form a step on a single bonding surface of the two bonding surfaces.

[0075] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E and Figure 2F is a cross-sectional view partially and schematically illustrating consecutive steps of an example of a method of transferring a semiconductor layer from a source substrate to a target substrate according to a second embodiment.

[0076] The second embodiment is similar to Figures 1A to 1F The first embodiment shown is different in that, in the second embodiment, the activation of the bonding surface is performed by depositing a thin layer of bonding material providing dangling bonds, which then enables the formation of covalent bonds when the activated surfaces are brought into contact. Figures 1A to 1F Only the elements that are common to the methods of Figures 1A to 1F differences in methods.

[0077] Similar to Figure 1A , Figure 2AA structure 110 is shown on its left part, which includes a source substrate 13 and a semiconductor layer 15 to be transferred, and a target substrate 17 is shown on its right part.

[0078] Similar to Figure 1B , Figure 2B The steps of etching a step 30 at the periphery of the upper surface of the target substrate 17 and etching a step 29 at the periphery of the upper surface of the layer 15 are shown.

[0079] Figure 2C The step of activating the bonding surface of the layer 15 and the bonding surface of the target substrate 17 is shown.

[0080] The activation step involves depositing a thin activation layer (also called a bonding layer) onto the surface to be activated. This enables the creation of dangling bonds that will be used to form covalent bonds in a subsequent step during contacting of the activation layer. This bonding technique is known as atomic diffusion bonding or ADB.

[0081] By way of example, during this step, a beam of atoms or ions, for example of a neutral gas (for example argon), bombards a target 24 made of a material whose atoms 25 are separated and deposited uniformly in a thin layer on the surface to be activated. By way of example, the target is metallic, for example made of tungsten or of titanium. As a variant, the target 24 is made of a semiconductor material, for example made of silicon, germanium, etc.

[0082] This step is carried out under vacuum, that is to say at a pressure below atmospheric pressure, for example under ultra-high vacuum, for example at a pressure below 10-7 mbar (for example below 10-8 mbar).

[0083] exist FIG. 2A to FIG. 2F In the embodiment of FIG. 5 , activation of the bonding surface by sputtering the bonding material is performed in the same ion treatment chamber as etching steps 29 , 30 .

[0084] In the example shown, activation of the bonding surface of the layer 15 and activation of the bonding surface of the target substrate 17 are performed simultaneously. As a variant, activation of the bonding surface of the layer 15 and activation of the bonding surface of the target substrate 17 are performed consecutively without breaking the vacuum.

[0085] Figure 1D The structure 110 and the target substrate 17 are shown at the end of the step of activating the upper surface of the layer 15 and the upper surface of the target substrate 17 .

[0086] At this stage, the bonding surface of the layer 15 and the bonding surface of the target substrate 17 are activated, that is, the top is covered with a layer 27 made of the material of the target 24. For example, the layers 27 each have a thickness greater than 0.2 nm, for example less than 100 nm. For example, the thickness of the layer 27 is in the range from 1 nm to 20 nm. In this embodiment, the layer 27 extends further in the steps 29 and 30, which are therefore activated in the same way as the central part of the layer 15 and the substrate 17.

[0087] Figure 2E Shows the Figure 2D The structure 110 is bonded to Figure 2C 17. During this step, a central portion of the bonding surface of layer 15 defined by step 29 is placed in contact with a central portion of the bonding surface of target substrate 17 defined by step 30. More specifically, layer 27 formed on layer 15 and layer 27 formed on target substrate 17 are placed in contact. Due to the geometry of structure 110 and substrate 17, only a central area of ​​the bonding surface of layer 15 defined by step 29 is placed in contact with a central area of ​​the bonding surface of substrate 17 defined by step 30 during this step.

[0088] The dangling bonds of the layer 27 deposited on the layer 15 and the dangling bonds of the layer 27 deposited on the substrate 17 generate covalent bonds when they are placed in contact to ensure that the layer 15 is bonded to the substrate 17. The depths of the steps 29, 30 are large enough that although the dangling bonds formed in the step 29 at the periphery of the layer 15 and the dangling bonds formed in the step 30 at the periphery of the substrate 15 are placed in front of each other, they do not form covalent bonds.

[0089] As an example, the bonding step is performed at a temperature ranging from 10° C. to 400° C., such as from 10° C. to 40° C., such as at room temperature.

[0090] For example, the interface resistivity between the layer 15 and the target substrate 17 is less than 10 -3 Ω.cm -2 , for example, less than 10 -5 Ω.cm -2 . This makes the bond electrically transparent.

[0091] Figure 2F Shown in Figure 2E The structure shown is the structure obtained at the end of the step of removing the source matrix 13 .

[0092] For example, the substrate 13 is made of the same semiconductor material as the layer 15 and is implanted with a buried layer (not visible in the figure) of, for example, hydrogen ions (H+) to separate the layer 15 from the source substrate 13. For example, the structure 110 is initially a single crystalline semiconductor wafer, which is implanted with, for example, hydrogen ions from its upper surface to form a buried implant layer that separates the layer 15 to be transferred from the source substrate 13. For example, the removal of the source substrate 13 may include a step of thermal annealing so that the structure 110 is broken in the plane of the buried implant layer to enable the removal of the source substrate 13 and to leave only the layer 15 on the target substrate 17.

[0093] More generally, removing the substrate 13 may be performed by any other known method for removing a source substrate during the transfer of a semiconductor layer from a source substrate to a target substrate, for example by grinding or by a laser lift-off method.

[0094] As previously described, during the removal of the source substrate 13, only the central region of the layer 15 to be transferred that is not located in front of the steps 29 and 30 remains bonded to the target substrate 17. However, the peripheral portion of the target substrate 17 that is located in front of the steps 29 and 30 remains free, that is, not covered by the layer 15.

[0095] Therefore, in FIG. 2A to FIG. 2F At the end of the method shown, the transferred layer 15 has flat and regular edges which correspond substantially to the edges of the steps 29 and / or 30 .

[0096] Activation step of bonding surface ( Figure 2C ) and bonding steps ( Figure 2E ) is carried out without breaking the vacuum, in the same apparatus (e.g. including the implementation Figure 2C Activation chamber and implementation of the activation step Figure 2E The bonding step is carried out in a bonding chamber).

[0097] exist Figure 2B In the example shown, etching of the layer 15 is performed through the masking disk 31 to form the step 29 in the layer 15, and etching of the target substrate 17 is performed through the masking disk 33 to form the step 30 in the target substrate 17. As a variant, the masking disk can be provided only on the layer 15 or only on the target substrate 17 to form a step on a single bonding surface of the two bonding surfaces.

[0098] In practice, during the bonding step, it is desirable to align the structures so that the central areas of the layer 27 delimited by the steps 29 and 30 coincide. However, even if the alignment is not perfect, the solution provided enables a flat edge of the transferred layer to be obtained, since only the portions of the layer 27 placed in contact will adhere to each other.

[0099] Figures 1A to 1F and FIG. 2A to FIG. 2F An advantage of the method is that the etching of the steps 29 and / or 30 makes it possible to increase the sharpness of the boundary between the bonded central area and the non-bonded peripheral area of ​​the layer 15 .

[0100] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will appreciate other variations. In particular, the described embodiments are not limited to the examples of materials and dimensions mentioned in this disclosure.

[0101] Furthermore, the embodiments have been described with respect to circular source and target substrates, but they may have different shapes.

[0102] Furthermore, although the provided methods are advantageous for transferring semiconductor layers from a source substrate to a target substrate, they can also be implemented to transfer layers of a different nature, such as metal layers or dielectric layers, from a source substrate to a target substrate.

[0103] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. A method for transferring a layer (15) from a source substrate (13) to a target substrate (17), the method comprising the following steps: a) arranging a masking disk (31, 33) on a central portion of the bonding surface of the layer (15) and / or on a central portion of the bonding surface of the target substrate (17); b) performing ion etching to form a step (29, 30) in front of a peripheral portion of the bonding surface of the layer (15) and / or the bonding surface of the target substrate (17) not covered by the masking disk (31, 33); c) removing the masking disc (31, 33); d) activating the bonding surface of the layer (15) and the bonding surface of the target substrate (17) by ion etching or ion deposition of a bonding material; and e) after step d), placing the bonding surface of the layer (15) in contact with the bonding surface of the target substrate (17), wherein steps b) and d) are performed sequentially in the same ion processing chamber; and Wherein, steps d) and e) are performed under vacuum, and the vacuum is not broken between the two steps.

2. The method according to claim 1, wherein: The target substrate (17) and / or the source substrate (13) has a tapered edge spanning a first width.

3. The method according to claim 2, wherein: After step b), the steps (29, 30) extend from an edge of the layer (15) and / or from an edge of the target substrate (17) over a width greater than or equal to the first width.

4. The method according to any one of claims 1 to 3, wherein: The diameter of the disk (31, 33) is smaller than the diameter of the source substrate (13) and / or smaller than the diameter of the target substrate (17).

5. Method according to any one of claims 1 to 4, comprising a step f) of removing the source matrix (13) after step e).

6. The method according to claim 5, wherein: Step f) comprises an annealing step which causes the assembly obtained at the end of step e) to break in the plane of the implanted buried layer separating said layer (15) from said source matrix (13).

7. The method according to any one of claims 1 to 6, wherein: The layer (15) is a semiconductor layer.

8. Method according to claim 7, comprising, after step f), a step of epitaxy on top of and in contact with the surface of the layer (15) opposite to the target substrate (17).

9. The method according to any one of claims 1 to 8, wherein: After step b), the steps (31, 33) extend downward from the bonding surface of the layer (15) and / or the bonding surface of the target substrate (17) to a depth of more than 700 nm.

10. The method according to any one of claims 1 to 9, wherein: Step d) comprises depositing a bonding layer (27) onto the bonding surface of said layer (15) and / or onto the bonding surface of said target substrate (17).

11. The method according to claim 10, wherein: The thickness of the bonding layer (27) is in the range of 0.2 nm to 100 nm, for example, in the range of 1 nm to 20 nm.

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