Wireless power transfer

Abstract

The power receiver (105) communicates with the power transmitter (101) using load modulation data symbols modulated by a chip sequence, the chip sequence being a combination of two binary sequences. The power transmitter (101) comprises: a data receiver (207) comprising a chip determiner (903) that determines a sequence of received chips; and two correlators (905, 907) that correlate the sequence with the two binary sequences. The two correlation values are combined into a single correlation value by a combiner (905). A detector (917) detects a received data symbol value in response to the combined correlation value. The method may provide for improved detection of data symbols and improved communication from the power receiver (105) to the power transmitter (101).

Description

Technical Field

[0001] The present invention relates to wireless power transfer and, in particular, but not exclusively, to communications in power transfer systems such as the Qi wireless power transfer specification. Background Art

[0002] Most electrical products today require dedicated electrical contacts to be powered from an external power source. However, this is often impractical and requires the user to physically plug in a connector or otherwise establish physical electrical contact. Typically, power requirements also vary significantly, and most current devices are equipped with their own dedicated power source, which results in a typical user having a large number of different power sources, each dedicated to a specific device. Although the use of internal batteries can avoid the need for a wired connection to a power source during use, this only provides a partial solution because the battery will need to be recharged (or replaced). The use of batteries can also substantially add weight to the device and may increase the cost and size of the device.

[0003] In order to provide a significantly improved user experience, it has been proposed to use wireless power, where power is transferred inductively from a transmitter coil in a power transmitter device to a receiver coil in an individual device.

[0004] Power transmission via magnetic induction is a well-known concept, mainly applied in transformers with tight coupling between the primary transmitter inductor / coil and the secondary receiver coil. By separating the primary transmitter coil and the secondary receiver coil between the two devices, wireless power transfer between these devices can be performed based on the principle of loosely coupled transformers.

[0005] Such an arrangement allows wireless power transfer to the device without requiring any wires or physical electrical connections to be made. In fact, it can simply allow a device to be placed near or on top of the transmitter coil in order to be charged or powered externally. For example, the power transmitter device can be arranged with a horizontal surface on which the device can simply be placed in order to be powered.

[0006] Furthermore, such a wireless power transfer arrangement can advantageously be designed so that a power transmitter device can be used with a range of power receiver devices. Specifically, a wireless power transfer method known as the Qi specification has been defined and is currently under further development. This method allows a power transmitter device that meets the Qi specification to be used with a power receiver device that also meets the Qi specification, without having to be from the same manufacturer or having to be dedicated to each other. The Qi standard also includes some functions for allowing operation to be adapted to a specific power receiver device (e.g., depending on a specific power consumption).

[0007] The Qi specification was developed by the Wireless Power Alliance, and more information can be found, for example, on their website: http: / / www.wirelesspowerconsortium.com / index.html , where, in particular, the specification files that define it can be found.

[0008] Based on the Qi specification, a method known as the Ki specification is being developed for high power applications, such as in particular for kitchen appliances.

[0009] To support efficient wireless power transfer, wireless power transfer systems (such as Qi-based systems) utilize substantial communication between a power transmitter and a power receiver. Initially, Qi only supported communication from a power receiver to a power transmitter using load modulation of the power transfer signal. Therefore, the initial Qi devices only supported one-way communication from a power receiver to a power transmitter.

[0010] However, the development of the standard has introduced bidirectional communication, and many functions are supported by the communication exchange between the power receiver and the power transmitter.In many systems, the communication from the power transmitter to the power receiver is accomplished by modulating the power transfer signal.

[0011] In some systems, it has been proposed to use a separate and dedicated communication function, such as, for example, Bluetooth or NFC (near field communication) based communication. However, while such an approach can often provide effective operation in many scenarios, it is also associated with a number of disadvantages, including requiring dedicated and complex communication circuitry, and potentially reducing the certainty that the power transmitter is indeed communicating with the power receiver being powered. Moreover, backward compatibility (e.g., with Qi-based devices) may be problematic for newer devices based on separate communications.

[0012] However, using load modulation of a power transfer signal to transfer power to a power receiver for communication also tends to have some associated disadvantages. For example, load modulation may tend to introduce some electrical noise, both to the device's signal and to radiated electromagnetic radiation. Load modulation may increase electromagnetic interference to other devices, and it has been found to be challenging to maintain adequate or optimal electromagnetic compatibility.

[0013] It has also been found in practice that load modulation can lead to the introduction of undesirable parasitic oscillations into the drive signal and the power transfer signal. The power transfer path in a wireless power transfer system often includes a considerable amount of inductance and often has resonant behavior. Therefore, load modulation tends to affect the power transfer path and, in fact, the communication path. Therefore, load modulation also leads to noise and interference (self-interference) to the communication itself. This is fundamentally different from other communication systems, in which random noise or interference from other transmissions is the main cause of bit errors.

[0014] Another disadvantage is that load modulation of the power transfer signal may cause acoustic noise. Such noise may arise from the influence of electromagnetic field changes caused by load modulation on mechanical elements, and in particular, it may cause mechanical elements to move and vibrate, resulting in the generation of potential acoustic noise.

[0015] In some cases, for example, load modulation communications as used in the initial version of the Qi specification may not have perfect reliability and in some cases some bit errors may occur. For example, high levels of noise or self-interference may cause bit errors and / or may require increased modulation depth, which may result in increased electrical or acoustic noise caused by the load modulation.

[0016] While changing to a different communication method may be desirable in some areas, maintaining backward compatibility or reducing the amount of changes required to existing designs and methods is a major challenge that often makes it unattractive.

[0017] Accordingly, improved methods would be advantageous and in particular methods allowing increased flexibility, reduced cost, reduced complexity, improved power transfer operation, increased reliability, reduced communication errors, improved backwards compatibility, improved electromagnetic compatibility, reduced electrical and / or acoustic noise, improved communications and / or improved performance would be advantageous. Summary of the invention

[0018] Accordingly, the Invention seeks to preferably mitigate, alleviate or eliminate one or more of the above mentioned disadvantages singly or in any combination.

[0019] According to aspects of the present invention, there is provided a power transmitter for wirelessly providing power to a power receiver via an electromagnetic power transfer signal, the power transmitter comprising: an output circuit comprising a transmitter coil, the transmitter coil being arranged to generate the power transfer signal in response to a drive signal being applied to the output circuit; a driver being arranged to generate the drive signal; and a data receiver being arranged to receive a load modulated data symbol modulated by at least one modulation chip sequence, at least a first modulation chip sequence of the at least one modulation chip sequence being a combination of a first binary chip sequence and a second binary chip sequence; wherein the receiver comprises The invention comprises: a load measurer, which is arranged to measure the loading of the power transmission signal to generate a measured load value; a code chip determiner, which is arranged to determine the received code chip sequence according to the measured load value; a first correlator, which is arranged to correlate the received code chip sequence with the first binary code chip sequence to generate a first correlation value; a second correlator, which is arranged to correlate the received code chip sequence with the second binary code chip sequence to generate a second correlation value; a combiner, which is arranged to generate a combined correlation value according to the first correlation value and the second correlation value; and a detector, which is arranged to detect the received data symbol value in response to the combined correlation value.

[0020] The invention may in many embodiments allow improved performance, and may specifically in many embodiments allow improved communication between a power receiver and a power transmitter.In many embodiments, it may allow improved power transfer.

[0021] The method may allow improved communication and, in many embodiments, may allow improved tradeoffs between different parameters and operating characteristics. The method may, for example, allow highly reliable communication, but allow the use of a reduced modulation depth. The method may reduce electrical noise and / or electromagnetic interference, and allow improved electromagnetic compatibility. In many cases, the method may reduce or prevent acoustic noise. In addition, the method may provide advantageous backward compatibility, and, for example, may allow relatively easy modification of existing methods, such as those used by the Qi or Ki specifications. The method may often reuse many functions from such existing methods. The method may allow a low complexity implementation, but provide highly efficient performance. The communication method may be particularly advantageous for use in power delivery systems, as bandwidth considerations may be less critical in such systems.

[0022] In many cases, the methods may allow for improved trade-offs between different parameters, including computational resource requirements, data detection accuracy, bit error rate, data rate, etc.

[0023] In many embodiments, the method may allow for improved and / or facilitated detection of load modulation data at the power transmitter.

[0024] In many scenarios, reduced sensitivity to time variations, noise, distortion, and in particular self-interference, etc. may be achieved for the communication of data from a power receiver to a power transmitter.

[0025] The chip sequence may be a sequence / pattern of chip values. Each chip value may be represented by such a load modulation level or pattern. The chip sequences for different data symbols have different sequences / patterns of chip values. The first binary chip sequence and the second binary chip sequence may be different chip sequences. The combined correlation value may increase monotonically for the first correlation value and may increase monotonically for the second correlation value. The combined correlation value may increase for an increasing value of the first correlation value and increase for an increasing value of the second correlation value. In some embodiments, the combined correlation value may be a weighted combination / sum / product of the first correlation value and the second correlation value. The weights for the first correlation value and the second correlation value may be positive. Each modulation chip sequence may represent a data symbol.

[0026] In many embodiments, the length of the chip sequence is no less than 10 chips and no more than 1024 chips.

[0027] The measured load value may be a sample of a signal indicative of a load of the power transfer signal.The measured load value may be a sample of a parameter of the drive signal.

[0028] The load measurer may be arranged to measure the loading (in particular by the power receiver) of the power transfer signal to determine a measured load value for a load time interval.

[0029] The function used to generate the combined correlation value may be monotonically increasing for both the first correlation value and the second correlation value.The first binary sequence and the second binary sequence may have the same length and may have the same length as the modulation chip sequence.

[0030] The correlator may be arranged to generate correlation values ​​for different and possibly all chip alignments between the received chip sequence and the first and second binary sequences. In such a case, the detector and possible combiner may process correlation values ​​corresponding to peak correlations. In some embodiments, the correlation values ​​are correlation values ​​for the first binary sequence and the second binary sequence aligned with the modulation chip sequence / received chip sequence. For example, the alignment may be determined by peak detection of the correlation.

[0031] According to an optional feature of the invention, the first modulation chip sequence comprises at least three different chip values.

[0032] In many embodiments this may provide improved performance.In many scenarios improved information may be provided relating to the modulation chip sequence and how this relates to the first binary sequence and the second binary sequence, thereby providing additional symbol detection.

[0033] According to an optional feature of the invention, at least two chip values ​​of the first modulation chip sequence are represented by a modulation load change, and the modulation load change is different for the at least two chip values; and the chip determiner is arranged to determine the received chip sequence in response to the modulation load change.

[0034] In many embodiments, the method may allow for improved and / or facilitated detection of load modulation data at the power transmitter. In many scenarios, it may reduce or eliminate the need to determine an average or nominal load reference level in order to detect modulation load levels and variations. For example, in many embodiments, only the modulation load value within the chip itself may be considered to determine the chip value.

[0035] In many scenarios, the load modulation for individual chips may not only indicate the chip value, but may also provide a reference load value to determine the chip value.

[0036] According to an optional feature of the present invention, each of the code chip time intervals of the first modulation code chip sequence is divided into at least two load time intervals, at least two code chip values ​​have different modulation loads for the at least two load time intervals, the pattern of the modulation load is different for different code chip values ​​of the at least two code chip values, and a third code chip value among at least three different code chip values ​​has the same modulation load in at least two load time intervals; and, the load measurer is arranged to determine the measured load value as the measured load value for the load time interval; and, the code chip determiner is arranged to determine the code chip value for the received code chip sequence in response to the difference in the measured load values ​​for different load time intervals for each code chip.

[0037] This may allow for improved and / or facilitated detection of load modulation data at the power transmitter.

[0038] In some embodiments, the load measurer is arranged to synchronise the measurement of the load of the power transfer signal with a period of the power transfer signal.

[0039] This may allow improved performance and / or facilitated operation and / or reduced complexity. In particular, it may allow improved and / or facilitated determination of a suitable load value for data symbol detection.

[0040] In some embodiments, each loading time interval has a duration of one cycle of the power transfer signal.

[0041] This may allow improved performance and / or facilitated operation and / or reduced complexity. In many scenarios, it may allow increased data rates.

[0042] In some embodiments, each load time interval has a duration of a plurality of cycles of the power transfer signal.

[0043] This may allow improved performance and / or facilitated operation and / or reduced complexity. In some embodiments, it may reduce the sensitivity to synchronization errors.

[0044] In some embodiments, the load measurer is arranged to perform a single load measurement per load time interval.

[0045] This may allow improved performance and / or facilitated operation and / or reduced complexity.

[0046] In some embodiments, the chip determiner is arranged to determine a binary chip value for a chip depending on the sign of a difference between measured load values ​​of two modulated load time intervals for the chip.

[0047] This may allow improved performance and / or facilitated operation and / or reduced complexity.

[0048] In some embodiments, the chip determiner is arranged to determine the received chip sequence in response to the magnitude of the difference between the measured load values ​​for two modulated load time intervals for the chip to include a soft decision chip value, and the correlator is arranged to perform correlation with the first binary chip sequence and the second binary chip sequence, respectively, in response to the soft decision chip value.

[0049] This may allow improved performance and / or facilitated operation and / or reduced complexity.

[0050] According to an optional feature of the invention, the first modulation chip sequence comprises three different chip values.

[0051] In many embodiments, this may provide particularly advantageous operation and / or performance.

[0052] According to an optional feature of the present invention, the first modulation code bit sequence has: a first value of alignment code bits for the first binary sequence and the second binary sequence both having a first binary value; a second value of alignment code bits for the first binary sequence and the second binary sequence both having a second binary value; and a third value of alignment code bits for the first binary sequence and the second binary sequence with different alignment values.

[0053] In many embodiments this may provide particularly advantageous operation and / or performance.Aligned chips may be chips at the same sequential position in the corresponding sequences.

[0054] According to an optional feature of the invention, the chip determiner is arranged to determine the received chip sequence as a binary chip sequence.

[0055] In many embodiments, this can allow particularly advantageous operation and / or performance. In many embodiments, it can allow efficient and / or low complexity implementations. For example, it can allow binary correlation. However, although the chip sequence received by the binary represents a possible non-binary modulation chip sequence, the method allows very accurate data symbol detection.

[0056] According to an optional feature of the invention, the code chip determiner and the first correlator are arranged so that a contribution of the first correlation value to at least one code chip value of the first modulation code chip sequence is less than 10% of a contribution of the first correlation value to at least one other code chip value of the modulation code chip sequence.

[0057] In many embodiments, this may provide particularly advantageous operation and / or performance.

[0058] According to an optional feature of the invention, the combiner is arranged to generate a combined correlation value in response to a product of the first correlation value and the second correlation value.

[0059] In many embodiments, this may provide particularly advantageous operation and / or performance.

[0060] According to an optional feature of the invention, the chip determiner is arranged to determine the received chip sequence as having chip values ​​that are likely to be chip values ​​for the first modulation chip sequence.

[0061] In many embodiments, this may provide particularly advantageous operation and / or performance.

[0062] According to an optional feature of the present invention, when the first binary sequence is aligned with the first modulation code sequence, the cross-correlation between the first binary sequence and the first modulation code sequence is not less than two-thirds of the length of the first binary sequence, and when the first binary sequence is not aligned with the first modulation code sequence, the cross-correlation between the first binary sequence and the first modulation code sequence is not greater than one-third of the length of the first binary sequence.

[0063] According to aspects of the present invention, there is provided a power receiver for wirelessly receiving power from a power transmitter via an electromagnetic power transfer signal, the power receiver comprising: an input circuit comprising a receiver coil, the receiver coil being arranged to extract power from the power transfer signal; a data transmitter being arranged to transmit data symbols to the power transmitter by load modulating the power transfer signal, each data symbol being modulated by a sequence of modulation load values ​​corresponding to a chip sequence of a set of modulation chip sequences, the chip sequences of the set of chip sequences being linked to different data symbol values; wherein at least one modulation chip sequence in the set of modulation chip sequences is a combination of a first binary chip sequence and a second binary chip sequence, and has at least three different chip values.

[0064] According to aspects of the present invention, there is provided a method of operating a power transmitter for wirelessly providing power to a power receiver via an electromagnetic power transfer signal, the power transmitter comprising: an output circuit comprising a transmitter coil, the transmitter coil being arranged to generate the power transfer signal in response to a drive signal being applied to the output circuit; a driver being arranged to generate the drive signal; and a data receiver being arranged to receive a load modulated data symbol modulated by at least one modulation chip sequence, at least a first modulation chip sequence of the at least one modulation chip sequence being a combination of a first binary chip sequence and a second binary chip sequence; wherein the method comprises the receiver performing the following steps: measuring the loading of the power transfer signal to generate a measured load value; determining a received chip sequence based on the measured load value; correlating the received chip sequence with the first binary chip sequence to generate a first correlation value; correlating the received chip sequence with the second binary chip sequence to generate a second correlation value; generating a combined correlation value based on the first correlation value and the second correlation value; and detecting a received data symbol value in response to the combined correlation value.

[0065] According to aspects of the present invention, there is provided a method for operating a power receiver for wirelessly receiving power from a power transmitter via an electromagnetic power transfer signal: the power receiver comprises: an input circuit comprising a receiver coil, the receiver coil being arranged to extract power from the power transfer signal; and the method comprises: a data transmitter transmitting data symbols to the power transmitter by load modulating the power transfer signal, each data symbol being modulated by a sequence of modulation load values ​​corresponding to a chip sequence of a set of modulation chip sequences, the chip sequences of the set of chip sequences being linked to different data symbol values; wherein at least one modulation chip sequence in the set of modulation chip sequences is a combination of a first binary chip sequence and a second binary chip sequence, and has at least three different chip values.

[0066] According to an aspect of the invention, there is provided a method for operation of a power receiver.

[0067] These and other aspects, features and advantages of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0069] Figure 1 illustrates examples of elements of a power delivery system according to some embodiments of the present invention;

[0070] Figure 2 illustrates examples of elements of a power transmitter according to some embodiments of the present invention;

[0071] Figure 3 An example of a half-bridge inverter for a power transmitter is shown;

[0072] Figure 4 An example of a full-bridge inverter for a power transmitter is shown;

[0073] Figure 5 illustrates examples of elements of a power receiver according to some embodiments of the present invention;

[0074] Figure 6 An example of a chip sequence is shown;

[0075] Figure 7 illustrates examples of correlation values ​​for load communication in a wireless power transfer system;

[0076] Figure 8 illustrates examples of elements of a power receiver according to some embodiments of the present invention;

[0077] Fig. 9 illustrates examples of elements of a power transmitter according to some embodiments of the present invention;

[0078] Fig.10 illustrates an example of simulation results for load modulation communication in a wireless power transfer system;

[0079] Fig.11 illustrates an example of simulation results for load modulation communication in a wireless power transfer system;

[0080] Fig.12 illustrates an example of simulation results for load modulation communication in a wireless power transfer system;

[0081] Fig.13 illustrates an example of load communication in a wireless power transfer system according to some embodiments of the present invention;

[0082] Fig.14 illustrates an example of simulation results for load modulation communication in a wireless power transfer system; and

[0083] Fig.15 An example of simulation results for load modulation communication in a wireless power transfer system is illustrated. DETAILED DESCRIPTION

[0084] The following description focuses on an embodiment of the invention applicable to a high power wireless power transfer system utilizing a power transfer method such as known from the Qi specification or the Ki specification. However, it will be appreciated that the invention is not limited to this application but may be applied to many other wireless power transfer systems.

[0085] Figure 1 An example of a power transfer system according to some embodiments of the present invention is illustrated. The power transfer system comprises a power transmitter 101, which comprises (or is coupled to) a transmitter coil / inductor 103. The system also comprises a power receiver 105, which comprises (or is coupled to) a receiver coil / inductor 107.

[0086] The system provides an inductive electromagnetic power transfer signal that can inductively transfer power from the power transmitter 101 to the power receiver 105. Specifically, the power transmitter 101 generates an electromagnetic signal that is propagated as magnetic flux propagation by the transmitter coil or inductor 103. The power transfer signal can typically have a frequency between about 20kHz and about 500kHz, and in many practical systems, can be about 120-150kHz. The transmitter coil 103 and the power receiving coil 107 are loosely coupled, and thus the power receiving coil 107 picks up (at least part of) the power transfer signal from the power transmitter 101. Therefore, power is transferred from the power transmitter 101 to the power receiver 105 via wireless inductive coupling from the transmitter coil 103 to the power receiving coil 107. The term power transfer signal is primarily used to refer to the induced signal / magnetic field (magnetic flux signal) between the transmitter coil 103 and the power receiving coil 107, but it will be understood that, by equivalents, it can also be considered and used as a reference for the electrical signal provided to the transmitter coil 103 or picked up by the power receiving coil 107.

[0087] In the example, the power receiver 105 is specifically a power receiver that receives power via a receiver coil 107. However, in other embodiments, the power receiver 105 may comprise a metallic element, such as a metallic heating element, in which case the power transfer signal directly induces eddy currents, resulting in direct heating of the element.

[0088] In the following, the operation of the power transmitter 101 and the power receiver 105 will be described with specific reference to embodiments generally in accordance with the Qi or Ki specifications (except for the modifications and enhancements described herein (or inferred)).

[0089] Many wireless power transfer systems utilize resonant power transfer, where the transmitter coil 103 is part of a resonant circuit, and typically the receiver coil 107 is also part of the resonant circuit. In many embodiments, the resonant circuit may be a series resonant circuit, and thus the transmitter coil 103 and the receiver coil 107 may be coupled in series with corresponding resonant capacitors. The use of a resonant circuit tends to provide more efficient power transfer.

[0090] Typically, wireless power transfer systems employ a power control loop in order to steer the system to an appropriate operating point. This power control loop varies the amount of power transmitted from a power transmitter to a power receiver. The received power (either voltage or current) may be measured, and an error signal may be generated along with a set point power value. The power receiver sends this error signal to a power control function in the power transmitter to reduce the static error, ideally to zero.

[0091] Figure 2 A more detailed illustration Figure 1 Elements of the power transmitter 101.

[0092] The power transmitter 101 includes a driver 201 that can generate a drive signal that is fed to the transmitter coil 103, which in turn generates an electromagnetic power transfer signal, thereby providing power transfer to the power receiver 105. The transmitter coil 103 is part of an output resonant circuit that includes the transmitter coil 103 and a capacitor 203. In the example, the output resonant circuit is a series resonant circuit, but it will be understood that in other embodiments, the output resonant circuit can be a parallel resonant circuit. It will be understood that any suitable resonant circuit can be used, including resonant circuits using multiple inductors and / or capacitors.

[0093] The driver 201 generates a current and a voltage which are fed to the output resonant circuit and hence to the transmitter coil 103. The driver 201 is typically a drive circuit in the form of an inverter which generates an AC signal from a DC voltage. The output of the driver 201 is typically a switching bridge, the drive signal being generated by appropriate switching of the switches of the switching bridge. Figure 3 A half-bridge switching bridge / inverter is shown. Switches S1 and S2 are controlled so that they are never closed at the same time. Alternatingly, S1 is closed while S2 is open, and S2 is closed while S1 is open. The switches are opened and closed at the desired frequency, generating an AC signal at the output. Typically, the output of the inverter is connected to the transmitter inductor via a resonant capacitor. Figure 4 A full-bridge switching bridge / inverter is shown. Switches S1 and S2 are controlled so that they are never closed at the same time. Switches S3 and S4 are controlled so that they are never closed at the same time. Alternatingly, switches S1 and S4 are closed while S2 and S3 are open, and then S2 and S3 are closed while S1 and S4 are open, creating a square wave signal at the output. The switches are opened and closed at the desired frequency.

[0094] The power transmitter 101 further comprises a power transmitter controller 205 arranged to control the operation of the power transmitter 101 according to a desired operating principle. In particular, the power transmitter 101 may comprise a number of functions required to perform power control according to the Qi specification or the Ki specification.

[0095] In particular, the power transmitter controller 205 is arranged to control the generation of the drive signal by the driver 201, and it may in particular control the power level of the drive signal, and accordingly control the level of the generated power transfer signal. The power transmitter controller 205 comprises a power loop controller which controls the power level of the power transfer signal in response to a power control message received from the power receiver 105 during the power transfer phase.

[0096] Figure 5 Some exemplary elements of the power receiver 105 are illustrated.

[0097] In the example, the receiver coil 107 is coupled to the power receiver controller 501 via the capacitor 503, which together with the receiver coil 107 forms an input resonant circuit. Therefore, the power transfer can be a resonant power transfer between the resonant circuits. In other embodiments, only one or none of the power receiver and the power transmitter can utilize the resonant circuit for power transfer.

[0098] The power receiver controller 501 couples the receiver coil 107 to the load 505 via the switch 507. The power receiver controller 501 includes a power control path that converts the power extracted by the receiver coil 107 into a suitable power supply for the load 505. In some embodiments, the power receiver controller 501 may provide a direct power path that simply connects the input resonant circuit to the switch 507 or the load 505, i.e., the power path of the power receiver controller 501 may be simply implemented by two wires. In other embodiments, the power path may include, for example, a rectifier and possible smoothing capacitors to provide a DC voltage. In other embodiments, the power path may include more complex functions, such as, for example, a voltage control circuit, an impedance matching circuit, a current control circuit, etc. Similarly, it will be understood that the switch 507 may only be present in some embodiments, and in some embodiments, the load 505 may be permanently coupled to the input resonant circuit.

[0099] In addition, the power receiver controller 501 may include various power receiver controller functions required to perform power transfer, and specifically, functions required to perform power transfer according to the Qi or Ki specifications.

[0100] The power receiver 105 is arranged to transmit data to the power transmitter 101. Such data may in particular include a power control loop error message for implementing a feedback power loop for controlling the power level of the power transfer signal during power transfer, as will be known to the skilled person. In many embodiments, the power receiver is capable of transmitting a series of different messages serving different purposes, as will be known to the skilled person. For example, a series of different messages may be transmitted, such as the messages specified in the Qi specification. The message may include one or more data bits / symbols.

[0101] The power receiver is arranged to transmit a message to the power transmitter using load modulation.

[0102] As will be well known to the skilled person, for load modulation, variations in the loading of the power transfer signal may be introduced by the power receiver, wherein the variations coincide with the data values ​​to be transmitted. These variations may then be detected by the power transmitter in order to decode the data from the power receiver.

[0103] Load modulation may be used as a method for a power receiver to transmit control messages or other data to a power transmitter according to, for example, the Qi wireless power standard.

[0104] There are generally two main ways of performing load modulation, namely directly changing the resistive load / power extraction of the input circuit and / or detuning the resonance of the input circuit, for example by changing reactive loading in the input circuit (usually switching capacitors on / off depending on the data to be generated). Similar methods can be used by the power receiver to load modulate the power transfer signal.

[0105] Accordingly, at the power transmitter, load changes may be detected using detection methods such as those known for Qi specification systems. For example, a direct measurement of the power level or current amplitude of the drive signal may be used as an indication of the load, and therefore of the load modulation changes introduced by the power receiver.

[0106] The power receiver 105 comprises a data transmitter 509 arranged to transmit data to the power transmitter 101 by load modulating the power transfer signal. For example, the data transmitter 509 may be arranged to switch on / off a communication capacitor (or other impedance) positioned in parallel with the power receiver controller 501 or the resonant capacitor 503, for example, so as to be able to change the resonant frequency and the loading of the power transfer signal.

[0107] The data transmitter 509 may be coupled to the power receiver controller 501 and may be arranged to receive data from the power receiver controller 501 for transmission to the power transmitter.

[0108] For example, the data transmitter 509 may receive power error control data from the power receiver controller 501 and may transmit a corresponding power error control message to the power transmitter 101 using load modulation. In operation, the system is generally arranged to control the drive signal so that the power transfer signal obtains suitable operating parameters / characteristics and the power transfer operates at a suitable operating point. To do so, the power transmitter is arranged to control the parameters of the drive signal using a power control loop, wherein the power characteristics of the power transfer signal / drive signal are controlled in response to the power control error message received from the power receiver.

[0109] The data transmitter 509 is arranged to transmit data symbols by load modulating the power transmission signal by a sequence of modulation load values ​​corresponding to the chip sequence. The data transmitter 509 can transmit data symbols using, for example, a method similar to direct sequence spread spectrum (DSSS), which modulates data symbols using a chip sequence. The data symbols / bits are modulated by a (usually pseudo-random) bit sequence also called a spreading sequence. Each spreading sequence bit (which is called a chip) has a much shorter duration (larger bandwidth) than the original message bit.

[0110] In the method, load modulation is employed, but each symbol is represented by a chip sequence comprising a plurality of chips, and typically has a sequence comprising 10 to 1023 chips. Thus, rather than simply varying the load per symbol or bit, the data transmitter 509 is arranged to transmit a given symbol (typically a bit) through a series of load changes and variations, wherein the changes and variations are different for each symbol. In particular, a chip sequence may be defined for each symbol, and when transmitting a given symbol, the data transmitter 509 may retrieve the chip sequence for that particular symbol and load modulate the power transfer signal according to the chip sequence for the symbol.

[0111] Similarly, as will be described in more detail later, the power transmitter may detect load modulation by considering the entire chip sequence, and in particular may seek to determine the received symbol as the symbol for which the measured load variation chip pattern most closely matches the chip sequence pattern for that symbol.

[0112] Such an approach may in particular allow the modulation depth, i.e. the amplitude of the load variation, to be substantially reduced, which may, for example, reduce electromagnetic noise and interference, may reduce acoustic noise, and may reduce parasitic oscillations. In many embodiments, it may also result in an improved signal-to-noise ratio, and may result in substantially improved and generally more reliable communications, e.g., generally with lower bit error rates. Thus, generally overall improved power transfer may be achieved.

[0113] Traditionally, such communications use binary sequences such as Figure 6 The exemplary chip sequences illustrated in illustrate examples of portions of two possible chip sequences. Each chip sequence comprises a sequence of chips. Traditionally, a set of chip values ​​is two, corresponding to a binary chip sequence. However, as will be described in more detail later, in many embodiments, the current method may use (at least one) modulation chip sequence with non-binary chip levels. In many embodiments, the chip may have one of three different chip levels, and the chip sequence comprises three different chip levels. The following description will focus on such examples, but it will be appreciated that in other embodiments, a binary chip sequence may be used, or indeed a chip sequence with four or possibly more levels may be used.

[0114] In the described method, the symbol time is divided into a plurality of chip intervals, wherein the chip sequence of chips is different for different data symbols. Typically, each sequence includes at least ten chips, and typically substantially more. In many embodiments, each chip sequence may have 2 N -1, where N is an integer usually not less than 4.

[0115] Each possible data symbol value may be linked / represented by a modulation chip sequence. Thus, for a given data symbol value to be transmitted, a corresponding / linked modulation chip sequence is determined and modulated onto the power transmission signal by load modulation. For example, in the case where only two data symbols are possible, i.e., in the case where binary communication is implemented, a set of chip sequences may include only two chip sequences.

[0116] In many embodiments, one or more chip sequences may be represented by a relationship to another chip sequence. For example, for binary communications, the data transmitter 509 may store a single modulation chip sequence corresponding to one of the binary data values. The chip sequence for the other binary data value may be represented by the same stored bit sequence, since it may be given as the inverse of the stored bit sequence. Thus, a set of chip sequences typically utilizes complementary inverse chip sequences for data symbol pairs, and thus typically only half of the chip sequences used are explicitly stored / determined in the data transmitter 509, with the remaining chip sequences automatically and implicitly stored / determined as the inverses of these chip sequences.

[0117] Thus, in some embodiments, the modulation chip sequence may comprise an inverse chip sequence.Equivalently, the same modulation chip sequence may be considered to represent two data symbol values, and in particular two binary data symbol values.

[0118] A modulation chip sequence for a given data symbol to be transmitted is selected from a set of modulation chip sequences, and in an example, the data transmitter 509 provides a set of modulation chip sequences, wherein each chip sequence is linked to a data symbol value. Typically, the set of modulation chip sequences includes a chip sequence for each possible data symbol value. For example, if binary communication is used, the first set of chip sequences may include only two chip sequences. It should be understood that the data transmitter 509 can store chip sequences in any suitable form, and does not need to store a complete sequence for each possible data symbol. For example, a given modulation chip sequence can be multiplied by a binary symbol value represented by a value of 1, -1. At the receiving end, i.e., the power transmitter, the data value can then be determined by correlation with a given modulation chip sequence and by determining the corresponding binary data value depending on whether this is a positive correlation or a negative correlation.

[0119] In many embodiments, therefore, binary communication may be used where only two data symbol values ​​(corresponding to either a "0" bit value or a "1" bit value) are possible. In such a case, one bit value may be represented by a given chip sequence, while the other bit value may be associated with an inverse bit sequence, i.e., a bit sequence produced by changing each chip value to an opposite value. Thus, the two bit sequences are typically complementary, with one being produced by the other by multiplying by -1 (where chip values ​​are represented by +1 and -1).

[0120] In such a case, a particular advantage is that demodulation is particularly easy, since a single correlation can be used to distinguish the bit values, since the magnitude of the correlation is the same for the chip sequence, but the sign of the correlation value is opposite.

[0121] It should be understood that the data symbol represented by the inverse modulation chip sequence is equivalently considered to be represented by one chip sequence or by two chip sequences. It should be understood that such a binary method using two inverse chip sequences is equivalent to considering two possible binary values ​​modulated by the same chip sequence, but the data symbol has opposite data values ​​(e.g., +1 and -1).

[0122] When the power receiver 105 is to transmit a data symbol, this value is fed from the power receiver controller 501 to the data transmitter 509 which proceeds to determine a chip sequence which is linked to the data symbol value to be transmitted.

[0123] The data transmitter 509 is arranged to modulate the chip sequence onto the power transfer signal. Specifically, the modulated load may be switched on and off (on / off) in line with the chips, ie the load may be changed according to the modulated load value of the chip sequence.

[0124] The chip sequences in a group are usually (but not necessarily) of the same length. For binary communication, as described above, a group of chip sequences may include only a single modulation chip sequence (or equivalently two inverse chip sequences). The following description will focus on such binary communication, but it should be understood that the present invention is not limited to binary communication.

[0125] Load modulation can provide advantageous operation in many systems and applications, and tends to provide reliable and low complexity operation suitable for power transfer systems, where the power transfer signal is generated for the purpose of transferring power. Reusing the power transfer signal as a communication carrier can generally reduce complexity and require less circuitry, thereby reducing cost. The Qi specification was originally implemented by unidirectional communication from a power receiver to a power transmitter using load modulation with a modulation symbol shape that easily distinguishes between binary data values.

[0126] However, load modulation as used in, for example, Qi systems may also have some associated disadvantages. Such disadvantages may, for example, be related to issues such as electromagnetic compatibility, communication quality (bit error rate), and audible noise.

[0127] Load modulation can generate additional components in the electromagnetic spectrum, resulting in additional electromagnetic interference and electrical noise. Therefore, compared to more traditional communication systems where noise and interference are usually unrelated or independent noise caused by other noise or interference sources, load modulation in power transmission systems often leads to a large amount of self-interference. Specifically, the power transmission path includes a large amount of inductance and resonance, which causes load changes to cause oscillations and other interference components. Compared to conventional systems, therefore, interference is not independent or random noise and interference, but often includes components related to the actual modulation.

[0128] Moreover, it has been found that in many cases, changes in the electromagnetic field caused by load modulation can cause mechanical forces and motions that result in audible noise. It has also been found that strong load modulation can disturb the energy balance in the wireless power system, which leads to parasitic oscillations within the communication carrier spectrum. In the presence of parasitic oscillations, the wireless power transmitter is usually unable to properly demodulate the signal, and therefore it must interrupt power delivery to maintain safe operation.

[0129] Therefore, there are many challenges for communication in wireless power transfer systems.

[0130] Higher power transfer levels tend to exacerbate these problems. In fact, as the power level of the power transfer signal increases, the load variation required for load modulation also increases. Typically, the load modulation is required to be a power level or maximum power level that is an appropriate proportion of the power transfer signal. For example, the load modulation caused by the load modulation is required to have an amplitude of no less than about 1% of the general load of the power receiver, for example (i.e., the load variation for the receiver coil caused by the load modulation may be required to be no less than 1% of the total load of the receiver coil 107). Qi was initially introduced for low power applications below about 5W. For such lower power levels, the impact of the load modulation disadvantages is relatively manageable, or even substantially insignificant. However, the maximum power level for Qi has been increased to a current maximum of 15W, and continues to increase to a maximum level of 45W. However, for such power levels, the above-mentioned disadvantages are often significant, and they may provide a major obstacle to the further development of the Qi specification.

[0131] Although chip sequence based load modulation communication offers a number of advantages and specifically allows for a reduction in the modulation depth of the load modulation, current approaches often do not provide ideal performance. In fact, in some cases, reducing the modulation depth can reduce detection accuracy and increase bit error rates. Interference from the load modulation, especially self-interference from the load modulation, can result in data symbols not being accurately detected. In some cases, correlations performed at the data receiver can be attributed to interference that is not correctly detected. For example, Figure 7An example of a correlator output between a received load sequence and a modulation chip sequence used to modulate the power transfer signal is shown. Due to interference, the correlation peak is reduced and the noise and peak 701 in the example will not be accurately detected.

[0132] In many scenarios, these and other issues can be addressed by Figure 1 , 2 and 5. A method for wireless power transfer system to address and mitigate.

[0133] In the method, a modulation chip sequence (in many embodiments, having three or more levels) is generated by combining a first binary chip sequence and a second binary chip sequence. The data symbols, in particular bits, to be transmitted are then encoded by (usually multiplied by) this (usually three (or more) levels) modulation chip sequence. The resulting sequence is then modulated onto a power transmission signal.

[0134] In the method, therefore, data symbols are encoded using at least one modulation chip sequence, which is a combination of a first binary chip sequence and a second binary chip sequence and, in many embodiments, has at least three different chip values. Different data symbols may be associated with different modulation chip sequences and, therefore, with different first binary sequences and / or second binary sequences.

[0135] At the data receiving function of the power transmitter, the received load sequence is not directly correlated with the (e.g., three-level) modulation chip sequence, but is correlated twice, i.e., with the first chip sequence and the second chip sequence, respectively. Then, for example, by multiplying the two correlation values, the two obtained correlation values ​​are combined into a combined correlation value, and the data symbol is detected based on the obtained combined correlation value.

[0136] Reference Figure 8 and Fig. 9 The method is described in more detail.

[0137] Figure 8 Elements of a data transmitter 509 are illustrated. The exemplary data transmitter 509 includes a first sequence source 801 and a second sequence source 803. Each of the first sequence source 801 and the second sequence source 803 provides a binary chip sequence to a combiner 805, which combines the binary sequence into a modulation chip sequence. In many embodiments, the modulation chip sequence is generated as three horizontal modulation chip sequences.

[0138] In many embodiments, the first binary chip sequence and the second binary chip sequence are selected to have the same length, ie to include the same number of chips. Furthermore, the combining is typically performed on a chip basis and the combined modulated chip sequence has the same chip length / number as the original chip sequence.

[0139] As mentioned previously, the length of the chip sequence may typically include at least ten chips, and typically substantially more. In many embodiments, each chip sequence may have 2 N -1, where N is an integer usually not less than 4.

[0140] The first binary chip sequence and the second binary chip sequence are typically selected to have a relatively high cross-correlation when the binary sequences are aligned in time / sequence, i.e. for a given offset which is typically zero, but to have low cross-correlation values ​​when they are not aligned, i.e. for other time / sequence offsets, providing improved detection and communication characteristics.

[0141] The combination further causes the correlation value with the modulation chip sequence to maintain a relatively high cross-correlation with at least one but typically both of the first and second binary chip sequences when the sequence is aligned with the modulation chip sequence, but to maintain a relatively low cross-correlation when the sequence is not aligned with the modulation chip sequence.

[0142] In particular, the first and second binary code bit sequences and combinations are designed so that when the first binary sequence and the modulation code bit sequence are aligned, the cross-correlation between the first and / or second binary sequence and the modulation code bit sequence is not less than two-thirds of the length of the first and / or second binary sequence, but when the first binary sequence and the modulation code bit sequence are not aligned, it does not exceed one-third of the length of the first and / or second binary sequence.

[0143] For example, the first sequence source 801 may be based on the polynomial x 5 +x 2 +1 provides a fifth-order first binary chip sequence, which contains a set of 31 chips, which can be represented as -1 and 1. At the same time, the second sequence source 803 can use a different polynomial (such as x 5 +x 4 +x 3 +x 2 +1) generates a fifth-order binary sequence, which contains a set of another 31 code chips, which can be represented as -1 and 1. Fig.10 The autocorrelation and cross-correlation functions of these sequences are shown in .

[0144] In different embodiments, the combining of combiner 805 may use different methods to generate a three-level (or higher) modulation chip sequence. Typically, combining is performed on a chip-by-chip basis.

[0145] As a specific example, the first binary chip sequence and the second binary chip sequence may be represented by the values ​​-1 and 1, and the combination may follow the following rule for generating a combined modulation chip sequence, where the chip is represented by three possible values ​​(-1, 0, 1):

[0146] If two binary sequences at the same position have a chip value of 1, the resulting modulated chip sequence is set to a value of 1 at the corresponding position.

[0147] If two binary sequences at the same position have a chip value of -1, the resulting modulation chip sequence is set to a value of -1 at the corresponding position.

[0148] If the two sequences have different values ​​(-1 and 1) at the same position, the resulting modulation chip sequence is set to a value of 0.

[0149] Applying these rules to the first and second binary chip sequences results in a three-state modulation chip sequence. Furthermore, remarkably, the resulting sequence is strongly correlated with the first and second binary chip sequences. Fig.11 The cross-correlation between each of the first and second binary chip sequences and the resulting modulation chip sequence is illustrated. Fig.11 The result of multiplying two separate cross-correlations is further illustrated. It can be seen that the correlation peak is clearer and more defined for the multiplied result. In particular, it reflects that the random local maxima (minima) for the separate cross-correlation functions (between the modulation sequence and the first or second binary chip sequence) are not aligned. Therefore, the multiplication of the correlation results allows for improved detection of the correlation peak.

[0150] The modulation chip sequence is fed to a modulator 807, which is further coupled to a data source 809. The data source provides the data symbols to be transmitted, and the modulator then generates the corresponding chip sequence and controls the modulation of the chip sequence onto the power transmission signal.

[0151] In a specific example, the data symbol may be a binary data symbol represented by values ​​of -1 and 1, and the chip sequence to be modulated onto the power transfer signal may be generated by multiplying a modulation chip sequence (represented by (-1, 0, 1) levels / values) with the data symbol value. In other embodiments, other methods may be used. For example, for each data symbol value, a stored modulation chip sequence linked to that symbol (generated as a combination of two binary sequences) is retrieved and modulated onto the power transfer signal.

[0152] In the example, the chip sequence is modulated onto the power transfer signal by modifying the modulation capacitor 811 of the power transmitter input resonant circuit. In the example, for example, the capacitor can be connected / disconnected to the resonant circuit depending on the chip value. It should be understood that since the modulation chip sequence in many embodiments includes three (or more) levels, the load change for a given chip can be represented by three (or more) load changes. In many cases, the modulator 807 can switch the capacitance between three different levels (for example, using two different modulation capacitors and two switches). In some embodiments, different modulations for each chip can be used, wherein the modulation load can vary within the chip depending on the chip value, and therefore, more values ​​can be represented using, for example, simple binary switching of the load / modulation capacitor 811. Such methods will be described in more detail later.

[0153] Therefore, the power receiver transmits data symbols to the power transmitter by load modulating the power transfer signal, wherein each data symbol is modulated by a modulation load value sequence corresponding to a chip sequence of a set of modulation chip sequences. The modulation chip sequence is a combination of a first binary chip sequence and a second binary chip sequence and has at least three different chip values.

[0154] exist Figure 8 In the example, the modulation code bit sequences are dynamically generated, but it will be appreciated that in many embodiments they may be predetermined and stored, for example, in the data transmitter 509, where the appropriate modulation code bit sequence for a given data symbol is retrieved when that data symbol is to be transmitted.

[0155] Fig. 9 Elements of the data receiver 207 of the power transmitter according to some demonstrative embodiments of the present invention are illustrated.

[0156] The data receiver 207 comprises a load measurer 901 arranged to measure the load of the power transfer signal to determine a measured load value for the power transfer signal. The measured load value may indicate the load of the power transfer signal by the power receiver and may therefore indicate the modulation load applied to the power transfer signal by the power receiver 105.

[0157] The load measurer 901 is coupled to a chip determiner circuit 903, which is arranged to determine a received chip sequence based on the measured load value. The received chip sequence may in particular be a binary chip value sequence corresponding to an estimated chip value derived from the load measurement result. In some embodiments, the received chip sequence may be a soft decision value indicating not only a chip data value but also a confidence level for the chip data value. Thus, the received chip sequence is determined based on a load change determined by measuring the load of the power transmission signal.

[0158] The chip determiner circuit 903 is coupled to a first correlator 905 and a second correlator 907, which are fed with the received chip sequence from the chip determiner circuit 903. The first correlator 905 is coupled to a first correlation chip sequence source 909, which feeds the first binary sequence to the first correlator 905. Similarly, the second correlator 907 is coupled to a second correlation chip sequence source 911, which feeds the second binary sequence to the second correlator 907. The first binary sequence and the second binary sequence used by the data receiver 207 and the correlators 905, 907 are the same as the first binary sequence and the second binary sequence used by the data transmitter 509 of the power receiver, i.e., they combine to form a modulation chip sequence. Therefore, the data receiver 207 stores a local copy of the first binary sequence and the second binary sequence, and associates them with the received chip sequence to generate a first correlation value and a second correlation value, respectively. The data receiver 207 accordingly generates a first correlation value and a second correlation value corresponding to the correlation between the received chip sequence and the two binary sequences.

[0159] Correlators 905, 907 are coupled to combiner 915, which is fed with the first correlation value and the second correlation value. Combiner 915 is arranged to generate a combined correlation value according to the first correlation value and the second correlation value. The function can be a monotone increasing function of the first correlation value and the second correlation value in particular. The function can be linear with respect to the first correlation value and / or the second correlation value, or can be nonlinear in some cases. In many embodiments, the combiner is arranged to combine the two partial correlation values ​​from the first correlator 905 and the second correlator 907 by multiplying them together.

[0160] The combiner 915 is coupled to a detector 917 which is arranged to determine the received data symbol value from the combined correlation value.

[0161] The detector 917 is arranged to determine the data symbols received from the power receiver in response to a combined correlation value generated by correlation with the stored first binary chip sequence and the second binary chip sequence (at least one of which is different for different symbols). In particular, in some embodiments, the load detector 917 can perform a correlation operation for all possible data symbols by selecting the first binary chip sequence and the second binary chip sequence for each data symbol and determining the corresponding combined correlation value. In some cases, such as the described binary case, where some sequences are inverses of each other, only one combined correlation value can be determined, where the sign of the value reflects which of the two possible inverse modulation chip sequences is most likely to be received (and therefore which binary value is most likely to be received).

[0162] The detector 917 may then determine the data symbol as a data symbol linked to the first binary chip sequence and the second binary chip sequence for which the associated combined correlation value is sufficiently high for a given threshold to be exceeded. In many embodiments, the threshold may be an adaptive threshold, e.g., the threshold may be set based on correlation values ​​with other symbols. As a specific example, the threshold may be set to the value of the next highest correlation value (e.g., subject to a minimum threshold), which results in the data symbol being selected as the symbol with the highest correlation value (e.g., subject to it exceeding the minimum threshold).

[0163] Thus, the power receiver can transmit data to the power transmitter using load modulation with a relatively long chip sequence for each data symbol, and the power transmitter can be arranged to receive the communication. The communication is based on using a modulation chip sequence for a given data symbol, which is a combination of two binary sequences. The data receiver 207 is arranged to determine the received symbol by a combination of two correlations with the two binary sequences, rather than directly correlating with the modulation chip sequence.

[0164] In many embodiments, the method can provide substantially improved communications and operations. Specifically, substantially improved communication performance and reliability, and in particular symbol signal-to-noise ratio, can be substantially increased. The method is particularly advantageous in addressing self-interference associated with the load modulation itself. The method can allow for a substantial reduction in modulation depth, and in particular modulation load variation relative to power transfer signal level / power transfer level. This can reduce and mitigate many of the disadvantages of using load modulation, and can, for example, reduce electromagnetic interference, reduce electrical noise, reduce mechanical noise, prevent or mitigate parasitic oscillations, etc.

[0165] In some embodiments, each chip may be represented by a constant modulation level, such as specifically a constant modulation load. In such embodiments, the modulation load varies only between chips. However, in some embodiments, each chip may be modulated / represented as a differential or load transition parameter. For example, in many embodiments, a first chip value (e.g., -1) may be represented by a chip that includes a modulation load change in a first direction (e.g., increasing or decreasing the load), a second chip value (e.g., +1) may be represented by a chip that includes a modulation load change in a second direction (e.g., increasing or decreasing the load opposite to the transition for the first chip value), and wherein a third chip value (e.g., 0) is represented by no modulation load transition occurring within the chip interval.

[0166] Such an approach may facilitate and / or improve the determination of received chip values. For example, using an approach with a constant modulation chip level, the chip value may be detected by comparing the measured load value with a threshold. For example, the load measurer 901 may be arranged to measure the load once for each chip value, i.e., the load measurement value may be a load measurement sample generated with one sample per chip.

[0167] For example, the load value (e.g., current and / or power) of the drive signal may be measured and sampled at time intervals corresponding to the chip interval during the time when the message is (expectedly) received from the power receiver. Thus, the received chip sequence is generated based on the sampling of the (one or more) signals of the output circuit.

[0168] However, typically, the load variations caused by load modulation are relatively small, which makes it difficult to accurately detect the chip value. Furthermore, since specific operating conditions often vary substantially, a fixed predetermined threshold is typically not ideal, or may not even be feasible. Instead, a suitable threshold may be determined based on the signal conditions, and in particular a threshold corresponding to an average modulation load level may be derived.

[0169] Fig.12 An example of how the power transfer signal is load modulated by chips of a chip sequence is illustrated. In this example, the modulation is synchronized with the power transfer signal at a rate of one chip every two power signal periods. Fig.12 The arrows in indicate the time at which the load of the power transfer signal is measured / sampled. The sampling is synchronized with the power transfer signal and one sample is generated for each chip.

[0170] To determine the (binary) chip value, the sampled load value is compared with an average level 1201. In a specific example, the load of the power transfer signal is determined as a peak period value of the measured signal (which may in particular be the current, voltage, phase or power of the power transfer signal), and the sampling is synchronized with the peaks of the power transfer signal. Furthermore, the average level 1201 of the peak period values ​​is first determined, and then the chip value is determined based on whether the measured sample value is above or below the average level 1201. For a three-level modulation chip sequence, two thresholds may be used to divide the load value into three intervals (and thus, wherein a -1 level is determined if the measured value is below the lowest threshold, a +1 level is determined if the measured value is above the highest threshold, and 0 is determined if the measured value is between the thresholds).

[0171] However, while such an approach can provide a very useful communication link in many cases, in some cases it can be sensitive to noise, errors, etc., and it can sometimes result in a higher bit error rate than would be preferred. In particular, for reference Fig.12With the described method, it is important to determine the average level with appropriate accuracy. Deviations and errors may have an impact not only on the individual chip values, but also on the correlation results used to determine the data symbols themselves. It may result in reduced peaks, strong sidelobes of the peaks or even peaks with opposite signs, etc. Thus, it may lead to a large number of bit errors.

[0172] In some embodiments, modulation of the chip level may be based on load transitions within the chip duration. In many scenarios, this may provide improved performance and / or facilitated operation. Rather than requiring determination of an exact average level, the method may effectively embed the reference level into the modulation format itself. It may also provide for a higher number of chip modulation levels, including providing efficient support for three (or, for example, four) level modulation chip sequences.

[0173] In the method, each chip is divided into two (or more) load time intervals, possibly with different modulation loads. Thus, each chip may include at least two load time intervals with potentially different modulation loads, and thus, the chip may be represented by at least two different modulation loads, and in particular, each chip is represented by a pattern of load modulation loads, which pattern of load modulation loads for at least two load time intervals may be different for at least some chip values. Furthermore, the pattern of different modulation loads is specific to a given chip value. Thus, different chip values ​​are linked to different patterns of load modulation. In the method, instead of considering the entire chip time interval as one (constant) load time interval, the chip time interval is divided into a plurality of load time intervals (wherein, in the example, the modulation load is constant within these time intervals).

[0174] In the case where the system may use a binary modulated load, that is, the modulated load applied by the power receiver may have one of two possible load values. Such an approach is advantageous by allowing a low complexity implementation and convenient operation. It generally facilitates load modulation operation for both transmit and receive functions and tends to result in efficient performance and reliable communications. It may also allow more chip values ​​(e.g., three or four values) to be effectively represented while using only a binary modulated load.

[0175] As an example, the data transmitter 509 may generally control the switching on or off of a modulation load component (such as a capacitor or a resistor), and thus may be applied to different modulation loads.

[0176] In many embodiments, therefore, binary load modulation may be used while still allowing non-binary chip values. In many embodiments, the chip time interval may be divided into two load time intervals, with one binary load value being applied to one load time interval and another load value being applied to the other load time interval. Two binary chip values ​​may then be determined to correspond to two possible patterns / orders of two modulation loads assigned to the two load time intervals. In particular, in some embodiments, each transmitted chip may be divided into two halves, with each half having opposite modulation loads, and the order of these loads (i.e., which modulation load is assigned to the first half) depends on the binary chip value.

[0177] Fig.13 1301 illustrates a chip sequence and a chip value, and a middle signal 1303 illustrates a modulation load value variation. As shown, each chip is divided into two load time intervals, one of which has, for example, a (relatively) high modulation load and one with a (relatively) low modulation load. Whether the first load time interval of a given chip is a (relatively) high or a (relatively) low modulation load depends on the chip value.

[0178] In particular, signal 1301 shows the chips in the sequence, and signal 1303 shows the switching of the modulation load by the data transmitter 509, i.e., shows the modulation load level in the load time interval. In the example, for a "1" chip, the data transmitter 509 turns off (or turns low) the modulation load in the first half, and turns on (or turns high) the modulation load in the second half. Conversely, for a "-1" chip, the data transmitter 509 turns on (or turns high) the modulation load in the first half, and turns off (or turns low) the modulation load in the second half.

[0179] In many embodiments, such binary chip values ​​can be extended by, for example, including a third chip value represented by a modulation load that does not change in the chip interval, i.e., the modulation load is the same in both load time intervals. In this way, additional chip values ​​and higher order chip value modulations can be implemented.

[0180] Therefore, such an approach not only allows the determination of chip values ​​without requiring an accurate threshold, but also can efficiently support modulation chip sequences with three or more possible chip values.

[0181] In the method, the power transmitter is arranged to determine the data symbol by taking into account the relative load variation within a chip. In particular, the load measurer 901 is arranged to measure the load of the power transmission signal to determine the measured load value for the load time interval. The measured load value / sample can be determined for each load time interval.

[0182] The chip determiner circuit 903 is arranged to determine an individual chip value in response to a difference between measured load values ​​for at least two modulation load time intervals of an individual chip.

[0183] In particular, the chip determiner circuit 903 may be arranged to determine the difference between two load time intervals, for example, the load value for the first load time interval may be subtracted from the load value for the second load time interval. Based on the result, the chip determiner circuit 903 may then proceed to determine the chip value based on the difference.

[0184] exist Fig.13 , signal 1305 represents the measurement result of the drive signal / power transfer signal. As can be seen, each code chip includes a load time interval with a high signal level (corresponding to a low modulation load) and a load time interval with a low signal level (corresponding to a high and low modulation load), where the order of these depends on the code chip value. In the example, an increasing signal level (the level for the second load time interval is higher than the level for the first load time interval) is decoded as a code chip value of "1", and a decreasing signal level (the level for the first load time interval is higher than the level for the second load time interval) is decoded as "-1". In addition, if the difference between the signal levels in the two time intervals is below a given (e.g., predetermined) threshold, the code chip value is set to 0.

[0185] The amplitude / level of the drive signal / power transfer signal in the first half of the chip (first load time interval) can be used as a reference level for measurements made in the second half of the chip (second load time interval), and vice versa. Thus, the reference for load modulation determination for individual chips is directly embedded in the modulation format. Therefore, the chip value can be determined without requiring the estimation or determination of an average value or reference level. Instead, local intra-chip relative measurements and comparisons can be used to determine the chip value.

[0186] The chip values ​​are then used to generate a received chip sequence, which is compared with the first binary chip sequence and the second binary chip sequence.

[0187] The method may provide substantially improved performance and more reliable data communications.

[0188] In many embodiments, the chip determiner circuit 903 may be arranged to determine the chip value as a binary chip value. The chip determiner circuit 902 may be particularly arranged to select a binary chip value to correspond to the sign of the difference between the load values / metrics in the load time intervals of the chips. For example, if the signal peak sample is higher in the first load time interval than in the second load time interval, the chip value may be determined as "1", and if the signal peak sample is lower in the first load time interval than in the second load time interval, the chip value may be determined as "-1" (or vice versa). In many embodiments, the chip determiner circuit 903 may determine the difference between the load values ​​in the load time intervals and set the binary value to correspond to the sign. However, if the absolute difference is below a threshold, the chip value may be determined as "0".

[0189] Such an approach can provide a low complexity but accurate determination of the received chip sequence, which is suitable for low complexity correlation. For example, since the multiplication can be replaced by a simple binary operation (such as a simple binary XOR operation), it can allow a binary correlation operation of substantially lower complexity and resource requirements. For a "0" value, the correlation can simply be skipped.

[0190] In some embodiments, the chip determiner circuit 903 may be arranged to determine that the received chip sequence comprises soft decision chip values.Rather than simply symbol values, the generated chip values ​​may also indicate a reliability or confidence level for the chip values.

[0191] For example, in addition to the sign, the magnitude of the difference may also be considered. For example, given a nominal situation without noise, the nominal magnitude of the difference may be determined (or, for example, the nominal difference may be determined by averaging / low filtering the differences over multiple and typically many chips). The deviation of the difference from that difference for a given chip may accordingly indicate the probability that the decision is the correct value. However, in most embodiments, the magnitude of the difference may simply indicate confidence or reliability, and the larger the measured difference, the more likely the sign is correct, i.e., the larger the magnitude of the difference, the higher the confidence in the chip value.

[0192] The correlation with the chip sequence of the set of chip sequences may be performed in response to the soft decision chip values, and in particular, the correlation may be performed using the soft decision values.

[0193] For example, in some embodiments, the correlation may be performed as a binary XOR operation between a stored binary chip sequence and a received chip sequence formed by the signs of the determined differences, wherein the result of each XOR operation is weighted (e.g., multiplied) by the magnitude of the difference (perhaps relative to a nominal difference) before summing the results. As another example, the stored chip sequence may be represented by chip values ​​of +1 and -1, and these values ​​may be directly multiplied by the corresponding chip load differences (corresponding to the received chip sequence). The correlation may then be determined by adding the multiplication results.

[0194] Such an approach may require more complex operations, but in many embodiments and scenarios may provide improved performance, and in particular may allow for more accurate data symbol detection.

[0195] In many embodiments, the chip determiner 211 is arranged to determine the received chip sequence as a binary chip sequence, and in particular, even if the modulation chip sequence is a three or higher level / value sequence, the received chip sequence is determined as a binary sequence. Even if the modulation chip sequence is a three or higher level sequence, the chip determiner 211 can also specifically determine the received chip sequence as a binary chip sequence. For example, even if the modulation chip sequence is represented by three possible levels (-1, 0, 1) for each chip, the chip determiner 211 can also be arranged to simply determine the chips of the received chip sequence as having binary values ​​(-1, 1). The binary received chip sequence is then fed to a correlator for correlation with the first binary chip sequence and the second binary chip sequence, respectively. In this case, a low complexity correlation and operation can be performed. In addition, this can be achieved while maintaining reliable performance and improved / reliable data symbol detection.

[0196] In some embodiments, the chip determiner 211 can determine the received chip sequence as having the same value that is possible / allowed for the modulation chip sequence. For example, for a three-level modulation chip sequence, the received chip sequence can be determined as a three-level modulation chip sequence. For example, the chip determiner 211 can determine the most likely chip value by selecting the possible value closest to the measured value. In such a case, the correlation can still be performed with the first binary sequence and the second binary sequence, that is, the correlation can be between the received chip sequence and the two binary sequences at three (or higher) levels. In some cases, the method can provide improved performance and can achieve improved data symbol detection. In addition, in many cases, this can be achieved in the case of low complexity and resource usage, because the correlation with the binary sequence can be effectively achieved, such as using a simple logic circuit to compare the values ​​and not requiring explicit multiplication.

[0197] In some embodiments, the chip determiner 211 may determine the chip value as a soft decision value. Such a chip value may include an indication of the likelihood that the detected chip value is correct. Uncertainty indications may be considered in the correlation, and in particular, a lower uncertainty indication may result in a higher weighting of the correlation value for that chip than a higher uncertainty indication.

[0198] For example, as described above, the chip value for a three-level modulation chip sequence having three levels may be represented by a load change in one direction, a load change in another direction, or no load change, respectively. The chip determiner 211 may be arranged to determine the chip value by determining the difference between the load values ​​in the first half and the second half of the chip. For a chip determiner 211 that determines the received chip sequence as a binary chip value, the chip value may be set to the sign of the difference. For a three-level received chip sequence, the chip determiner 211 may determine the chip value as a sign unless the absolute value is below a threshold, in which case the chip level may be set to a third value, such as a zero value. For a soft decision chip determiner 211, the chip value may simply be set to a difference (e.g., normalized relative to a suitable reference level).

[0199] In many embodiments, the chip determiner 211 may determine the received chip sequence as a binary received chip sequence. In such a case, the first binary value for the received chip sequence may represent the first chip value of the modulation chip sequence, and the second binary value for the received chip sequence may represent the second chip value of the modulation chip sequence. For a modulation chip sequence having at least three possible values, the chip determiner 211 may be arranged to determine the binary value as the first binary value or the second binary value with a probability of no more than 10% or even 5%. This determination may depend on the noise / interference and may meet the requirements for symmetric noise and interference. In fact, in most embodiments, the chip determiner 211 may be arranged to determine the binary value for the binary received chip sequence with substantially equal symmetric noise probability for at least one chip level of the modulation chip sequence.

[0200] In many embodiments, the chip determiner 211 may be arranged to implement, for at least one chip value of the modulation chip sequence, a symmetric decision between a first chip value and a second chip value for the received chip sequence.

[0201] As a specific example, the modulation chip sequence may be arranged to use chip values ​​-1, 0, 1, where these chip values ​​are load modulated by a modulation load, where the modulation load for value 0 is between the modulation loads for -1 and +1. The chip determiner 211 may be arranged to determine the received chip sequence as a binary sequence having values ​​-1 and +1, respectively. In this case, the binary chip value for the modulation chip sequence chip value of 0 may be determined to be -1 or +1 with equal probability.

[0202] As another example, if differential / load conversion modulation of chip values ​​is used, the chip determiner 211 can determine the load difference between the first time interval and the second time interval, and then determine the chip value as the sign of the difference. For the chip value of the modulation chip sequence (0) without the introduction of load conversion, the sign of the difference is random, 50% of any value changes, and therefore, the probability that the received chip sequence is determined to be any binary value is 50%.

[0203] In many embodiments, the data receiver 207 is arranged such that the contribution of the first correlation value and / or the second correlation value for at least one chip value of the modulation chip sequence is less than 10% (or even less than 5% or 1%) of the contribution for at least one other chip value of the modulation chip sequence. The contribution may be the contribution when no noise or interference is present, or may be regarded as an average contribution in the presence of symmetrical (with respect to the chip value) noise, for example.

[0204] For example, when the binary chip value of the received chip sequence is determined to be the first binary value or the second binary value with equal probability for one modulation chip sequence chip value (0), the average contribution to the first correlation and the second correlation will be zero. In some embodiments, the data receiver 207 may, for example, be arranged to detect that the third chip level is received and explicitly ignore it in the correlation. For example, for the load switching method, differences with an absolute level below a given threshold may be ignored or set to zero.

[0205] Such methods may provide improved operation and generally provide more accurate data detection in the presence of noise.The method may utilize that the correlation of difference chip sequences combined into a modulation chip sequence may reflect different correlation characteristics that may be combined to provide overall improved performance.

[0206] The method may generally provide improved communication channel resilience against random detection errors (false correlation peaks), as well as improved detectability of signals under severe interference (eg, spurious oscillations in the system). Fig.14The correlation output for a single correlation is illustrated with the measured load shift / difference and a single full chip sequence compared to the combined correlation value from two correlations with the first and second sequences. It can be observed that the ratio of the average correlation peak amplitude to the average output of the correlator is about 16 dB in the first case and about 36 dB in the second case. Fig.15 Another example is illustrated, where noise and interference are further taken into account. As can be seen in the example, using the described method but not using a simple single correlation, the correlation peak around sample 257 can be clearly detected.

[0207] The above description has focused on the scenario where the modulation chip sequence is a non-binary sequence, where the chip can be one of three or more different levels. However, although such an approach can provide advantageous operation in many embodiments, in some embodiments, it is also possible to determine the modulation chip sequence itself as a binary sequence.

[0208] In the method described above, for the situation that the first binary sequence and the second binary sequence have different bit values, the third level is selected. The third level is determined as a binary value with equal probability by the data receiver 207, so that the average contribution to the correlation is ideally reduced to zero. However, in some embodiments, the selection of binary values ​​can be performed on the data transmitter side. For example, the chip value of the chip in which the first binary sequence and the second binary sequence have different values ​​can be selected to alternate between the value set as the first binary sequence and the value of the second sequence. In such a case, the contribution of these values ​​to the first correlation value and the second correlation value can be reduced to a value that is usually not significant (and may even be reduced to an average zero contribution). In addition, such a method can maintain a balanced influence on the correlation of two individuals, which provides an improved detection accuracy in many cases.

[0209] It should be understood that other methods for selecting binary values ​​in the case of different values ​​for the first binary value and the second binary value may be used, such as, for example, randomly selecting from either sequence, alternately selecting from either sequence, using an index into the sequence to select between either sequence, etc.

[0210] The chip time interval may generally be synchronized with the period of the power transfer signal. Similarly, the load time interval may generally be synchronized with the period of the power transfer signal. In many embodiments, the system may be arranged to synchronize the load modulation communication (and in particular the chip time interval and the load time interval) with the power transfer signal / drive signal.

[0211] In many embodiments, the data transmitter 509 may be particularly arranged to synchronize the load modulation of the chip sequence and the load time interval with the power transfer signal. The power transfer signal has an operating frequency typically in the range of 10kHz-500kHz, and is often about 100kHz for Qi. The data transmitter 509 may synchronize the timing of the chip time interval and the load time interval with the oscillation and period of the power transfer signal. For example, in many embodiments, the data transmitter 509 may use a chip duration / time interval and / or a load time interval (duration) that is a multiple of the power transfer signal period. Thus, each load time interval may have a duration that is a multiple of the cycle time of the power transfer signal, i.e., the duration of the load time interval may be N*T, where N is an integer and T is the duration of the period of the power transfer signal / drive signal.

[0212] In many embodiments, the data transmitter 509 may not only synchronize the duration of the load time interval with the duration of the period of the power transfer signal, but may also time the start and / or stop timing of the load time interval with the timing of the power transfer signal. In particular, the transition times between the modulation levels of the load time interval may be synchronized to occur at the zero crossing of the power transfer signal or, for example, have a fixed offset relative to the zero crossing of the power transfer signal. It will be appreciated that the synchronization may be based on the timing of the signal induced in the receiver coil 107 by the power transfer signal.

[0213] Similarly, the power transmitter may be arranged to generate the received chip sequence from samples / measurements of the load of the power transfer signal / drive signal (possibly after applying matched filtering).

[0214] The load measurer 901 may specifically sample a signal of the output circuit that corresponds to the power transfer signal, such as the current and / or power of the drive signal, the relative phase between the current and voltage of the drive signal, the current through the transmitter coil 103, etc. The load modulation data receiver 207 may then generate a received chip sequence based on the difference between such load measurements at given sampling times of different load time intervals belonging to a given chip.

[0215] In many embodiments, the load measurer 901 may be arranged to synchronize the sampling with the power transfer signal, and in particular this may be achieved by synchronizing it with the drive signal.

[0216] In many embodiments, the synchronization may be sampling such that, for example, one sampling is performed every load time interval (possibly after matched filtering). In particular, if the load time interval duration is equal to N times the period of the power transfer signal, the sampling may also be synchronized to once every N times. Thus, in many embodiments, the synchronization may be such that the sampling rate is equal to the load time interval frequency of the load modulation.

[0217] In some embodiments, sampling can be a two-stage process in which multiple samples are generated at a higher frequency and then decimated to a given sampling rate. For example, for a load time interval duration of ten times the period of the power transfer signal, the sampler can take one sample per cycle. The averaging filter can then add the last ten samples, that is, it can be a square window FIR filter (with equal weights) that sums the last ten samples. The output of the sampling can be the sampled output of the filter, such as specifically, the output of every ten cycles, which is consistent with the filter, which is the sum of ten cycles falling within a single code chip. Therefore, sampling at the synchronization time can be effectively achieved by decimation suitable for synchronization at the output of the filter.

[0218] However, in most embodiments, only a single sampling / measurement is performed per load time interval. In such cases, the timing of the sampling can be synchronized for each sample to occur at the peak of the cycle of the signal / parameter being measured. If the load time interval and sampling are synchronized with the power transfer signal cycle, this can be simply achieved by sampling / measuring at the center time of the load time interval.

[0219] In many embodiments, the operating frequency of the drive signal and the power transfer signal can therefore be an integer multiple of the sampling rate of the sampling of the signal of the output circuit and / or an integer multiple of the load time interval and the chip frequency of the load modulation. The multiple can specifically be one. In fact, in many embodiments, the integer multiple is advantageously relatively low to allow efficient communication and higher data rates. In many embodiments, the integer is advantageously no more than 1, 3, 5, 10 or 20.

[0220] Synchronization of load modulation with the power transfer signal may allow an increase in the chip rate and / or bit rate in many practical implementations, since it can reduce the amount of sampling that the power transmitter must perform. In the extreme case where the chip frequency is the same as the power transfer signal frequency, the power receiver may change the load according to the chip sequence at every cycle of the power transfer signal, and for two load time intervals, the load may change every half cycle of the power transfer signal. Alternatively, the power receiver may change the load according to the chip sequence every N cycles of the power signal, which reduces the chip frequency by a factor of N.

[0221] Synchronous modulation simplifies modulation detection at the power transmitter side by enabling the power transmitter side to apply synchronous sampling techniques and after this step to correlate the detected signal with the modulation sequence. The method can generally be substantially facilitated while achieving efficient communication.

[0222] The length of the chip sequence may be selected for the specific preferences and requirements of an individual embodiment, and may be selected to provide a suitable tradeoff between communication reliability and performance (e.g., bit rate), data rate, bandwidth, modulation depth and associated drawbacks, etc. In most embodiments, a length of no less than 8 and / or no greater than 128 chips will provide suitable and advantageous performance for a wireless power transfer system, such as specifically for a Qi system.

[0223] The specific chip sequence and pattern used may depend on the preferences and requirements of individual embodiments. Typically, a sequence is selected to provide good correlation properties, and in particular, a set of chip sequences is selected to include sequences having high autocorrelation values ​​and low cross-correlation values. In many embodiments, a chip sequence may be selected as a maximum length sequence. For example, in many embodiments, a chip sequence may be selected as a maximum length sequence generated from a polynomial of a polynomial order selected by a power receiver according to a desired / selected modulation depth and a desired communication speed. In particular, pseudo noise sequences developed for direct sequence spread spectrum communications and code division multiple access systems and used therein may tend to also be suitable for the described method.

[0224] As previously mentioned, a set of sequences may include mirror or inverse chip sequences, i.e., for a given binary chip sequence, a set of chip sequences may also include chip sequences where all chips have complementary values. For example, if the load values ​​are represented by 1 and -1, then for each chip sequence, a set of chip sequences may also include chip sequences generated by multiplication by -1 (equivalent to swapping between 0 and 1 for all chips for a chip sequence represented by values ​​of 1 and 0). In fact, in some embodiments, the set of chip sequences may only include chip sequences and inverse chip sequences. It will be appreciated that in such embodiments, only a single representation needs to be stored to represent a pair of chip sequences and inverse chip sequences.

[0225] Such an approach may be particularly suitable for many applications and may result in good performance and low complexity. For example, a single correlation between a received chip sequence and a reference chip sequence may provide correlation values ​​for both the reference chip sequence and the inverse chip sequence. In fact, if there is no noise, the correlation value for one of the reference chip sequences may be +1, and the correlation value for the inverse reference chip sequence would be -1. Thus, a single correlation value applicable to two symbol values / sequences may be determined and used directly to select between the two symbols.

[0226] It will be appreciated that the method using the inverse reference chip sequence can be considered equal to the product of a binary data symbol and a single reference chip sequence (using the values ​​of 1 and -1 to represent the binary value).

[0227] In the described paradigm for load switching modulation, each chip is divided into two load time intervals with different modulation loads. This can allow efficient operation with improved performance. In many embodiments, it can specifically allow low complexity and low resource usage while still providing significantly improved performance.

[0228] However, in some embodiments, each chip may be divided into three or more load time intervals with different modulation loads.

[0229] For example, in some embodiments, each chip may be divided into three load time intervals, wherein the load level for the first load time interval is a reference level. For a first binary chip value, the load in the second load time interval may be higher than the reference level, and the load in the third load time interval may be lower than the reference level. For other binary values, the load may be lower than the reference level in the second load time interval, and may be higher than the reference level in the third load time interval. The chip determiner circuit 903 may then determine a (e.g., binary) chip value that may detect whether there are two load changes and the direction of the changes in the individual load time intervals. Such an approach may allow for improved chip value determination in different scenarios. For example, it may reduce sensitivity to the direction of the load change.

[0230] In many embodiments, each load time interval may have a duration of a single period of the power transfer signal. This may be advantageous in many embodiments because it may, for example, reduce the minimum time required for each chip, thereby allowing the use of higher data rates or, for example, longer chip sequences.

[0231] However, in some embodiments, each load time interval may have a duration of multiple cycles of the power transfer signal. In some embodiments, each load time interval may have a duration of no less than two, three, five, or ten cycles of the power transfer signal. This may be advantageous in many scenarios, for example by facilitating or improving the measurement process. For example, synchronization of sampled peaks of the power transfer signal / drive signal may be relatively easy to achieve, but synchronization between a chip and a set of cycles corresponding to each load time interval of a chip may be more difficult. For example, alignment of the cycle peaks of individual chips with the load time interval may be disrupted, which may cause the power transmitter to assign load measurements to the wrong load time interval / chip.

[0232] For example, in many embodiments, the determination of the next power transfer signal period may be determined by detecting zero crossings of the power transfer signal. However, due to noise etc., it is possible that erroneous additional zero crossings may be detected, or (less likely) zero crossings may be missed. For the case where each load time interval has a duration of one power transfer signal period, this may result in a misalignment between the period / measurement results and the load time intervals of the individual chips, which results in detection errors.

[0233] However, by having a load time interval that is a multiple of the cycle of the power transfer signal in duration, such errors may be mitigated.

[0234] The modulated load may be a load component of the load of the power transfer signal / drive signal caused by / depending on / varying with load modulation.

[0235] It will be appreciated that, for clarity, the above description has described embodiments of the present invention with reference to different functional circuits, units and processors. However, it will be apparent that any suitable distribution of functionality may be used between different functional units or processors without departing from the present invention. For example, functions shown to be performed by separate processors or controllers may be performed by the same processor or controller. Therefore, references to specific functional units or circuits are only viewed as references to suitable means for providing the described functionality, rather than indicating a strict logical or physical structure or organization.

[0236] The present invention can be implemented in any suitable form, including hardware, software, firmware or any combination of these. The present invention can be optionally implemented at least in part as computer software running on one or more data processors and / or digital signal processors. The elements and components of embodiments of the present invention can be implemented physically, functionally and logically in any suitable manner. In fact, the function can be implemented in a single unit, in multiple units or as a part of other functional units. Therefore, the present invention can be implemented in a single unit, or can be physically and functionally distributed between different units, circuits and processors.

[0237] Although the present invention has been described in conjunction with some embodiments, the present invention is not intended to be limited to the specific forms set forth herein. On the contrary, the scope of the present invention is limited only by the appended claims. In addition, although features may appear to be described in conjunction with specific embodiments, those skilled in the art will recognize that the various features of the described embodiments may be combined according to the present invention. In the claims, the term "comprising" does not exclude the presence of other elements or steps.

[0238] In addition, although listed separately, multiple devices, elements, circuits or method steps may be implemented by, for example, a single circuit, unit or processor. In addition, although individual features may be included in different claims, these features may be advantageously combined, and inclusion in different claims does not imply that the combination of features is not feasible and / or advantageous. In addition, the inclusion of a feature in a class of claims does not imply a limitation to the class, but rather indicates that the feature is equally applicable to other claim classes as appropriate. The inclusion of a feature in a dependent claim of an independent claim does not imply a limitation to the independent claim, but rather indicates that the feature is equally applicable to other independent claims as appropriate. In addition, the order of features in the claims does not imply that the features must work in any particular order, and in particular the order of individual steps in a method claim does not imply that the steps must be performed in that order. On the contrary, the steps may be performed in any suitable order. In addition, singular references do not exclude pluralities. Therefore, references to "one", "a", "first", "second", etc. do not exclude multiples. The figure marks in the claims are provided only as clarification examples and should not be interpreted as limiting the scope of the claims in any way.

Claims

1. A power transmitter (101) for wirelessly providing power to a power receiver (105) via an electromagnetic power transfer signal, the power transmitter (101) comprising: an output circuit (203, 103) comprising a transmitter coil (103) arranged to generate the power transfer signal in response to a drive signal being applied to the output circuit (203, 103); a driver (201) arranged to generate the drive signal; as well as a data receiver (207) arranged to receive load modulated data symbols modulated by at least one modulation chip sequence, at least a first modulation chip sequence of the at least one modulation chip sequence being a combination of a first binary chip sequence and a second binary chip sequence; Wherein, the receiver (207) comprises: a load measurer (901) arranged to measure a loading of the power transfer signal to generate a measured load value; a chip determiner (903) arranged to determine a received chip sequence based on the measured load value; a first correlator (905) arranged to correlate the received chip sequence with the first binary chip sequence to generate a first correlation value; a second correlator (907) arranged to correlate the received chip sequence with the second binary chip sequence to generate a second correlation value; a combiner (915) arranged to generate a combined correlation value based on the first correlation value and the second correlation value; The detector (917) is arranged to detect a received data symbol value in response to the combined correlation value.

2. The power transmitter according to claim 1, wherein: The first modulation chip sequence includes at least three different chip values.

3. The power transmitter according to claim 1 or 2, wherein: At least two chip values ​​of the first modulation chip sequence are represented by a modulation load variation, which is different for the at least two chip values; and the chip determiner (903) is arranged to determine the received chip sequence in response to the modulation load variation.

4. The power transmitter according to claim 2 or 3, wherein: Each of the chip time intervals of the first modulation chip sequence is divided into at least two load time intervals, at least two chip values ​​have different modulation loads for the at least two load time intervals, a pattern of the modulation load is different for different chip values ​​of the at least two chip values, and a third chip value of the at least three different chip values ​​has the same modulation load in the at least two load time intervals; and The load measurer (901) is arranged to determine the measured load value as a measured load value for a load time interval; and The chip determiner (903) is arranged to determine a chip value for a received chip sequence in response to differences in measured load values ​​for different load time intervals for each chip.

5. A power transmitter according to any preceding claim, wherein: The first modulation chip sequence includes three different chip values.

6. The power transmitter according to claim 5, wherein: The first modulation code chip sequence has a first value of alignment code chips for the first binary sequence and the second binary sequence both having a first binary value, a second value of alignment code chips for the first binary sequence and the second binary sequence both having a second binary value; and a third value of alignment code chips for the first binary sequence and the second binary sequence having different alignment values.

7. A power transmitter according to any preceding claim, wherein: The chip determiner (903) is arranged to determine the received chip sequence as a binary chip sequence.

8. The power transmitter according to claim 7, wherein: The chip determiner (903) and the first correlator (905) are arranged such that a contribution of the first correlation value to at least one chip value of the first modulation chip sequence is less than 10% of a contribution of the first correlation value to at least one other chip value of the modulation chip sequence.

9. A power transmitter according to any preceding claim, wherein: The combiner (915) is arranged to generate a combined correlation value in response to a product of the first correlation value and the second correlation value.

10. A power transmitter according to any preceding claim, wherein: The chip determiner (903) is arranged to determine the received chip sequence as having chip values ​​that are possible chip values ​​for the first modulation chip sequence.

11. A power transmitter according to any preceding claim, wherein: When the first binary sequence and the first modulation code sequence are aligned, the cross-correlation between the first binary sequence and the first modulation code sequence is not less than two-thirds of the length of the first binary sequence, and when the first binary sequence and the first modulation code sequence are not aligned, the cross-correlation between the first binary sequence and the first modulation code sequence is not greater than one-third of the length of the first binary sequence.

12. A power receiver (105) for wirelessly receiving power from a power transmitter (101) via an electromagnetic power transfer signal, the power receiver (105) comprising: an input circuit (107, 503) comprising a receiver coil (107) arranged to extract power from the power transfer signal; a data transmitter (509) arranged to transmit data symbols to the power transmitter by load regulating the power transfer signal, each data symbol being modulated by a sequence of modulation load values ​​corresponding to a chip sequence of a set of modulation chip sequences, the chip sequences of the set of chip sequences being linked to different data symbol values; At least one modulation chip sequence in a group of modulation chip sequences is a combination of a first binary chip sequence and a second binary chip sequence, and has at least three different chip values.

13. A method of operation of a power transmitter (101) for wirelessly providing power to a power receiver (105) via an electromagnetic power transfer signal, the power transmitter (101) comprising: an output circuit (203, 103) comprising a transmitter coil (103) arranged to generate the power transfer signal in response to a drive signal being applied to the output circuit (203, 103); a driver (201) arranged to generate the drive signal; as well as a data receiver (207) arranged to receive load modulated data symbols modulated by at least one modulation chip sequence, at least a first modulation chip sequence of the at least one modulation chip sequence being a combination of a first binary chip sequence and a second binary chip sequence; The method comprises the receiver (207) performing the following steps: measuring loading of the power transfer signal to generate a measured load value; determining a received chip sequence according to the measured load value; correlating the received chip sequence with the first binary chip sequence to generate a first correlation value; correlating the received chip sequence with the second binary chip sequence to generate a second correlation value; generating a combined correlation value based on the first correlation value and the second correlation value; A received data symbol value is detected in response to the combined correlation value.

14. A method of operation of a power receiver (105) for wirelessly receiving power from a power transmitter (101) via an electromagnetic power transfer signal, the power receiver (105) comprising: an input circuit (107, 503) comprising a receiver coil (107) arranged to extract power from the power transfer signal; Furthermore, the method comprises: A data transmitter (509) transmits data symbols to the power transmitter by load modulating the power transfer signal, each data symbol being modulated by a sequence of modulation load values ​​corresponding to a chip sequence of a set of modulation chip sequences, the chip sequences of the set of chip sequences being linked to different data symbol values; At least one modulation chip sequence in a group of modulation chip sequences is a combination of a first binary chip sequence and a second binary chip sequence, and has at least three different chip values. 15 . A wireless power transfer system comprising the power transmitter according to claim 1 and the power receiver according to claim 12 .

Images