Receiver synchronization for optical communications

Abstract

An optical communication system, receiver, and method for synchronizing a receiver and a transmitter to decode a data input stream transmitted by the transmitter and received at the receiver. The method includes receiving, at a receiver, a data input stream having a first data rate set based on a transmitter clock rate; generating a wave; obtaining a phase error between the data input stream and the generated wave; determining a synchronous clock rate by adjusting the frequency of the generated wave using the phase error to match the frequency of the generated wave to a transmitter clock rate of the data input stream; and decoding the data input stream using the synchronous clock rate, thereby obtaining data encoded in the data input stream.

Description

Technical Field

[0001] The present disclosure relates to methods and systems for synchronizing a receiver to decode communications transmitted using an optical communication system, such as synchronizing a receiver's clock to a received data input stream. Background Art

[0002] Optical or optical communication systems, in which light is modulated to encode data or information communicated between optical communication nodes, can be used for various applications, such as establishing ad hoc networks between peers; for example, in a vehicular application, such optical communication systems can be used for vehicular communications, as described in U.S. Pat. No. 11,245,469. However, such systems may involve or rely on external synchronization to synchronize the receiver with the transmitter so that the encoded data can be correctly decoded. Such external synchronization refers to a synchronization process in which the receiver is synchronized with the transmitter using communications other than (and distinct from) the optical communication system with the receiver to be synchronized. For example, external synchronization may involve notifying the receiver of the data or clock rate of the input stream to be transmitted by using a cellular network or dedicated short range communication (DSRC). It has been discovered that there is a need for a system and method for achieving internal synchronization of a self-organizing optical communication network, i.e., synchronization of a self-organizing optical communication network that does not rely on external communication (e.g., communication using DSRC or cellular communication) or on configuration being provided to the vehicle during manufacturing (e.g., by setting all clock rates of the optical communication nodes to be the same).

[0003] U.S. Patent No. 11,245,469 teaches a vehicle line-of-sight optical communication system for use in an ad hoc network formed with vehicles as they travel along a road. As discussed therein, vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) networks provide the ability to significantly reduce vehicle collisions by allowing vehicles to exchange information with other vehicles (e.g., "lane change," "emergency braking," "ice surface," etc.). Active and passive sensor-based vehicle object detection systems, which do not involve V2V and V2I communications, rely on the interpretation of signals to determine the behavior of nearby vehicles and other objects. Signals may be corrupted or interfered with, resulting in erroneous interpretations. Sensors may also fail, resulting in loss of functionality. V2V networks, on the other hand, rely on explicit information exchanged between vehicles in the form of data packets. If received correctly, these packets will provide clear information from nearby vehicles about the current state (e.g., position, speed, and direction) and intentions (e.g., lane change, emergency braking, right turn). This information can be fused with information from existing sensors (e.g., cameras, radars, lidars) to improve driving.

[0004] In real traffic scenarios (e.g., a major road with heavy traffic), the number of vehicles, the speed at which they move, and their changing positions and directions relative to each other make it extremely challenging to implement low-latency, reliable V2V and / or V2I networks.

[0005] V2V networks that rely on radio frequency (RF) communications, such as those using DSRC, are widely envisioned as a solution to this problem. However, these RF networks have inherent disadvantages due to the propagation characteristics of RF signals. RF signals tend to propagate in an omnidirectional and in-plane pattern. As a result, more vehicles than expected will receive RF signals transmitted from the host vehicle. Therefore, DSRC-based network architectures may require additional processing and hardware overhead to determine which vehicles form subnets, manage orthogonal channel allocations (e.g., time, frequency, decoding, and space) to these subnets, and then route packets between vehicles in the subnets. In addition, because the positions and orientations of vehicles relative to each other are constantly changing, these networks must be able to perform these tasks very quickly.

[0006] In some implementations, synchronization of the transmitter (e.g., one or more light sources) and the receiver can be performed using external communication (e.g., Wi-Fi TM 、Bluetooth TMNonetheless, as described above, it has been discovered that there is a need for a system and method for achieving internal synchronization of a self-organizing optical communication network, i.e., synchronization of a self-organizing optical communication network that does not rely on external communications (such as any of those DSRCs described above), or by constraining the system to predefined properties or parameters. Summary of the invention

[0007] According to one aspect of the present disclosure, a method for synchronizing a receiver with a transmitter to decode a data input stream sent by the transmitter and received at the receiver is provided. The method includes: receiving a data input stream at the receiver, the data input stream having a first data rate set based on a transmitter clock rate; generating a wave; obtaining a phase error between the data input stream and the generated wave; adjusting the frequency of the generated wave by using the phase error so that the frequency of the generated wave matches the transmitter clock rate of the data input stream, thereby determining a synchronization clock rate; and decoding the data input stream using the synchronization clock rate to obtain data encoded in the data input stream.

[0008] According to various embodiments, the method may further include any one of the following features or any technically feasible combination of some or all of these features:

[0009] - the method further comprises: inputting the phase error into a proportional integral (PI) controller, wherein the PI controller is connected to a wave generator for generating the generated wave;

[0010] - Wave generators include phase generators and direct digital synthesizers (DDS);

[0011] - the PI controller outputs a phase step which is input to a phase generator, wherein the phase generator is operatively connected to the DDS;

[0012] - The generated wave output by the DDS is mixed or multiplied with the data input stream to produce a phase error;

[0013] - The synchronous clock rate is determined based on a feedback process that modifies the frequency of the generated wave and / or

[0014] or phase, until the phase error is below a predetermined threshold, at which point the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match;

[0015] - recursively or iteratively performing the step of obtaining a phase error until the phase error between the data input stream and the generated wave is below a predetermined threshold, at which point the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match;

[0016] - the generated wave is a sine wave;

[0017] - the method is performed by an optical communication node having a receiving device configured to perform the method; and / or

[0018] - An initial frequency is used for initial generation, wherein the initial frequency is predetermined.

[0019] According to another aspect of the present disclosure, an optical communication receiver is provided. The optical communication receiver includes: a photodetector and a clock extraction module. The photodetector is used to receive a data input stream, and the clock extraction module has a phase generator, a direct digital synthesizer (DDS), and a proportional integral (PI) controller, the DDS is operatively connected to the output of the phase generator, and the output of the PI controller is operatively connected to the phase generator. The output of the DDS is used to obtain a phase error input to the PI controller. The clock extraction module is configured to perform a feedback process, which includes adjusting the frequency of the generated wave based on the obtained phase error until the phase error is below a predetermined threshold, at which point the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match. The optical communication receiver is configured to decode the data input stream using a synchronous clock rate determined based on the feedback process to obtain data.

[0020] According to various embodiments, the automatic topology determination system may further include any one of the following features or any technically feasible combination of some or all of these features:

[0021] - determining a synchronization clock rate based on the adjusted frequency of the generated wave when the transmitter clock rate of the data input stream and the frequency of the generated wave are deemed to match;

[0022] - a PI controller for generating a phase step as an output, the output being operatively connected to the phase generator, wherein the phase step is generated based on the phase error;

[0023] - Obtaining the phase error by mixing or multiplying the data input stream with the generated wave;

[0024] - Synchronous clock rate is intrinsically synchronized with the data input stream without the use of external communications;

[0025] - the clock extraction module is configured to provide a synchronous clock rate to the finite state machine; and / or

[0026] -The finite state machine is operatively connected to the processor to provide data to the processor.

[0027] BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Preferred exemplary embodiments will be described below with reference to the accompanying drawings, wherein like names refer to like elements, wherein:

[0029] Figure 1 An optical communication system according to one embodiment is described, comprising a transmitting device and a receiving device;

[0030] Figure 2 Described according to one embodiment Figure 1 A schematic diagram of exemplary components of a transmitter of a transmitting device;

[0031] Figure 3 An example of encoding bytes using an exemplary four-cycle encoding scheme according to one embodiment is described;

[0032] Figure 4 Described according to one embodiment Figure 1 A schematic diagram of exemplary components of a receiver of a receiving device;

[0033] Figure 5 Described according to one embodiment Figure 4 A schematic diagram of exemplary components of a clock extraction module of a receiver;

[0034] Figure 6 Described according to one embodiment Figure 5 A schematic diagram of exemplary components of a proportional-integral (PI) controller of a clock extraction module of FIG.

[0035] Figure 7 is a flow chart of a method of synchronizing a receiver with a transmitter to decode a data input stream transmitted by the transmitter and received at the receiver according to one embodiment;

[0036] Figure 8 is a flow chart of a method of synchronizing a receiver with a transmitter to decode a data input stream transmitted by the transmitter and received at the receiver according to one embodiment;

[0037] Fig. 9 is an example diagram of square wave input data generated according to one embodiment;

[0038] Fig.10 is an example diagram of a sine wave generated by a direct digital synthesizer (DDS) of a clock extraction module according to one embodiment;

[0039] Fig.11 According to one embodiment Fig. 9 and Fig.10 The product graph of two signals;

[0040] Fig.12 According to one embodiment, filtering is performed based on Fig.11 Filtered signal diagram of the signal;

[0041] Fig.13 is a phase step (ΔΦ) diagram of a PI controller according to one embodiment;

[0042] Fig.14 is a unit circle according to one embodiment, with values ​​around it shown and used by the DDS;

[0043] Fig.15 is a sawtooth function representing the phase of the generated signal according to one embodiment;

[0044] Fig.16 is a schematic diagram of a vehicle communication system according to one embodiment, the vehicle communication system including a host vehicle and other vehicles communicating using an optical communication system; and

[0045] Fig.17 According to one embodiment Fig.16 A description of a host vehicle comprising a plurality of optical communication modules. DETAILED DESCRIPTION

[0046] The systems and methods discussed herein can achieve synchronization of communication between two electronic devices using light or optical communication, and in particular, at least according to some embodiments, the systems and methods can achieve internal self-organizing synchronization of such communication. Each of such electronic devices with optical or optical communication capabilities (e.g., line-of-sight optical communication capabilities) is referred to as an optical communication node, and may include one or more transmitters for emitting light to send data to another node, and / or may include one or more receivers for receiving light to obtain data sent by another node. The "light" or "optical" communication discussed herein means not only visible light, but also light invisible to the human eye with a wavelength suitable for line-of-sight communication, including at least part of the infrared (IR), visible and ultraviolet (UV) spectrum. The transmitter uses light to encode or modulate data at or according to the transmitter clock rate, and sends the encoded data as a data input stream, which is then received at the receiver. At least in some embodiments, in order to correctly decode and / or interpret the data input stream to obtain data communicated by the transmitter, the receiver synchronizes a clock that matches the clock used by the transmitter to encode the data input stream. In this embodiment, the synchronized clock is then used to decode the data input stream in order to obtain the data.

[0047] According to at least some embodiments, a method for synchronizing a receiver with a transmitter to decode a data input stream sent by a transmitter and received at a receiver is provided. According to an embodiment, the method includes: receiving a data input stream at a receiver, the data input stream having a first data rate set based on a transmitter clock rate; generating a wave; obtaining a phase error between the data input stream and the generated wave; adjusting the frequency of the generated wave by using the phase error so that the phase and / or frequency of the generated wave matches the transmitter clock rate of the data input stream, thereby determining a synchronization clock rate; and decoding the data input stream using the synchronization clock rate to obtain data encoded in the data input stream.

[0048] According to some embodiments, an optical communication receiver is provided, comprising: a photodetector and a clock extraction module; the photodetector is used to receive a data input stream, the clock extraction module has a phase generator, a direct digital synthesizer (DDS) and a proportional integral (PI) controller, the DDS is operatively connected to the output of the phase generator, and the output of the PI controller is operatively connected to the phase generator. In this embodiment, the output of the DDS is used to obtain a phase error, which is input to the PI controller, and once the frequency of the generated wave matches the transmitter data rate of the data input stream, a synchronous clock rate is obtained. According to this embodiment, the clock extraction module is configured to perform a feedback process, which includes adjusting the frequency of the generated wave based on the obtained phase error until the phase error is below a predefined threshold, at which point the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match. At least according to this embodiment, the optical communication receiver is configured to decode the data input stream using the synchronous clock rate determined based on the feedback process.

[0049] refer to Figure 1 , an optical communication system 10 having a transmitting device 12 and a receiving device 14 is shown. The transmitting device 12 has a transmitter 16, which is used to communicate data with a receiver 18 of the receiving device 14. In one embodiment, the transmitting device 12 is a first vehicle (e.g., a first car) and the receiving device 14 is a second vehicle (e.g., a second car). The transmitter 16 can be composed of one or more light sources and transmitter circuits, and data is transmitted by modulating or encoding data using the emitted light, and this light emission with encoded data is called a data input stream. The data input stream is received at the receiver 18, and the receiver 18 can be composed of a receiver circuit having a photodetector 19, and in some embodiments, the receiver 18 can include certain components or circuits of the receiver circuit 78 or dedicated receiver circuit 78' described in U.S. Patent No. 11,245,469, which is incorporated herein by reference.

[0050] The transmitter 16 may include one or more light sources, such as one or more light emitting diodes (LEDs), and other transmitter circuits, such as an integrated driver circuit 76 and / or a dedicated driver circuit 76' as described in U.S. Pat. No. 11,245,469, which is incorporated herein by reference. According to at least some embodiments, in order to transmit a message, the light emitted by the transmitter 16 (e.g., light emitted by one or more LEDs) can be encoded or modulated (pulsed) by the transmitter circuit (or other transmitter control) using a transmit signal modulated according to the message to be transmitted. In this way, the light source (e.g., LED(s)) effectively optically conveys the message from the transmitter 16. Various encoding techniques can be used, such as time, frequency, or digital encoding; for example, frequency shift keying (FSK) is used to digitally transmit the message as binary data. The message can be sent in a data packet, using error checking, encryption, and other data messaging techniques as needed or desired for a particular application.

[0051] refer to Figure 2 , a transmitter 16 is shown, which includes a power supply 20, an electronic controller 22, and a light source 24, and the electronic controller 22 is shown as a field programmable gate array (FPGA). It should be understood that other types of processors or controllers can be used instead of or in addition to the FPGA of the electronic controller 22. The electronic controller 22 can obtain data transmitted in digital form, and the data can be encoded so that a clock signal (or transmitter clock rate) can be derived or extracted using the receiver 18. In one embodiment, four clock cycles or phases are used to transmit each bit, and this enables the clock signal to be consistently extracted by using the internal synchronization method described herein. For example, with reference to Figure 3 , shows an example of encoding binary data bytes 11000010 (as shown in 25a-h) using this four-cycle encoding scheme. In other embodiments, an N-cycle encoding scheme may be used, where N is a number different from four (4). At least according to some embodiments, since the data is encoded in a manner that only transmits the clock signal, this ensures that all pulses are in phase with each other, and there is no receiver 18 (specifically, the clock extraction module 30 of the receiver 18, as described above with respect to Figure 4 This is achieved by transmitting a clock signal and allocating four clock cycles to each bit. Figure 3 As shown, when a 0 bit is transmitted, a single clock cycle runs low.

[0052] Receiver 18 may be comprised of a receiver circuit that may include components and / or circuits of receiver circuit 78 and / or dedicated receiver circuit 78' described in U.S. Pat. No. 11,245,469, which is incorporated herein by reference. Figure 1 and Figure 4 , shows a receiver 18, which includes a photodetector 19 ( Figure 1 ), a clock extraction module 30, a finite-state machine (FSM) 32, a system clock 34, a processor 36, and a memory 37. The photodetector 19 may include one or more photodiodes (e.g., a pn photodiode, a pin photodiode, an avalanche photodiode) and / or other photodetector elements, such as a metal-semiconductor-metal (MSM) photodetector. The receiver 18 is also shown as having an analog-to-digital converter (ADC) 38, which can convert the data input stream from an analog form (indicated at 51) to a digital form (indicated at 52) ​​before the data is fed to the clock extraction module 30, as shown. Figure 4 shown.

[0053] refer to Figure 5 , the clock extraction module 30 shown includes a mixer / multiplier 42, a proportional-integral (PI) controller 44, a phase generator 46, and a direct digital synthesizer (DDS) 48. As shown at 52, the clock extraction module 30 takes a digital data input stream as input and provides a synchronous clock output (indicating a synchronous clock rate) 66 that is synchronized with the data input stream. In at least some embodiments, the purpose of the clock extraction module (or clock-data recovery (CDR) module) 30 is to extract the clock rate (transmitter clock rate) of the data input stream and replicate a clock with a matching frequency (synchronous clock rate) at the receiver 18. This enables the data input stream to be correctly decoded at the receiver by using the synchronous clock rate. As shown at Figure 5 As shown, the mixer / multiplier 42 is used to obtain the phase error, as shown at 54, which is then fed to the PI controller 44.

[0054] refer to Figure 6, the PI controller 44 is shown as taking the obtained phase error 54 and the adjusted clock (referred to as the "synchronous progress clock") as inputs, as shown at 56, and providing a phase step (ΔΦ) as shown at 60 (which is used as clock control feedback), which is used to control the frequency of the wave generated by the DDS 48. In at least some embodiments, the DDS 48 operates as a wave generator for generating a starting wave or fundamental wave at an initial frequency. The phase generator 46 is used to control the frequency of the DDS 48. The DDS 48 uses a 12-bit lookup table corresponding to values ​​around the unit circle. The phase generator 46 outputs a sawtooth function representing the phase of the generated signal. When the PI controller 44 corrects by increasing or decreasing the frequency, the phase step (ΔΦ) of the sawtooth function (as shown at 60) will increase / decrease to match. The phase generator 46 and the DDS 48 act as a wave generator for generating a wave (as shown at 62) that is fed as an input to the clock extraction module 30. As shown, the phase step 60 is determined by the PI controller 44 through feedback from the DDS 48 (as shown at 62), which allows correction until the phase and frequency (i.e., clock or data rate) of the data input stream and the generated wave match, and determines the extracted or synchronized clock rate (as shown at 66), thereby enabling decoding of the data input stream to obtain data. Figure 5 As shown, the phase generator 46 then uses the phase step 60 to generate a phase input 61 which is fed to the DDS 48 and used to generate the wave.

[0055] The PI controller 44 includes an accumulator 70 which takes as input the phase error 54 and the synchronous progress clock 56, and then outputs a phase step (ΔΦ) 60 which is used to adjust the generated wave. The accumulator 70 is used to provide an input to an integral gain component 72 of the PI controller 44, which is then used together with a proportional gain component 74 to provide the phase step (ΔΦ) 60.

[0056] refer to Figure 7 , an embodiment of a method 200 of synchronizing a receiver and a transmitter is shown to decode a data input stream transmitted by a transmitter and received at a receiver. According to at least some embodiments, the method 200 is performed by a receiver 18 of a receiving device 14, and as such, the method 200 may include using one or more components of the receiving device 14, as will be understood by those skilled in the art from the following discussion. It should also be understood that while steps 210-250 are discussed as being performed in a particular order, these steps may be performed in any suitable and technically feasible order.

[0057] The method 200 begins at step 210, where a data input stream is received at a receiver, the data input stream being transmitted at a first data rate set based on a transmitter clock rate. The term "transmitter clock rate" as used herein refers to a clock rate used by a transmitter as part of encoded data of a data input stream sent to a receiver. Also, as used herein, the term "data rate" refers to the rate at which data bits are provided over time, such as the rate at which data bits are transmitted by a transmitter. The data rate at which the data input stream is transmitted is assumed to be the same as the data rate at which the data input stream is received by the receiver because, at least according to some embodiments and implementations, such as when the method 200 is used for certain vehicle-to-everything (V2X) communications, such practical differences are negligible. The method 200 continues to step 220.

[0058] In step 220, a wave is generated, wherein the wave has an initial frequency. In at least some embodiments, the wave is a sine wave generated by the DDS 48. The initial frequency may be predetermined and may be stored in a memory, such as the memory 37 of the receiver 18. The wave may be generated by a wave generator, such as the DDS 48, which may be based on Figure 5 The phase input 61 in generates a wave. The phase input 61 can be generated by the phase generator 46. Figure 5 As shown, the clock extraction module 30 implements a feedback loop in which the frequency and / or phase of the generated wave is adjusted. The method 200 continues to step 230 .

[0059] In step 230, the phase error between the data input stream and the generated wave is obtained. Figure 5 As shown, in one embodiment, the mixer / multiplier 42 of the clock extraction module 30 is used to generate a phase error 54 based on the data input stream 52 and the generated wave 62. The sine wave of the generated wave 62 is multiplied by the data input stream, where the resulting product is similar to the trigonometric identity In this identity, the term cos(xy) represents the phase difference between the two signals. After removing cos(x+y) with a low pass filter, the resulting signal is used as the phase error 54.

[0060] exist Figure 9-12 In the example shown, square wave input data 400 ( Fig. 9 ) is transmitted at 10kHz, while the DDS sine wave 420 generates a 10.5kHz sine wave ( Fig.10 The product of these two signals is 440 ( Fig.11 ) is a signal composed of a 20.5kHz signal plus a 0.5kHz signal. After filtering the 20.5kHz signal, only the phase difference of 460 ( Fig.12The method 200 continues to step 240.

[0061] In step 240, the synchronization clock rate is determined by adjusting the frequency of the generated wave using the phase error so that the frequency of the generated wave matches the transmitter clock rate of the data input stream. The synchronization clock rate may also be referred to as an extracted clock rate because it is extracted from the data input stream. In at least some embodiments, the phase error is fed as an input into the PI controller 44, and the PI controller 44 controls the frequency of the sinusoid generated by the DDS 48, which means that as the phase error 54 approaches zero, the frequency of the sinusoid converges to the value of the received data input stream 52. For example, as Fig.13 As shown, the phase step (ΔΦ) 60 of the PI controller 44 is shown to converge over time as shown at 480. The phase generator 46 is used to control the frequency of the DDS 48. In the embodiment shown, the DDS 48 is a 12-bit lookup table that corresponds to values ​​around the unit circle 500, as shown in FIG. Fig.14 The phase generator 46 outputs a sawtooth function representing the phase of the generated signal, as shown in FIG. Fig.15 As the PI controller 44 makes corrections by increasing or decreasing the frequency, the phase step (ΔΦ) 60 of the sawtooth function will increase / decrease to match the transmitter clock rate. The method 200 continues to step 250 .

[0062] In step 250, the data input stream is decoded using the synchronous clock rate to obtain the data encoded in the data input stream. Since the transmitter clock rate of the data input stream is extracted to the synchronous clock rate, the data input stream can be interpreted by the receiver. For example, the receiver 18 can demodulate or otherwise decode the data using the synchronous clock rate, such as by dividing the data input stream into segments, each segment represented by four cycles, such as Figure 3 The method 200 ends.

[0063] refer to Figure 8 , an embodiment of a method 300 of synchronizing a receiver and a transmitter is shown to decode a data input stream transmitted by a transmitter and received at a receiver. According to at least some embodiments, the method 300 is performed by a receiver 18 of a receiving device 14. The method 300 may include using one or more components of the receiving device 14, as will be understood by those skilled in the art from the following discussion. In step 310, a data input stream is received, which step is similar to step 210 of method 200, and the discussion pertains to this step 310. The method 300 continues to step 320.

[0064] In step 320, the clock rate is extracted by a feedback clock rate matching process 322. In at least one embodiment, the feedback clock rate matching process includes steps 210-240 of the method 200 described above. In some embodiments, the feedback clock rate matching process includes tuning or adjusting the frequency of the generated wave (e.g., a sine wave) until the frequency matches the transmitter clock rate, which is the clock rate used to encode the data transmitted by the transmitter. In some embodiments, an encoding scheme is used in which each bit is represented by four cycles of the transmitter clock rate, which allows the transmitter clock rate to be extracted at the receiver by using the feedback clock rate matching process. The feedback clock rate matching process includes: multiplying / mixing the wave generated by the DDS 48 with the data input stream as described above, and then using the PI controller 44, the phase generator 46 and the DDS 48 to adjust the frequency of the generated wave until the frequency matches the transmitter clock rate. The method 300 continues to step 330.

[0065] In step 330, the data input stream is decoded using the extracted clock rate to obtain the data encoded in the data input stream. This step is similar to step 250 of method 200, and the discussion pertains to this step 330. Method 300 ends.

[0066] In some embodiments, the extracted / synchronized clock rate for a particular transmitting device may be stored in a memory of the receiving device 14, such as the memory 37 of the receiver 18, and used in communications with that particular transmitting device. For example, the device ID of the transmitting device may be transmitted using the data input stream, or generated by the receiving device 14, which may assign the generated device ID to each unique device detected. The generated ID may be stored in the memory 37 along with the extracted clock rate and used in communications with that device.

[0067] In at least some embodiments, method 200 and / or method 300 may implement self-organizing data communication synchronization such that for each data input stream sent and received at receiver 18, receiver 18 or receiving device 14 may determine a synchronization or extraction clock rate for that data input stream. Thus, in such embodiments, there is no need to store the synchronization or extraction clock rate, as it may be readily determined using steps 220-240 of method 200 or step 320 of method 300.

[0068] As will now be appreciated by those skilled in the art, the method 200, the method 300 and / or the optical communication system 10 may be adapted to extract a clock rate from a data input stream, such that the data input stream may be decoded to obtain data communicated between the transmitting device and the receiving device, for example, for the purpose of communicating information between the transmitting device 12 and the receiving device 14. Various specific vehicle applications will be apparent to those skilled in the art.

[0069] Fig.16 An example is provided for a vehicle application in which components and / or features of the above-described system 10 and methods 200 , 300 may be used. Specifically, Fig.16 A vehicle communication system 600 is described, which includes a first or host vehicle 610, a second vehicle 611, a third vehicle 612, a fourth vehicle 613, a fifth vehicle 614, a sixth vehicle 615, and a roadside equipment (RSE) 617. Each of the vehicles 610-616 and the RSE 617 can include one or more optical communication modules, which include a transmitting device and / or a receiving device, and can therefore be referred to as an optical communication node 612-617, and the optical communication nodes 612-617 communicate with each other in the self-organizing optical communication network 601. For example, each optical communication node 612-617 can include one or more transmitting devices and one or more receiving devices, such as for performing two-way communication with other optical communication nodes 612-617 in the self-organizing optical communication network 601. The one or more transmitting devices of the optical communication nodes 612-617 can each be a transmitting device characterized as the transmitting device 12 above. One or more receiving devices of optical communication nodes 612-617 may each be a transmitting device characterized above as receiving device 14. The discussion of a self-organizing line-of-sight optical communication network described in US Pat. No. 11,245,469 is incorporated herein by reference and pertains to vehicle communication system 600.

[0070] Fig.17 A host vehicle 610 is depicted, which is shown to include a vehicle electronics 611 having a left headlight communication module 621, a right headlight communication module 622, a left taillight communication module 623, a right taillight communication module 624, a center taillight communication module 625, a left mirror communication module 626, and a right mirror communication module 627. Each of these optical communication modules 621-627 includes a transmitting device and a receiving device for bidirectional optical communication and is integrated into an existing headlight or taillight of the host vehicle 610, such as described in U.S. Patent No. 11,245,469, which is incorporated herein by reference and is attributed to the host vehicle 610, to the extent that the discussion is inconsistent with the explicit discussion of the host vehicle 610 herein. Furthermore, it should be understood that in other embodiments, the transmitting devices and / or receiving devices of the optical communication modules 621-627 may be integrated into other components of the host vehicle 610 (rather than headlights or other external vehicle light / lamp modules), and / or may vary in configuration and quantity.

[0071] The transmitting device of each of the communication modules 621-627 can be the transmitting device characterized as the transmitting device 12 described above. The receiving device of each of the communication modules 621-627 can be the transmitting device characterized as the receiving device 14 described above. Each of the other optical communication nodes 612-617 can also have an optical communication module similar to the optical communication module 621-627 of the main vehicle 610, and these optical communication modules can be used to perform two-way communication in the self-organizing optical communication network 601. In at least some embodiments, the self-organizing optical communication network 601 is a line-of-sight self-organizing optical communication network, because the optical communication in such an embodiment is line-of-sight optical communication or optical communication. In order to synchronize the communication between the optical communication modules within the self-organizing optical communication network 601, each optical communication module discussed above can implement method 200 and / or method 300.

[0072] It should be understood that the foregoing description is directed to one or more embodiments of the present invention. The present invention is not limited to the specific embodiments disclosed herein, but is limited only by the following claims. In addition, the statements contained in the foregoing description relate to the disclosed embodiments and should not be interpreted as limitations on the scope of the present invention or the definitions of the terms used in the claims, unless a term or phrase is clearly defined above. Various other embodiments and various changes and modifications to the disclosed embodiments will become apparent to those skilled in the art.

[0073] As used in this specification and claims, the terms "for example," "for example," "for example," "such as," and "similar," and the verbs "to include," "to have," "to include," and their other verb forms, when used in conjunction with a list of one or more components or other items, are each to be interpreted as open-ended, meaning that the list is not to be construed as excluding other, additional components or items. Other terms are to be interpreted using their broadest reasonable meaning unless they are used in a context that requires a different interpretation. In addition, the term "and / or" should be interpreted as an inclusive or. Thus, for example, the phrase "A, B, and / or C" should be interpreted to include all of the following: "A"; "B"; "C"; "A and B"; "A and C"; "B and C"; and "A, B, C."

Claims

1. A method for synchronizing a receiver with a transmitter to decode a data input stream sent by the transmitter and received at the receiver, the method comprising: receiving, at a receiver, an input stream of data having a first data rate set based on a transmitter clock rate; Generate waves; obtaining a phase error between the data input stream and the generated wave; determining a synchronization clock rate by adjusting the frequency of a generated wave using the phase error to match the frequency of the generated wave with a transmitter clock rate of the data input stream; as well as The data input stream is decoded using the synchronous clock rate to obtain data encoded in the data input stream.

2. The method of claim 1, wherein: The method further comprises inputting the phase error into a proportional-integral (PI) controller, wherein the PI controller is connected to a wave generator for generating the generated wave.

3. The method according to claim 2, wherein: The wave generator includes a phase generator and a direct digital synthesizer DDS.

4. The method according to claim 3, wherein: The PI controller outputs a phase step which is input to a phase generator, and wherein the phase generator is operatively connected to the DDS.

5. The method according to claim 4, wherein: The generated wave output by the DDS is mixed or multiplied with the data input stream to produce a phase error.

6. The method of claim 1, wherein: The synchronization clock rate is determined based on a feedback process that modifies the frequency and / or phase of the generated wave until the phase error is below a predetermined threshold, at which point the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match.

7. The method according to claim 6, wherein: The step of obtaining the phase error is performed recursively or iteratively until the phase error between the data input stream and the generated wave is below a predetermined threshold, at which point the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match.

8. The method of claim 1, wherein The generated wave is a sine wave.

9. The method according to claim 1, wherein: The method is performed by an optical communication node having a receiving device configured to perform the method.

10. The method according to claim 1, wherein: An initial frequency is used to initially generate the wave, and wherein the initial frequency is predetermined.

11. An optical communication receiver, comprising: a photodetector for receiving a data input stream; as well as a clock extraction module having a phase generator, a direct digital synthesizer (DDS) and a proportional integral (PI) controller, wherein the DDS is operatively connected to an output of the phase generator, and an output of the PI controller is operatively connected to the phase generator, wherein the output of the DDS is used to obtain a phase error input to the PI controller; wherein the clock extraction module is configured to perform a feedback process, the feedback process comprising adjusting the frequency of the generated wave based on the obtained phase error until the phase error is below a predetermined threshold, at which point the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match; and The optical communication receiver is configured to decode the data input stream using a synchronous clock rate determined based on the feedback process to obtain data.

12. The optical communication receiver according to claim 11, wherein: The synchronization clock rate is determined based on the adjusted frequency of the generated wave when the transmitter clock rate of the data input stream and the frequency of the generated wave are deemed to match.

13. The optical communication receiver according to claim 11, wherein: The PI controller is for generating a phase step as an output, the output being operatively connected to the phase generator, and wherein the phase step is generated based on the phase error.

14. The optical communication receiver according to claim 11, wherein: The phase error is obtained by mixing or multiplying the data input stream with the generated wave.

15. The optical communication receiver according to claim 11, wherein: The synchronous clock rate is inherently synchronized with the data input stream without the use of external communications.

16. The optical communication receiver according to claim 11, wherein: The clock extraction module is configured to provide the synchronized clock rate to a finite state machine.

17. The optical communication receiver according to claim 15, wherein: The finite state machine is operatively connected to a processor to provide data to the processor.

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