Array column integrator

Abstract

The described embodiments may provide a chemical detection circuit with an improved signal-to-noise ratio. The chemical detection circuit may include a current source, a chemical detection pixel, an amplifier, and a capacitor. The chemical detection pixel may include a chemically sensitive transistor, which may have first and second line terminals and a row select switch coupled between the current source and the chemically sensitive transistor. The amplifier may have a first input and a second input, where the first input is connected to an output of the chemically sensitive transistor via a switch, and the second input is coupled to an offset voltage line. A capacitor may be coupled between an output of the amplifier and a first input of the amplifier. The capacitor and amplifier may form an integrator and may be shared by columns of chemical detection pixels.

Description

[0001] This application is a divisional application, the invention name of the parent case is “Array Column Integrator”, the application date is June 30, 2011, and the application number is 202111171347.9.

[0002] Related Applications

[0003] This application claims the benefit of priority to previously filed U.S. Provisional Patent Application Serial No. 61 / 360,493 filed on June 30, 2010, U.S. Provisional Application Serial No. 61 / 360,495 filed on July 1, 2010, U.S. Provisional Application Serial No. 61 / 361,403 filed on July 3, 2010, and U.S. Provisional Application Serial No. 61 / 365,327 filed on July 17, 2010. All of their disclosures are incorporated herein by reference in their entireties. Background Art

[0004] Electronic devices and components have found numerous applications in chemistry and biology (more generally, "life sciences"), particularly for detecting and measuring various chemical and biological reactions, and for identifying, detecting and measuring various chemical compounds. One such electronic device is known as an ion-sensitive field effect transistor, often denoted "ISFET" (or pHFET) in the relevant literature. ISFETs are conventionally employed primarily in the scientific and research communities to facilitate the measurement of the hydrogen ion concentration (commonly denoted "pH") of a solution.

[0005] More specifically, an ISFET is an impedance conversion device that operates in a manner similar to a metal oxide semiconductor field effect transistor (MOSFET) and is specifically constructed to selectively measure ion activity in solution (e.g., hydrogen ions in solution are the "analyte"). A detailed theory of operation of the ISFET is given in "Thirty years of ISFETOLOGY: what happened in the past 30years and what may happen in the next 30years," P. Bergveld, Sens. Actuators, 88 (2003), pp. 1-20 ("Bergveld"), which publication is incorporated herein by reference in its entirety.

[0006] Details of fabricating ISFETs using conventional complementary metal oxide semiconductor (CMOS) methods can be found in: Rothberg, et al., U.S. Patent Publication No. 2010 / 0301398, Rothberg, et al., U.S. Patent Publication No. 2010 / 0282617, and Rothberg et al., U.S. Patent Publication No. 2009 / 0026082; these patent publications are collectively referred to as "Rothberg" and are all incorporated herein by reference in their entirety. In addition to CMOS, bipolar and CMOS (biCMOS) processing can be used, such as methods including p-channel MOS FET arrays having bipolar structures on the periphery. Alternatively, other technologies can be used in which the sensitive element can be made with a three-terminal device in which the sensed ion results in the formation of a signal that controls one of the three wire terminals; such technologies can also include, for example, gallium arsenide (GaAs) and carbon nanotube technologies.

[0007] Taking CMOS as an example, P-type ISFET fabrication is based on a p-type silicon substrate in which an n-type hole forms the "body" of the transistor. Highly doped p-type (p+) source (S) and drain (D) regions are formed within the n-type hole. A highly doped n-type (n+) region B may also be formed within the n-type hole to provide a conductor (or "bulk") connection to the n-type hole. An oxide layer may be disposed over the source, drain, and body contact regions, through which openings are made to provide electrical connections (via electrical conductors) to these regions. Between the source and drain, at a location above the n-type hole region, a polysilicon gate may be formed over the oxide layer. Because it is disposed between the polysilicon gate and the body of the transistor (i.e., the n-type hole), the oxide layer is often referred to as the "gate oxide."

[0008] Similar to the MOSFET, the operation of the ISFET is based on the regulation of charge concentration (and thus channel conductance) caused by a metal oxide semiconductor (MOS) capacitor consisting of a polysilicon gate, a gate oxide, and a hole (e.g., an n-type hole) region between the source and drain. When a negative voltage is applied between the gate and source regions, a channel is established at the interface of this region and the gate oxide by depriving this region of electrons. In the case of an n-hole, the channel is a p-channel. In the case of an n-hole, the p-channel extends between the source and drain, and conducts current through the p-channel when the gate-source potential is negative enough to attract holes from the source into the channel. The gate-source potential at which the channel begins to conduct current is called the threshold voltage V of the transistor. TH (When V GS With a voltage greater than the threshold voltage V THThe transistor conducts when the absolute value of p is greater than 0.01. The source gets its name because it is the source of charge carriers flowing through the channel (holes for a p-channel); similarly, the drain is where the charge carriers leave the channel.

[0009] As described by Rothberg, an ISFET can be fabricated with a floating gate structure formed by coupling a polysilicon gate to multiple metal layers disposed within one or more additional oxide layers disposed on top of the gate oxide. The floating gate structure derives its name because it is electrically isolated from other ISFET-related conductors; that is, it is sandwiched between the gate oxide and a passivation layer disposed on top of the metal layer (e.g., a top metal layer) of the floating gate.

[0010] As further described by Rothberg, the ISFET passivation layer constitutes an ion-sensitive membrane that produces the ion sensitivity of the device. The presence of an analyte (such as an ion) in an analyte solution (i.e., a solution containing a target analyte (including an ion), or a solution in which the target analyte is tested for presence) in contact with the passivation layer (particularly a sensitive region that may be located above a floating gate structure) changes the electrical characteristics of the ISFET, thereby regulating the current flowing through the channel between the source and drain of the ISFET. The passivation layer may comprise any of a variety of different materials to promote sensitivity to specific ions; for example, a passivation layer comprising silicon nitride or silicon oxynitride and a metal oxide (such as an oxide of silicon, aluminum, or tantalum) will generally provide sensitivity to the concentration of hydrogen ions (pH) in the analyte solution, while a passivation layer comprising polyvinyl chloride (containing valinomycin) will provide sensitivity to the concentration of potassium ions in the analyte solution. Materials suitable for use in the passivation layer that are sensitive to other ions such as sodium, silver, iron, bromine, iodine, calcium, and nitrate are known, and the passivation layer may comprise a variety of materials (e.g., metal oxides, metal nitrides, and metal oxynitrides). With respect to chemical reactions at the analyte solution / passivation layer interface, the surface of a particular material for the passivation layer of an ISFET may include chemical groups that can donate protons to the analyte solution, or accept protons from the analyte solution, leaving negatively charged, positively charged, and neutral sites on the surface of the passivation layer at the analyte solution interface at any given time.

[0011] With respect to ion sensitivity, a potential difference, often referred to as a "surface potential," appears at the solid / liquid interface of the passivation layer and the analyte solution, which varies with the ion concentration in the sensitive region due to chemical reactions (e.g., dissociation of oxide surface groups by ions typically contained in the analyte solution near the sensitive region). This surface potential, in turn, affects the threshold voltage of the ISFET; thus, the threshold voltage of the ISFET varies with changes in the ion concentration in the analyte solution near the sensitive region. As described by Rothberg, since the threshold voltage V TH Sensitive to ion concentration, source voltage V S A signal is provided that is directly related to the concentration of ions in the analyte solution near the sensitive area of ​​the ISFET.

[0012] Arrays of chemically sensitive FETs ("chemFETs"), or more specifically ISFETs, can be used to monitor reactions, including, for example, nucleic acid (e.g., DNA) sequencing reactions, based on monitoring analytes present, produced, or used during the reaction. More generally, arrays, including large arrays of chemFETs, can be used to detect and measure static and / or dynamic quantities or concentrations of a variety of analytes (e.g., hydrogen ions, other ions, non-ionic molecules or compounds, etc.) in a variety of chemical and / or biological processes (e.g., biological or chemical reactions, cell or tissue culture or monitoring, neural activity, nucleic acid sequencing, etc.), where valuable information can be obtained based on such analyte measurements. Such chemFET arrays can be used in methods for detecting analytes and / or in methods for monitoring biological or chemical processes by changes in charge at the surface of a chemFET. Such uses of chemFET (or ISFET) arrays include: detecting analytes in solution, and / or detecting changes in charge bound to a chemFET surface (e.g., an ISFET passivation layer).

[0013] Research on the fabrication of ISFET arrays is described in the following publications: "A large transistor-based sensor array chip for direct extracellular imaging," MJ Milgrew, MORiehle, and DRS Cumming, Sensors and Actuators, B: Chemical, 111-112, (2005), pp. 347-353, and "The development of scalable sensor arrays using standard CMOS technology," MJ Milgrew, PA Hammond, and DRS Cumming, Sensors and Actuators, B: Chemical, 103, (2004), pp. 37-42, which are incorporated herein by reference and are collectively referred to as "Milgrew et al." in Rothberg, there is a description of the fabrication and use of ChemFET or ISFET arrays for chemical detection, including detection of ions associated with DNA sequencing. More specifically, Rothberg describes the use of a chemFET array (particularly an ISFET) to sequence nucleic acids, which includes: incorporating known nucleotides into a plurality of identical nucleic acids in a reaction chamber, the reaction chamber being in contact with or capacitively coupled to a chemFET, wherein the nucleic acids are bound to a single bead in the reaction chamber, and detecting a signal at the chemFET, wherein detection of the signal indicates the release of one or more hydrogen ions derived from the incorporation of the known nucleotide triphosphates into the synthesized nucleic acids.

[0014] However, conventionally, the ion concentration in the analyte solution is measured by measuring the instantaneous voltage at the output of the ISFET. In many cases, the signal-to-noise ratio provided by the instantaneous voltage may not be as high as desired. Furthermore, with the scaling of ISFET sensor array designs, more ISFET sensors are packed on a chip. Thus, there is a need in the art to provide better SNR than instantaneous voltage measurements, as well as on-chip data compression. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A 1T ion-sensitive pixel according to one embodiment of the present invention is explained.

[0016] Figure 2 A cross section of a 1T pixel according to an embodiment of the present invention is explained.

[0017] Figure 3 A schematic diagram of a pixel array with column readout switches according to one embodiment of the present invention is shown.

[0018] Figure 4 A source follower configuration of a IT pixel according to one embodiment of the present invention is shown.

[0019] Figure 5A A 1 T common source ion sensitive pixel according to one embodiment of the present invention is shown.

[0020] Figure 5B A pixel is shown in a common source readout configuration according to one embodiment of the present invention.

[0021] Figure 5C A common source equivalent circuit according to one embodiment of the present invention is shown.

[0022] Figure 6 A schematic diagram of a pixel array with column readout switches according to one embodiment of the present invention is shown.

[0023] Fig. 7A A cross section of a IT common source pixel according to one embodiment of the present invention is shown.

[0024] Figure 7B A cross section of a IT common source pixel according to one embodiment of the present invention is shown.

[0025] Figure 8 A common source pixel with a cascode row select arrangement according to one embodiment of the present invention is shown.

[0026] Fig. 9 A single-transistor pixel array with cascode column circuitry is shown in accordance with one embodiment of the present invention.

[0027] Fig. 10A and 10B A single transistor pixel array according to one embodiment of the present invention is shown.

[0028] Fig.11 A two-transistor (2T) pixel according to one embodiment of the present invention is shown.

[0029] Figures 12A to 12H A 2T pixel configuration according to an embodiment of the present invention is explained.

[0030] Figures 13A to 13D A common source 2T cell configuration according to an embodiment of the present invention is explained.

[0031] Fig.14AA 2T pixel array according to one embodiment of the present invention is shown.

[0032] Fig. 14B and 14C The layout of a 2X22T pixel array according to one embodiment of the present invention is shown.

[0033] Fig.15 A capacitive charge pump according to one embodiment of the present invention is shown.

[0034] Fig.16 A charge pump according to one embodiment of the present invention is shown.

[0035] Fig.17 A charge pump according to one embodiment of the present invention is shown.

[0036] Fig.18 A charge pump according to one embodiment of the present invention is shown.

[0037] Fig.19 A basic IS stacked pixel according to one embodiment of the present invention is shown.

[0038] Fig. 20 A surface potential diagram showing basic charge accumulation according to one embodiment of the present invention is shown.

[0039] Fig.21 and 22 An IS stacked pixel with 2 transistors according to one embodiment of the present invention is shown.

[0040] Fig.23 According to one embodiment of the present invention, Fig. 22 Surface potential map of a pixel.

[0041] Fig.24 An IS stacked pixel with 2 transistors and 4 electrodes is shown according to one embodiment of the present invention.

[0042] Fig.25 According to one embodiment of the present invention, Fig.24 Surface potential map of a pixel.

[0043] Fig.26 An IS stacked pixel with 1 transistor and 3 electrodes is shown according to one embodiment of the present invention.

[0044] Fig. 27 A three-transistor (3T) autopixel sensor according to one embodiment of the present invention is shown.

[0045] Fig.28 An alternative embodiment of a 3T auto-pixel sensor is shown.

[0046] Fig.29 A 3T auto-pixel sensor with a sample-and-hold circuit is shown according to one embodiment of the present invention.

[0047] Fig.30 A 3T auto-pixel sensor with associated dual sampling circuitry is shown in accordance with one embodiment of the present invention.

[0048] Fig.31 A 2.5T autopixel sensor array according to one embodiment of the present invention is shown.

[0049] Fig.32 A 1.75T autopixel sensor array according to one embodiment of the present invention is shown.

[0050] Fig.33 A block diagram of a chemical detection circuit according to one embodiment of the present invention is explained.

[0051] Fig.34 A block diagram of another chemical detection circuit according to another embodiment of the present invention is explained.

[0052] Fig.35 A block diagram of another chemical detection circuit according to another embodiment of the present invention is explained.

[0053] Fig.36 A method for generating a chemical detection circuit output according to one embodiment of the present invention is explained.

[0054] Fig.37 A block diagram of a chemical detection circuit according to one embodiment of the present invention is explained.

[0055] Fig.38A A block diagram illustrating components of a chemical detection circuit according to one embodiment of the present invention is illustrated.

[0056] Fig.38B The shift directions in different quadrant plates according to one embodiment of the present invention are explained.

[0057] Fig.39 A block diagram of a channel of a chemical detection circuit according to one embodiment of the present invention is explained.

[0058] Fig.40 A swizzle configuration of a signal line of a chemical detection circuit according to an embodiment of the present invention is explained.

[0059] Fig.41 A method of outputting data from a chemical detection circuit according to an embodiment of the present invention is explained.

[0060] Fig.42 The system architecture of a chemical detection according to one embodiment of the present invention is explained.

[0061] Fig.43 An analog readout board for a chemical detection circuit according to one embodiment of the present invention is explained.

[0062] Fig.44 A digital readout board for a chemical detection circuit according to one embodiment of the present invention is explained.

[0063] Fig.45 Block diagram illustrating the analog front end and noise calculation of a chemical detection circuit according to one embodiment of the present invention

[0064] Fig.46 A block diagram illustrating bandwidth utilization of a chemical detection circuit according to one embodiment of the present invention.

[0065] Fig.47 A block diagram of a clock distribution according to an embodiment of the present invention is explained.

[0066] Fig.48 A block diagram illustrating power distribution according to one embodiment of the present invention is explained.

[0067] Fig.49 A block diagram of a digital-to-analog conversion (DAC) of an analog readout board according to one embodiment of the present invention is illustrated.

[0068] Fig.50 A block diagram of a field programmable gate array (FPGA) configuration according to one embodiment of the present invention is explained.

[0069] Fig.51 A block diagram of FPGA power monitoring according to one embodiment of the present invention is explained.

[0070] Fig.52 A digital chemical detection circuit according to an embodiment of the present invention is explained.

[0071] Fig.53 An embodiment according to the present invention is explained. Fig.52 A more detailed block diagram of the digital chemical detection circuit.

[0072] Fig.54 A serializer circuit according to one embodiment of the present invention is explained.

[0073] Fig.55 According to one embodiment of the present invention, Fig.54 A more detailed block diagram of the serializer.

[0074] Fig.56 A block diagram of a digital chemical detection circuit according to an embodiment of the present invention is explained.

[0075] Fig.57 A block diagram of another digital chemical detection circuit according to an embodiment of the present invention is explained.

[0076] Fig.58 A block diagram of another digital chemical detection circuit according to an embodiment of the present invention is explained. DETAILED DESCRIPTION

[0077] Single transistor pixel array

[0078] A floating gate (FG) transistor can be used to detect ions in close proximity to a gate electrode. The transistor can be constructed with other transistors to form a pixel that can be placed into an addressable readout array. In the simplest form, an auxiliary transistor is used alone to separate and select the floating gate transistor for readout in an array. The floating gate transistor can be a chemically sensitive transistor, more specifically, a chemically sensitive field effect transistor (ChemFET). The ChemFET can be designed using a metal oxide semiconductor field effect transistor (MOSFET) containing self-aligned source and drain device implants manufactured using a standard complementary metal oxide semiconductor (CMOS) process. The ChemFET can be an ion sensitive FET (ISFET) and can be a PMOS or NMOS device.

[0079] A floating gate (FG) transistor can be used to detect ions in close proximity to a gate electrode. The transistor can be constructed with other transistors to form a pixel that can be placed into an addressable readout array. In the simplest form, an auxiliary transistor is used alone to separate and select the floating gate transistor for readout in an array. The floating gate transistor can be a chemically sensitive transistor, more specifically, a chemically sensitive field effect transistor (ChemFET). The ChemFET can be designed using a metal oxide semiconductor field effect transistor (MOSFET) containing self-aligned source and drain device implants manufactured using a standard complementary metal oxide semiconductor (CMOS) process. The ChemFET can be an ion sensitive FET (ISFET) and can be a PMOS or NMOS device.

[0080] To reduce the pixel size to the smallest size and simplest form of operation, the auxiliary transistor can be eliminated to form an ion-sensitive field effect transistor (ISFET) using a single transistor. This single-transistor (or 1T) pixel can provide gain as follows: the drain current is converted to a voltage in the column. The parasitic overlap capacitance between the line ends of the transistor will limit the gain. The capacitance ratio will also provide consistent pixel-to-pixel gain matching and relatively constant current operation, which justifies the use of row selection lines that can collect the necessary current without causing unacceptable variations. Its derivatives allow programmable gain to be added through cascode transistors implemented in the readout process. Buildable pixels can be established to achieve common source readout as well as source follower readout.

[0081] Figure 1 A 1T ion-sensitive pixel according to one embodiment of the present invention is explained. As shown, the pixel 100 can have one and only one transistor 101, one and only one row line R, and one and only one column line C. In this embodiment, the transistor 101 is shown as an n-channel MOSFET (NMOS) transistor in a p-type epitaxial substrate, which can be obtained using a standard CMOS process. It should be understood that NMOS is only used as an example of the present invention, and the transistor 101 can also be a PMOS. The choice of NMOS or PMOS as a preferred device depends on whether the device does not require a top-side bulk contact in a given process. Generally, when a P+ wafer with a P-epitaxial layer (called an epitaxial wafer) is used, NMOS is preferred because the P+ substrate below will bias the body on the pixel array without the need for bulk contacts at each pixel location. Therefore, the overall bulk contact is an attractive combination for use with a 1T pixel, where a small pixel pitch is required. The floating gate G of transistor 101 may contain trapped charge, which may be suitably released so that the electrode is at substantially the same potential as the substrate when all other line terminals are also biased at substrate potential. The row line R may be capacitively coupled to the drain D of transistor 101, and the column line may be coupled to the source S of transistor 101. A gate to the drain overlap capacitance Cgd may be formed between gate G and drain D. The pixel 100 may be addressed from the row line R, which supplies the column current (i.e., the drain-to-source current of transistor 101) and enhances the potential at the floating gate.

[0082] In single-transistor pixel arrays such as Figure 3 In the one shown), by strengthening the FG junction of a particular row, row selection can be facilitated. In one embodiment, the readout of the pixel is a winner-takes-all circuit, which will be described below.

[0083] Figure 2 A cross section of a 1T pixel according to one embodiment of the present invention is explained. By installing a drain D and a source S formed using an n-type implant in a p-type semiconductor, a transistor in a 1T pixel can be formed using an n-channel FET device. As shown, the transistor can have a floating gate G, a drain D, and a source S. The source S can be connected to a column line C, and the drain D can be connected to a row line R. A lightly doped drain (LDD) region can establish a gate to a drain overlap capacitance Cgd and / or a gate to a source overlap capacitance Cgs.

[0084] In one embodiment, the 1T ion pixel 100 can operate by directing the row select line R to the floating gate G, while at the same time providing a current source for the column line bias. In the simplest form, this directing can occur without adding any additional capacitors. The gate to the drain overlap capacitance Cgd (e.g. Figure 1 and 2 To increase the capacitive coupling, the row select metal lines can form additional metal capacitors to the floating metal electrodes, or more important source and drain extensions can be made with ion implantation.

[0085] Figure 3 Schematic diagram of a pixel array with column readout switches according to one embodiment of the present invention is shown. For illustrative purposes, four 1T pixels 301, 302, 303, and 304 of array 300 are shown, arranged in two rows and two columns, although array 300 can be extended to arrays of 1T pixels of any size. The 1T pixels can be connected to Figure 1The 1T pixel shown is similar. The drains of pixels 301 and 302 are connected to the row line R0, and the sources of pixels 301 and 302 are connected to the column lines C0 and C1, respectively. The drains of pixels 303 and 304 are connected to the row line R1, and the sources of pixels 303 and 304 are connected to the column lines C0 and C1, respectively. The pixel array can be loaded with a current source, but the simplest implementation uses only a single switch, which precharges the column line to a low potential, such as a substrate potential. The column readout switch 305 is connected to the column line C0, and the column readout switch 306 is connected to the column line C1. The column readout switch 305 includes a switch Sa, a switch Sb, a current source Isource, and a capacitor Cw. The switch Sa is used to precharge the column line and quickly initialize the column line between samples. The switch Sb is used to sample and retain the analog value read out on the column line. In some cases, if the pixel is converted to digital by an analog-to-digital converter and the pixel is kept under bias at the same time, the sampling capacitor and switch Sb are not required. The switch Sa is used to ground the column line C0. After the column line switch Sb is opened, the sample is held in the capacitor, and the final value on the column line (as the capacitor is sampled) will depend almost entirely on the active row, since the circuit operates according to a "winner takes all" mode (i.e., the resulting voltage represents the maximum voltage of the ISFETs connected to the readout circuit). The column readout circuit 306 operates similarly.

[0086] The operation of this pixel relies on the fact that the signal range of any given pixel is small compared to the supply voltage or readout range of the source follower. For example, the useful signal range may be only 100mV and the supply voltage may be 3.3V. When a row is selected, the R line is driven to an active high voltage VH, while all other row lines remain at an active low voltage VL. The voltage VL is selected to be approximately equal to the nominal voltage on the column line C during any given pixel readout. In this embodiment, because the signal range is small, it is known that this voltage is within 100mV. Therefore, the drain of the source voltage to all inactive pixels is always maintained at a small value. This is only critical if the gate of the source voltage to the inactive pixels is close to the device threshold. For a row driven to VH, the FG voltage of this row is significantly higher than other rows because the bootstrap occurs when the row line switches to VH. After the column line switch Sb is turned on, the final value on the column line will depend almost entirely on the active row because the circuit operates according to the winner-takes-all mode.

[0087] There are 2 current sources from other rows that can distort the signal value (one adds current, one takes away), and there must be enough guidance available to successfully read out the pixel without significant interaction from the other rows generating these sources. The analysis to determine how much guidance is needed is as follows. Before the time the pixel is sampled, the device has entered the subthreshold region of operation, which has a transconductance slope of, for example, about 100mV / decade. This means that for every 100mV change in gate voltage, the current changes by a factor of 10. In order to effectively read out a single pixel, a criterion is set so that 99% of the current on the column line can be attributed to the active row, and only 1% can be attributed to the inactive row (distortion current). From this it can be determined that multi-chamber guidance is necessary. With only 2 rows in the pixel array, a floating gate voltage difference of 200mV is required, based on the subthreshold slope. Since a signal range of about 100mV also needs to be compensated, the total requirement is about 300mV. If there are 10 rows, the contribution from the inactive rows can be 10 times more. Therefore, an additional 100mV is needed. If you increase the array to 100 rows, you need another 100mV. n As an example, 10000(10 4 ) A row pixel array only requires a total of 700mV (300+100*4) of conduction. This amount of conduction can be achieved from the overlap capacitance of the gate and drain. If more capacitance is needed, additional coupling can be facilitated in the mask design. The above analysis only applies to pixels that contribute to the readout current.

[0088] The pixel can also take current from the column line and sink it through the deactivated row line. Since the deactivated row line is set approximately at the column line level, this current take-off will be minimal, but it must still be quantified and controlled. To achieve this, the final current on the column line should be allowed to decrease beyond a certain level. This is ensured by loading the column with a small current sink such as luA. For a W / L (width to length) ratio of 1, a transistor biased at its threshold will have a saturation current of about 0.1uA. This current drops by a factor of 10 for every 100mV reduction in the gate to source voltage. If a current contribution of less than 1% is required, the VGS of the inactive pixels needs to be kept below the threshold voltage by 100+100*n mV, where 10 nis the number of pixels in the row. Thus, for a 10,000 row pixel array, VGS needs to remain 500mV below threshold. A typical 3.3V NMOS transistor has a VT of 600mV. Therefore, VGS should be less than 100mV for inactive pixels. Assuming that FG has a nominal voltage of 0V when the row (R) and column (C) lines are at 0V, this condition is met, even with R and C connected to FG. If FG has a nominal voltage greater than 0V (for example, due to trapped charge), more guidance is required to cause the column line to reach a level within 100mV of FG. As long as the nominal FG voltage is low enough, the second criterion for minimizing distortion current is not a limiting factor. Finally, sufficient guidance is required to produce a current on the column line that matches the outflow current so that the pixel can produce a measurable voltage on the column line. If VG is nominally 0v, 700mV is required for guidance. Therefore, for an NMOS with a VT as large as 600mV, the amount of bootstrap required is limited only by VT. To read out the pixel with margin, a good target for bootstrap is 1V. This leaves a 300mV range. Achieving 1V of bootstrap is practical within a 3.3V supply.

[0089] All current from the column readout is distributed over the row lines. If the column current is also significant, this can cause a significant drop in the row line voltage. The voltage drop affects the lead level, but is harmless to the source follower readout, since variations in the drain voltage have only secondary effects. Since the pixel is read out with multiple samples, the deviations are cancelled so that the drop does not affect the sensitivity of the pixel.

[0090] It should be noted that the same design can be used for source follower readout and common source readout, as long as neither readout is optimized. Only necessary adjustments are made in the column circuits. This results in a flexible readout architecture, and either readout method can be used depending on the required signal range. If the signal requires high gain, common source mode should be used. Otherwise, source follower mode can be used.

[0091] Figure 4 A source follower configuration of a 1T pixel according to an embodiment of the present invention is shown. The source follower mode has a buffered readout and operates in voltage mode and has a gain of less than 1. As shown, a single transistor 401 can be connected to an input voltage Vi (at its gate G) and to a fixed voltage (at its drain D). The source S of transistor 401 can be grounded via a current source Isource. The output voltage Vo can be taken from the source of transistor 401. A coupling capacitor Cc can exist between the input and gate of transistor 401, a parasitic capacitor Cgd can exist between the gate G and drain D of transistor 401, and a parasitic capacitor Cgs can exist between the gate and source S of transistor 401.

[0092] The following analysis is given regarding the gain of the source follower readout. Figure 4 , the gain (G) of the circuit can be defined as Vo / Vi. Using a reference pixel, the electrodes of the system can be swept to measure the gain so that Vo / Vi=G. Using the measured value of the parameter G (in this embodiment, it is 0.65), the ratio of Cc to Cgd can be determined. As will be discussed later, this ratio will determine the gain in common source mode. The input capacitance of the source follower is Ci=Cgd+Cgs(1-Asf), where Asf is the gain of the source follower. Due to the body effect, Asf is approximately 0.85. The capacitive voltage divider related to the input voltage on the FET is Cc / (Ci+Cc), and therefore Cc / (Ci+Cc)=G / Asf. Since Cgs is approximately 3-5 times greater than Cgd and Asf is approximately 0.85, Ci is approximately 2Cgd. Therefore, Cc=2Cgd(G / (Asf-G)). In this embodiment, the ratio of Cc to Cgd is approximately 6.5.

[0093] In one embodiment, the present invention obtains voltage gain by reading out with a common source configuration. It is desirable to achieve a reduction in pixel size and an increase in signal level. The present invention eliminates the auxiliary transistor in other pixel designs (e.g., 2T and 3T discussed below) and uses the source of the ISFET as a select line to achieve these two goals. The common source modes are gain mode and current mode.

[0094] Figure 5A A 1T common source ion sensitive pixel according to one embodiment of the present invention is shown. As shown, pixel 500 can have one and only one transistor 501, one and only one row line R, and one and only one column line C. In this embodiment, transistor 501 is shown as an n-channel MOSFET (NMOS) transistor in a p-type epitaxial substrate, which can be obtained using a standard CMOS process, although it can also be a p-channel MOSFET. NMOS devices are generally preferred for use with P+ epitaxial wafers, which do not require front-side bulk contacts. Technically, PMOS can be used with N+ epitaxial wafers, but this configuration is not produced in a standard CMOS process as is common. The row line R can be connected to the source S of transistor 501, and the column line can be connected to the drain D of transistor 501. Row selection is facilitated by switching to the path of the source voltage, and the readout of the pixel is through the drain.

[0095] exist Figure 6 6 shows a schematic diagram of a pixel array with column readout switches according to one embodiment of the present invention. The array 600 has four 1T common source pixels 601, 602, 603 and 604. The 1T pixel can be connected to Figure 5A1T pixel shown is similar. In this embodiment, the pixels are arranged in 2 rows and 2 columns. The drains of pixels 601 and 602 are connected to the column line C0, and the sources S of pixels 601 and 602 are connected to the row lines R0 and R1, respectively. The drains of pixels 603 and 604 are connected to the column line C1, and the sources S of pixels 603 and 604 are connected to the row lines R0 and R1, respectively. The column readout switch 605 is connected to the column line C0, and the column readout switch 606 is connected to the column line C1. The column readout switch 605 includes a switch Sa, a switch Sb, a resistor R and a capacitor Cw0. The column readout switch 606 includes a switch Sa, a switch Sb, a resistor R and a capacitor Cw1. The switch Sa can pull the voltage on the column line to a fixed voltage, for example, to a 3.3V supply. When the column line switch Sb is turned on, the final value on the column line will be determined by the active row because the switch Sb acts as a sample-and-hold circuit together with the capacitor Cw0.

[0096] The pixel array can be loaded with a current source or other load device such as a resistor with a finite output resistance. In general, the row select line will remain at an active high voltage VH. When a row is selected for readout, its row select line is pulled down to VL. The value of VL is set so that the nominal current level is about 1uA. If FG has a value 100mV higher than the rating, 10 times the current will be generated on the column line. If the value of FG is 100mV lower than the rating, the current will be 10 times lower. The settling time of the signal on the column line will be signal dependent. By selecting the R value, a voltage gain is achieved, and it is structurable to achieve programmable gain. For example, if R is 100k ohms, then 100mV is converted to 1V at the output.

[0097] The actual circuit is more complex than just a single common source amplifier because of the parasitic capacitance involved. Since the FG junction is not driven, but capacitively coupled to the output, there is a feedback mechanism that limits the gain. The limit is roughly equal to the ratio of the total capacitance at the FG junction to the gate to the drain capacitance. The ratio can be about 3. It can be designed to achieve higher gains such as 10 times with careful masking operations to reduce the source and drain extensions.

[0098] Fig. 7A A cross section of a 1T common source pixel according to one embodiment of the present invention is shown. By installing a drain D and a source S formed using an n-type implant in a p-type semiconductor, a transistor in a 1T pixel can be formed using an n-channel FET device. As shown, the transistor can have a floating gate G, a drain D, and a source S. The source S can be connected to a row line R, and the drain D can be connected to a column line C. A lightly doped drain (LDD) region can establish a gate to a source overlap capacitance Cgs and a gate to a drain overlap capacitance Cgd.

[0099] By skipping the LDD implant at the drain of the device, the overlap capacitance created by the LDD region can be reduced. Figure 7B A cross section of a IT common source pixel according to one embodiment of the present invention is shown. Figure 7B A drain device junction with a missing LDD region is shown. The missing region will reduce capacitance and increase gain. This can be achieved by masking over the LDD implant and can be implemented in standard CMOS processing.

[0100] exist Figure 5A In the 1T pixel shown, since the source current must be supplied from the row select line, current variations caused by signal variations will produce voltage variations. These variations can distort the measurement results. Therefore, the row select line should be low resistance and the driver of this line should also supply a stable source voltage independent of the current load. In the event that this is not possible, the current can be supplied from the column line and a second select transistor can be added to form a 2T pixel for common source readout, as described below. Fig. 10A As shown. Since the gain is limited by the parasitic overlap capacitance, it is foreseen that the best load to use is a current source implemented with a transistor with a high output resistance. In this case, a relatively constant current will be maintained in all devices because the gain is achieved by the capacitor ratio. This makes the 1T configuration feasible because the voltage variation at the source is minimal, even with a single row select line carrying all the current.

[0101] exist Figure 5B A pixel in a common source readout configuration is shown in FIG. The transistor forms an amplifier with a negative voltage gain. The negative voltage gain forms a natural feedback loop with a parasitic capacitor to control the gain. The open loop gain of the amplifier is A = gm(ro), where gm is the transconductance. For a given bias condition and process technology, the value A is typically greater than 100. Figure 5C As shown, the common source equivalent circuit has feedback capacitance Cgd, coupling capacitances Cc and Cgs.

[0102] Since A is large relative to the loop gain, the negative input line terminal can be considered a virtual ground junction, and the gain of the circuit can be determined to be Vo / Vi=-Cc / Cgd. Because this ratio is known from analysis or measurement of the source follower configuration, the gain can be determined to be approximately 6.5. However, compared to the source follower, the gain is Vo / Vi=2 / (Asf-G). In this embodiment, a gain of 10 is achieved over the source follower configuration. A lower bound on this gain is given by the following assumptions: the input capacitance of the source follower is attributed solely to Cgd, and Asf is equal to 1. In this case, the gain is approximately 3. Since neither of these conditions is realistic, it is expected that the gain will always exceed this value. Therefore, if the gain of the source follower configuration of a pixel is known, the gain of the common source configuration of the pixel is also known. In addition, the higher the gain, the more sensitive the pixel. This makes the common source configuration preferred.

[0103] Flicker noise can be reduced by using the same type of channel doping as the minority carrier. For example, an NMOS with an n-type implant creates a buried channel transistor. To shift the work function of the device, a P+ gate electrode can be used.

[0104] Single transistor pixel array with cascode column circuit

[0105] A derivative of the single-transistor pixel allows for the addition of programmable gain via a cascode transistor implemented during readout.

[0106] Since the gain of the common source readout is limited by the Cgd capacitance (e.g. Figure 5B As shown), reducing this capacitance can increase gain. Figure 8 A common source pixel with a common source and common gate row selection device is shown. As shown, transistor 801 can be added to the common source pixel, for example, in Figure 5B The circuit shown in . The gate of transistor 801 can be connected to voltage Vb and the source of transistor 801 can be connected to the drain of transistor 501. The output voltage Vo can be taken from the drain of transistor 801. The cascode effectively removes the Cgd capacitance from the feedback loop and replaces it with a much smaller Cds. Gains of the order of the loop gain are then achievable, which can exceed 100.

[0107] By bringing the cascode device outside the column line pixels, higher gain and variable gain can be generated in a IT configuration. Fig. 9A single transistor pixel array with a cascode column circuit is shown. This allows high gain and still allows the pixel pitch to be minimized, with only 1 transistor per pixel. The pixel array shown is a column with many single transistor pixels (e.g., 500) connected in series, and has a cascode arrangement at the base of the array. The cascode arrangement may include transistor 901. The gate of transistor 901 may be coupled to a bias voltage Vb, the source of transistor 901 may be coupled to the drain of transistor 501, and the drain of transistor 901 may be coupled to a fixed voltage via a current source. The output voltage Vo may be taken from the drain of transistor 901. It should be understood that the array may have many columns.

[0108] In this case, the cascode forces the drain of the pixel to remain at a fairly constant voltage over the input range. This causes the pixel to push almost all of the changes in current through the cascode at the base of the array and into the current load. This reduces the negative feedback from Cds, which would otherwise limit the gain. Given that the current load has infinite output resistance and there is effectively no coupling capacitor connected to the FG junction, the gain of the pixel is now -(gm1r01+I)gm2r02, where gm1 is the transconductance of the cascode at the base of the column line, and gm2 is the transconductance of the pixel, and r01 and r02 are the small signal output resistances seen at the drain. The value of the output resistance is determined by the channel length adjustment. Longer gate lengths generate higher output resistances because the effects of channel length adjustment are minimized. Because the gain is so large, the current source output resistance (which is at Fig. 9 Displayed as R adj ) can be limited and configured. This allows programmable gain at the column level while maintaining only 1 transistor pixel. The gain of the pixel is then set by -gm2RL, assuming the load resistor RL is much smaller than the output resistance of the cascode configuration, where R L YesR adj The gain is now configurable and programmable in the range of 1-100 or more. For example, if the bias current is about 5uA and the transconductance of the pixel is about 50uA / V, a load resistance of 20K ohms is required for a gain of 1. A gain of 10 is achieved with a 200K ohm load, and a gain of 100 is achieved with a 2M ohm load. There are many ways to achieve the effect of a cascode device at the column line. The main purpose of the cascode (shown as an NMOS transistor in Figure 901) is to keep the column line at a potential that is largely independent of the current level in the pixel. A differential amplifier with high gain can be applied to maintain this condition more accurately. This scheme is called a gate-cathode amplifier (cascoding) with enhanced gain.

[0109] Different design choices can be made to implement 1T and 2T transistors. To reduce the size of the pixel, the source and drain of adjacent pixels can be shared. In this way, a single row select line can activate 2 rows at a time. This reduces row wiring: for a given column pitch, 2 columns are read out at a time. Such a scheme is shown in Fig. 10A and 10B As shown, the pixel array 1000 includes transistors 1001, 1002, 1003, and 1004 in a column. The source of 1001 is connected to the row line R2, and the source of 1004 is connected to the row line R0. Transistors 1001 and 1002 can form a mirror image M1, and transistors 1003 and 1004 can form a mirror image M2. The drains of 1001 and 1002 are connected to the column line CA, and the drains of 1003 and 1004 are connected to the column line CB.

[0110] In one embodiment, a differential amplifier is used in feedback to enhance the gain of a cascode device to control a transistor that maintains a constant voltage on the column line.

[0111] Two-transistor pixel array

[0112] In a pixel array, row select devices can be used for selection and separation. When the row select line is activated, the row select device (MOSFET) forms a channel (due to the gate voltage exceeding the threshold voltage) and acts like a switch. When the row select is deactivated, the channel is reduced. It is important to note that the row select device is never truly fully "on" or "off". It only simulates a switch. When the gate is significantly lower than the source of the row select transistor, good separation is achieved and pixels with active row select can be effectively read out without the need for input from deactivated pixels. Due to the many rows in the pixel array, a given level of separation must be achieved for each row select device. That is, the requirements of the row select device depend on the number of rows.

[0113] Fig.11 A two-transistor (2T) pixel according to one embodiment of the present invention is shown. As shown, the 2T pixel 1100 includes an ISFET 1101 and a row selection device 1102. In the pixel 1100, the source of the ISFET 1101 is connected to the column line Cb, the drain of the row selection device 1102 is connected to the column line Ct, and the drain of the ISFET 1101 is connected to the source of the row selection device 1102. The gate of the row selection device 1102 is connected to the row line R.

[0114] ISFET 1101 and row select device 1102 are both shown as NMOS, but other types of transistors may be used. 2T pixel 1100 is constructed in source follower readout mode, although 2T pixels can be constructed in common source readout mode.

[0115] Figures 12A to 12HMore 2T pixel configurations according to embodiments of the present invention are explained. In these figures, "BE" stands for "with body effect", i.e., the ISFET is body-implemented because the body line terminal is connected to the analog supply voltage or the analog ground voltage (depending on whether the ISFET transistor type is p-channel or n-channel MOS). If the body line terminal is connected to the source line terminal of the transistor, the body effect is eliminated. "PR" stands for "PMOS device in reverse position", i.e., the position of the p-channel ISFET and the row selection device in the pixel circuit topology has been reversed (or turned around). "PNR" stands for "PMOS / NMOS device in reverse position", i.e., the position of the p-channel ISFET and the n-channel row selection device in the pixel circuit topology has been reversed (or turned around).

[0116] Fig. 12A A 2T pixel according to an embodiment of the present invention is explained. As shown in the figure, the ISFET and the row selection device SEL are both p-channel MOS transistors, and the source line terminal of the ISFET is connected to the drain line terminal of the row selection device. The drain line terminal of the ISFET is connected to an analog ground voltage, and the source line terminal of the row selection device is connected to a current source, which provides a bias current to the pixel. The output voltage V is read from the source line terminal of the row selection device. out .

[0117] Fig. 12B A 2T pixel according to an embodiment of the present invention is explained. As shown in the figure, the ISFET and the row selection device SEL are both p-channel MOS transistors, wherein the source line terminal of the ISFET is connected to the body line terminal to eliminate the body effect, and is connected to the drain line terminal of the row selection device. The drain line terminal of the ISFET is connected to an analog ground voltage, and the source line terminal of the row selection device is connected to a current source, which provides a bias current to the pixel. The output voltage V is read from the source line terminal of the row selection device out .

[0118] Fig. 12C A 2T pixel according to one embodiment of the present invention is explained. As shown in the figure, the ISFET and the row selection device SEL are both p-channel MOS transistors, wherein the drain line terminal of the ISFET is connected to the source line terminal of the row selection device. The drain line terminal of the row selection device is connected to an analog ground voltage, and the source line terminal of the ISFET is connected to a current source. The output voltage V is read from the source line terminal of the ISFET out .

[0119] Fig.12DA 2T pixel according to one embodiment of the present invention is explained. As shown in the figure, the ISFET and the row selection device SEL are both p-channel MOS transistors, wherein the drain line terminal of the ISFET is connected to the source line terminal of the row selection device. The drain line terminal of the row selection device is connected to an analog ground voltage, and the source line terminal of the ISFET is connected to a current source, which provides a bias current to the pixel. The output voltage V is read from the source line terminal of the ISFET out The source line terminal of the ISFET is connected to the body line terminal to eliminate the body effect.

[0120] Fig.12E A 2T pixel according to one embodiment of the present invention is explained. As shown in the figure, the ISFET and the row selector SEL are p-channel and n-channel MOS transistors, respectively, with their source terminals connected together. The drain terminal of the ISFET is connected to an analog ground voltage, and the drain of the row selector is connected to a current source, which provides a bias current to the pixel. The output voltage V is read from the drain terminal of the row selector out .

[0121] Fig.12F A 2T pixel according to one embodiment of the present invention is explained. As shown in the figure, the ISFET and the row selector SEL are p-channel and n-channel MOS transistors, respectively, with their source terminals connected together. The drain terminal of the ISFET is connected to an analog ground voltage, and the drain of the row selector is connected to a current source, which provides a bias current to the pixel. The output voltage V is read from the drain terminal of the row selector out The source line terminal of the ISFET is connected to the body line terminal to eliminate the body effect.

[0122] Figure 12G A 2T pixel according to one embodiment of the present invention is explained. As shown in the figure, the ISFET and the row selection device SEL are p-channel and n-channel MOS transistors, respectively, wherein their drain line terminals are connected together. The source line terminal of the row selection device is connected to an analog ground voltage, and the source line terminal of the ISFET is connected to a current source, which provides a bias current to the pixel. The output voltage V is read from the source line terminal of the ISFET out .

[0123] Fig.12H A 2T pixel according to one embodiment of the present invention is explained. As shown in the figure, the ISFET and the row selection device SEL are p-channel and n-channel MOS transistors, respectively, wherein their drain line terminals are connected together. The source line terminal of the row selection device is connected to an analog ground voltage, and the source line terminal of the ISFET is connected to a current source, which provides a bias current to the pixel. The output voltage V is read from the source line terminal of the ISFET outThe source line terminal of the ISFET is connected to the body line terminal to eliminate the body effect.

[0124] Figures 13A to 13D The common source 2T cell configuration according to an embodiment of the present invention is explained. Fig.13A and 13B In the example, the ISFET and the row select device are both n-channel MOS transistors, and in Fig. 13C and 13D In the embodiment, the ISFET and the row select device are both p-channel MOS transistors.

[0125] exist Fig.13A In the embodiment, the source terminal of the ISFET is connected to the analog ground supply, and the drain terminal of the row selection device is connected to a current source, which provides a bias current to the pixel. The source terminal of the row selection device and the drain terminal of the ISFET are connected together. The output voltage V is read from the drain terminal of the row selection device out .

[0126] exist Fig. 13B In the embodiment, the source terminal of the row selection device is connected to the analog ground supply, and the drain terminal of the ISFET is connected to a current source, which provides a bias current to the pixel. The drain terminal of the row selection device and the source terminal of the ISFET are connected together. The output voltage V is read from the drain terminal of the ISFET out .

[0127] exist Fig. 13C In the embodiment, the source line terminal of the ISFET is connected to the analog supply voltage, and the drain line terminal of the row selection device is connected to a current source, which provides a bias current to the pixel. The source line terminal of the row selection device and the drain line terminal of the ISFET are connected together. The output voltage V is read from the drain line terminal of the row selection device out .

[0128] exist Fig.13D In the embodiment, the source line terminal of the row selection device is connected to the analog supply voltage, and the drain line terminal of the ISFET is connected to the current source, which provides a bias current to the pixel. The drain line terminal of the ISFET is connected together. The output voltage V is read from the drain line terminal of the ISFET out .

[0129] Fig.14AA 2T pixel array according to one embodiment of the present invention is shown. For illustrative purposes, eight 2T pixels are shown arranged in two columns, although the 2T pixel array 1400 can be extended to 2T pixel arrays of any size. Each column spacing contains three column lines cb[0], ct[0], and cb[1]. Row lines rs[0], rs[1], rs[2], and rs[3] are connected in parallel to all columns. The row selection device 1401RS and the ISFET 1401IS can form a 2T pixel, where the source of 1401 is connected to the drain of 1401RS. The source of 1401RS is connected to the column line cb[0], and the drain of 1401IS is connected to the column line ct[0]. The gate of 1401RS is connected to the row line rs[0]. The pixel is mapped in a pixel including 1402IS and 1402RS, wherein the drains of 1401IS and 1402 are connected to the column line ct[0], and the gate of 1402RS is connected to the row line rs[1]. The pixel including 1402IS and 1402RS is mapped in a pixel including 1403IS and 1403RS, wherein the sources of 1402RS and 1403RS are connected to the row line cb[1], and the gate of 1403RS is connected to the row line rs[2]. The pixel including 1403IS and 1403RS is mapped in a pixel including 1404IS and 1404RS, wherein the drains of 1403IS and 1404 are connected to the row line ct[0], and the gate of 1404RS is connected to the row line rs[3], and the source of 1404RS is connected to the column line cb[0]. In the embodiment shown in FIG. 14 , each IS device is an ISFET and each RS device is a row select device.

[0130] The right column (including: pixels composed of 1405RS and 1405IS, pixels composed of 1406RS and 1406IS, pixels composed of 1407RS and 1407IS, and pixels composed of 1408RS and 1408IS) is connected to column lines cb[2], ct[1] and cb[3] in basically the same manner as described above.

[0131] Fig. 14B and 14C The design of a 2X22T pixel array according to one embodiment of the present invention is shown. The 2X22T pixel array can be a part of the pixel array 1400. Fig. 14BIt is shown that the polysilicon gates of 1401RS, 1401IS, 1402RS and 1402IS can be placed on the continuous diffusion layer 1410, and the polysilicon gates of 1405RS, 1405IS, 1406RS and 1406IS can be placed on the continuous diffusion layer 1412. In one embodiment, the continuous diffusion layers 1410 and 1412 can be connected from the top of the pixel array to the bottom of the pixel array. In other words, the diffusion layer can have no interruption in the pixel array.

[0132] Fig. 14C The microwells of ISFETs 1401IS, 1402IS, 1405IS, and 1406IS are shown where they can be placed. The microwells can be used to hold an analyte solution to be analyzed by the ISFETs. Fig. 14C As shown, in one embodiment, the microwells can each have a hexagonal shape and be stacked like a honeycomb. In addition, in one embodiment, the contacts can be placed directly on top of the gate structure. That is, the ISFET can have contacts placed on the polysilicon gate on top of the thin oxide.

[0133] Pixel array 1400 has high density because of continuous diffusion, shared contacts, mirrored pixels, and 1 ct (column top) line and 2 cb (column bottom) lines per physical column. Global contacts can be achieved by using a P+ wafer with P- epitaxial regions.

[0134] The arrangement of pixel array 1400 provides high speed operation. Row lines RS[0] and RS[1] are selected together and read out through CB[0] and CB[1]. This results in a 4 times faster readout due to doubling the number of pixels that can be read out individually and halving the parasitic load of the continuous array, allowing each column to settle 2 times faster. In one embodiment, the entire array is divided into a top half and a bottom half. Due to doubling the number of pixels read out at one time (at the top and bottom) and halving the parasitic load of the continuous array, this results in an additional 4 times faster readout time. Thus, the total increase in speed compared to a continuous array with a single row selection is 16 times.

[0135] In one embodiment, during the readout process, the top half and bottom half of the pixel array can be activated simultaneously. This can allow multiplexing of the readout between the top half and the bottom half. For example, one half can be "washed" (e.g., reactants are flushed out of the hole above the pixel device) and the other half can be read out. Once the other half is read out, the readout of the two halves is switched.

[0136] In one embodiment, a 2T pixel design may include two chemically sensitive transistors (e.g., ISFETs) instead of one. Figure 11-14 and a row selection device. The chemically sensitive transistor or ISFET can be an NMOS or PMOS device and constructed in source follower or common source readout mode. A possible use of such a 2T pixel can be a situation where the first chemically sensitive transistor has a different sensitivity to a specific analyte than the second chemically sensitive transistor, thereby allowing local and in-pixel differentiated measurements to be made. Alternatively, the two chemically sensitive transistors can have the same sensitivity to a specific analyte, thereby allowing local and in-pixel averaged measurements to be made. These are 2 examples of potential applications of this embodiment, and based on the description herein, a person of ordinary skill in the art will recognize other uses for a 2T pixel design comprising two chemically sensitive transistors (e.g., ISFETs).

[0137] In one embodiment, the column circuits allow the column lines to be swapped for sampling circuits so that source-side or drain-side row selections can be made in source-follower mode or common-source mode.

[0138] Capacitive Charge Pump

[0139] One or more charge pumps may be used to amplify the output voltage from a chemically-sensitive pixel comprising one or more transistors, such as those described above.

[0140] One or more charge pumps may be used to amplify the output voltage from a chemically-sensitive pixel comprising one or more transistors, such as those described above.

[0141] Fig.15 A capacitive charge pump with a voltage gain of 2 is shown according to one embodiment of the present invention. The charge pump 1500 may include Switches 1501, 1502, 1503 and 1504, Switches 1505 and 1506 and capacitors 1507 and 1508. Vref1 and Vref2 are set to obtain the desired DC deviation of the output signal, both selected to avoid output saturation during the boost phase. The operation of the charge pump can be controlled by a timing signal, which can be provided by a timing circuit.

[0142] At time t0, all switches are closed.

[0143] At time t1, Switches 1501, 1502, 1503 and 1504 are turned on. The tracking phase can start. The input voltage Vin (which can come from the ion-sensitive pixel) can start charging capacitors 1507 and 1508.

[0144] At time t2, Switches 1501 , 1502 , 1503 , and 1504 are closed, and capacitors 1507 and 1508 are charged to Vin-Vref1 .

[0145] At time t3, Switches 1505 and 1506 are turned on, and Switches 1501, 1502, 1503, and 1504 remain closed. The enhancement phase can start. Capacitor 1507 can start to discharge through capacitor 1508. Since the capacitors are in parallel in the tracking phase and in series in the enhancement phase, and the total capacitance is halved in the enhancement phase while the total charge remains fixed, the voltage across the total capacitance must double, making V out It is about twice that of Vin.

[0146] A source follower SF may be used to decouple the gain circuit from the stages described below.

[0147] The charge pump 1500 can provide a gain of 2 and does not require a noise amplifier to provide a virtual ground.

[0148] Fig.16 A charge pump according to one embodiment of the present invention is shown.

[0149] At time t0, all switches are closed.

[0150] At time t1, Switches 1501, 1502, 1503, 1504, 1601 and 1602 are turned on.

[0151] The tracking phase may start. The input voltage Vin (which may come from an ion-sensitive pixel) may start charging capacitors 1507 , 1508 , and 1604 .

[0152] At time t2, Switches 1501 , 1502 , 1503 , 1504 , 1601 , and 1602 are closed, and capacitors 1507 , 1508 , and 1604 are charged to Vin-Vref1 .

[0153] At time t3, Switches 1505 and 1603 are turned on, and at the same time Switches 1501, 1502, 1503, 1504, 1601 and 1602 remain closed. The enhancement phase can be initiated. Capacitor 1507 can be initiated to discharge through capacitors 1508 and 1604, and capacitor 1508 can be initiated to discharge through capacitor 1604. Since the capacitors are in parallel in the tracking phase and in series in the enhancement phase, and the total capacitance is divided by 3 in the enhancement phase while the total charge remains fixed, the voltage on the total capacitance must be 3 times, making Vout It is about 3 times that of Vin.

[0154] Fig.17 An embodiment of a charge pump according to an embodiment of the present invention is shown. Fig.15 The two charge pumps 1500 are connected in series, thereby achieving gain pipelining and amplifying the input voltage Vin by 4 times.

[0155] Additional series charge pumps may be added to further increase the gain. In a multi-stage charge pump, the capacitor values ​​do not have to be the same size between stages. It can be observed that the total area occupied by the capacitors increases with the square of the gain. Although in some cases this feature may be undesirable in terms of area usage, power consumption, and throughput, when the total noise generated by the ion-sensitive pixels and the associated fluid noise is greater than the charge pump KT / C noise with reasonable capacitor sizes, a charge pump can be used without these penalties.

[0156] Fig.18 An embodiment of a charge pump according to an embodiment of the present invention is shown. The source follower SFP and the switch The feedback path is added to the charge pump 1500, thereby increasing the output V out Returns the input of the charge pump.

[0157] At time t0, all switches are closed.

[0158] At time t1 , switch cpsp is turned on, thereby providing input voltage Vin to the input of charge pump 1500 .

[0159] From time t2 to time t5, the charge pump 1500 operates to drive the output voltage V out To 2 (Vin-Vref1), as mentioned above Fig.15 described.

[0160] From time t6 to t7, the switch turns on, returning the output voltage 2 (Vin-Vref1) to the input of the charge pump 1500, and the first cycle ends.

[0161] During the second cycle, the charge pump 1500 amplifies the output voltage by 2 (2(Vin-Vref1)). The process repeats, amplifying the output during each cycle.

[0162] CCD-based multi-transistor automatic pixel sensor array

[0163] Ion-sensitive MOS electrodes are charge coupled to adjacent electrodes to facilitate carrier confinement and separation. Ion concentration is measured by discrete charge packets generated at each pixel and confined by potential barriers and wells. Ion-sensitive electrodes can act as barrier levels or potential wells. Working in the charge domain provides several benefits, including, but not limited to: 1) increased signal levels and improved signal-to-noise ratios through the accumulation of multiple charge packets within each pixel, 2) better threshold matching of MOS sensing and reference structures, 3) flicker noise reduction, and 4) total fast-shooting operation.

[0164] A floating electrode is used to detect ions in the immediate vicinity of the electrode. The electrode is charge coupled with other electrodes and other transistors to form a pixel that can be placed into an addressable readout array. Gain may be obtained by accumulating charge in another electrode or on a floating diffusion (FD) junction or directly on a column line. It is desirable to achieve a reduction in pixel size and an increase in signal level. To reduce pixel size, auxiliary transistors may be eliminated and charge storage junctions with a specific activation and deactivation sequence may be used.

[0165] Ion-sensitive (IS) stacking pixels incorporate some of the following concepts:

[0166] 1. The electrode is charge coupled to the IS electrode;

[0167] 2. The source of the carrier of the charge packet (electrons or holes);

[0168] 3. The reference electrode acts as a barrier or sink for the charge packets;

[0169] 4. Floating diffusion junction for charge-to-voltage conversion;

[0170] 5. Auxiliary transistors for providing buffering and separation of addressable readout; and

[0171] 6. Eliminate the sequence of some or all auxiliary transistors depending on the application.

[0172] The basic IS stacked pixels are displayed in Fig.19 Charge accumulation can occur locally during readout or globally during a single integration time. Fig.19The embodiment in is a three-transistor three-electrode (3T3E) pixel. The three transistors include a reset transistor RT, a source follower 1901, and a row select transistor RS, and the three electrodes include an electrode VS, an electrode VR, and an ion-sensitive electrode 1902. The pixel also includes a transfer gate TX. It is also possible to construct an IS stacking pixel in which additional elements are used to achieve simultaneous stacking and readout. This can be achieved as follows: for example, by adding another 2 electrodes to pipeline the process. In this basic configuration, charge is accumulated on a floating diffusion junction, which is connected to the source of the reset (RT) control gate. In rolling shutter operation, the floating diffusion (FD) is reset to CD=VDD. The row is then selected and read out by a source follower implemented by row select (RS). Next, charge is accumulated on the FD junction, which releases the parasitic capacitor. A second sample is then taken. The difference between the samples represents the ion concentration. The samples are correlated and collected relatively quickly in time. Therefore, thermal noise of the readout circuit is eliminated and 1 / f noise is reduced. To operate in total switch mode, all FD junctions are reset to VDD at the same time. Then, charge is accumulated on each separate FD junction. After accumulation, each row is selected by activating the RS gate. The signal value is read out on the column line with a load on the source follower. Next, the pixel is reset and sampled again. The difference between the samples represents the ion concentration. By double sampling, 1 / f noise is reduced. However, thermal reset noise is not eliminated because the reset values ​​are not correlated in time. Thermal noise can be reduced as follows: the power is halved by following the reset operation with a subthreshold reset before sampling. In general, thermal noise is lower than the signal generated by charge accumulation. Reset schemes associated with total switches are available in other configurations.

[0173] The basic charge accumulation scheme using the surface potential map is shown in Fig. 20 Only the electrodes are shown, since the transistor is only used for readout. In each of these sequences, the increasing potential points downward, as is the convention for showing a potential well containing electrons. Fig. 20 Four cycles of charge accumulation are shown in AQ. First, all charge is taken from the channel under the IS electrode and the channel is completely emptied using a high potential on the FD (A). Next, the TX gate is switched to a low potential, which creates a confinement barrier (B). A fill and overflow operation is used to generate a charge packet proportional to the ion concentration at the IS electrode (CD). In the next cycle, this charge packet is transferred to the FD junction, which is released by the electrons. The simplified diagram shows the electron accumulation at the FD junction, but the voltage actually decreases. After many cycles, as shown in Figure 2, the charge packet is transferred to the FD junction, which is released by the electrons. Fig. 20 As shown by the EQ, the signal-to-noise ratio is improved and the signal can be read out with gain. Hundreds to millions of cycles can be used to amplify the signal.

[0174] In alternative embodiments, the order of the electrodes can be switched, and / or the IS electrodes can be used as barriers instead of wells. Transistors can be added to the stacked lines to achieve large pixel arrays. Auxiliary transistors are used to increase speed. However, it should be noted that no transistors are required to achieve a complete pixel array of the stacked lines. Instead, the array can be allocated so that no transistors are required. In one embodiment, the FD junction is connected to the column line. Before reading out the pixel, the column line is reset to VDD. Then, the row is selected as follows: the charge of the row is directly stacked on the column line. After many cycles, the column is released to a value directly proportional to the ion concentration. Since the capacitance of the column line depends on the total number of rows, the amount of stacking required depends on the number of rows. The array can be divided into sub-arrays to make the timing scalable. For example, every 100 rows can contain a local source follower buffer, which is connected to the total array. This layered scheme can generally be used with all readout schemes to quickly read out large pixel arrays.

[0175] Due to the thermal activity of the carriers, charge packets cannot be generated without noise. Each fill and overflow operation generates a charge error proportional to KTC (thermal noise in the floating diffusion capacitor), where C = Cox × area of ​​the ion sensitive electrode. During the fill operation, charge can flow freely between the electron source and the confinement well. However, during the overflow operation, the device enters subthreshold mode and the carriers move by diffusion (mostly in one direction only), which causes the thermal noise resisting the channel to be halved. The total noise in the electrons of each charge packet is therefore sqrt(KTC / 2) / q, where q represents the charge of 1 electron in coulombs (1.6 x 10 -19 ). The signal of the electrons is equal to VC / q. The signal-to-noise ratio after n cycles is equal to V*sqrt(2nC / KT). It should be noted that the signal-to-noise ratio increases with the square root of the number of stacking cycles. For small signal levels, the amount of stacking will be limited to the threshold mismatch between the VR reference electrode and the ion-sensitive electrode. Since there is a reference electrode in each pixel and the electrodes are charge coupled, the relative threshold mismatch between each pair of electrodes is small. Assuming that the difference is about 1mV, more than 1000 stacking cycles should be feasible, thereby improving the signal-to-noise ratio by more than 30 times. As an example, if the signal is 1mV and the electrode area is 1 square micron, Cox=5fF / um is satisfied 2 , the signal-to-noise ratio after 1000 cycles is 50:1. Since the signal level then reaches 1 V, no other noise sources are expected to be relevant. For clarity, the dominant noise is only the well-known charge packet thermal noise.

[0176] Fig.21 and 22An IS stacked pixel with only 2 transistors is shown. By using a deactivation sequence after the row is read out, the select transistor is eliminated. For deactivation, the FD junction is released, which lowers the potential of the FD junction and quiesces the source follower of the row. Fig. 22 The surface potential map of the pixel is shown in Fig.23 middle.

[0177] Fig.24 An IS pile-up pixel with 2 transistors and 4 electrodes is shown. The pixel generates fill and overflow charge packets and reads out all FD junctions simultaneously. The 4th electrode allows total switch operation and associated double sampling. For faster readout, single sampling can be used if the charge pile-up sufficiently reduces the 1 / f noise contribution. Fig.25 Shows Fig.24 Surface potential map of the pixel base operation.

[0178] Fig.26 An IS stacked pixel with 1 transistor and 3 electrodes is shown. The channel can be emptied and supplied from the same junction. This pixel relies on charge coupling and has a lower signal range than the other pixels.

[0179] Several design variations are available, depending on the desired mode of operation. The CCD channel is a surface mode and built in standard CMOS technology (preferably below 0.13um). Additional implants can be added to avoid surface traps and other defects. The channel stopper and channel can be formed from donor and acceptor impurity implants. The channel can be made with a variety of implants to produce the best potential profile for the mode of operation.

[0180] Fig. 27 An embodiment of a three-transistor (3T) automatic pixel sensor is shown. The three transistors are a reset transistor 2701, a source follower 2702, and a row select switch 2703. The reset transistor 2701 has: a gate controlled by a reset signal RST, a source connected to the floating diffusion (FD) of the pixel, and a drain connected to a fixed voltage. The gate of the source follower 2702 is connected to the source of the reset transistor 2701, and its drain is connected to a fixed voltage. The gate of the row select transistor 2703 is connected to the row line, its drain is connected to a fixed voltage, and its source is connected to the column. Other electrodes that interact with the pixel include: a transfer gate TG, an ion selection electrode ISE, an input control gate ICG, and an input diffusion ID. These three elements form a charge-coupled electrode that is connected to the pixel in a manner similar to that of the ion selection electrode ISE. Fig.19 VS, VR and TX operate in the same way.

[0181] Fig.28 An alternative embodiment of a 3T auto-pixel sensor is shown. Fig.28 The sensors and Fig. 27 The difference between the sensors shown is that sensor 2800 has a second input control gate ICG2 which allows more control over the potential barrier near the ion sensitive electrode.

[0182] Fig.29 An embodiment of a 3T auto pixel sensor with a sample and hold circuit is shown, which can be used to eliminate signal variations. As shown, the gate of the row select transistor 2703 is controlled by the row elm signal provided by the row select shift register. The source of the row select transistor 2703 is connected to the current sink ISink2902 and the column buffer 2903. The current sink ISink2902 can be biased by a voltage VB1, and the column buffer (which can be an amplifier) ​​can be biased by a voltage VB2.

[0183] The sample-and-hold circuit 2901 may include: a switch SH, a switch CAL, a capacitor Csh and an amplifier Amp. The input of the switch SH is connected to the output of the column buffer 2903, and its output is connected to the voltage VREF (through the switch CAL), the upper part of the capacitor Csh and the input of the amplifier Amp. The amplifier is biased by the voltage VB2. The output of the amplifier is connected to the switch 2904, and the switch 2904 is controlled by the signal ColSeln from the column selection shift register. The output of the switch 2904 reaches the output line terminal V out Previously buffered by output buffer 2905. The output buffer is biased by voltage VB3.

[0184] Fig.30 One embodiment of a 3T auto-pixel sensor with associated dual sampling circuitry is shown. Fig.30 The sensors and Fig.29 The most significant difference between the sensors in FIG. 300 and FIG. 300 is that the former uses an associated dual sampling circuit 3001 to measure the signal from the column buffer 2903. The amplifier in the associated dual sampling circuit 3001 receives the output of the column buffer 2903 at its first input via a switch SH and a capacitor Cin. The amplifier receives a reference voltage VREF at its second input and is biased by a voltage VB2. A reset switch RST and a capacitor Cf are connected in parallel with the amplifier.

[0185] Fig.31 An embodiment of a 2.5T auto-pixel sensor for a 4 pixel array is shown. Each pixel has its own transfer transistor TX1, TX2, TX3 and TX4 and its own reset transistor. The drain of each transfer transistor is connected to the source of the reset transistor in the same pixel, and the source of each transfer transistor is connected to the gate of a source follower.

[0186] Fig.32An embodiment of a 1.75T auto-pixel sensor for a 4 pixel array is shown. Each pixel has its own transfer transistor. The source of each transfer transistor is connected to the floating diffusion of the same pixel, and the drain of each transfer transistor is connected to the drain of the reset transistor RST of the sensor.

[0187] Array Integrator

[0188] The described embodiments can provide a chemical detection circuit with an improved signal-to-noise ratio. The chemical detection circuit can include: a current source, a chemical detection pixel, an amplifier, and a capacitor. The chemical detection pixel can include a chemically sensitive transistor (which can have a first and a second line end) and a row select switch connected between the current source and the chemically sensitive transistor. The amplifier can have a first input and a second input, wherein the first input is connected to the output of the chemically sensitive transistor via a switch, and the second input is connected to an offset voltage. A capacitor can be connected between the amplifier output and the first input of the amplifier. The capacitor and the amplifier can form an integrator, which can be shared by a column of chemical detection pixels.

[0189] Some embodiments may also provide a chemical detection circuit with an improved signal-to-noise ratio. The chemical detection circuit may include multiple chemical detection pixel columns. Each chemical detection pixel column may include a current source, multiple chemical detection pixels, an amplifier, and a capacitor. Each chemical detection pixel may include a chemically sensitive transistor (which may have a first and a second line end) and a row select switch connected between the current source and the chemically sensitive transistor. The amplifier may have a first input and a second input, wherein the first input is connected to the output of each chemically sensitive transistor via a switch, and the second input is connected to an offset voltage. A capacitor may be connected between the output of the amplifier and the first input of the amplifier. The capacitor and the amplifier may form an integrator, which may be shared by the chemical detection pixel columns.

[0190] Other embodiments may provide a method of generating an output signal from a chemical detection circuit. The method may include selecting a chemical detection pixel from a column of chemical detection pixels for readout, integrating a readout current from the chemical detection pixel into an integrator, and reading out an output voltage of the integrator.

[0191] Fig.33 FIG. 3 illustrates a block diagram of a chemical detection circuit 3300 according to an embodiment of the present invention. The chemical detection circuit 3300 may include a plurality of chemical detection pixels 3302.1-3302.N, a current source 3308, an amplifier 3310, an offset voltage V sd 3314、Capacitor C int3312 and three switches 3316, 3318 and 3320. Each chemical detection pixel (e.g., 3302.1 or 3302.N) can include a chemically sensitive transistor (e.g., 3304.1 or 3304.N, respectively) and a row select switch (e.g., 3306.1 or 3306.N, respectively). The amplifier 3310 can have a first input line terminal (connected to the output of the current source 3308) and a second input line terminal (connected to the offset voltage V sd 3314 connection). Capacitor C int 3312 may have a first side (connected to the first input terminal of the amplifier 3310) and a second side (connected to the output terminal of the amplifier 3310 via the switch 3318). The switch 3316 may be connected to the capacitor C int The switch 3320 may be connected between the first side of the capacitor C int In one embodiment, the plurality of chemical detection pixels 3302.1 to 3302.N may form a chemical detection pixel column. Capacitor C int 3312 can be configured as a negative feedback loop of amplifier 3310, and thus, capacitor C int 3312 and amplifier 3310 may form an integrator for a column of chemical detection pixels. In one embodiment, the integrator may be shared by all chemical detection pixels in the column and may be referred to as a column integrator.

[0192] Each chemically sensitive transistor may have a gate terminal, which may be covered by a passivation layer. The gate terminal may have a floating gate structure (e.g., Figure 2 During operation, the passivation layer may be exposed to an analyte solution to be analyzed. Each chemically sensitive transistor 3304.1-3304.N may additionally have a first terminal (connected to a first side of a corresponding row select switch 3306.1-3306.N) and a second terminal (connected to ground). For example, Fig.33 As shown, transistor 3304.1 can be a PMOS having a first terminal (e.g., source) connected to a first side of row select switch 3306.1 and a second side (e.g., drain) connected to ground. Each row select switch (e.g., 3306.1 or 3306.N) of each chemical detection pixel can have a second side connected to current source 3308. The second side of each row select switch can also be coupled to a first input of amplifier 3310.

[0193] In one embodiment, the chemical detection circuit 3300 can be configured so that each chemically sensitive transistor (e.g., 3304.1, or 3304.N) can operate in current-mode. That is, each chemically sensitive transistor can function as a transconductance amplifier. Through the current output, the ion concentration of the analyte measured by the chemically sensitive transistor can be detected. In one embodiment, each chemically sensitive transistor 3304.1-3304.N can be an ion-sensitive field effect transistor (ISFET), and each row select switch 3306.1-3306.N can also be a transistor.

[0194] During operation, when a chemical detection pixel is selected, the corresponding row selection switch can be turned off. Fig.33 As shown, chemical detection pixel 3302.1 can be selected, and thus row select switch 3306.1 can be closed. Current source 3308 can provide a DC bias current I dc , to select the chemically sensitive transistor 3304.1. The signal current I generated by the gate voltage change of the chemically sensitive transistor 3304.1 sig Can be integrated to capacitor C int 3312, and the output signal of the amplifier 3310 can be read as V out The offset voltage V applied to the second input of amplifier 3310 sd 3314 can provide a source-to-drain voltage V sd , for chemically sensitive transistor operation.

[0195] Each measurement run may include 2 phases. The first phase of the run may be an integration phase, and the second phase of the run may be a clearing phase to clear the charge. In the first phase of the run, switch 3318 may be closed, and switches 3316 and 3320 may be open. out Afterwards, the operation may enter the second phase, during which switches 3316 and 3320 may be closed and switch 3318 may be opened to eliminate the accumulated charge on capacitor C int 3312. In one embodiment, a correlated double sampling (CDS) scheme can be implemented by closing switch 3320 in the second phase. This can allow the inherent offset voltage of amplifier 3310 to be stored on capacitor C int 3312 up.

[0196] In one embodiment, current source 3308 may be a programmable current source connected to each column to provide a DC bias current I dc , the latter can be relatively large. In this configuration, the bias current I dc will not be integrated into capacitor C int3312, so the integrator can avoid premature saturation. int The value and integration duration can be used to derive the amplification level.

[0197] In addition, in one embodiment, the output signal V out Converted into a digital signal. For example, using a single slope integrating ADC can digitize the charging signal current I sig , so that the counter can increment (count) until the integrator output voltage crosses a certain threshold defined by the comparator. When using a single slope integrating ADC, a calibration can be performed to determine the capacitor C int 3312. Alternatively, a "dual slope integrating ADC" may be used, which uses a fixed integration phase followed by a variable release phase. In other embodiments, the output signal V may be converted to out Convert into digital signal.

[0198] In one embodiment, integration of the current response of a chemically-sensitive transistor may provide a better signal-to-noise ratio (SNR) than instantaneous voltage output measurements of the chemically-sensitive transistor.

[0199] In one or more embodiments, it may be difficult to completely eliminate the DC current of the chemically sensitive transistor using the current source 3308. Therefore, in one embodiment, the size of the capacitor may be limited to a certain size. In another embodiment, the duration of the integration time may be limited to, for example, 1 ps. If the integration time is limited, a dual slope ADC with a much slower release phase may be used to convert the output voltage V out Converted to digital output.

[0200] Fig.34 FIG. 3 illustrates a block diagram of another chemical detection circuit 3400 according to an embodiment of the present invention. The chemical detection circuit 3400 may include a plurality of chemical detection pixels 3402.1-3402.N, a current source 3408, an amplifier 3410, a resistor 3424, an offset voltage V set 3414、Capacitor C int3412 and three switches 3416, 3418 and 3420. Each chemical detection pixel (e.g., 3402.1 or 3402.N) can include a chemically sensitive transistor (e.g., 3404.1 or 3404.N, respectively), a row selection switch (e.g., 3406.1 or 3406.N, respectively) and an output switch (e.g., 3422.1, 3422.N). The amplifier 3410 can have a first input line terminal, which is connected to the output switch of the chemical detection pixel, so that when the chemical detection pixel is selected, its output switch can be closed to generate an output signal at the first input line terminal of the amplifier 3410. The amplifier 3410 can also have a second input line terminal, which is connected to the offset voltage V set 3414 connection. Capacitor C int 3412 may have a first side (connected to the first input terminal of the amplifier 3410) and a second side (connected to the output terminal of the amplifier 3410 via the switch 3418). The switch 3416 may be connected to the capacitor C int The switch 3420 may be connected between the first side of the capacitor C int In one embodiment, the plurality of chemical detection pixels 3402.1-3402.N may form a chemical detection pixel column. Capacitor C int 3412 can be configured as a negative feedback loop of amplifier 3410, and thus, capacitor C int 3412 and amplifier 3410 can form an integrator for a column of chemical detection pixels. The integrator can be shared by all chemical detection pixels in the column and can be called a column integrator.

[0201] The gate structure of each chemically sensitive transistor 3404.1-3404.N may be similar to the gate structure of the chemically sensitive transistor 3302.1-3302.N. Each chemically sensitive transistor 3404.1-3404.N may additionally have a first terminal connected to a first side of a corresponding row select switch 3406.1-3406.N and a first side of a corresponding output switch 3422.1-3422.N. Each chemically sensitive transistor 3404.1-3404.N may also have a second terminal connected to a ground line. For example, Fig.34As shown, transistor 3404.1 can be a PMOS having a first line terminal (e.g., source) connected to a first side of row select switch 3406.1 and a first side of output switch 3422.1. In addition, transistor 3404.1 can also have a second side (e.g., drain) connected to ground. Each row select switch (e.g., 3406.1 or 3406.N) of each chemical detection pixel 3402.1-3402.N can have a second side connected to current source 3408. The second side of each output switch 3422.1-3422.N can also be connected to the first input of amplifier 3410 via resistor 3424.

[0202] In one embodiment, the chemical detection circuit 3400 can be configured so that each chemically sensitive transistor (e.g., 3404.1 or 3404.N) can operate in voltage-mode. That is, during operation, each chemically sensitive transistor can function as a voltage amplifier. The ion concentration of the analyte measured by the chemically sensitive transistor can be detected by the voltage level at the output. When a chemical detection pixel is selected, the corresponding row selection and output switch can be closed. The offset voltage V set An appropriate voltage may be set between the virtual ground (eg, the first terminal or the negative terminal) of the amplifier 3410 and the output of the selected chemically sensitive transistor. Fig.34 As shown, the chemical detection pixel 3402.1 can be selected, and thus the row select switch 3406.1 and the output switch 3422.1 can be closed. The current source 3408 can provide current to the selected chemically sensitive transistor 3404.1. The resistor 3424 can be used to convert the output voltage at the selected chemically sensitive transistor to be integrated to the capacitor C int The charging current I on 3412 is The output signal of amplifier 3410 can be read as V out .

[0203] Similar to the operation of chemical detection circuit 3300, the operation of chemical detection circuit 3400 may have an integration phase and a clearing phase for clearing the charge. In the integration phase, switch 3420 may be closed, and switches 3416 and 3420 may be opened. out Afterwards, the operation may enter the second phase, during which switches 3416 and 3420 may be closed and switch 3418 may be opened to eliminate the accumulated charge on capacitor C int Charge on 3412.

[0204] In one embodiment, each chemically sensitive transistor 3404.1-3404.N can be an ion sensitive field effect transistor (ISFET), and each row select switch 3406.1-3406.N can be a transistor. Each output switch 3422.1-3422.N can also be a transistor.

[0205] In addition, similar to the chemical detection circuit 3300, the ADC can convert the output signal V of the chemical detection circuit 3400 into out Converted into a digital signal. For example, using a single slope integrating ADC or a dual slope integrating ADC, the charging current I is In other embodiments, the output signal V of the chemical detection circuit 3400 may be converted to out Convert into digital signal.

[0206] Additionally, in one embodiment, the resistance of resistor 3424 may dominate the resistance of the series of row select switches (e.g., 3406.1-3406.N) to limit the resistance required on capacitor C int The current integrated on the 3412.

[0207] Fig.35 FIG. 3 is a block diagram of another chemical detection circuit 3500 according to another embodiment of the present invention. The chemical detection circuit 3500 may have a pass transistor 3524 that replaces the resistor 3424 of the chemical detection circuit 3400. Except for the transistor 3524, the other components of the chemical detection circuit 3500 may be the same as the chemical detection circuit 3400. The pass transistor 3524 may have a gate voltage V 偏压 , which is connected to some process, voltage and temperature (PVT) independent bias circuitry. The on-resistance of the pass transistor 3524 can be designed to dominate the resistance of the series row select switches in the pixel.

[0208] Fig.36 A process 3600 for generating a chemical detection circuit output according to one embodiment of the present invention is explained. The process 3600 may be derived from the above description of Figure 33-35 The chemical detection circuitry of 3300, 3400, and 3500 are performed. The process 3600 may begin at step 3602, where a chemical detection pixel may be selected for readout. Fig.33 As shown, for example, when chemical detection pixel 3302.1 is selected, row select switch 3306.1 can be closed. Fig.34 and 35As shown, for example, when chemical detection pixel 3402.1 is selected, row select switch 3406.1 and output switch 3422.1 may be closed.

[0209] Then, process 3600 may proceed to step 3604. At step 3604, process 3600 may integrate the readout current from the chemical detection pixel into an integrator. As described above, the readout current may be caused by a voltage change at the gate terminal of the selected chemical detection pixel. In one embodiment, Fig.33 As shown, the chemical detection pixels can function in current mode, and selected chemical detection pixels can supply a readout current to charge the capacitor of the integrator. In another embodiment, as shown Fig.34 and 35 As shown, the chemical detection pixel can function in voltage mode, and a resistor or a pass transistor can convert the output voltage from the chemical detection pixel into a current to charge the capacitor of the integrator.

[0210] Then, at step 3506, process 3600 can read the output voltage of the integrator. As described above, the output voltage of the integrator (V out or the output of amplifier 3410) can have a better signal-to-noise ratio (SNR) than instantaneous voltage measurement for detecting the ion concentration of the analyte analyzed by the chemical detection pixel.

[0211] Although in the above description, chemically sensitive transistors may be described as PMOS devices, they may also be implemented as NMOS devices in one embodiment. In addition, in one embodiment, switches (e.g., row select switches, output switches, charge removal switches) may be implemented in PMOS or NMOS transistors.

[0212] Array configuration and readout scheme

[0213] The described embodiments may provide a chemical detection circuit which may include: a plurality of first output circuits at a first side, and a plurality of second output circuits at a second and opposite side of the chemical detection circuit. The chemical detection circuit may further include a plurality of pixel panels (tiles), each of which is placed between corresponding first and second output circuit pairs. Each panel array may include 4 quadrants of pixels. Each quadrant may have a column named a first column, which is interlaced with a second column. Each first column may be connected to a corresponding first output circuit in the first and second quadrants, and to a corresponding second output circuit in the third and fourth quadrants. Each second column may be connected to a corresponding second output circuit in the first and second quadrants, and to a corresponding first output circuit in the third and fourth quadrants.

[0214] Some embodiments may also provide a chemical detection system, which may include a motherboard having: at least one central processor, an output device connected to the motherboard, and a chemical detection readout board connected to the motherboard. The chemical detection readout board may have a chemical detection circuit, which may include a plurality of first output circuits at a first side, and a plurality of second output circuits at a second and opposite side of the chemical detection circuit. The chemical detection circuit may additionally include a plurality of pixel panels (tiles), each of which is placed between corresponding first and second output circuit pairs. Each panel array may include 4 quadrants of pixels. Each quadrant may have a column named a first column, which is interlaced with a second column. Each first column may be connected to a corresponding first output circuit in the first and second quadrants, and to a corresponding second output circuit in the third and fourth quadrants. Each second column may be connected to a corresponding second output circuit in the first and second quadrants, and to a corresponding first output circuit in the third and fourth quadrants.

[0215] Other embodiments may provide a method of reading out data from a chemical detection circuit. The method may include: selecting a first quadrant of a board to read out data, selecting a first column group and a second column group, reading out data of the first column group from a first set of output pins located at a first side of the chemical detection circuit, reading out data of the second column group from a second set of output pins located at a second side of the chemical detection circuit, and repeating the selection and data readout of the next first column group and second column group until all remaining first quadrant columns are read out.

[0216] Fig.37A block diagram of a chemical detection circuit 3700 according to one embodiment of the present invention is explained. The chemical detection circuit 3700 may include: a plurality of pixel panels 3702.1-3702.N and 3704.1-3704.N, output circuits 3706 and 3708, control logic and digital interface 3710, and bias circuits and diagnostic output logic 3712. Each panel 3702.1-3702.N and 3704.1-3704.N may include pixels formed in columns, wherein each column contains a number of rows. For example, each panel may contain 6848 columns x 11136 rows of pixels. The panels 3702.1-3702.N may form a sheet (e.g., a top sheet), and the panels 3704.1-3704.N may form another sheet (e.g., a bottom sheet). The plurality of panels 3702.1-3702.N and 3704.1-3704.N may form a clustered pixel array. The output circuit 3706 and 3708 can be placed at 2 opposite sides (e.g., top and bottom) of the plate. The output circuit 3706 and 3708, control logic and digital interface 3710, and bias circuit and diagnostic output logic 3712 can each contain multiple pins for input and output data of chemical detection circuit 3700. In one embodiment, chemical detection circuit 3700 can be formed on an integrated circuit chip. In addition, in one embodiment, output circuit 3706 and 3708 can include analog-to-digital converter (ADC) to produce digital output. In addition, in one embodiment, 2 sheets can be operated independently and exposed to different analytes. For example, when reading the data of the top plate, the fluid of the bottom plate can be flushed out for another round of testing. This can be used in combination with a dual channel flow cell (e.g., fixed on the top of the chemical detection circuit 3700), in which 2 different flow channels can perform different tasks simultaneously.

[0217] The pixels of each panel 3702.1-3702.N and 3704.1-3704.N can be divided into 4 quadrants, and the data generated at each pixel can be read out from the top or bottom. An exemplary configuration of pixels within a pair of panels is shown in Fig.38A middle.

[0218] Fig.38A A chemical detection circuit 3700 ( Fig.37 ) is a block diagram 3800 of components. Fig.38AAs shown, board 3702.1 may include 4 quadrants: upper left (TL) quadrant 3802, upper right (TR) quadrant 3804, lower left (BL) quadrant 3806, lower right (BR) quadrant 3808; and 4 row select registers: upper left row select register 3828, upper right row select register 3836, lower left row select register 3830, lower right row select register 3838. Board 3704.1 may include 4 quadrants: upper left quadrant 3816, upper right quadrant 3818, lower left quadrant 3812, lower right quadrant 3814; and 4 row select registers for each respective quadrant: upper left row select register 3832, upper right row select register 3844, lower left row select register 3834, lower right row select register 3846. Boards 3702.1 and 3704.1 may share a current source and swizzles block 3810. The current source and mixing block 3810 can be sandwiched between the plate pairs. In addition, plates 3702.1 and 3704.1 can share top and bottom output circuits, including channel circuits 3820 and 3822, column multiplexers 3848 and 3850, output multiplexers 3824 and 3826, and output buffers 3840 and 3842. The channel circuits 3820 and 3822 can include sample-and-hold (S / H) circuits. In one embodiment, each quadrant of a plate can include multiple columns, and each column can include multiple rows. For example, a quadrant can have 1712 columns, and each column can contain 2784 rows of pixels. In one embodiment, every plate can include reference pixels. For example, a predetermined number (e.g., 4) of pixel columns and / or rows at the periphery of every plate can be designated as reference pixels. The reference pixels can be used to generate a signal representing a background, and are not exposed to analytes.

[0219] When a row of pixels is selected according to the corresponding row select register of the quadrant, each column can generate an output signal. In one embodiment, each quadrant column can be named as the first or second column (e.g., odd column or even column), and the output signal can be read out from the top or bottom output circuit. The columns can be grouped for parallel readout operation. That is, the first column group or the second column group (n columns, n is an integer greater than 1) can be read out together in parallel at the same time. For example, if n is equal to 8, the odd column group can be columns [1:8], [17:24], [33:40], etc., and the even column group can be [9:16], [25:32], [41:48], etc. The column groups can be connected according to the quadrants in which they are located. For the upper left quadrant (e.g., 3802, 3812), the odd column groups may be connected to the output circuits at the first side (e.g., the top output circuits, including the channel circuits 3820, the column multiplexers 3848, the output multiplexers 3824, and the output buffers 3840), and the even column groups may be connected to the output circuits at the second side (e.g., the bottom output circuits, including the channel circuits 3822, the column multiplexers 3850, the output multiplexers 3826, and the output buffers 3842). For the upper right quadrant (e.g., 3804, 3814), the odd column groups may be connected to the output circuits at the first side, and the even column groups may be connected to the output circuits at the second side. For the lower left quadrant (e.g., 3806, 3816), the odd column groups may be connected to the output circuits at the second side, and the even column groups may be connected to the output circuits at the first side. For the lower right quadrant (eg, 3808, 3818), odd-numbered column groups may be connected to output circuits at the second side, and even-numbered column groups may be connected to output circuits at the first side.

[0220] In one embodiment, the first column group and the second column group may form a data channel that is read out together simultaneously from the first or second side of the output circuit. Each data channel may include one first column group and one second column group located in each quadrant between the first side of the output circuit and the second side of the output circuit (e.g., n first columns and n second columns from each of TL3802, BL 3806, BL 3816, TL 3812).

[0221] The readout operation can use a row select shift register (e.g., a vertical shift register) for selecting rows and a column shift register (e.g., a horizontal shift register) for selecting columns. When the operation begins, switches within the current source and mixing block 3810 can be activated to provide drive current to the signal line, any pixel select lines of the unused flow cell can be disabled, and all row and column shift registers can be reset. The vertical shift register can then begin counting in increments of 1 and the horizontal shift register can begin counting in increments of 16. The data for the frame can start from the vertical shift register that selects row 1 of TL, TR, BL, and BR after reset. In one embodiment, the word "mixing" can refer to a configuration in which a metal line that passes through a column in the top circuit can be routed in the space between the top and bottom circuits in a manner that allows it to pass through different columns in the bottom circuit, as shown below in Fig.40 as shown in .

[0222] The readout operation may start from the TL quadrant (e.g., TL quadrant 3802). Through the horizontal shift register, the first group of odd columns in TL 3802 (e.g., n first columns [1:8]) and the first group of even columns in TL 3802 (e.g., n second columns [9:16]) may be selected. The selected odd column pixels in row 1 of TL 3802 may be routed to the top output through channel circuit 3820, column multiplexer 3848, and output multiplexer 3824, and then they may be read out through top output buffer 3840. At the same time, the selected even column pixels in row 1 of TL may be routed to the bottom output through channel circuit 3822, column multiplexer 3850, and output multiplexer 3826, and then they may be read out through bottom output buffer 3842.

[0223] During the above readout time, the next group of odd pixels in row 1 of TL 3802 (e.g., columns [17:24]) can be connected to top column multiplexer 3848 and output multiplexer 3824 via channel circuit 3820. Similarly, the next group of even pixels in row 1 of TL 3802 (e.g., columns [25:32]) can be connected to bottom column multiplexer 3850 and output multiplexer 3826 via channel circuit 3822. Top and bottom output multiplexers 3824 and 3826 can then switch their respective multiplexers, and then the next group of odd pixels in row 1 of TL 3802 can be read out through the top output, and the next group of even pixels in row 1 of TL 3802 can be read out through the bottom output. This can continue until all pixels from row 1 of TL 3802 have been read out. At the end of row 1 readout, the vertical shift register of the TL 3802 can move to the next row and the output can begin to stabilize.

[0224] After completing the first row of the TL quadrant 3802, the readout operation may continue to the TR quadrant 3804. Through the horizontal shift register, the first group of odd columns (e.g., columns [1:8]) in the TR quadrant 3804 and the first group of even columns (e.g., columns [9:16]) in the TR quadrant 3804 may be selected. Then, the selected first group of odd column pixels in the first row of the TR quadrant 3804 may be routed to the top output through the channel circuit 3820, the column multiplexer 3848, and the output multiplexer 3824, and then they may be read out through the top output buffer 3840. At the same time, the selected first group of even column pixels [9:16] in the first row of the TR 3804 may be routed to the bottom output through the channel circuit 3822, the column multiplexer 3850, and the output multiplexer 3826, and then they may be read out through the bottom output buffer 3842.

[0225] During the above readout time, the next group of odd pixels in row 1 of TR 3804 (e.g., columns [17:24]) can be connected to top column multiplexer 3848 and output multiplexer 3824 via channel circuit 3820. Similarly, the next group of even pixels in row 1 of TR 3804 (e.g., columns [25:32]) can be connected to bottom column multiplexer 3850 and output multiplexer 3826 via channel circuit 3822. Top and bottom output multiplexers 3824 and 3826 can then switch their respective multiplexers, and then the next group of odd pixels in row 1 of TR 3804 can be read out through the top output, and the next group of even pixels in row 1 of TR 3804 can be read out through the bottom output. This can continue until all pixels from row 1 of TR 3804 have been read out. At the end of row 1 readout, the vertical shift register of the TR 3804 can transfer to the next row and the output can begin to stabilize.

[0226] After completing the first row of the TR quadrant 3804, the readout operation may continue to the BL quadrant 3806. Through the horizontal shift register, the first group of odd columns (e.g., columns [1:8]) in the BL quadrant 3806 and the first group of even columns (e.g., columns [9:16]) in the BL quadrant 3806 may be selected. Then, the selected first group of odd column pixels in the first row of the BL quadrant 3806 may be routed to the bottom output through the channel circuit 3822, the column multiplexer 3850, and the output multiplexer 3826, and then they may be read out through the bottom output buffer 3842. At the same time, the selected first group of even column pixels [9:16] in the first row of the BL 3806 may be routed to the top output through the channel circuit 3820, the column multiplexer 3848, and the output multiplexer 3824, and then they may be read out through the top output buffer 3840.

[0227] During the above readout time, the next group of odd pixels in row 1 of BL 3806 (e.g., columns [17:24]) can be connected to bottom column multiplexer 3850 and output multiplexer 3826 via channel circuit 3822. Similarly, the next group of even pixels in row 1 of BL 3806 (e.g., columns [25:32]) can be connected to top column multiplexer 3848 and output multiplexer 3824 via channel circuit 3820. Top and bottom output multiplexers 3824 and 3826 can then switch their respective multiplexers, and then the next group of odd pixels in row 1 of BL 3806 can be read out through the bottom output, and the next group of even pixels in row 1 of BL 3806 can be read out through the top output. This can continue until all pixels from row 1 of BL 3806 have been read out. At the end of row 1 readout, the vertical shift register of BL 3806 can transfer to the next row and the output can begin to stabilize.

[0228] After completing row 1 of BL quadrant 3806, the readout operation may continue to BR quadrant 3808. Through the horizontal shift register, the first group of odd columns (e.g., columns [1:8]) in BR quadrant 3808 and the first group of even columns (e.g., columns [9:16]) in BR quadrant 3808 may be selected. Then, the selected first group of odd column pixels in row 1 of BR quadrant 3808 may be routed to the bottom output through channel circuit 3822, column multiplexer 3850, and output multiplexer 3826, and then they may be read out through bottom output buffer 3842. At the same time, the selected first group of even column pixels [9:16] in row 1 of BR quadrant 3808 may be routed to the top output through channel circuit 3820, column multiplexer 3848, and output multiplexer 3824, and then they may be read out through top output buffer 3840.

[0229] During the above readout time, the next group of odd pixels in row 1 of BR quadrant 3808 (e.g., columns [17:24]) can be connected to bottom column multiplexer 3850 and output multiplexer 3826 via channel circuit 3822. Similarly, the next group of even pixels in row 1 of BR quadrant 3808 (e.g., columns [25:32]) can be connected to top column multiplexer 3848 and output multiplexer 3824 via channel circuit 3820. Top and bottom output multiplexers 3824 and 3826 can then switch their respective multiplexers, and then the next group of odd pixels in row 1 of BR quadrant 3808 can be read out through the bottom output, and the next group of even pixels in row 1 of BR quadrant 3808 can be read out through the top output. This can continue until all pixels from row 1 of BR quadrant 3808 have been read out. At the end of the readout of row 1, the vertical shift register of BR quadrant 3808 can transfer to the next row and the output can begin to stabilize.

[0230] After reading out row 1 of all 4 quadrants, the run can return to TL and the pattern can be repeated until all rows in TL, TR, BL, and BR are read out to complete one frame of one board (e.g., 3702.1). The run can then proceed in the next board (e.g., 3702.2). This scheme can allow row n in a quadrant to stabilize in 3 / 4 of the time required to read out row n from all 4 quadrants.

[0231] In one embodiment, the readout operation can be performed to complete one quadrant at a time. That is, after a row of a quadrant has been completed, move to the next row of the same quadrant; and continue to the next quadrant only after all rows of the same quadrant have been completed.

[0232] In one embodiment, the plates at the top sheet (e.g., 3702.1-3702.N) can run in parallel, and the plates at the bottom sheet can run alternately with the corresponding top sheet plates (e.g., 3702.1 and 3704.1 run alternately).

[0233] Fig.38B The transfer directions in different quadrants of the plate are explained according to one embodiment of the present invention. Fig.38B As shown, in one embodiment, the readout operation can start from the center of the board and move outward (eg, adding row and column select registers).

[0234] Fig.39A block diagram illustrating components of a data channel 3900 of a chemical detection circuit 3700 according to an embodiment of the present invention. The data channel 3900 may include: n first columns 3902 and n second columns 3904 of a TL quadrant 3802, and n first columns 3908 and n second columns 3906 of a BL quadrant 3806. Fig.39 Only the data channels 3900 in the top sheet (e.g., TL quadrant 3802 and BL quadrant 3806 of sheet 3702.1) are shown. Although not shown, the data channels 3900 may additionally include n first columns and n second columns in each of the TL quadrant 3812 and BL quadrant 3816 of sheet 3704.1. Fig.39 As shown, the data channel 3900 can have two 2n signal lines, wherein the top 2n signal line is connected to the output channel circuit 3820 at the right side. Although not shown, the bottom 2n signal line can be connected to the output channel circuit 3822 at the left side. The pixels of the n first columns 3902 and the n second columns 3906 can each be connected to their respective top 2n signal lines. The pixels of the n second columns 3904 and the n first columns 3908 can each be connected to their respective bottom 2n signal lines. The current source and mixing block 3810 at the left side of the 2n signal lines can provide 2n current sources, each of which can drive its own signal line. In addition, the 2n signal lines can be mixed in the current source and mixing block 3810 (which will be referred to later). Fig.40 Describes the details of an exemplary embodiment of mixing).

[0235] During operation, data from the top 2n signal lines can be read out from channel circuit 3820, column multiplexer 3848, output multiplexer 3824 and output buffer 3840, and the bottom 2n signal lines can be read out from the corresponding circuits on the left.

[0236] Fig.40 A chemical detection circuit 3700 ( Fig.37 ) of the signal lines. In one embodiment of the chemical detection circuit 3700, there may be two output lines arranged through each column, so that a column of pixels can be connected to a column circuit (e.g., an IC chip) at the top of the chemical detection circuit 3700, or to a column circuit at the bottom of the chemical detection circuit 3700. The column output lines can run the entire height of the die and can be very long, so they can be prone to crosstalk. To reduce crosstalk, a plurality of output lines can be arranged in the center of the chemical detection circuit 3700 (e.g., at the bottom of the chemical detection circuit 3700). Fig.38A The current source and mixing block 3810) mix the column output line. Fig.40As shown, 4 columns may have 8 lines (e.g., each column may contain 2 lines). Each line may be connected to the top column circuit 4002 or the bottom column circuit 4004. For example, lines A, D, E, and H may be connected to the top column circuit 4002, and lines B, C, F, and G may be connected to the bottom column circuit 4004. The order of the 8 lines may be mixed in the middle. For example, the top half of line A may run through pixels in column 1, and the bottom half of line A may run through pixels in column 2, the top half of line B may run through pixels in column 1, and the bottom half of line B may run through pixels in column 3, the top half of line C may run through pixels in column 2, and the bottom half of line C may run through pixels in column 1, the top half of line D may run through pixels in column 2, and the bottom half of line D may run through pixels in column 4, the top half of line E may run through pixels in column 3, and the bottom half of line E may run through pixels in column 1, the top half of line F may run through pixels in column 3, and the bottom half of line F may run through pixels in column 4, the top half of line G may run through pixels in column 4, and the bottom half of line G may run through pixels in column 2, the top half of line H may run through pixels in column 4, and the bottom half of line H may run through pixels in column 3. In one embodiment, the steps of: Fig.40 As a result, crosstalk can be reduced by up to 50%.

[0237] Fig.41 A process 4100 for outputting data from a chemical detection circuit according to one embodiment of the present invention is explained. The process 4100 may be performed by the chemical detection circuit 3700. The process 4100 may begin at step 4102, where the first quadrant of the plate may be selected for reading data. Fig.38A As described, for example, by starting at the upper left quadrant 3802, a readout operation of the board (e.g., 3702.1) can be performed. The process 4100 can then proceed to step 4104. At step 4104, the process 4100 can select a first column group and a second column group. As described above, the readout operation can be performed in the first column group and the second column group (e.g., odd columns [1:8] and even columns [9:16]). Then, at step 4106, the process 4100 can read out data from the first column group of the first output pin set (e.g., top output buffer 3840) and data from the second column group of the second output pin set (e.g., bottom output buffer 3842).

[0238] Then, the process 4100 may proceed to step 4108. At step 4108, the process 4100 may repeat the selection and data readout of the next group of first columns and the next group of second columns until all remaining columns of the first quadrant are read out. For example, the chemical detection circuit 3700 may repeat the readout operation of the odd column groups [17:24], [33:40], etc. and the even column groups [25:32], [41:48], etc. of all remaining columns of the first quadrant (e.g., TL quadrant 3802).

[0239] Fig.42 A system architecture 4200 for chemical detection according to one embodiment of the present invention is explained. The system architecture 4200 may include a motherboard 4202, an output device 4208, a readout board 4210, and a valve board 4212. The motherboard 4202 may include a CPU 4204 and a memory 4206 (e.g., a double data rate (DDR) memory device). The CPU 4204 may be enlarged from 2 cores to 6 cores. The memory DDR 4206 may be 1GB to 96GB DDR3 (double data rate type 3). The motherboard 4202 may also support on-board RAID (6 SATA ports) and a graphics processor board (GPU). The output device 4208 may be a color display with high brightness (e.g., XGA multi-touch input independent and display independent 8-line analog resistance). The readout board 4210 may include a sensor 4218 (e.g., chemical detection circuit 3700) and other surrounding circuits (details of analog and digital chemical sensors are shown in FIG. 3 , respectively). Fig.43 and 44 ). The valve plate 4212 may include an FPGA 4214 and a valve controller 4216. During operation, the FPGA 4214 may be loaded with control logic to control the operation of the valve plate. The valve controller 4216 may include a plurality of valves (e.g., 30 valves) that control the flow of a fluid containing an analyte to be analyzed by a sensor 4218. The valve plate 4212 may additionally include a thermistor input, a pressure sensor input, and may additionally include a heater / cooler control (not shown) that may control the sensor 4218 and the heater / cooler of the analyte (e.g., to assist in controlling the reaction during sample testing). In one embodiment, the motherboard 4202 and the readout board 4210 may be connected according to the PCI Express (PCIe) standard, and the readout board 4210 and the valve plate 4212 may be connected via a serial connection over LVDS (low voltage differential signaling).

[0240] Fig.43The analog readout board 4300 of the chemical detection circuit according to one embodiment of the present invention is explained. The analog readout board 4300 may include: an analog chemical sensor 4302, a clock 4304, a power supply 4306, a serial connection of LVDS 4308, a reader FPGA 4310, a memory 4312, an ADC 4314, a PCIe switch 4316, a PCIe connector 4318, 2 satellite FPGA blocks 4320 and 4322, and a voltage reference and DAC block 4324. The analog chemical sensor 4302 may be an IC chip embodiment of the chemical detection circuit 3700. The analog data readout from the analog chemical sensor 4302 may be digitized by the ADC 4314, which may use a voltage reference and DAC 4324. The digitized data may be sent to the satellite FPGA 4320 or 4322, which may perform a stabilization correction and then sent to the reader FPGA 4310. The reader FPGA 4310 can buffer the data in memory 4312, which can include multiple DDR memory blocks. The reader FPGA 4310 can also perform frame averaging (e.g., average pixel data values ​​between multiple frames; this is possible because analog chemical sensors can read out data at a higher frame rate than required (e.g., 30 FPS)) or variable rate frame averaging (e.g., averaging different parts of the pixel time history at different rates) and then send the data to the server motherboard (e.g., PCIe switch 4316 and PCIe connector 4318) via PCIe switch 4316 and PCIe connector 4318. Fig.42 The PCIe switch 4316 may include a multiplexer that multiplexes to the PCIex 16 connections of the PCIe connector 4318. The LVDS 4308 may provide communication with the valve board (e.g., Fig.42 The power for the readout board 4300 can be provided by a power supply 4306, and the timing signal can be provided by a clock 4304. In one embodiment, the ADC 4314 can be placed near the analog chemical sensor 4302.

[0241] Fig.44 A digital readout board 4400 of a chemical detection circuit according to one embodiment of the present invention is explained. The digital readout board 4400 may include: a digital chemical sensor 4402, a clock 4404, a power supply 4406, a serial connection of a LVDS 4408, a reader FPGA 4410, a memory 4412, a PCIe switch 4416, and a PCIe connector 4418. The digital chemical sensor 4402 may be a chemical detection circuit 3700 ( Fig.37) IC chip embodiment, wherein the ADC is integrated on the chip, and the chip digitizes the output data signal on the chip. The clock 4404, power supply 4406, serial connection of LVDS 4408, reader FPGA 4410, memory 4412, PCIe switch 4416 and PCIe connector 4418 can perform functions similar to their counterparts on the analog digital readout board 4300. In one embodiment, the digital chemical sensor 4402 can be placed on a replaceable board separate from the digital readout board 4400.

[0242] Fig.45 A block diagram 4500 is illustrated that illustrates the output configuration of a chemical detection circuit according to one embodiment of the present invention. The block diagram 4500 may show the noise calculation of the analog front end and the analog data output from the analog chemical detector 4502. The DAC 4504 may generate an analog signal based on a digital reference value, and the analog signal from the DAC 4504 may be buffered by buffers 4506.1-4506.4. The output from the analog chemical detector 4502 may be amplified by amplifiers 4508.1-4508.4, and the amplified signal may be filtered by low pass filters 4510.1-4510.4. The filtered signal may be input into an ADC module 4512, which may contain a plurality of differential amplifiers 4514.1-4514.4. The amplified signal may pass through another round of low pass filters 4516.1-4516.4, and then finally converted to digital data by a Quad ADC 4518 and sent to an FPGA. The Quad ADC 4518 may receive a clock signal from a clock fan-out 4524. The PLL 4522 can generate a clock signal based on a signal from the oscillator 4520. In one embodiment, the analog chemical detector 4502 can be an IC chip implementation of the chemical detection circuit 3700.

[0243] Fig.46 Block diagram 4600 illustrates bandwidth utilization of a chemical detection circuit according to one embodiment of the present invention. An analog chemical detector 4602 may send its data to a plurality of ADCs 4604. The ADCs 4604 may send digital data to an FPGA 4606, which in turn may send data to a CPU 4608 and storage units 4616 and 4618 (e.g., DDR3 memory). The CPU 4608 may cache data in a memory cache 4610 (e.g., DDR3 memory) and hard drives 4612 and 4614. In one embodiment, the analog chemical detector 4602 may be an IC chip implementation of the chemical detection circuit 3700. In Fig.46The numbers given in may be theoretical maximums. The FPGA 4606 may perform 3:1 compression of samples (eg, stabilization correction) and 2:1 or greater compression of frames (eg, frame averaging).

[0244] Fig.47 An analog readout plate (e.g., Fig.43 4700 of the analog readout board 4300). Based on the 100 MHz oscillator 4702, clock signals for different components of the analog readout board can be generated. The clock generator 4704 can receive the signal from the 100 MHz oscillator 4702 and generate different clock signals. For example, the clock generator 4704 can generate a 120 MHz clock signal, which will be sent to two zero delay buffers 4706.1 and 4706.2, a flip-flop 4716, and a first PLL of the FPGA 4714 (e.g., the reader FPGA 4310 of the analog readout board 4300). The zero delay buffers 4706.1 and 4706.2 can provide a 120 MHz clock signal to the ADC sets 4718.1 and 4718.2 of the ADC to send the digitized data to the FPGAs 4720.1 and 4720.2 (e.g., the satellite FPGAs 4320 and 4322 of the analog readout board 4300) at a frequency of, for example, 840 MHz. The first PLL of the FPGA 4714 can send the clock signal to the first PLL in the corresponding FPGAs 4720.1 and 4720.2, and can also send the clock signal internally to the trigger port of the FPGA 4714. Based on the output of the trigger port of the FPGA 4714 and the 120 MHz clock signal from the clock generator 4704, the flip-flop 4716 can generate a channel increment / decrement signal for data readout. The oscillator 4702 may also generate a 33 MHz clock signal for a clock driver 4708, which may provide clock signals for a second PLL in FPGAs 4720.1 and 4720.2, respectively, and a second PLL in FPGA 4714. The second PLL in FPGA 4714 may generate an internal clock (e.g., 267 MHz). In one embodiment, biasing all of these clocks may allow synchronization of channel outputs of sensors and sampling of ADCs.

[0245] External communication with the analog board reader can be based on a 100 MHz clock signal from the PCIe connector. The 100 MHz clock signal from the PCIe connector can be buffered by a PCIe clock buffer 4710. The buffered 100 MHz clock signal can be sent to the first and second SerDes PLLs (serialization / deserialization phase-locked loops) of FPGA 4714, and can also be sent to a PCIe switch 4712 (e.g., PCIe switch 4316).

[0246] In one embodiment, zero delay buffers 4706.1 and 4706.2 can implement asymmetric regulation between the ADC sampling clock and the data channel of the chemical detector (not shown). Where possible, the clock can be differential LVDS, but the clock of the channel of the chemical detector can be differential low voltage positive supply emitter coupled logic (LVPECL). In addition, in one embodiment, the combination of the ADC and data channel 120MHz clock needs to be low jitter (e.g., <15ps - with pull-out ~4.5rms). In one embodiment, in the case of an analog chemical sensor, the "clock" provided to the sensor can be a "channel increment / decrement signal" - thereby allowing synchronization of channel switching and ADC sampling.

[0247] Fig.48 A block diagram 4800 illustrating the power distribution of system components according to one embodiment of the present invention is shown. An APC power supply 4802 can be coupled to an AC input. A valve board 4804 (e.g., valve board 4212 of system architecture 4200) can receive power from the PC power supply 4802 via two 4-pin connectors. A motherboard 4806 (e.g., motherboard 4202 of system architecture 4200) can receive power from the PC power supply 4802 via two 8-pin connectors and one 24-pin connector. The 24-pin cable used to power the motherboard 4806 can be "Y-cabled" and also power a readout board 4808 (e.g., readout board 4210 of system architecture 4200, which can be an analog readout board (e.g., 4300) or a digital readout board (e.g., 4400)). The readout board 4808 may include an on-board power supply 4810, which may include a plurality of power regulators (e.g., low runaway linear regulators, programmable output low runaway regulators) and / or DC / DC power supplies (e.g., high voltage high current DC / DC power supplies). In one embodiment, all DC / DC switching power supplies may be synchronized with a master readout board clock. This may keep any switching noise from the power supplies from being "beating" relative to clocks used elsewhere. Additionally, the clocks for the switching power supplies may be timed so that the instantaneous current load on the PC power supply is minimized.

[0248] Fig.49A block diagram 4900 of a DAC of an analog readout board according to one embodiment of the present invention is illustrated. The DAC configuration 4900 may include: a voltage reference 4902, a DAC 4904, a low pass filter including a resistor 4906 and a capacitor 4908. The filtered signal may be amplified by an operational amplifier 4910. The output from the operational amplifier 4910 may be filtered by a bead 4912 and a plurality of capacitors 4914 (e.g., a bulk LPF / LF charge). The filtered signal may then be sent to a first input of an operational amplifier 4916.1-4916.4 via a local decoupling circuit (e.g., a capacitor 4918 and a corresponding resistor 4920). A second input to the operational amplifier 4916.1-4916.4 may be a corresponding channel input 4924.1-4924.4. The output of the operational amplifier 4916.1-4916.4 may be fed back to the first input via a corresponding feedback resistor 4922.1-4922.4. In one embodiment, multiple DACs may be provided for channel offset, reference voltage, electrode driver, built-in self-test (BIST) driver, and ISFET bias.

[0249] Fig.50A block diagram of an FPGA configuration of an analog readout board 5000 according to an embodiment of the present invention is explained. The analog readout board 5000 may be an embodiment of the analog readout board 4300. The analog readout board 5000 may include a plurality of ADC modules 5002.1 and 5002.2, two satellite FPGAs 5004.1 and 5004.2 (e.g., satellite FPGAs 4320 and 4322), a reader FPGA 5006 (e.g., reader FPGA 4310) and its memory modules 5008.1 and 5008.2, an APCIe switch 5010 (e.g., PCIe switch 4316), an analog chemical sensor 5012 (e.g., analog chemical sensor 4302), an LVDS driver and receiver 5014 (e.g., LVDS 4308), and a plurality of DAC modules 5016 and 5018. In one embodiment, each ADC of the ADC modules 5002.1 and 5002.2 may include a PLL. The satellite FPGAs 5004.1 and 5004.2 can perform sample averaging, which can be controlled by the Dstrobe signal from the reader FPGA 5006 and software settings in the satellite FPGAs 5004.1 and 5004.2. In addition, in one embodiment, the control logic of the reader FPGA 5006 can be loaded from the memory module 5008.1 and / or 5008.2, which can be a SPI flash device (e.g., EEPROM) that holds 2 images: (1) a default "load" image, and (2) a current run time image. The control logic (e.g., images) of the satellite FPGAs 5004.1 and 5004.2 can be loaded by the reader FPGA 5006 from the motherboard (e.g., motherboard 4202) over PCIe. In addition, in one embodiment, the FPGA (including the valve FPGA 4214) can be deconfigured and reloaded through an APCIe reset. And, once the PCIe FPGA can be programmed, a PCI count can be triggered.

[0250] Fig.51A block diagram of FPGA power monitoring of a readout board 5100 according to one embodiment of the present invention is explained. The readout board 5100 can be an embodiment of the readout board 4808. The readout board 5100 can include a power module 5102 (e.g., power supply 4810) that receives 5V and 12V inputs from a 24-pin connector 5106. The power module 5102 can provide power to the rest of the reader 5104. The output voltage from the power module 5102 can be monitored by multiple voltage monitors 5108 and 5112. The first voltage monitor 5108 can receive its power supply VCC from the 24-pin connector 5106 and generate a reset RST signal if one of the monitored voltages (including VCC) deviates from a predetermined voltage level by more than a certain threshold (e.g., 1.5% deviation). The RST signal from the voltage monitor 5108 can be "ORed" with the reset signal from the APCIe connector 5110 by an OR gate 5116. The output of the OR gate 5116 can be input as a monitored voltage of a second voltage monitor 5112, which can also receive its power supply VCC from the 24-pin connector 5106 and generate a reset RST signal if one of the monitored voltages (including VCC) deviates from a predetermined voltage level by more than a certain threshold (e.g., 1.5% deviation). The RST signal from the voltage monitor 5112 can be sent to the clock driver 5114, which can generate a reset signal and an nCONFIG signal to the rest of the reader 5104. The reset signal from the clock driver 5114 can be sent to the APCIe switch of the readout board. The nCONFIG signal from the clock driver 5114 can be sent to the FPGA of the readout board to cause the FPGA to reload. In one embodiment, ORing the RST signal from the voltage monitor 5108 with the reset signal from the PCIe connector 5110 can ensure that the nCONFIG pulse width requirement is met.

[0251] Column ADC and Serializer Circuit

[0252] The described embodiments may provide a chemical detection circuit that may include a column of chemically sensitive pixels. Each chemically sensitive pixel may include a chemically sensitive transistor and a row selection device. The chemical detection circuit may further include: a column interface circuit coupled to the column of chemically sensitive pixels, and an analog-to-digital converter (ADC) coupled to the column interface circuit.

[0253] Some embodiments may also provide a chemical sensor, which may include a plurality of chemically sensitive pixel columns. Each column may include a plurality of chemically sensitive pixels forming a row. Each chemically sensitive pixel may include a chemically sensitive transistor and a row selection device. The chemical sensor may further include: a column interface circuit coupled to the chemically sensitive pixel column, and an analog-to-digital converter (ADC) coupled to the column interface circuit.

[0254] Other embodiments may provide a method for generating an output signal of a chemical detection circuit. The method may include: generating a row select signal by a row decoder of the chemical detection circuit. The chemical detection circuit may have a pixel array, and the pixel array includes a chemical detection pixel column. Each chemical detection pixel may include a chemically sensitive transistor and a row select device. The method may further include: applying the row select signal to the corresponding row select device of the selected chemical detection pixel, converting the analog signal at the readout signal line of the chemical detection pixel column into a digital signal through an analog-to-digital converter (ADC), and outputting the converted digital signal as the output signal of the chemical detection circuit.

[0255] The described embodiments may further provide a chemical detection circuit, which may include a pixel array, the pixel array including a plurality of chemically sensitive pixels forming columns and rows. Each chemically sensitive pixel may include a chemically sensitive transistor and a row selection device. The chemical detection circuit may further include: a pair of analog-to-digital converter (ADC) circuit blocks, a pair of input / output (I / O) circuit blocks respectively connected to the pair of ADC circuit blocks, and a plurality of serial connection line terminals connected to the pair of I / O circuit blocks.

[0256] The described embodiments may additionally provide a method of reading out data from a chemical detection device. The method may include: reading out data in parallel from a plurality of chemically sensitive pixel columns of a chemical detection device. Each chemically sensitive pixel may include a chemically sensitive transistor and a row selection device. The method may additionally include: digitizing the data read out from the plurality of chemically sensitive pixel columns in parallel, serializing the parallel digitized data for each chemically sensitive pixel column separately, and transmitting the buffered digitized data in parallel to a plurality of serial connections.

[0257] Fig.52A digital chemical detection circuit 5200 according to one embodiment of the present invention is explained. The digital chemical detection circuit 5200 can be an IC chip, and the IC chip includes: a pixel array 5202, row decoders 5204.1 and 5204.2, column ADCs 5206.1 and 5206.2, an I / O circuit 5208.1, a plurality of bias circuits 5210.1-5210.3, a timing meter 5212 and 5208.2, and a plurality of output line terminals D[0]-D[N-1]. The pixel array 5202 can include chemical detection pixels forming columns, wherein each column includes a plurality of pixel rows. In one embodiment, the pixel array 5202 can include a plurality of pixel panels, and the panels can be placed in a sheet, as described above with respect to Fig.37 The row decoders 5204.1 and 5204.2 may generate row select signals for pixel rows based on control logic.

[0258] In one embodiment, column ADCs 5206.1 and 5206.2 may include multiple ADCs, each corresponding to a column. In another embodiment, column ADCs 5206.1 and 5206.2 may include multiple ADCs, and each ADC may be shared among several columns (e.g., using one or more multiplexers). In addition, in one embodiment, the column ADCs 5206.1 and 5206.2 may perform skew cancellation.

[0259] The bias circuits 5210.1-5210.3 can generate all bias and reference voltages required by the chemical detection circuit 5200 on the chip. That is, the chemical detection circuit 5200 does not need to have any external analog reference. The bias circuits 5210.1-5210.3 may require an external power supply (such as VDDA) to function. The timing meter 5212 can provide internal timing signals for the chemical detection circuit 5200.

[0260] The multiple output line terminals D[0]-D[N-1] can provide a serial connection with one or more devices outside the IC chip. The serial connection can use a printed circuit board transmission line. The signaling on the transmission line can use a differential signal or a CMOS signaling. The differential signal can be any differential signal scheme, for example, a low voltage differential signal (LVDS) or a current mode logic (CML). In one embodiment, half of the output pins can be placed on one side of the chip 5200, and the other half can be placed on the opposite side. The number N can be an even number (for example, 24, 32). In addition, in one embodiment, the serial interface can be programmable. For example, the strength of the driver can be programmed and modulated for a given system. The driver type (LVDS, CML, CMOS) can also be programmed. In addition, termination on the chip can be activated or eliminated. Different aspects of the scheme can be constructed, such as stroke length control and format.

[0261] Fig.53 According to one embodiment of the present invention, Fig.52 A more detailed block diagram of the output circuit of the digital chemical detection circuit 5300 is shown. Fig.53 As shown, column interface 5302 can be connected to a pixel array (e.g., pixel array 5202) to read out data of the pixel array. Column comparator 5304 can include multiple comparators (e.g., ADC). In one embodiment, column comparator 5304 can perform deviation cancellation.

[0262] DACs 5312.1 and 5312.2 may provide reference voltages for column comparators 5304 to perform analog-to-digital conversions. A pair of latch circuit blocks 5306 and 5308 may provide buffers for output data. The digitized data may be sent from the column comparator first to the A latch circuit 5306 and then from the A latch circuit 5306 to the B latch circuit 5308, according to control provided by Gray code blocks 5314.1 and 5314.2. A plurality of output serializers 5310.1-5310.n may be coupled between the buffers and output line terminals D[0]-D[n-1] (e.g., n=N / 2). The Gray code circuits 5314.1-5314.2 may distribute digital counts to all latch circuits controlled by the comparator 5304 so that the Gray code may be latched in memory when a given comparator switches. The Gray code can be set to count synchronously with the DAC ramp circuit, which establishes a total reference for all comparators of comparator 5304. When the total reference drops below the pixel value held in a given column, the corresponding comparator can be activated. Since the comparators can switch asynchronously with the clock, the count can be distributed with a Gray code, where only one bit transition is made at any time to avoid invalid codes.

[0263] In one embodiment, each output line terminal may include 2 pins for differential signaling (e.g., low voltage differential signaling). In one embodiment, the A latch line 5306 may be a master latch line, and the B latch line 5308 may be a slave latch line. The latch lines may allow analog-to-digital conversion to run in parallel to the readout of the previous conversion line.

[0264] On-chip bias and reference voltages may be provided by bias and reference circuit block 5316. Fig.53 As shown, bias and reference circuit block 5316 can provide bias and reference voltages to column interface circuit 5302, DACs 5312.1 and 5312.2, and Gray code circuits 5314.1-5314.2. Fig.53 As shown, the timing instrument circuit 5320 can provide timing signals to the Gray code circuits 5314.1-5314.2, DACs 5312.1-5312.2, row decoders 5318.1-5318.2, pixel controllers, and column controllers. The timing instrument 5320 can be connected to the pins TMODE, TEN, RST for reset and test modes. The timing instrument 5320 can also be connected to the pins SDA, SCL, CLK for programming registers (using a serial scheme such as SPI). The timing instrument 5320 can control all timing on the chip as follows: advance each row in the frame period and provide stimulation to the circuit in each row time. Because the pixel can operate in many different ways, the timing instrument 5320 can be reprogrammed to change the operation of the control signal.

[0265] Fig.54 A serializer circuit 5400 according to one embodiment of the present invention is explained. The serializer circuit 5400 may include a plurality of shift registers 5402, a bit alignment logic 5406, a pair of switch registers 5406, a multiplexer 5408 for selecting one of the switch registers, a multiplexer 5410 for multiplexing the output from the multiplexer 5408 and a built-in self test (BIST), an encoder 5412, a serializer 5416, and a driver 5418.

[0266] Shift register 5402 may be part of an I / O buffer. In one embodiment, Fig.54 As shown, a 14-bit shift register can be used. The data transferred from the shift register can be sent to the bit alignment logic 5406, where the data can be compared. For example, according to the comparison control, 14-bit data can be compared with 8-bit data. The comparison data from the comparison logic 5406 can be sent to the pair of switch registers 5406, which lock each parallel word containing timing overlap to prevent false signals in the data.

[0267] Then, multiplexer 5408 can select one of the pair of switch registers 5406 to output its data to multiplexer 5410. The multiplexer 5410 can select the output data from multiplexer 5408 or the BIST data to be sent to encoder 5412. In order to achieve DC balance, a coding scheme such as 8b / 10b can be used. Thus, in one embodiment, encoder 5412 can be an 8B10B encoder. It should be noted that other coding schemes can also be used. The encoded data from encoder 5412 can be serialized in serializer 5413 and sent out by driver 5418. In one embodiment, the serializer 5413 can be driven by a PLL clock signal. In one embodiment, the driver 5418 can be configured to transmit data signals by low voltage differential signals. In one embodiment, the driver 5418 can work in differential mode, wherein 1 bit can be transmitted at each transmission clock signal, and the pair of output pins can carry differential data pairs. In another embodiment, the driver 5418 can operate in a dual channel mode, where the output pair of the output line terminals can transmit 2 bits in parallel in each transmit clock cycle.

[0268] Fig.55 A more detailed block diagram 5500 is explained. Fig.55 As shown, the serializer 5413 can include multiple registers 5502, a pair of multiplexers 5504, a pair of registers 5506, a multiplexer 5508 and a buffer register 5510. The registers 5502 can each retain one bit of the encoded data. The registers 5502 can operate at a clock speed of 1 / 10 of the PLL clock signal. The output from the register 5502 can be sent to the pair of multiplexers 5504. Each multiplexer 5504 can generate an output, which will be sent to one of the pair of registers 5506. The pair of registers 5506 can run at half the clock speed of the PLL clock signal. The output from the pair of registers 5506 can be input to the multiplexer 5508, which can select one of the outputs from the pair of registers 5506 as an output. The output from the multiplexer 5508 can be sent to the buffer register 5510. The buffer register 5510 can run at the clock speed of the PLL clock signal to send its content to the driver 5418.

[0269] Fig.56 A block diagram of a digital chemical detection circuit according to an embodiment of the present invention is explained. Fig.56 One design of a digital chemical detection circuit according to one embodiment of the present invention is shown.

[0270] Fig.57 A block diagram of another digital chemical detection circuit according to an embodiment of the present invention is explained. Fig.56 Another design of a digital chemical detection circuit according to an embodiment of the present invention is shown.

[0271] Fig.58 A block diagram of another digital chemical detection circuit 5800 according to an embodiment of the present invention is explained. The digital chemical detection circuit 5800 may include a pixel array 5802, a plurality of output circuits 5804.1-5804.2, a plurality of serial output circuits 5806.1-5806.2, a plurality of row selection circuits 5808.1-5808.2, a clock tree 5810, and a plurality of thermometers 5812. The pixel array 5802 may be Fig.14A The 2T pixel array 1400 shown in FIG. 1 includes multiple Fig.14A The row selections 5808.1-5808.2 may be as described above with respect to Figure 52-53 Furthermore, the output circuits 5804.1-5804.2 may include: column interface, deviation cancellation and column ADC, as described above with respect to Figure 52-53 The serial output circuits 5806.1-5806.2 may include the above Figure 52-55 The clock tree 5810 can be the serializer circuit shown above. Figure 52-53 An embodiment of the timing instrument. In one embodiment, the digital chemical detection circuit 5800 may include four thermometers placed on the chip. In addition, in one embodiment, the four thermometers may be placed at or near the four corners of the pixel array 5802.

[0272] Several embodiments of the present invention are specifically explained and described herein. However, it should be understood that the above teachings cover improvements and variations of the present invention. In other cases, well-known operations, components and circuits are not described in detail to avoid affecting the understanding of the embodiments. It is understood that the specific structural and functional details disclosed herein may be representative and do not necessarily limit the scope of the embodiments. For example, some embodiments are described using NMOS. The technician will understand that PMOS may also be used.

[0273] Those skilled in the art will appreciate from the foregoing description that the present invention can be implemented in a variety of forms, and that the various embodiments can be implemented individually or in combination. Therefore, although the embodiments of the present invention have been described in conjunction with their specific examples, the true scope of the embodiments and / or methods of the present invention should not be so limited, as other modifications will become apparent to the skilled practitioner after studying the drawings, the specification, and the following claims.

[0274] Each embodiment can be implemented using hardware elements, software elements or their combination. Examples of hardware elements may include: processors, microprocessors, circuits, circuit elements (such as transistors, resistors, capacitors, inductors, etc.), integrated circuits, application specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software may include: software components, programs, applications, computer programs, applications, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, processes, software interfaces, application program interfaces (APIs), instruction sets, computing codes, computer codes, code segments, computer code segments, words, values, symbols or any combination thereof. Determine whether an embodiment is implemented using hardware elements and / or software elements, which may be changed according to any number of factors, such as desired computing rates, power levels, heat resistance, processing cycle budgets, input data rates, output data rates, memory resources, data bus speeds, and other design or performance limitations.

[0275] Some embodiments may be implemented, for example, using a computer-readable medium or product, which may store instructions or instruction sets that, if executed by a machine, cause the machine to perform methods and / or operations according to the embodiments. Such a machine may include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, processor, etc., and may be implemented using any suitable combination of hardware and / or software. The computer-readable medium or product may include, for example, any suitable type of memory unit, memory device, memory product, memory medium, storage device, storage product, storage medium and / or storage unit, such as memory, removable or non-removable media, erasable or non-erasable media, writable or rewritable media, digital or analog media, hard disk, floppy disk, compact disk read-only memory (CD-ROM), recordable compact disk (CD-R), rewritable compact disk (CD-RW), optical disk, magnetic media, magneto-optical media, removable memory card or disk, various types of digital versatile disks (DVD), magnetic tape, cassette tape, etc. The instructions may include any appropriate type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, etc., implemented using any appropriate high-level, low-level, object-oriented, visual, compiled and / or interpreted programming language.

Claims

1. A chemical sensor chip, comprising: An array of chemically-sensitive pixels arranged in a plurality of columns and a plurality of rows, each chemically-sensitive pixel comprising: Chemically sensitive transistors; and Row selection device; A chemical detection circuit on a chip, comprising: a column interface circuit coupled to the plurality of columns of chemically-sensitive pixels; and An analog-to-digital converter (ADC) circuit is coupled to the column interface circuit. 2 . The chemical sensor chip according to claim 1 , wherein the chemically sensitive transistor is an ion sensitive field effect transistor (ISFET). The chemical sensor chip according to claim 2 , wherein the ISFET is sensitive to hydrogen ion concentration. 4 . The chemical sensor chip of claim 2 , wherein each pixel in the array of chemically sensitive pixels comprises a floating gate structure located between each gate oxide and each corresponding passivation layer.

5. The chemical sensor chip of claim 4, wherein the output signal from a pixel in the array of chemically sensitive pixels is directly related to the change in threshold voltage.

6. The chemical sensor chip of claim 1, wherein each chemically sensitive pixel is a two-transistor (2T) pixel. 7 . The chemical sensor chip according to claim 6 , wherein each 2T pixel is configured in a source follower readout mode.

8. The chemical sensor chip according to claim 1, wherein the chemical detection circuit further comprises: a bias and reference circuit configured to provide bias and reference voltages to the column interface circuit; as well as A timing machine is configured to control all timings on the chemical sensor chip. 9 . The chemical sensor chip according to claim 8 , wherein the timing meter provides timing signals to the Gray code circuit, the row decoder, the pixel controller, and the column controller. 10 . The chemical sensor chip according to claim 1 , wherein the chemical detection circuit further comprises a serializer output circuit coupled to a plurality of output terminals. 11 . The chemical sensor chip according to claim 10 , wherein each of the plurality of output terminals comprises two pins for a differential signal.

12. The chemical sensor chip according to claim 1, wherein the on-chip chemical detection circuit further comprises: a first column interface circuit on a first side of the chemical sensor chip coupled to a first half of the columns of chemically sensitive pixels, wherein a first ADC circuit is coupled to the first column interface circuit; as well as A second column interface circuit on an opposite second side of the chemical sensor chip; the second column interface circuit is coupled to a second half of the columns of chemically sensitive pixels, wherein a second ADC circuit is coupled to the second column interface circuit.

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