A method for efficiently measuring transistor gate dielectric breakdown

Abstract

The present invention proposes a method for efficiently measuring the breakdown of transistor gate dielectrics. The method belongs to the technical field of semiconductor device testing; the method comprises: when designing the layout of the chip, introducing WL, BL and SL dedicated to the test; in the test stage, applying high-level signals to all SL lines, and then applying high-level signals to all WL lines in turn, to detect whether the gate dielectric of the MOS tube is broken down; if it is determined that there is a failed transistor in the chip, the specific failed transistor is further located, and high-level signals are applied to all SL lines again, and high-level signals are applied to each WL line in turn, and the output of each BL line is observed. Through the systematic test steps, the failure point of the transistor gate dielectric can be quickly located, reducing the test time and labor costs.

Description

Technical Field

[0001] The invention provides a method for efficiently measuring transistor gate dielectric breakdown, belonging to the technical field of semiconductor device testing. Background Art

[0002] As time goes by, integrated circuit products will inevitably be damaged. The components in the integrated circuit begin to degrade after they are manufactured, until some key components degrade to a certain extent and the integrated circuit can no longer be used. The method of using passive screening to detect product reliability is costly and time-consuming, and it cannot fundamentally improve the reliability of semiconductor integrated circuits.

[0003] To reduce the cost of each device and improve performance, device geometries continue to shrink, with device feature sizes shrinking by 0.7 times the current node, following Moore's Law, and playing a vital role in the success of semiconductors. This shrinkage leads to higher electric fields in materials, bringing materials closer to their breakdown strength and higher current density in metals, causing electrical migration (EM) problems. Higher electric fields can exacerbate reliability issues such as time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI), and bias temperature instability (BTI).

[0004] Time-dependent gate dielectric breakdown (TDDB) is an important and common integrated circuit failure phenomenon. It refers to the leakage or breakdown of the gate dielectric layer of MOS devices due to various reasons under strong electric fields, leading to device failure. It is generally believed that the failure mechanism is: after a relatively long period of defect accumulation, bonds are broken and vacancies are formed. Due to severe current problems, catastrophic thermal runaway occurs, and the dielectric layer eventually breaks down. This local high-density current and the associated severe Joule heat will cause a filamentary conductive path to form in the dielectric, short-circuiting the originally isolated polysilicon gate and substrate in the MOSFET device, thereby short-circuiting the anode and cathode. Gate dielectric breakdown will cause integrated circuit failure, so an efficient method for measuring transistor gate dielectric breakdown can improve the reliability of semiconductor integrated circuits and continuously produce highly reliable IC products. Summary of the invention

[0005] The present invention provides a method for efficiently measuring transistor gate dielectric breakdown to solve the following technical problems:

[0006] 1) In order to reduce the cost of each chip and improve performance, the geometric size of transistors continues to shrink, so the difficulty of testing transistors continues to increase. It is impossible to directly apply voltage or current to the transistor to test the transistor.

[0007] 2) As the geometric size of transistors inside chips continues to shrink, the integration of chips continues to increase, and how to efficiently test so many transistors is also a problem.

[0008] 3) Through functional testing of the chip, we can determine whether the chip is failed, but there is no way to find out which transistor failed. If the failed transistor can be found, we can analyze whether it is a problem with the size of the transistor or the process during design, so as to optimize it.

[0009] The present invention provides a method for efficiently measuring gate dielectric breakdown of a transistor, the method comprising:

[0010] S1. When designing the chip layout, introduce test-specific WL, BL and SL;

[0011] S2. In the test phase, a high level signal is applied to all SL lines, and then a high level signal is applied to all WL lines in turn to detect whether the gate dielectric of the MOS tube is broken down;

[0012] S3. If it is determined that there is a failed transistor in the chip, further locate the specific failed transistor, and apply a high level signal to all SL lines again, and apply a high level signal to each WL line in turn, and observe the output of each BL line;

[0013] S4, determining the specific location of the failed transistor by comparing the output of the BL line when different WL lines are activated;

[0014] S5. After locating the failed transistor, check the relevant parameters of the failed transistor and conduct an in-depth analysis of the failure cause. Based on the analysis results, determine the specific cause of the gate dielectric breakdown and perform optimization and improvement.

[0015] Furthermore, the S1 includes:

[0016] S11. Perform basic circuit layout planning according to chip functional requirements, and reserve an area specifically for gate dielectric breakdown testing at the chip edge or in a specific test layer;

[0017] S12. In the test area, design multiple independent WLs, each WL being connected to gates of multiple MOS transistors;

[0018] S13 and BL are connected to the drain of the MOS transistor, and SL is connected to the source. Mark the test circuit in the layout file.

[0019] Furthermore, the S2 includes:

[0020] S21, applying a high level signal higher than the normal operating voltage to all SL lines to ensure that all sources are in a high potential state;

[0021] S22, applying high-level signals to all WL lines one by one through programming control to simulate the gate voltage during normal operation;

[0022] S23. After each activation of WL, the output states of all BL lines are detected; if all BL lines output a high level, the gate dielectric of the corresponding MOS tube is not broken down.

[0023] S24. If a certain BL line outputs a low level, the combination of WL and BL is recorded and marked as a potential failure point.

[0024] Furthermore, the S22 includes:

[0025] Determine the specific value of the gate voltage Vgg according to the chip specification and design requirements; the specific value of Vgg is higher than the normal operating voltage but lower than the breakdown voltage of the gate dielectric;

[0026] Set the voltage step, that is, instead of raising the gate voltage to Vgg all at once, increase it gradually in certain steps, and observe and record the BL line output state at each step;

[0027] Based on the test script, the WL line is programmed and controlled by the automated test equipment;

[0028] According to the test script, apply high-level signals to all WL lines one by one; and before applying voltage each time, ensure that all SL lines are in a high potential state;

[0029] While applying the voltage, the output status of all BL lines is monitored in real time through the built-in sensors of the ATE;

[0030] After applying the gate voltage, keep it for a while and check whether the voltage is stable; if the voltage fluctuation exceeds the allowable range, readjust the voltage source or test equipment;

[0031] Perform multiple gate voltage application and removal cycle tests on some WL lines to evaluate the reliability of gate dielectrics under long-term operation;

[0032] During the test, if a BL line is found to output a low level, the current WL line test will be stopped immediately, and the combination of WL and BL will be marked as a potential failure point;

[0033] Record key information when the anomaly occurs, conduct a preliminary analysis of the anomaly, and determine whether it is caused by gate dielectric breakdown.

[0034] Furthermore, the S3 includes:

[0035] S31. Based on the result of S2, retest the WL-BL combination marked as potential failure, repeat the steps of S2 multiple times, and activate only one WL each time, while observing and recording the responses of all BLs;

[0036] S32, by changing the voltage state of SL and monitoring the change of BL response, the location range of the failed transistor is further narrowed;

[0037] S33, and during the test, the exact failure location is marked on the chip surface using non-destructive means.

[0038] Furthermore, the S4 includes:

[0039] S41, collecting all test data, and establishing a test database based on the collected test data;

[0040] S42, analyzing the data in the test database by using a data analysis algorithm, and identifying the failure mode based on the analysis results;

[0041] S43, performing an IV characteristic test on the located failed transistor, and evaluating the degree of gate dielectric damage based on the characteristic test result;

[0042] S44. Based on high-precision imaging technology, the microstructure of the failed transistor is analyzed through machine vision algorithms, and physical damage or defects are judged based on the analysis results.

[0043] Furthermore, the S42 includes:

[0044] Use statistical methods to test outliers in the test data, mark and remove the detected outliers;

[0045] Unify the format of relevant information in the test data, count the number of failures of each WL or BL combination in the test database, and identify combinations that frequently fail;

[0046] Use clustering algorithms to group test data and identify groups with similar failure characteristics;

[0047] The association relationships in the test data are analyzed by association rule mining algorithm to identify the potential connections between WL activation sequence, BL response and SL status, as well as the correspondence between these connections and failure modes;

[0048] For test data with time series characteristics, time series analysis techniques are used to identify trends and periodic laws of failure modes;

[0049] Failure modes identified through data analysis are validated and prioritized by combining process knowledge, design documents and historical experience.

[0050] Furthermore, the S43 includes:

[0051] The IV test equipment is calibrated using standard samples, and a series of gradually increasing voltages are applied to the gate while monitoring the change in drain current. When the drain current begins to increase significantly, the corresponding gate voltage is the threshold voltage. The threshold voltage value of each failed transistor is recorded and compared with the threshold voltage of a normal transistor.

[0052] Under a fixed gate voltage, measure the magnitude of the drain current; record the drain current value of each failed transistor and analyze its difference with the drain current of a normal transistor;

[0053] Repeated threshold voltage and leakage current tests at different temperatures to evaluate the temperature dependence of gate dielectric damage;

[0054] comparing the threshold voltage of the failed transistor with the threshold voltage of the normal transistor, and calculating the threshold voltage offset;

[0055] Calculate the leakage current density based on the leakage current value and the effective channel area of ​​the transistor;

[0056] Based on the test results of threshold voltage offset and leakage current density, combined with process experience and historical data, the degree of gate dielectric damage is graded;

[0057] Record the IV characteristic test results of each failed transistor, conduct in-depth analysis of the test results, and identify the common characteristics of failed transistors.

[0058] Furthermore, the S44 includes:

[0059] Failed transistor samples from the test database are processed accordingly, and imaging technology is selected based on the expected damage type and scale of the failed transistors;

[0060] Using SEM and / or TEM to image the microstructure of the failed transistor and collect high-quality image data; preprocessing the collected images, wherein the preprocessing includes denoising, contrast enhancement, and edge detection;

[0061] Use machine vision algorithms to extract key features from images, match the extracted features with a known library of physical damage or defect features, and identify the specific physical damage or defect type in the failed transistor;

[0062] Based on the results of feature matching and classification, the degree of physical damage in the failed transistor is evaluated. The physical damage analysis results are combined with the previous failure mode identification and IV characteristic test results to explore the failure mode and mechanism of the failed transistor.

[0063] Record the microstructure analysis results of each failed transistor and prepare a failure analysis report based on the analysis results.

[0064] Furthermore, the S5 includes:

[0065] S51. Analyze specific factors that may cause gate dielectric breakdown based on the size and process parameters of the failed transistor;

[0066] S52. Formulate process improvement measures based on the analysis results, wherein the process improvement measures include adjusting the oxidation temperature and optimizing the doping process;

[0067] S53. In subsequent designs, redundant structures will be added, a long-term gate dielectric quality monitoring system will be established, and the test process and results will be reviewed regularly.

[0068] The beneficial effects of the present invention are as follows: through systematic testing steps, the failure point of the transistor gate dielectric can be quickly located, reducing testing time and labor costs; by activating the WL lines one by one and observing the output of the BL lines, the position of the failed transistor can be accurately determined, reducing the ambiguity of the traditional method; by combining IV characteristic testing and microstructure analysis, the damage degree of the gate dielectric and its failure mechanism can be comprehensively evaluated, promoting product improvement; establishing a test database and applying a data analysis algorithm are helpful to identify frequent failure modes and provide a basis for subsequent process improvements; based on the failure analysis results, targeted design and process optimization can be carried out to improve the reliability and production yield of the transistor; by establishing a quality monitoring system and regular review, the quality control of the gate dielectric can be continuously improved, and the failure risk of future products can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1 It is a step diagram of the method of the present invention;

[0070] Figure 2 A schematic diagram of the test structure of the method for testing transistor gate dielectric breakdown provided by the present invention. DETAILED DESCRIPTION

[0071] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0072] One embodiment of the present invention, as Figure 1 As shown, a method for efficiently measuring gate dielectric breakdown of a transistor, the method comprising:

[0073] S1. When designing the chip layout, the test-specific WL (WordLine), BL (BitLine) and SL (SourceLine) are introduced. These lines are specially reserved during the chip manufacturing process for subsequent testing;

[0074] S2. In the test phase, a high-level signal is applied to all SL lines, and then a high-level signal is applied to all WL lines in turn. At this time, if all BL lines output a high-level signal, it proves that all MOS tubes connected to the WL line have no gate dielectric breakdown; if a BL line outputs a low-level signal, it indicates that the MOS tubes connected to the WL line and the BL line have gate dielectric breakdown;

[0075] S3. If it is determined that there is a failed transistor in the chip, the specific failed transistor is further located. At this time, a high-level signal is applied to all SL lines again, and then a high-level signal is applied to each WL line in turn, and the output of each BL line is observed;

[0076] S4, determining the specific location of the failed transistor by comparing the output of the BL line when different WL lines are activated;

[0077] S5. After locating the failed transistor, check the relevant parameters of the failed transistor, including size and process parameters, and conduct in-depth analysis on the cause of the failure. Based on the analysis results, determine the specific cause of the gate dielectric breakdown, and perform optimization and improvement.

[0078] The working principle of the above technical solution is as follows: in the chip design stage, WL (word line), BL (bit line) and SL (source line) are specially designed and reserved for testing. These lines do not participate in calculations or data storage in normal chip functions, but they are crucial for detecting and locating gate dielectric breakdown in the test stage. In the test stage, first apply a high-level signal to all SL lines to ensure that all sources are in a high potential state. Then, apply a high-level signal to all WL lines in turn; since the WL line controls the gate of the MOS tube, when the WL line is activated, the MOS tube connected to it should be turned on. If all BL lines output a high-level signal, all MOS tubes connected to the WL line are in normal working state, and the gate dielectric has not been broken down; if a BL line outputs a low-level signal, it indicates that the gate dielectric of the MOS tube connected to the WL line and the BL line has been broken down, resulting in the MOS tube being unable to be turned on normally. Once it is determined that there is a failed transistor in the chip, more precise positioning is required. By applying a high-level signal to all SL lines again, and applying a high-level signal to each WL line in turn, while observing the output of each BL line. By comparing the output of the BL line when different WL lines are activated, it is possible to determine which BL lines are connected to the failed transistor, thereby locating the specific location of the failed transistor. After locating the failed transistor, it is necessary to check its related parameters, including size and process parameters. By deeply analyzing the parameters and process of the failed transistor, the specific cause of the gate dielectric breakdown can be determined. Based on the analysis results, the chip design or manufacturing process can be optimized and improved to prevent similar problems from occurring in the future.

[0079] The effects of the above technical solution are as follows: through dedicated test lines (WL, BL, SL) and orderly test steps, the solution can quickly locate the transistor where the gate dielectric breakdown occurs, avoiding the inefficiency and time-consuming test of each transistor in the traditional method; by applying a high-level signal to all SL lines at the same time, and then testing all WL lines in turn, the states of a large number of transistors can be checked in parallel, thereby improving the test efficiency; when a certain BL line outputs a low-level signal when the corresponding WL line is activated, it directly indicates that the MOS tube connected to the WL line and the BL line has a gate dielectric breakdown, providing clear failure information; since the test is based on direct measurement of electrical signals, the method has a high sensitivity to gate dielectric breakdown and can detect tiny breakdown events; after locating the failed transistor, by checking its related parameters (such as size, process parameters, etc.) and conducting an in-depth analysis of the cause of failure, the specific factors leading to gate dielectric breakdown, such as process abnormalities, material defects, etc., can be revealed; based on the results of the failure analysis, the chip design or manufacturing process can be optimized and improved in a targeted manner to reduce the occurrence of gate dielectric breakdown in future products and improve product quality and reliability; Figure 2As shown, compared with the traditional transistor-by-transistor testing method, this scheme reduces the dependence on external test hardware and reduces the testing cost by integrating the test circuit; the ordered test steps and clear failure indications simplify the test process and reduce the operational complexity and time cost of the testers; due to the high efficiency and parallelism of the test process, this scheme is suitable for rapid quality inspection and failure analysis in large-scale production; the test-specific WL, BL and SL circuits can be easily integrated into the chip layout without affecting the normal function and adding additional manufacturing complexity.

[0080] In one embodiment of the present invention, the S1 includes:

[0081] S11. According to the functional requirements of the chip, basic circuit layout planning is performed, including logic units and storage arrays; an area dedicated to gate dielectric breakdown testing is reserved at the edge of the chip or in a specific test layer;

[0082] S12. In the test area, design multiple independent WLs, each WL being connected to gates of multiple MOS transistors;

[0083] S13 and BL are connected to the drain of the MOS transistor, and SL is connected to the source. Mark the test lines in the layout file, and take measures in the manufacturing process to protect them from accidental damage during processing.

[0084] The working principle of the above technical solution is as follows: according to the functional requirements of the chip, the layout planning of basic circuits such as logic units and storage arrays is carried out; an area dedicated to gate dielectric breakdown testing is reserved at the edge of the chip or in a specific test layer; this area is isolated from the main functional area of ​​the chip to ensure that the test process will not have any impact on the normal function of the chip; in the test area, multiple independent WL lines are designed; each WL line is connected to the gates of multiple MOS transistors to form a test network; through the carefully designed WL line layout, it is ensured that the test can cover all possible process variations, including transistors of different sizes, different gate dielectric materials, different manufacturing process steps, etc.; the BL line is connected to the drain of the MOS transistor, and the SL line is connected to the source; such a design enables each BL and SL line to be independently controlled, which is convenient for applying voltage signals during testing; the location and connection relationship of the test line are clearly marked in the layout file so that it can be accurately identified and operated in the subsequent manufacturing and testing process; measures are taken in the manufacturing process to protect the test line from accidental damage during processing. This may include using special protective layers, adjusting processing parameters, etc.

[0085] The effects of the above technical solution are: by reserving a test area at the edge of the chip or in a specific test layer and designing independent WL, BL and SL lines, the integration of test functions is achieved, avoiding the cumbersomeness of additional test hardware required in traditional test methods and improving test efficiency; each WL is connected to the gates of multiple MOS transistors, ensuring that the test can cover all possible process variations, helping to discover the potential risk of gate dielectric breakdown under different process conditions and improving test accuracy; because the test circuit is cleverly integrated in the chip, testing can be performed without additional test hardware, thereby reducing the cost of test hardware. The independent BL and SL circuit designs make the test process more concise and clear, reduce the test steps and complexity, and further reduce the test cost; measures are taken in the manufacturing process to protect the test circuit from accidental damage during the processing, ensuring the integrity and reliability of the test circuit; the test area is reserved at the edge of the chip or in a specific test layer, isolated from the main functional area, avoiding the impact of the test process on the normal function of the chip; by observing the output of the BL circuit, the transistor with gate dielectric breakdown can be quickly located, which facilitates the subsequent failure analysis; checking the relevant parameters of the failed transistor and deeply analyzing the cause of failure can reveal the specific factors leading to gate dielectric breakdown and provide strong guidance for process improvement; due to the high efficiency and parallelism of the test process, this solution is very suitable for rapid quality inspection and failure analysis in large-scale production; the design of the test circuit is easy to integrate into the chip layout and can be expanded as needed to meet the testing needs of chips of different scales and complexities.

[0086] In one embodiment of the present invention, the S2 includes:

[0087] S21, applying a high level signal (such as Vdd+Margin) higher than the normal operating voltage to all SL lines to ensure that all sources are in a high potential state;

[0088] S22, applying high level signals (such as Vgg) to all WL lines one by one through programming control to simulate the gate voltage during normal operation;

[0089] S23. After each activation of WL, the output states of all BL lines are detected; if all BL lines output a high level, the gate dielectric of the corresponding MOS tube is not broken down.

[0090] S24. If a certain BL line outputs a low level, the combination of WL and BL is recorded and marked as a potential failure point.

[0091] The working principle of the above technical solution is: apply a high-level signal (such as Vdd+Margin) higher than the normal operating voltage to all SL lines, where Vdd is the normal operating voltage of the chip, and Margin is an additional voltage margin to ensure that the test voltage is high enough to detect potential gate dielectric breakdown; through programming control, apply a high-level signal (such as Vgg) to all WL lines one by one, where Vgg is the simulated gate voltage. This voltage value is usually determined according to the design specifications and test requirements of the chip; after each activation of WL, the output state of all BL lines is detected. If all BL lines output a high level, it means that the gate dielectric of the corresponding MOS tube has not been broken down, because the breakdown of the gate dielectric will cause current leakage between the drain (Drain) and the gate, so that the BL line outputs a low level; if a BL line outputs a low level, the combination of the WL and BL is recorded and marked as a potential failure point. This means that the gate dielectric of the MOS tube connected to the WL and BL may have been broken down.

[0092] The effect of the above technical solution is: by applying high-level signals to all WL lines one by one and detecting the output states of all BL lines, the solution can fully cover all MOS tube gate dielectrics in the chip to ensure that none are missed; because the test voltage (Vdd+Margin) is higher than the normal operating voltage, the solution has a higher sensitivity to gate dielectric breakdown, and can detect tiny breakdown phenomena to avoid missed detection. Although the test is performed on the WL lines one by one, after each WL line is activated, the output states of all BL lines can be detected at the same time, realizing parallel testing and improving test efficiency. By programming and controlling the test process, the test is automated, reducing manual intervention and further improving test efficiency. When a BL line outputs a low level, the solution can accurately record the corresponding WL and BL combination, that is, the location of the failure point, providing accurate information for subsequent failure analysis. Accurate recording of failure points helps to quickly locate problems, analyze the causes of failure, and provide strong support for process improvement. The solution does not require additional test hardware, only requires reserving test lines during the chip design phase, reducing test costs. Through accurate testing, potential gate dielectric breakdown problems can be discovered in a timely manner, defective products can be prevented from entering the market, and product yield can be improved. During the test process, the test circuit is fully protected, additional damage caused by the test is avoided, and the reliability of the test is enhanced. Since the test voltage is higher than the normal operating voltage and the test process is strictly controlled, misjudgment caused by voltage fluctuations or interference is avoided.

[0093] In one embodiment of the present invention, the S22 includes:

[0094] Determine the specific value of the gate voltage Vgg according to the chip specification and design requirements; the specific value of Vgg is higher than the normal operating voltage but lower than the breakdown voltage of the gate dielectric;

[0095] Set the voltage step, that is, instead of raising the gate voltage to Vgg all at once, increase it gradually in certain steps, and observe and record the BL line output state at each step;

[0096] Based on the test script, the WL line is programmed and controlled by automated test equipment (such as ATE); the script should contain parameters such as test sequence, voltage step setting, test time, etc.

[0097] According to the test script, apply high-level signals to all WL lines one by one; and before applying voltage each time, ensure that all SL lines are in a high potential state;

[0098] While applying the voltage, the output status of all BL lines is monitored in real time through the built-in sensors of the ATE;

[0099] After applying the gate voltage, keep it for a while (such as a few seconds or minutes) to check whether the voltage is stable; if the voltage fluctuation exceeds the allowable range, readjust the voltage source or test equipment;

[0100] Perform multiple gate voltage application and removal cycle tests on some WL lines to evaluate the reliability of gate dielectrics under long-term operation;

[0101] During the test, if a BL line is found to output a low level, the current WL line test will be stopped immediately, and the combination of WL and BL will be marked as a potential failure point;

[0102] The key information when the abnormality occurs is recorded, and the key information includes the gate voltage value, the BL line output state and the test time, and a preliminary analysis is performed on the abnormality to determine whether it is caused by the breakdown of the gate dielectric.

[0103] The working principle of the above technical solution is as follows: according to the chip specification and design requirements, determine the specific value of the gate voltage Vgg, which should be higher than the normal operating voltage but lower than the breakdown voltage of the gate dielectric to ensure the effectiveness and safety of the test; in order to avoid excessive impact on the gate dielectric caused by the sudden application of high voltage, the gate voltage is gradually increased by voltage stepping. At each step, observe and record the output state of the BL line to detect abnormalities in time; program and control the WL line through the test script of the automated test equipment (ATE). The script contains parameters such as test sequence, voltage step setting, and test time to ensure the accuracy and repeatability of the test process; before applying the gate voltage, ensure that all SL lines are in a high potential state. Then, according to the test script, apply high-level signals to all WL lines one by one. While applying the voltage, the output state of all BL lines is monitored in real time through the built-in sensor of the ATE; after applying the gate voltage, keep it for a period of time (such as a few seconds or minutes) to check whether the voltage is stable. If the voltage fluctuation exceeds the allowable range, readjust the voltage source or test equipment to ensure the accuracy of the test; perform multiple gate voltage application and withdrawal cycle tests on some WL lines to evaluate the reliability of the gate dielectric under long-term operation, which helps to discover potential problems of the gate dielectric under long-term stress; during the test, if a BL line is found to output a low level, stop the current WL line test immediately and mark the combination of WL and BL as a potential failure point. At the same time, record the key information when the abnormality occurs, including the gate voltage value, BL line output status, and test time, so as to conduct a preliminary analysis of the abnormality. Perform a preliminary analysis of the recorded abnormal information to determine whether it is caused by gate dielectric breakdown. This helps to determine the nature of the problem and provides valuable clues for subsequent failure analysis and process improvement.

[0104] The effects of the above technical solution are as follows: according to the chip specification and design requirements, the specific value of the gate voltage Vgg is accurately determined to ensure that the test voltage is both higher than the normal operating voltage and lower than the breakdown voltage of the gate dielectric, thereby effectively detecting the breakdown of the gate dielectric; by setting the voltage step and gradually increasing the gate voltage with a certain step length, the performance of the gate dielectric under different voltages can be observed more carefully, thereby improving the accuracy and sensitivity of the test; while applying the voltage, the output status of all BL lines is monitored in real time through the built-in sensor of the ATE, so that anomalies can be discovered in time to ensure the accuracy of the test; based on the test script, the WL line is programmed and controlled through the automated test equipment (ATE), so as to realize the automation of the test, reduce manual intervention and improve the test efficiency; although the test is performed on the WL lines one by one, before each voltage is applied, it can be ensured that all SL lines are in a high potential state, and the ATE can monitor the output status of all BL lines at the same time, so as to realize a certain degree of parallel testing and further improve the test efficiency. During the test, if a BL line is found to output a low level, the current WL line test will be stopped immediately, and the key information when the abnormality occurs will be accurately recorded, including the gate voltage value, the BL line output state, and the test time, providing accurate data support for subsequent failure analysis; by accurately recording the abnormal information, the position of the MOS tube where the gate dielectric breakdown occurs, that is, the failure point, can be quickly located, providing strong support for subsequent repairs and improvements; multiple cycles of gate voltage application and withdrawal on some WL lines can evaluate the reliability of the gate dielectric under long-term work, providing a guarantee for the long-term stable operation of the chip. Through cycle testing, potential problems of the gate dielectric under long-term stress can be discovered, and timely measures can be taken to repair and improve it to prevent the occurrence of potential failures. Through automated testing and parallel testing, the test time is reduced and the test cost is reduced. Automated testing and accurate recording of abnormal information improve test efficiency and further reduce test costs.

[0105] In one embodiment of the present invention, S3 includes:

[0106] S31. Based on the result of S2, retest the WL-BL combination marked as potential failure, repeat the steps of S2 multiple times, and activate only one WL each time, while observing and recording the responses of all BLs;

[0107] S32, by changing the voltage state of SL (such as applying voltages or pulses of different magnitudes), monitoring the change of BL response, and further narrowing the location range of the failed transistor;

[0108] S33. During the test, the exact failure location is marked on the chip surface using non-destructive means (such as laser marking).

[0109] The working principle of the above technical solution is as follows: In the S2 stage, the potential failed WL-BL combinations have been marked through a series of test steps. In the S31 stage, these combinations are tested more deeply to verify whether the results of the S2 stage are accurate and to eliminate the interference of accidental factors. By repeating the S2 steps multiple times and activating only one WL each time, the response of all BLs can be observed and recorded more accurately. This test method helps to confirm which WL-BL combinations do have failure problems and which may be misjudged due to accidental factors. The voltage state of the SL (source line) has an important impact on the working state of the transistor. By changing the voltage state of the SL, such as applying voltages or pulses of different sizes, the changes in the response of the BL (bit line) can be further observed. The test method helps to narrow the location of the failed transistor because different SL voltage states will affect different transistors, thereby changing the response of the BL. During the test, the exact failure location is marked on the chip surface using non-destructive means (such as laser marking). This marking method will not cause further damage to the chip and can provide clear instructions for subsequent analysis and repair work.

[0110] The effect of the above technical solution is: by repeating the step of S2 multiple times and activating only one WL in each test, the response of BL can be observed and recorded more accurately, which helps to eliminate misjudgments caused by accidental factors (such as noise, interference, etc.), thereby improving the accuracy of the test. By changing the voltage state of SL and monitoring the changes in the response of BL, the location range of the failed transistor can be further narrowed. It helps to quickly locate the specific failure area and provide strong support for subsequent analysis and repair work. During the test process, the exact failure position is marked on the chip surface by non-destructive means (such as laser marking), which can greatly shorten the time for locating the failure position and improve the test efficiency. Accurate failure position marking helps to conduct in-depth analysis of the cause of failure in the future. By analyzing the transistor characteristics, connection methods, etc. of the failure area, the failure mechanism can be further understood, providing important reference for improving production processes and designs. Through accurate test methods and steps, the number of unnecessary repeated tests can be reduced, the test cost can be reduced, and the test efficiency can be improved. Accurate test methods and efficient test processes can make full use of test resources (such as test equipment, test time, etc.). This helps to improve the utilization of test resources and reduce test costs.

[0111] In one embodiment of the present invention, the S4 includes:

[0112] S41, collecting all test data, the test data including WL activation sequence, BL response and SL status, and establishing a test database based on the collected test data;

[0113] S42, analyzing the data in the test database by a data analysis algorithm, and identifying failure modes based on the analysis results, wherein the failure modes include frequent failures of specific WL or BL combinations, which may point to problems in specific process steps;

[0114] S43, performing an IV characteristic test on the located failed transistor, wherein the characteristic test includes a threshold voltage and a leakage current, and evaluating the degree of gate dielectric damage based on the characteristic test result;

[0115] S44. Based on high-precision imaging technologies such as SEM and TEM, the microstructure of the failed transistor is analyzed through machine vision algorithms, and physical damage or defects are determined based on the analysis results.

[0116] The working principle of the above technical solution is: through a specific test device or system, all relevant test data are comprehensively collected. These test data cover key information such as WL (word line) activation sequence, BL (bit line) response, and SL (source line or select line) status. Subsequently, based on these collected data, a test database is established to provide a basis for subsequent data analysis; advanced data analysis algorithms are used to deeply mine and analyze the data in the test database. By comparing the data differences under different test conditions, potential failure modes are identified. These failure modes may manifest as frequent failures of specific WL or BL combinations, thus pointing to specific process steps or design problems. The identification of failure modes provides important clues for subsequent positioning and repair; IV (current-voltage) characteristic tests are performed for the failed transistors that have been located. The test content mainly includes key parameters such as threshold voltage and leakage current. By comparing the IV characteristic curves of normal transistors and failed transistors, the degree of damage to the gate dielectric can be evaluated. This step provides important reference information for subsequent microstructure analysis; based on high-precision imaging technologies such as SEM (scanning electron microscope) and TEM (transmission electron microscope), the microstructure of the failed transistor is carefully observed. The collected image data is automatically processed and analyzed through machine vision algorithms to extract key feature information. These feature information include the shape, size, location and distribution of defects, which are crucial for determining the type and extent of physical damage or defects. Based on these analysis results, the specific cause and mechanism of failure can be further inferred.

[0117] The effects of the above technical solutions are as follows: by collecting comprehensive test data such as WL activation sequence, BL response and SL status, the working status and failure status of the device can be more comprehensively reflected, providing a solid foundation for subsequent analysis; using data analysis algorithms to conduct in-depth analysis of test data, failure modes can be accurately identified, such as frequent failures of specific WL or BL combinations, which helps to quickly locate the problem and reduce the possibility of misjudgment and missed judgment; by performing IV characteristic tests on failed transistors, including measurement of key parameters such as threshold voltage and leakage current, the degree of damage to the gate dielectric can be directly reflected, providing a strong basis for subsequent repair and improvement; by comparing the IV characteristic curves of normal transistors and failed transistors, the degree of damage to the gate dielectric can be quantitatively evaluated, making the evaluation results more objective and accurate; using high-precision imaging technologies such as SEM and TEM, it is possible to clearly and accurately Observing the microstructure of the failed transistor provides intuitive evidence for judging physical damage or defects; by introducing machine vision algorithms, the collected image data can be automatically processed and analyzed, which can significantly improve the efficiency and accuracy of the analysis, while reducing errors caused by human factors; by accurately identifying failure modes and deeply analyzing the microstructure, the root cause of the problem can be traced, such as problems in specific process steps or material defects, and targeted suggestions can be provided for subsequent process improvements; based on the analysis results, the design of the device can be optimized, such as adjusting the size of the transistor, improving the gate dielectric material, etc., to improve the reliability and stability of the device; by accurately identifying failure modes and deeply analyzing, the problem can be quickly located, reducing the time for troubleshooting and repair, and improving production efficiency; by timely discovering and repairing failed transistors, the scrap rate caused by device failure can be reduced, thereby reducing production costs.

[0118] In one embodiment of the present invention, the S42 includes:

[0119] Use statistical methods (such as Z-score, IQR, etc.) to check outliers in the test data. The outliers may be caused by test equipment failure, human operating errors, or environmental factors. The detected outliers are marked and removed.

[0120] Unify the format of relevant information in the test data, including WL activation sequence, BL response, and SL status, count the number of failures of each WL or BL combination in the test database, and identify combinations that frequently fail;

[0121] Use clustering algorithms (such as K-means, hierarchical clustering, etc.) to group test data and identify groups with similar failure characteristics;

[0122] Analyze the association relationships in the test data through association rule mining algorithms (such as Apriori, FP-Growth, etc.) to identify the potential connections between WL activation sequence, BL response and SL status, and the correspondence between these connections and failure modes;

[0123] For test data with time series characteristics (such as the change in the number of failures over time in multiple tests), use time series analysis techniques (such as ARIMA, LSTM, etc.) to identify the trends and periodicity of failure modes;

[0124] Combining process knowledge, design documents and historical experience, the failure modes identified through data analysis are verified, and the identified failure modes are prioritized according to factors such as the severity of the failure mode, the scope of impact, and the repair cost.

[0125] The working principle of the above technical solution is: use statistical methods (such as Z-score, IQR, etc.) to test the test data and identify possible outliers. Outliers may be caused by test equipment failure, human operation errors or environmental factors. Mark and remove the detected outliers to improve the accuracy of subsequent analysis. Unify the format of relevant information in the test data (such as WL activation sequence, BL response, SL status, etc.). This helps to ensure the consistency and comparability of the data and facilitate subsequent analysis. Count the number of failures of each WL or BL combination in the test database. Through the statistical results, combinations with frequent failures can be identified, providing important clues for subsequent failure mode analysis. Use clustering algorithms (such as K-means, hierarchical clustering, etc.) to group the test data. Through cluster analysis, groups with similar failure characteristics can be identified, further revealing the potential laws of failure modes. Apply association rule mining algorithms (such as Apriori, FP-Growth, etc.) to analyze the association relationships in the test data. Through association rule mining, the potential connections between WL activation sequence, BL response and SL status, as well as the correspondence between these connections and failure modes can be identified. For test data with time series characteristics (such as the change in the number of failures over time in multiple tests), time series analysis techniques (such as ARIMA, LSTM, etc.) are used for analysis. Time series analysis helps to identify the trends and periodic laws of failure modes, providing a scientific basis for predicting and preventing failures. Combined with process knowledge, design documents and historical experience, the failure modes identified through data analysis are verified. The identified failure modes are prioritized according to factors such as the severity of the failure mode, the scope of impact, and the cost of repair. This helps to determine the failure modes that are prioritized and provides guidance for subsequent repair and improvement work.

[0126] The effect of the above technical solution is: by testing and eliminating outliers in the test data by statistical methods, errors caused by test equipment failure, human operation errors or environmental factors can be significantly reduced. This helps to improve the accuracy and reliability of subsequent data analysis. The relevant information in the test data is formatted in a unified manner to ensure the consistency and comparability of the data. This facilitates subsequent data analysis and improves the accuracy of the analysis. By counting the number of failures of each WL or BL combination in the test database, the combination with frequent failures can be quickly identified. This helps to focus on the problem area and provide a focus for subsequent analysis and repair work. By grouping the test data through a clustering algorithm, groups with similar failure characteristics can be identified. This helps to discover potential failure modes and provide clues for subsequent failure cause analysis. Applying an association rule mining algorithm to analyze the association relationship in the test data can reveal the potential connection between the WL activation sequence, BL response and SL state. This helps to understand the correspondence between failure modes and test parameters, and provides guidance for subsequent repairs and improvements. For test data with time series characteristics, the trend and periodicity of failure modes can be identified using time series analysis technology. This helps predict future failures and provides a basis for preventive maintenance and repair work. Failure modes identified through data analysis are verified by combining process knowledge, design documents and historical experience. This ensures that the identified failure modes are real and reliable, providing strong support for subsequent repair and improvement work. The identified failure modes are prioritized according to factors such as the severity of the failure mode, the scope of impact, and the cost of repair. This helps determine the priority failure modes and optimize the resource allocation for repair and improvement work.

[0127] In one embodiment of the present invention, the S43 includes:

[0128] Use standard samples to calibrate IV test equipment, including calibrating current sources, voltmeters, and measurement circuits; apply a series of gradually increasing voltages to the gate while monitoring changes in drain current; when the drain current begins to increase significantly, the corresponding gate voltage is the threshold voltage; record the threshold voltage value of each failed transistor and compare it with the threshold voltage of a normal transistor;

[0129] Under a fixed gate voltage, measure the magnitude of the drain current; record the drain current value of each failed transistor and analyze its difference with the drain current of a normal transistor;

[0130] Repeated threshold voltage and leakage current tests at different temperatures to evaluate the temperature dependence of gate dielectric damage;

[0131] Compare the threshold voltage of the failed transistor with the threshold voltage of the normal transistor, and calculate the threshold voltage offset by the following formula;

[0132]

[0133] in, represents the threshold voltage of the failed transistor; represents the threshold voltage of a normal transistor;

[0134] Based on the leakage current value and the effective channel area of ​​the transistor, the leakage current density is calculated by the following formula;

[0135]

[0136] in, Indicates leakage current in ampere (A). Represents the effective channel area of ​​the transistor in square meters;

[0137] Based on the test results of threshold voltage offset and leakage current density, combined with process experience and historical data, the degree of gate dielectric damage is graded;

[0138] Record the IV characteristic test results of each failed transistor, including key parameters such as threshold voltage, leakage current, temperature dependence, etc., conduct in-depth analysis of the test results, and identify the common characteristics of failed transistors, such as the distribution of threshold voltage offset, the change trend of leakage current density, etc.

[0139] The working principle of the above technical solution is as follows: the IV test equipment is calibrated using a standard sample to ensure the accuracy of the test results. The calibration includes key components such as a current source, a voltmeter, and a measurement circuit. A series of gradually increasing voltages are applied to the gate while monitoring the change in the drain current. When the drain current begins to increase significantly, the corresponding gate voltage is the threshold voltage. The threshold voltage value of each failed transistor is recorded and compared with the threshold voltage of a normal transistor. The magnitude of the threshold voltage offset can reflect the number of charge traps in the gate dielectric or the change in the thickness of the gate dielectric, thereby indirectly evaluating the degree of damage to the gate dielectric. Under a fixed gate voltage, the magnitude of the drain current is measured. The leakage current value of each failed transistor is recorded and analyzed for its difference from the leakage current of a normal transistor. Based on the leakage current value and the effective channel area of ​​the transistor, the leakage current density is calculated. An increase in the leakage current density may indicate the presence of pinholes, cracks, or other defects in the gate dielectric, resulting in current leakage. The threshold voltage and leakage current tests are repeated at different temperatures. By comparing the test results at different temperatures, the temperature dependence of gate dielectric damage is evaluated. Based on the test results of threshold voltage offset and leakage current density, combined with process experience and historical data, the degree of gate dielectric damage is graded. The IV characteristic test results of each failed transistor are recorded, including key parameters such as threshold voltage, leakage current, and temperature dependence. In-depth analysis of the test results is performed to identify common characteristics of failed transistors, such as the distribution of threshold voltage offset and the change trend of leakage current density. This helps to further understand the mechanism and cause of gate dielectric damage and provide guidance for subsequent repair and improvement work.

[0140] The effect of the above technical solution is: the IV test equipment is calibrated using standard samples to ensure the accuracy and reliability of the test equipment. This helps to reduce test errors and improve the accuracy of test results. By accurately measuring key parameters such as threshold voltage and leakage current, the performance state of the transistor can be accurately reflected. This helps to discover potential problems in the transistor in a timely manner and provide strong support for subsequent analysis and repair work. By comparing the threshold voltages of failed transistors and normal transistors, the threshold voltage offset can be calculated. The magnitude of the threshold voltage offset can reflect the number of charge traps in the gate dielectric or the change in the thickness of the gate dielectric, thereby indirectly evaluating the degree of damage to the gate dielectric. According to the leakage current value and the effective channel area of ​​the transistor, the leakage current density can be calculated. An increase in the leakage current density may indicate that there are pinholes, cracks or other defects in the gate dielectric, resulting in current leakage. This helps to further understand the damage of the gate dielectric and provide guidance for subsequent repair and improvement work. Repeating the threshold voltage and leakage current tests at different temperatures can evaluate the temperature dependence of gate dielectric damage. This helps to understand the performance changes of the gate dielectric at different temperatures and provides an important basis for subsequent reliability evaluation and life prediction. Based on the test results of threshold voltage offset and leakage current density, combined with process experience and historical data, the degree of gate dielectric damage can be graded. This helps to quantify the degree of gate dielectric damage and provide clear guidance for subsequent repair and improvement work. Record the IV characteristic test results of each failed transistor and conduct in-depth analysis of the test results. This helps to identify common characteristics of failed transistors, such as the distribution of threshold voltage offset, the changing trend of leakage current density, etc. This provides important clues and basis for subsequent troubleshooting and repair work.

[0141] In one embodiment of the present invention, the S44 includes:

[0142] Select representative failed transistor samples from the test database and perform corresponding processing, including necessary cleaning, cutting and thinning, and select imaging technology based on the expected damage type and scale of the failed transistor; for example, SEM is suitable for observing surface morphology and larger defects, while TEM can provide higher-resolution internal structure information;

[0143] Using SEM and / or TEM to image the microstructure of the failed transistor and collect high-quality image data; preprocessing the collected images, wherein the preprocessing includes denoising, contrast enhancement, and edge detection;

[0144] Using machine vision algorithms to extract key features in the image, the key features include defect shape, size, location and distribution, matching the extracted features with a known physical damage or defect feature library, and identifying specific physical damage or defect types in the failed transistor;

[0145] Based on the results of feature matching and classification, the degree of physical damage in the failed transistor is evaluated, such as crack length, defect density, etc. The physical damage analysis results are combined with the previous failure mode identification (S42) and IV characteristic test (S43) results to explore the failure mode and mechanism of the failed transistor;

[0146] The microstructure analysis results of each failed transistor are recorded, and the analysis results include imaging parameters, image data, feature extraction results, damage degree assessment, cause analysis, etc. Based on the analysis results, a failure analysis report is prepared, and the analysis report includes a description of the failed transistor, the microstructure analysis process, damage judgment and cause analysis, and suggested improvement measures, etc.

[0147] The working principle of the above technical solution is: select representative failed transistor samples from the test database. Perform necessary cleaning, cutting and thinning on the selected samples to ensure the imaging quality; select appropriate imaging technology according to the expected damage type and scale of the failed transistor; SEM is suitable for observing surface morphology and larger defects. TEM can provide higher resolution internal structure information; Microstructure imaging and image preprocessing: Use SEM and / or TEM to image the microstructure of the failed transistor; Preprocess the collected images, including denoising, contrast enhancement, edge detection, etc., to improve image quality and analysis accuracy; Use machine vision algorithms to extract key features in the image, such as defect shape, size, location and distribution; Match the extracted features with a known physical damage or defect feature library; Identify the specific physical damage or defect type in the failed transistor; Based on the results of feature matching and classification, evaluate the degree of physical damage in the failed transistor; Combine the physical damage analysis results with the previous failure mode identification (S42) and IV characteristic test (S43) results; Explore the failure mode and mechanism of the failed transistor; Record the microstructure analysis results of each failed transistor; Including imaging parameters, image data, feature extraction results, damage degree assessment, cause analysis, etc.; Prepare a failure analysis report based on the analysis results; The report includes a description of the failed transistor, the microstructure analysis process, damage judgment and cause analysis, and recommended improvement measures.

[0148] The effects of the above technical solution are: selecting representative failed transistor samples from the test database to ensure the universality and applicability of the analysis results; using SEM and / or TEM for microstructure imaging to capture tiny defects and damage in the failed transistor and improve the accuracy of the analysis; performing preprocessing such as denoising, contrast enhancement and edge detection on the collected images to improve image quality and reduce analysis errors; using machine vision algorithms to extract key features in the image and match them with a known physical damage or defect feature library to achieve automated, high-precision damage identification and classification; combining the physical damage analysis results with the previous failure mode identification (S42) and IV characteristic test (S43) results to explore the failure mode and mechanism of the failed transistor from multiple perspectives; recording each failed crystal The microstructure analysis results of the tube, including imaging parameters, image data, feature extraction results, damage degree assessment, etc., provide detailed data support for subsequent analysis and improvement; analyze the causes of physical damage in failed transistors to clarify the root cause of failure; prepare a failure analysis report based on the analysis results, and propose targeted improvement measures and suggestions to prevent similar failures from happening again; by analyzing the microstructure of failed transistors, problems and deficiencies in the production process can be discovered, providing an important basis for process optimization; through high-precision microstructure analysis and machine vision algorithms, problem areas and damage types in failed transistors can be quickly located to improve R&D efficiency; incorporating the S44 technical solution into the quality control process can promptly discover and correct potential problems in the production process and improve product quality.

[0149] In one embodiment of the present invention, S5 includes:

[0150] S51. Analyze the specific factors that may cause gate dielectric breakdown based on the size and process parameters (such as gate oxide thickness, doping concentration, etc.) of the failed transistor; and consider the impact of environmental factors such as temperature, humidity, and pollution during the production process on the quality of the gate dielectric;

[0151] S52. Formulate process improvement measures based on the analysis results, wherein the process improvement measures include adjusting the oxidation temperature and optimizing the doping process;

[0152] S53. In subsequent designs, redundant structures should be added, or more reliable gate dielectric materials should be used, a long-term gate dielectric quality monitoring system should be established, and the test process and results should be reviewed regularly.

[0153] The working principle of the above technical solution is as follows: First, the size information of the failed transistor needs to be clarified, including its physical dimensions such as length and width. These dimensions will directly affect the electric field strength borne by the gate dielectric. At the same time, process parameters such as gate oxide thickness and doping concentration are also key factors. The thinner the gate oxide layer, the better the performance of the device, but it will also reduce its ability to withstand voltage and increase the risk of breakdown. Changes in doping concentration will affect the charge distribution at the interface between the gate dielectric and the semiconductor, thereby affecting the breakdown voltage of the gate dielectric; environmental factors such as temperature, humidity, and pollution during the production process will also have a significant impact on the quality of the gate dielectric. For example, high temperature may lead to more defects in the gate oxide layer, reducing its breakdown voltage; humidity and pollution may trigger chemical reactions on the surface of the gate dielectric, causing its performance degradation; by precisely controlling the temperature during the gate oxidation process, the growth quality and microstructure of the gate oxide layer can be optimized, thereby reducing defects and increasing the breakdown voltage; by adjusting the parameters of the doping process, such as the concentration of the doping source, the doping time and the temperature, the charge distribution at the interface between the gate dielectric and the semiconductor can be precisely controlled, thereby optimizing the breakdown characteristics of the gate dielectric; by adding redundant gate dielectric structures in the design, the fault tolerance of the device can be improved to a certain extent. When part of the gate dielectric breaks down, the redundant structure can take over its function to ensure the normal operation of the device; with the development of materials science, gate dielectric materials with higher breakdown voltage, lower leakage current and better stability are constantly emerging. By adopting these new materials, the performance and reliability of the device can be significantly improved; in order to ensure that the quality of the gate dielectric is stable and controllable, a complete monitoring system needs to be established. This includes real-time monitoring of the growth process of the gate oxide layer, regular testing of the breakdown voltage of the gate dielectric, and statistical analysis of the test results. Through these measures, problems with gate dielectric quality can be discovered and resolved in a timely manner. As time goes by and process technology continues to advance, the original test process and standards may no longer be applicable. Therefore, it is necessary to review the test process and results regularly to ensure their accuracy and effectiveness. This helps to discover potential problems in a timely manner and make improvements, thereby further improving the reliability and stability of the gate dielectric.

[0154] The effect of the above technical solution is: through step S51, the technical solution can conduct in-depth analysis based on the size and process parameters (such as gate oxide thickness, doping concentration, etc.) of the failed transistor, and accurately locate the specific factors that may cause the gate dielectric breakdown. At the same time, the influence of environmental factors such as temperature, humidity, and pollution in the production process on the quality of the gate dielectric is considered to make the analysis more comprehensive and accurate. This ability to accurately locate the cause is helpful for the subsequent formulation of targeted improvement measures to improve the reliability and stability of the gate dielectric. In step S52, based on the analysis results of S51, process improvement measures are formulated, such as adjusting the oxidation temperature and optimizing the doping process. These improvement measures can directly improve the key factors of gate dielectric breakdown, thereby improving the quality of the gate dielectric. By optimizing the process parameters, the defects and impurities in the gate dielectric can be reduced, and its breakdown voltage and stability can be improved, thereby extending the service life of the device. In step S53, the reliability of the device is further enhanced by adding a redundant structure or using a more reliable gate dielectric material. The redundant structure can compensate for the functional loss caused by the breakdown of the gate dielectric to a certain extent, ensuring that the device can still work normally in a harsh environment. The use of a more reliable gate dielectric material can fundamentally improve the performance of the gate dielectric and reduce the risk of breakdown. In addition, the establishment of a long-term gate dielectric quality monitoring system and regular review of the test process and results can timely discover and correct problems in the production process and ensure the continuous stability of the gate dielectric quality. This technical solution indirectly improves production efficiency and reduces costs by accurately locating the cause of gate dielectric breakdown, improving gate dielectric quality and enhancing device reliability. On the one hand, it reduces device failure and scrapping due to gate dielectric breakdown, reducing production costs; on the other hand, it improves device reliability and stability, reducing downtime and labor costs caused by fault repair and replacement. In the implementation of this technical solution, it is necessary to conduct in-depth research and exploration on the gate dielectric breakdown mechanism, which will help promote the innovation and development of related technologies. At the same time, the adoption of more advanced processes and materials has promoted the upgrading and transformation of the semiconductor industry. This technological innovation and industrial upgrading not only improves the performance and quality of gate dielectrics, but also injects new vitality and impetus into the development of the entire semiconductor industry.

[0155] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for efficiently measuring transistor gate dielectric breakdown, characterized in that: The method comprises: S1. When designing the chip layout, introduce test-specific WL, BL and SL; Said S1 comprises: S11. Perform basic circuit layout planning according to chip functional requirements, and reserve an area at the edge of the chip specifically for gate dielectric breakdown testing; S12. In the test area, design multiple independent WLs, each WL being connected to gates of multiple MOS transistors; S13 and BL are connected to the drain of the MOS transistor, and SL is connected to the source. Mark the test circuit in the layout file; S2. In the test phase, a high level signal is applied to all SL lines, and then a high level signal is applied to all WL lines in turn to detect whether the gate dielectric of the MOS tube is broken down; The S2 comprises: S21, applying a high level signal higher than the normal operating voltage to all SL lines to ensure that all sources are in a high potential state; S22, applying high-level signals to all WL lines one by one through programming control to simulate the gate voltage during normal operation; The S22 comprises: According to the chip specification and design requirements, determine the specific value of the gate voltage Vgg; the specific value of Vgg is higher than the normal operating voltage but lower than the breakdown voltage of the gate dielectric; Set the voltage step, that is, instead of raising the gate voltage to Vgg all at once, increase it gradually in certain steps, and observe and record the BL line output state at each step; Based on the test script, the WL line is programmed and controlled by the automated test equipment; According to the test script, apply high-level signals to all WL lines one by one; and before applying voltage each time, ensure that all SL lines are in a high potential state; While applying the voltage, the output status of all BL lines is monitored in real time through the built-in sensors of the ATE; After applying the gate voltage, keep it for a while and check whether the voltage is stable; if the voltage fluctuation exceeds the allowable range, readjust the voltage source or test equipment; Perform multiple gate voltage application and removal cycle tests on some WL lines to evaluate the reliability of gate dielectrics under long-term operation; During the test, if a BL line is found to output a low level, the current WL line test will be stopped immediately, and the combination of WL and BL will be marked as a potential failure point; Record key information when an anomaly occurs, conduct a preliminary analysis of the anomaly, and determine whether it is caused by gate dielectric breakdown; S23, after each activation of WL, the output states of all BL lines are detected; if all BL lines output a high level, the gate dielectric of the corresponding MOS tube is not broken down; S24, if a certain BL line outputs a low level, the combination of WL and BL is recorded and marked as a potential failure point; S3. If it is determined that there is a failed transistor in the chip, further locate the specific failed transistor, and apply a high level signal to all SL lines again, and apply a high level signal to each WL line in turn, and observe the output of each BL line; S4, determining the specific location of the failed transistor by comparing the output of the BL line when different WL lines are activated; S5. After locating the failed transistor, check the relevant parameters of the failed transistor and conduct in-depth analysis on the failure cause. Based on the analysis results, determine the specific cause of the gate dielectric breakdown and perform optimization and improvement. The S3 includes: S31. Based on the result of S2, retest the WL-BL combination marked as potential failure, repeat the steps of S2 multiple times, and activate only one WL each time, while observing and recording the responses of all BLs; S32, by changing the voltage state of SL and monitoring the change of BL response, the location range of the failed transistor is further narrowed; S33, and during the test, the exact failure location is marked on the chip surface using non-destructive means.

2. A method for efficiently measuring transistor gate dielectric breakdown according to claim 1, characterized in that: The S4 comprises: S41, collecting all test data, and establishing a test database based on the collected test data; S42, analyzing the data in the test database by using a data analysis algorithm, and identifying the failure mode based on the analysis results; S43, performing an IV characteristic test on the located failed transistor, and evaluating the degree of gate dielectric damage based on the characteristic test result; S44. Based on high-precision imaging technology, the microstructure of the failed transistor is analyzed through machine vision algorithms, and physical damage or defects are judged based on the analysis results.

3. A method for efficiently measuring transistor gate dielectric breakdown according to claim 2, characterized in that: The S42 includes: Use statistical methods to test outliers in the test data, mark and remove the detected outliers; Unify the format of relevant information in the test data, count the number of failures of each WL or BL combination in the test database, and identify combinations that frequently fail; Use clustering algorithms to group test data and identify groups with similar failure characteristics; The association relationships in the test data are analyzed by association rule mining algorithm to identify the potential connections between WL activation sequence, BL response and SL status, as well as the correspondence between these connections and failure modes; For test data with time series characteristics, time series analysis techniques are used to identify trends and periodic laws of failure modes; Failure modes identified through data analysis are validated and prioritized by combining process knowledge, design documents and historical experience.

4. A method for efficiently measuring transistor gate dielectric breakdown according to claim 2, characterized in that: The S43 includes: The IV test equipment is calibrated using standard samples, and a series of gradually increasing voltages are applied to the gate while monitoring the change in drain current. When the drain current begins to increase significantly, the corresponding gate voltage is the threshold voltage. The threshold voltage value of each failed transistor is recorded and compared with the threshold voltage of a normal transistor. Under a fixed gate voltage, measure the magnitude of the drain current; record the drain current value of each failed transistor and analyze its difference with the drain current of a normal transistor; Repeated threshold voltage and leakage current tests at different temperatures to evaluate the temperature dependence of gate dielectric damage; comparing the threshold voltage of the failed transistor with the threshold voltage of the normal transistor, and calculating the threshold voltage offset; Calculate the leakage current density based on the leakage current value and the effective channel area of ​​the transistor; Based on the test results of threshold voltage offset and leakage current density, combined with process experience and historical data, the degree of gate dielectric damage is graded; Record the IV characteristic test results of each failed transistor, conduct in-depth analysis of the test results, and identify the common characteristics of failed transistors.

5. A method for efficiently measuring transistor gate dielectric breakdown according to claim 2, characterized in that: The S44 comprises: Failed transistor samples from the test database are processed accordingly, and imaging technology is selected based on the expected damage type and scale of the failed transistors; Use SEM and / or TEM to image the microstructure of the failed transistor and collect high-quality image data; pre-process the collected images; Use machine vision algorithms to extract key features from images, match the extracted features with a known library of physical damage or defect features, and identify the specific physical damage or defect type in the failed transistor; Based on the results of feature matching and classification, the degree of physical damage in the failed transistor is evaluated. The physical damage analysis results are combined with the previous failure mode identification and IV characteristic test results to explore the failure mode and mechanism of the failed transistor. Record the microstructure analysis results of each failed transistor and prepare a failure analysis report based on the analysis results.

6. A method for efficiently measuring transistor gate dielectric breakdown according to claim 1, characterized in that: The S5 comprises: S51. Analyze specific factors that may cause gate dielectric breakdown based on the size and process parameters of the failed transistor; S52. Formulate process improvement measures based on the analysis results, wherein the process improvement measures include adjusting the oxidation temperature and optimizing the doping process; S53. In subsequent designs, redundant structures will be added, a long-term gate dielectric quality monitoring system will be established, and the test process and results will be reviewed regularly.

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