Display panel and display device

Abstract

The invention discloses a display panel and a display device, and relates to the technical field of display. Pixels in an array substrate of the display panel comprise a plurality of sub-pixels of different colors, each data line is connected with a column of sub-pixels arranged in the first direction, and each grid line is connected with at least one sub-pixel arranged in the first direction. Moreover, the light-emitting areas of the sub-pixels are located on the two sides of the grid lines, that is, the light-emitting areas can cross the two opening areas located on the two sides of the grid lines, and continuous display of the two opening areas arranged in the first direction can be achieved conveniently. Moreover, the black matrix structure does not cover the target line segment of the grid line, so that the influence of the black matrix structure on continuous display in the first direction can be avoided, continuous display of the display panel in the first direction is ensured, and the display effect of the display panel is relatively good.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] 3D (dimension, D) display technology can realize many functions that 2D display does not have due to its depth information. As the display technology continues to develop, its application is becoming more and more extensive.

[0003] In the related art, the display panel includes a plurality of data lines extending along a first direction and arranged along a second direction, a plurality of gate lines extending along a second direction and arranged along a first direction, and a plurality of sub-pixels arranged in an array. Each data line is connected to a column of sub-pixels to provide a data signal for the column of sub-pixels, and each gate line is connected to a row of sub-pixels to provide a gate signal for a row of sub-pixels. The sub-pixels included in the display panel can emit light under the joint control of the data lines and the gate lines. In addition, the display panel also includes a black matrix layer, the black matrix layer includes a plurality of first black matrix structures extending along the first direction and arranged along the second direction, and a plurality of second black matrix structures extending along the second direction and arranged along the first direction. Each first black matrix structure covers a data line, and each second black matrix structure covers a gate line.

[0004] However, the above solution is difficult to achieve continuous display of the display panel in the first direction or the second direction, and the display effect is poor. Summary of the invention

[0005] The present application provides a display panel and a display device, which can solve the problem of difficulty in achieving continuous display and poor display effect in related technologies. The technical solution is as follows:

[0006] In one aspect, a display panel is provided, the display panel comprising: an array substrate and a color filter substrate arranged opposite to each other, and a liquid crystal layer located between the array substrate and the color filter substrate; the array substrate comprises:

[0007] a first substrate;

[0008] A plurality of pixels located on the first substrate, each of the pixels comprising: a plurality of first sub-pixels of a first color, a plurality of second sub-pixels of a second color, and a plurality of third sub-pixels of a third color, the plurality of first sub-pixels and a plurality of sub-pixels of each color are arranged along a first direction, and the plurality of second sub-pixels and the plurality of third sub-pixels are arranged along a second direction, and the second direction intersects the first direction;

[0009] A plurality of data lines extending along the first direction and arranged along the second direction, each of the data lines being connected to a column of sub-pixels arranged along the first direction;

[0010] and, a plurality of gate lines extending along a third direction and arranged along the first direction, each of the gate lines being connected to at least one sub-pixel arranged along the first direction, and light-emitting areas of at least some of the sub-pixels included in the pixel being located on both sides of the gate lines, and the third direction intersecting the first direction;

[0011] The color film substrate includes: a second substrate and a black matrix layer located on the second substrate, the black matrix layer includes a plurality of black matrix structures extending along the first direction and arranged along the second direction, each of the black matrix structures covers at least one of the data lines, and the black matrix layer does not overlap with a target line segment of the gate line, and the target line segment is a line segment located between adjacent sub-pixels along the first direction and does not overlap with the data line.

[0012] Optionally, the array substrate further comprises: a pixel electrode layer located on the first substrate, the pixel electrode layer comprising a plurality of pixel electrodes arranged at intervals;

[0013] Among them, the shape of the positive projection of the pixel electrode on the first substrate is a strip, the extension direction of the pixel electrode intersects with the first direction, the second direction and the third direction, and each of the first sub-pixel, the second sub-pixel and the third sub-pixel includes: one pixel electrode.

[0014] Optionally, the orthographic projection of the pixel electrode on the first substrate overlaps with a positive pixel portion of at least one of the gate lines on the first substrate.

[0015] Optionally, in the second direction, there is a gap between any two adjacent sub-pixels of the colors, and at least two of the plurality of data lines are located in the same gap, wherein at least one of the data lines located in the same gap is connected to a sub-pixel of one of the two adjacent sub-pixels of the colors, and at least one of the data lines located in the same gap is connected to a sub-pixel of another of the two adjacent sub-pixels of the colors;

[0016] Each of the gate lines is connected to at least two sub-pixels adjacent to each other along the first direction, and the third direction intersects with the first direction;

[0017] Each of the black matrix structures covers at least two of the data lines located in the same gap.

[0018] Optionally, two of the plurality of data lines are located in the same gap; one of the data lines is connected to a sub-pixel of one color among two adjacent sub-pixels of different colors, and the other data line is connected to a sub-pixel of another color among the two adjacent sub-pixels of different colors; or,

[0019] Three of the multiple data lines are located in the same gap; one of the data lines is connected to a sub-pixel of one of two adjacent colors, and the other two data lines are connected to a sub-pixel of the other of the two adjacent colors; or, two of the data lines located in the same gap are connected to a sub-pixel of one of two adjacent colors, and the other data line is connected to a sub-pixel of the other of the two adjacent colors.

[0020] Optionally, the display panel further includes a common electrode layer, the common electrode layer including: a plurality of first electrode portions arranged along the second direction, and a plurality of second electrode portions arranged along the second direction, the plurality of first electrode portions and the plurality of second electrode portions being arranged alternately;

[0021] The orthographic projection of the first electrode portion on the first substrate is located within the orthographic projection of the black matrix structure on the first substrate;

[0022] The second electrode portion includes a plurality of common electrode patterns arranged and spaced apart along the first direction, one end of each of the common electrode patterns being connected to one of two adjacent first electrode portions, and the other end of each of the common electrode patterns being connected to the other of the two adjacent first electrode portions;

[0023] Among them, the shape of the orthographic projection of each common electrode pattern on the first substrate is a bar, and the extension direction of the common electrode pattern is parallel to the extension direction of the pixel electrode, and the orthographic projection of the common electrode pattern on the first substrate and the orthographic projection of the pixel electrode included in the sub-pixel on the first substrate at least partially overlap.

[0024] Optionally, each of the sub-pixels further includes: a switch transistor, the switch transistor including a source, a drain and a channel located between the source and the drain, the source being connected to the data line, and the drain being connected to a pixel electrode included in the sub-pixel;

[0025] The array substrate comprises: a gate layer and a transparent electrode layer in contact with the gate layer, and the gate line is located on the gate layer;

[0026] The transparent electrode layer includes a plurality of transparent electrode patterns. In a fourth direction, an orthographic projection of the transparent electrode pattern on the first substrate covers an orthographic projection of the gate line on the first substrate, and a length of the orthographic projection of the transparent electrode pattern on the first substrate along the fourth direction is greater than a length of the orthographic projection of the gate line on the first substrate along the fourth direction; a length of the orthographic projection of the transparent electrode pattern on the first substrate along the fourth direction is a length of the channel, and the fourth direction is perpendicular to the third direction.

[0027] Optionally, the array substrate comprises: a buffer layer, an active layer, a gate insulating layer, the gate layer, the transparent electrode layer, an interlayer dielectric layer, a source-drain electrode layer, a first passivation layer, a first planarization layer, the pixel electrode layer, a second passivation layer, a second planarization layer, and the common electrode layer, which are located on the first substrate and stacked in sequence;

[0028] The active layer includes a plurality of active patterns, each of which includes a source region, a drain region and a channel region;

[0029] The interlayer dielectric layer and the gate insulating layer have a first via hole, and the first via hole is used to expose the source region;

[0030] The source-drain electrode layer includes the plurality of data lines and a plurality of source-drain patterns, each of the source-drain patterns is connected to one of the data lines, and each of the source-drain patterns is connected to a source region of the active pattern through the first via hole;

[0031] The gate insulating layer, the interlayer dielectric layer, the first passivation layer and the first planar layer have a second via hole, and the second via hole is used to expose the drain region;

[0032] Each pixel electrode in the pixel electrode layer has a first portion located in the second via hole and a second portion located on a side of the first planar layer away from the first substrate, the first portion and the drain region of the active pattern are connected through the second via hole, and a distance between the first portion and the first substrate is smaller than a distance between the second portion and the first substrate;

[0033] At least a portion of the second flat layer is located on a side of the first portion away from the first substrate, and a surface of the common electrode layer close to the first substrate is a flat surface.

[0034] Optionally, the array substrate comprises: a buffer layer, an active layer, a gate insulating layer, the gate layer, the transparent electrode layer, an interlayer dielectric layer, a source-drain electrode layer, a first passivation layer, an electrode transfer layer, a first planarization layer, the pixel electrode layer, a second passivation layer, and the common electrode layer, which are located on the first substrate and stacked in sequence;

[0035] The active layer includes a plurality of active patterns, each of which includes a source region, a drain region and a channel region;

[0036] The interlayer dielectric layer and the gate insulating layer have a first via hole, and the first via hole is used to expose the source region;

[0037] The source-drain electrode layer includes the plurality of data lines and a plurality of source-drain patterns, each of the source-drain patterns is connected to one of the data lines, and each of the source-drain patterns is connected to a source region of the active pattern through the first via hole;

[0038] The gate insulating layer, the interlayer dielectric layer and the first passivation layer have a third via hole, and the third via hole is used to expose the drain region;

[0039] The electrode switching layer includes a plurality of electrode switching patterns, the electrode switching patterns are connected to a drain region of the active pattern through the third via hole, and an orthographic projection of the electrode switching pattern on the first substrate at least partially overlaps with an orthographic projection of the data line on the first substrate;

[0040] The first planar layer has a fourth via hole, the fourth via hole is used to expose the electrode switching pattern, and the orthographic projection of the fourth via hole on the first substrate and the orthographic projection of the data line on the first substrate at least partially overlap;

[0041] Each pixel electrode in the pixel electrode layer has a third portion located in the fourth via hole, and a fourth portion located on a side of the first flat layer away from the first substrate, the third portion and the electrode transfer pattern are connected through the fourth via hole, and the distance between the third portion and the first substrate is smaller than the distance between the fourth portion and the first substrate.

[0042] Optionally, the first passivation layer includes a first sub-passivation layer and a second sub-passivation layer; the array substrate further includes: a shielding layer located between the first sub-passivation layer and the second sub-passivation layer, the shielding layer includes a plurality of shielding patterns, and the shielding patterns are located between the data lines and the electrode switching patterns;

[0043] In the second direction, the orthographic projection of the shielding pattern on the first substrate covers the orthographic projections of the at least two data lines on the first substrate, and the length of the shielding pattern along the second direction is less than the length of the black matrix structure along the second direction.

[0044] Optionally, the array substrate further includes: a spacer layer located between the first sub-passivation layer and the shielding layer;

[0045] The orthographic projection of the spacer layer on the first substrate at least covers the orthographic projection of the shielding pattern on the first substrate.

[0046] Optionally, the array substrate comprises: a source-drain electrode layer, a buffer layer, an active layer, a gate insulating layer, the transparent electrode layer, the gate layer, a first passivation layer, a first flat layer, an electrode transfer layer, a second passivation layer, a second flat layer, the pixel electrode layer, a third passivation layer, and the common electrode layer, which are located on the first substrate and stacked in sequence;

[0047] The source-drain electrode layer includes the plurality of data lines and a plurality of source-drain patterns, each of the source-drain patterns being connected to one of the data lines;

[0048] The buffer layer has a fifth via hole, and the fifth via hole is used to expose a partial area of ​​the source and drain pattern;

[0049] The active layer includes a plurality of active patterns, each of the active patterns includes a source region, a drain region and a channel region, and the source region and the source-drain pattern are connected through the fifth via hole;

[0050] The first passivation layer and the first planar layer have a sixth via hole, and the sixth via hole is used to expose the drain region;

[0051] The electrode switching layer includes a plurality of electrode switching patterns, each of the electrode switching patterns has a fifth portion located in the sixth via hole, and a sixth portion located on a side of the first flat layer away from the first substrate, the fifth portion and the drain region of the active pattern are connected through the sixth via hole, and a distance between the fifth portion and the first substrate is smaller than a distance between the sixth portion and the first substrate;

[0052] At least a portion of the second planar layer is located in the sixth via hole, and a surface of the pixel electrode layer close to the first substrate is a planar surface;

[0053] The second passivation layer and the second planar layer have a seventh via hole, and the seventh via hole is used to expose a partial area of ​​the sixth portion;

[0054] Each pixel electrode in the pixel electrode layer and one of the sixth portions are connected through the seventh via hole.

[0055] Optionally, the array substrate comprises: a source-drain electrode layer, a buffer layer, an active layer, a gate insulating layer, the transparent electrode layer, the gate layer, a first passivation layer, an electrode transfer layer, a first flat layer, the pixel electrode layer, a second passivation layer, and the common electrode layer, which are located on the first substrate and stacked in sequence;

[0056] The source-drain electrode layer includes the plurality of data lines and a plurality of source-drain patterns, each of the source-drain patterns being connected to one of the data lines;

[0057] The buffer layer has a fifth via hole, and the fifth via hole is used to expose a partial area of ​​the source and drain pattern;

[0058] The active layer includes a plurality of active patterns, each of the active patterns includes a source region, a drain region and a channel region, and the source region and the source-drain pattern are connected through the fifth via hole (g5);

[0059] The first passivation layer has an eighth via hole, and the eighth via hole is used to expose the drain region;

[0060] The electrode switching layer includes a plurality of electrode switching patterns, and each of the electrode switching patterns is connected to the drain region through the eighth via hole;

[0061] The first planar layer has a ninth via hole, and the ninth via hole is used to expose a partial area of ​​the electrode switching pattern;

[0062] The pixel electrode has a seventh portion located in the ninth via hole, and an eighth portion located on a side of the first flat layer away from the first substrate, the seventh portion and the electrode transfer pattern are connected through the ninth via hole, and a distance between the seventh portion and the first substrate is smaller than a distance between the eighth portion and the first substrate;

[0063] Wherein, the black matrix structure covers the ninth via hole.

[0064] Optionally, the pixel electrode has a first pixel portion, a second pixel portion and a third pixel portion; an orthographic projection of the first pixel portion on the first substrate is located within an orthographic projection of a first target black matrix structure on the first substrate, an orthographic projection of the second pixel portion on the first substrate is located between the first target black matrix structure and the second target black matrix structure, an orthographic projection of the third pixel portion on the first substrate is located within an orthographic projection of the second target black matrix structure on the first substrate, and the first target black matrix structure and the second target black matrix structure are two black matrix structures adjacent in the second direction;

[0065] A length of the first pixel portion in the second direction and a length of the third pixel portion in the second direction are both greater than or equal to 1 micrometer.

[0066] Optionally, the display panel further comprises a lens layer located on a side of the color film substrate away from the array substrate; the lens layer comprises a plurality of lens structures, and a surface of each lens structure away from the array substrate is a curved surface;

[0067] The shape of the orthographic projection of the lens structure on the array substrate is a strip, and the extension direction of the lens structure intersects with the first direction, the second direction and the third direction.

[0068] Optionally, an extension direction of the lens structure intersects with an extension direction of a pixel electrode included in the sub-pixel.

[0069] Optionally, under a first condition, the first direction is a pixel column direction of the display panel, the second direction is a pixel row direction of the display panel, and a first conditional angle α1 between the extending direction of the pixel electrode and the second direction satisfies:

[0070] tanα1=(db) / (ac);

[0071] The angle β between the extension direction of the lens structure and the second direction satisfies:

[0072] tanβ=d / (ac);

[0073] Wherein, a is the length of the sub-pixel along the second direction, b is the length of the sub-pixel along the first direction, c is the length of the black matrix structure along the second direction, and d is the length of the portion of the lens structure located between two adjacent black matrix structures along the first direction;

[0074] The first condition is that the length of the portion of the lens structure located in the opening area in the first direction is equal to the maximum distance between the two ends of the sub-pixel in the first direction.

[0075] Optionally, under the second condition, the third direction is parallel to the second direction, and a second condition angle α2 between the extending direction of the pixel electrode and the second direction satisfies:

[0076] tanα2=e / (ac);

[0077] Wherein, the e is the distance between two adjacent gate lines along the first direction; the angle between the extending direction of the pixel electrode and the second direction is the common multiple of the first condition angle and the second condition angle;

[0078] The second condition is that the length of the portion of the pixel electrode located between adjacent black matrix structures in the first direction is equal to the distance between adjacent gate lines along the first direction.

[0079] Optionally, under a third condition, the third direction intersects the second direction, and a third condition angle γ1 between the third direction and the second direction satisfies:

[0080] tanγ1=(|e-(ac)tanα1|) / (ac);

[0081] Wherein, said e is the distance between two adjacent gate lines along the first direction;

[0082] The third condition is that the sum of the length of the portion of the pixel electrode located between adjacent black matrix structures in the first direction and the length of the portion of the gate line located between adjacent black matrix structures in the first direction is equal to the distance between adjacent gate lines along the first direction.

[0083] Optionally, under a fourth condition, the third direction intersects the second direction, and a fourth condition angle γ2 between the third direction and the second direction satisfies:

[0084] tanγ2=(|2e-(ac)tanα1|) / (ac);

[0085] Wherein, said e is the distance between two adjacent gate lines along the first direction;

[0086] The fourth condition is: the sum of the length of the portion of the pixel electrode located between adjacent black matrix structures in the first direction and the length of the portion of the gate line located between adjacent black matrix structures in the first direction is equal to the distance between the first target gate line and the second target gate line along the first direction, there is also a third target gate line between the first target gate line and the second target gate line, and the orthographic projection of the pixel electrode on the first substrate and the orthographic projection of the third target gate line on the first substrate partially overlap.

[0087] Optionally, the extension directions of the multiple lens structures in the display panel are parallel, and the extension directions of the multiple pixel electrodes included in the pixel electrode layer in the display panel are parallel.

[0088] On the other hand, a display device is provided, the display device comprising: a power supply component and the display panel as described in the above aspect;

[0089] Wherein, the power supply component is used to supply power to the display panel.

[0090] The beneficial effects of the technical solution provided by this application include at least:

[0091] The present application provides a display panel and a display device, wherein the pixels in the array substrate of the display panel include a plurality of sub-pixels of different colors, each data line is connected to a column of sub-pixels arranged along a first direction, and each gate line is connected to at least one sub-pixel arranged along the first direction. In addition, the light-emitting area of ​​the sub-pixel is located on both sides of the gate line, that is, it can cross two opening areas located on both sides of the gate line, so as to facilitate the continuous display of the two opening areas arranged in the first direction. In addition, since the black matrix structure does not cover the target line segment of the gate line, the influence of the black matrix structure on the continuous display in the first direction can be avoided, so as to ensure that the display panel realizes continuous display in the first direction, and the display effect of the display panel is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0093] Figure 1 is a structural schematic diagram of a display panel provided in an embodiment of the present application;

[0094] Figure 2 It is a partial schematic diagram of an array substrate and a color filter substrate provided in an embodiment of the present application;

[0095] Figure 3 is a schematic diagram of an opening area provided in an embodiment of the present application;

[0096] Figure 4 is a schematic diagram of an angle of a pixel electrode provided in an embodiment of the present application;

[0097] Figure 5 is a partial schematic diagram of another array substrate and a color filter substrate provided in an embodiment of the present application;

[0098] Figure 6 It is a partial schematic diagram of another array substrate and a color filter substrate provided in an embodiment of the present application;

[0099] Figure 7 is a partial schematic diagram of a common electrode layer provided in an embodiment of the present application;

[0100] Figure 8 is a partial cross-sectional view of an array substrate provided in an embodiment of the present application;

[0101] Fig. 9 is a partial cross-sectional view of another array substrate provided in an embodiment of the present application;

[0102] Fig.10is a partial cross-sectional view of another array substrate provided in an embodiment of the present application;

[0103] Fig.11 is a partial cross-sectional view of another array substrate provided in an embodiment of the present application;

[0104] Fig.12 is a partial cross-sectional view of another array substrate provided in an embodiment of the present application;

[0105] Fig.13 is a partial cross-sectional view of another array substrate provided in an embodiment of the present application;

[0106] Fig.14 is a partial schematic diagram of a source and drain layer provided in an embodiment of the present application;

[0107] Fig.15 is a partial schematic diagram of a buffer layer provided in an embodiment of the present application;

[0108] Fig.16 It is a schematic diagram of partial superposition of a source / drain layer and a buffer layer provided in an embodiment of the present application;

[0109] Fig.17 is a partial schematic diagram of an active layer provided in an embodiment of the present application;

[0110] Fig.18 It is a schematic diagram of partial superposition of a source and drain layer, a buffer layer and an active layer provided in an embodiment of the present application;

[0111] Fig.19 is a partial schematic diagram of a transparent electrode layer provided in an embodiment of the present application;

[0112] Fig. 20 It is a schematic diagram of partial superposition of a source and drain layer, a buffer layer, an active layer and a transparent electrode layer provided in an embodiment of the present application;

[0113] Fig.21 is a partial schematic diagram of a gate layer provided in an embodiment of the present application;

[0114] Fig. 22 It is a schematic diagram of partial superposition of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer and a gate layer provided in an embodiment of the present application;

[0115] Fig.23 is a partial schematic diagram of a first passivation layer and a first planarization layer provided in an embodiment of the present application;

[0116] Fig.24 It is a schematic diagram of partial superposition of a source-drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer and a first planar layer provided in an embodiment of the present application;

[0117] Fig.25 It is a partial schematic diagram of an electrode transfer layer provided in an embodiment of the present application;

[0118] Fig.26 It is a schematic diagram of partial superposition of a source-drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, a first flat layer and an electrode transfer layer provided in an embodiment of the present application;

[0119] Fig. 27 is a partial schematic diagram of a second flat layer provided in an embodiment of the present application;

[0120] Fig.28 It is a schematic diagram of partial superposition of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, a first flat layer, an electrode transfer layer and a second flat layer provided in an embodiment of the present application;

[0121] Fig.29 is a partial schematic diagram of a second passivation layer provided in an embodiment of the present application;

[0122] Fig.30 It is a schematic diagram of partial superposition of a source-drain electrode layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, a first flat layer, an electrode transfer layer, a second flat layer and a second passivation layer provided in an embodiment of the present application;

[0123] Fig.31 is a partial schematic diagram of a pixel electrode layer provided in an embodiment of the present application;

[0124] Fig.32 It is a schematic diagram of partial superposition of a source-drain electrode layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, a first flat layer, an electrode transfer layer, a second flat layer, a second passivation layer and a pixel electrode layer provided in an embodiment of the present application;

[0125] Fig.33 is a partial schematic diagram of a common electrode layer provided in an embodiment of the present application;

[0126] Fig.34 It is a partial superposition schematic diagram of a source-drain electrode layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, a first flat layer, an electrode transfer layer, a second flat layer, a second passivation layer, a pixel electrode layer and a common electrode layer provided in an embodiment of the present application;

[0127] Fig.35 is a partial schematic diagram of a black matrix layer provided in an embodiment of the present application;

[0128] Fig.36It is a partial superposition schematic diagram of a source-drain electrode layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, a first flat layer, an electrode transfer layer, a second flat layer, a second passivation layer, a pixel electrode layer, a common electrode layer and a black matrix layer provided in an embodiment of the present application;

[0129] Fig.37 is a partial schematic diagram of a source and drain layer provided in an embodiment of the present application;

[0130] Fig.38 is a partial schematic diagram of a buffer layer provided in an embodiment of the present application;

[0131] Fig.39 It is a schematic diagram of partial superposition of a source / drain layer and a buffer layer provided in an embodiment of the present application;

[0132] Fig.40 is a partial schematic diagram of an active layer provided in an embodiment of the present application;

[0133] Fig.41 It is a schematic diagram of partial superposition of a source and drain layer, a buffer layer and an active layer provided in an embodiment of the present application;

[0134] Fig.42 is a partial schematic diagram of a transparent electrode layer provided in an embodiment of the present application;

[0135] Fig.43 It is a schematic diagram of partial superposition of a source and drain layer, a buffer layer, an active layer and a transparent electrode layer provided in an embodiment of the present application;

[0136] Fig.44 is a partial schematic diagram of a gate layer provided in an embodiment of the present application;

[0137] Fig.45 It is a schematic diagram of partial superposition of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer and a gate layer provided in an embodiment of the present application;

[0138] Fig.46 is a partial schematic diagram of a first passivation layer provided in an embodiment of the present application;

[0139] Fig.47 It is a schematic diagram of partial superposition of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer and a first passivation layer provided in an embodiment of the present application;

[0140] Fig.48 It is a partial schematic diagram of an electrode transfer layer provided in an embodiment of the present application;

[0141] Fig.49It is a schematic diagram of partial superposition of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer and an electrode transfer layer provided in an embodiment of the present application;

[0142] Fig.50 is a partial schematic diagram of a first flat layer provided in an embodiment of the present application;

[0143] Fig.51 It is a schematic diagram of partial superposition of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, an electrode transfer layer and a first flat layer provided in an embodiment of the present application;

[0144] Fig.52 is a partial schematic diagram of a pixel electrode layer provided in an embodiment of the present application;

[0145] Fig.53 It is a schematic diagram of partial superposition of a source and drain electrode layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, an electrode transfer layer, a first planar layer and a pixel electrode layer provided in an embodiment of the present application;

[0146] Fig.54 A partial schematic diagram of a common electrode layer provided in an embodiment of the present application;

[0147] Fig.55 It is a partial superposition schematic diagram of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, an electrode transfer layer, a first flat layer, a pixel electrode layer, a second passivation layer and a common electrode layer provided in an embodiment of the present application;

[0148] Fig.56 is a partial schematic diagram of a black matrix layer provided in an embodiment of the present application;

[0149] Fig.57 It is a partial superposition schematic diagram of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, an electrode transfer layer, a first flat layer, a pixel electrode layer, a second passivation layer, a common electrode layer and a black matrix layer provided in an embodiment of the present application;

[0150] Fig.58 is a brightness curve diagram under different grayscales provided in an embodiment of the present application;

[0151] Fig.59 is a brightness curve diagram of the positions of pixel electrodes of adjacent pixels at different gray scales provided by an embodiment of the present application;

[0152] Fig.60 is a partial schematic diagram of a display panel provided in an embodiment of the present application;

[0153] Fig.61is a brightness curve diagram of a sub-pixel provided in an embodiment of the present application;

[0154] Fig.62 is a schematic diagram of a moiré pattern provided in an embodiment of the present application;

[0155] Fig.63 is a partial schematic diagram of a lens structure provided in an embodiment of the present application, in which an extension direction of the lens structure is parallel to an extension direction of the pixel electrode;

[0156] Fig.64 is a partial schematic diagram of the intersection of an extension direction of a lens structure and an extension direction of a pixel electrode provided in an embodiment of the present application;

[0157] Fig.65 It is a partial schematic diagram of a pixel electrode, a common electrode pattern and a black matrix structure provided in an embodiment of the present application;

[0158] Fig.66 This is a partial schematic diagram of a pixel electrode, a gate line and a black matrix structure provided in an embodiment of the present application;

[0159] Fig.67 This is a partial schematic diagram of another pixel electrode, gate line and black matrix structure provided in an embodiment of the present application;

[0160] Fig.68 This is a partial schematic diagram of another pixel electrode, gate line and black matrix structure provided in an embodiment of the present application;

[0161] Fig.69 It is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0162] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0163] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 1 It can be seen that the display panel 10 includes: an array substrate 101 and a color filter substrate 102 that are arranged opposite to each other, and a liquid crystal layer 103 located between the array substrate 101 and the color filter substrate 102 .

[0164] Figure 2 is a partial schematic diagram of an array substrate and a color filter substrate provided in an embodiment of the present application. Figure 2 It can be seen that the array substrate 101 includes: a first substrate 1011 , a plurality of pixels 1012 , a plurality of data (source) lines 1013 and a plurality of gate (gate) lines 1014 .

[0165] refer to Figure 2 , a plurality of pixels 1012 are located on the first substrate 1011, and each pixel 1012 includes: a plurality of first sub-pixels 10121 of a first color, a plurality of second sub-pixels 10122 of a second color, and a plurality of third sub-pixels 10123 of a third color. The plurality of sub-pixels of each color are arranged along a first direction (A1). Figure 2 A pixel 1012 is shown in the figure, and the pixel 1012 includes 12 first sub-pixels 10121, 12 second sub-pixels 10122 and 12 third sub-pixels 10123.

[0166] Optionally, the first color, the second color, and the third color are different from each other. For example, the first color is red (red, R), the second color is green (green, G), and the third color is blue (blue, B). That is, the first sub-pixel 10121 is a red sub-pixel, the second sub-pixel 10122 is a green sub-pixel, and the third sub-pixel 10123 is a blue sub-pixel.

[0167] Furthermore, the plurality of first sub-pixels 10121, the plurality of second sub-pixels 10122, and the plurality of third sub-pixels 10123 are arranged along the second direction A2. Optionally, the second direction A2 intersects with the first direction A1. For example, the first direction A1 is the pixel column direction of the display panel 10, and the second direction A2 is the pixel row direction of the display panel 10.

[0168] refer to Figure 2 , a plurality of data lines 1013 extend along a first direction A1 and are arranged along a second direction A2. Each data line 1013 is connected to a column of sub-pixels arranged along the first direction A1, and is used to provide a data signal for the column of sub-pixels.

[0169] refer to Figure 2 The display panel 10 includes a plurality of gate lines 1014 extending along the third direction A3 and arranged along the first direction A1 ( Figure 2 The third direction A3 is parallel to the second direction A2). Each gate line 1014 is connected to at least one sub-pixel arranged along the first direction A1, and the light-emitting areas of at least some of the sub-pixels included in the pixel are located on both sides of the gate line 1014. The third direction A3 intersects the first direction A1.

[0170] refer to Figure 3 The display panel 10 includes a plurality of opening areas 10a ( Figure 3, two opening areas 10a are shown, each opening area 10a is an area surrounded by two black matrix structures 10211 arranged and adjacent to each other along the second direction A2, and two gate lines 1014 arranged and adjacent to each other along the first direction A1. By making the light-emitting area of ​​the sub-pixel located on both sides of the gate line 1014, the light-emitting area of ​​the sub-pixel can cross the gate line 1014 and be located in the two opening areas 10a arranged along the first direction A1, so as to occupy at least two opening areas 10a arranged along the first direction A1. For each sub-pixel, its light-emitting area occupies two opening areas 10a, so as to facilitate continuous display of the two opening areas 10a.

[0171] refer to Figure 2 The color film substrate 102 includes: a second substrate ( Figure 2 The second substrate is a substrate that is not shown in the figure and a black matrix (BM) layer 1021 located on the second substrate. The black matrix layer 1021 includes a plurality of black matrix structures 10211 extending along the first direction A1 and arranged along the second direction A2. Each black matrix structure 10211 covers at least one data line 1013.

[0172] Furthermore, the orthographic projection of the black matrix layer 1021 on the first substrate 1011 does not overlap with the orthographic projection of the target line segment of the gate line 1014 on the first substrate 1011. The target line segment is a line segment located between adjacent sub-pixels along the first direction A1 and does not overlap with the data line 1013. That is, the black matrix layer 1021 does not include a black matrix structure for covering the gate line 1014.

[0173] In the embodiment of the present application, since the gate line 1014 is not covered by the black matrix structure 10211, the display panel 10 includes a plurality of sub-pixels arranged along the first direction A1, and the continuity of the light-emitting areas is good, so that the display panel 10 can achieve continuous display in the first direction A1, and the display effect of the display panel 10 is better.

[0174] In summary, an embodiment of the present application provides a display panel, in which pixels in an array substrate of the display panel include a plurality of sub-pixels of different colors, each data line is connected to a column of sub-pixels arranged along a first direction, and each gate line is connected to at least one sub-pixel arranged along the first direction. In addition, the light-emitting area of ​​the sub-pixel is located on both sides of the gate line, that is, it can cross two opening areas located on both sides of the gate line, so as to facilitate the continuous display of the two opening areas arranged in the first direction. In addition, since the black matrix structure does not cover the target line segment of the gate line, the influence of the black matrix structure on the continuous display in the first direction can be avoided, so as to ensure that the display panel realizes continuous display in the first direction, and the display effect of the display panel is better.

[0175] refer to Figure 2It can also be seen that the array substrate 101 further includes: a pixel electrode layer b1 located on the first substrate 1011. The pixel electrode layer b1 includes a plurality of pixel electrodes b1a arranged at intervals. The shape of the positive projection of the pixel electrode b1a on the first substrate 1011 is a strip. The extension direction of the pixel electrode b1a intersects the first direction A1, the second direction A2 and the third direction A3. That is, the pixel electrode b1a is inclined relative to the data line 1013 and the gate line 1014. Optionally, the distance between adjacent pixel electrodes b1a can range from 5μm (micrometers) to 10μm.

[0176] Each of the first sub-pixel 10121, the second sub-pixel 10122 and the third sub-pixel 10123 includes: a pixel electrode b1a. One pixel electrode b1a is used to form a light-emitting area of ​​one sub-pixel.

[0177] In the embodiment of the present application, the light-emitting area of ​​the sub-pixel is located on both sides of the gate line 1014 by tilting the pixel electrode b1a of the sub-pixel. That is, the pixel electrode b1a of the sub-pixel can occupy at least two opening areas 10a arranged along the first direction A1. In addition, the pixel electrode b1a is tilted to avoid the generation of rainbow lines on the display panel 10.

[0178] Since the pixel electrode b1a is tilted, Figure 2 and Figure 3 , the orthographic projection of the pixel electrode b1a on the first substrate 1011 partially overlaps with the orthographic projection of at least one gate line 1014 on the first substrate 1011. That is, one end of the pixel electrode b1a is located at the opening area 10a on the first side of the gate line 1014, and the other end is located at the opening area 10a on the second side of the gate line 1014. The pixel electrode b1a may cross the gate line 1014 and be disposed in the two opening areas 10a on both sides of the gate line 1014.

[0179] In the embodiment of the present application, the extension directions of the plurality of pixel electrodes b1a in the display panel 10 are parallel (the extension direction of the pixel electrode b1a is a fixed direction, and the inclination angle of the pixel electrode b1a relative to the second direction A2 is a fixed angle) to ensure the display uniformity of different areas of the display panel 10. Moreover, for any pixel electrode b1a, the extension direction of the pixel electrode b1a is collinear with the extension direction of the pixel electrodes b1a in different rows in the first direction A1. That is, the pixel electrode b1a can completely overlap with the pixel electrodes b1a in different rows when extending along the inclination angle.

[0180] refer to Figure 4 , the angle α between the extending direction of the pixel electrode b1a and the second direction A2 satisfies:

[0181] tanα=(n×b) / a=i / j Formula (1)

[0182] Wherein, in the above formula (1), a is the length of the sub-pixel along the second direction A2, b is the length of the sub-pixel along the first direction A1, and n, i and j are all positive integers. The length a of the sub-pixel along the second direction A2 is equal to the sum of the length of the black matrix structure 10211 along the second direction A2 and the distance between adjacent black matrix structures 10211 in the second direction A2.

[0183] Moreover, the length a of the sub-pixel along the second direction A2 is equal to the length L2 of the pixel 1012 along the second direction A2 divided by the number of sub-pixels along the second direction A2 included in the pixel 1012. For example, if the number of sub-pixels along the second direction A2 included in the pixel 1012 is 3, then the length a of the sub-pixel along the second direction A2=L2 / 3. The length b of the sub-pixel along the first direction A1 is equal to the length L1 of the pixel 1012 along the first direction A1 divided by the number of sub-pixels along the first direction A1 included in the pixel 1012 ( Figure 4 ( L1 is not marked in the figure). For example, the number of sub-pixels included in the pixel 1012 along the second direction A2 is 12, and the length b of the sub-pixels along the second direction A2 is L1 / 12.

[0184] In the embodiment of the present application, the optimal value of the angle α is related to the type of actual product. For example, when the display panel is applied to a mobile terminal (smartphone) or a tablet computer, since the user may display the screen horizontally or vertically when using the mobile terminal and the tablet computer, if a 3D display effect is required in both the horizontal and vertical directions, the product optimal value of the angle α may be 45° (degrees). Alternatively, when the display panel is applied to a laptop computer, a desktop computer or a television, since the user usually only needs a horizontal screen display when using a laptop computer, a desktop computer and a television, it is sufficient to only realize a 3D display effect in the horizontal direction, and the product optimal value of the angle α may be 90°.

[0185] For a display panel with a certain number of views (the number of views can represent the number of sub-pixels of any color included in each pixel), different angles α are calculated by selecting different n using the above formula (1). Based on the type of product, an angle α closest to the optimal value of the product is selected from the multiple calculated angles α as the optimal angle α for the number of views. That is, the angle α needs to satisfy the above formula (1) and be closest to the optimal value of the product. Among them, the n corresponding to the optimal angle α calculated by the above formula (1) can be used as the most reasonable n.

[0186] Optionally, when the pixel 1012 includes 12 first sub-pixels 10121, 12 second sub-pixels 10122, and 12 third sub-pixels 10123 (this solution may be referred to as 12view), the angle between the extension direction of the pixel electrode b1a and the second direction A2 may preferably be arctan(1 / 2), arctan(3 / 4), and 45°. When the pixel 1012 includes 13 first sub-pixels 10121, 13 second sub-pixels 10122, and 13 third sub-pixels 10123 (this solution may be referred to as 13view), the angle between the extension direction of the pixel electrode b1a and the second direction A2 may preferably be arctan(3 / 13), arctan(6 / 13), arctan(9 / 13), arctan(12 / 13), and arctan(15 / 13). When the pixel 1012 includes 11 first sub-pixels 10121, 11 second sub-pixels 10122 and 11 third sub-pixels 10123 (this scheme can be called 11view), the angle between the extension direction of the pixel electrode b1a and the second direction A2 can preferably be arctan (12 / 11), arctan (9 / 11), arctan (6 / 11) and arctan (15 / 11).

[0187] In the embodiment of the present application, in the second direction A2, there is a gap between any two adjacent sub-pixels of different colors. Figure 5 In the embodiment, a plurality of first sub-pixels 10121 of a first color and a plurality of second sub-pixels 10122 of a second color are adjacent to each other in the second direction A2, and there are gaps between the plurality of first sub-pixels 10121 and the plurality of second sub-pixels 10122. Alternatively, a plurality of second sub-pixels 10122 of a second color and a plurality of third sub-pixels 10123 of a third color are adjacent to each other in the second direction A2, and there are gaps between the plurality of second sub-pixels 10122 and the plurality of third sub-pixels 10123.

[0188] Continue to refer Figure 5 , the gap between any two adjacent sub-pixels of color has at least two data lines 1013. At least one data line 1013 located in the same gap is connected to a sub-pixel of one color of the two adjacent sub-pixels, and at least one data line 1013 located in the same gap is connected to a sub-pixel of the other color of the two adjacent sub-pixels. For example, Figure 5 There are two data lines 1013 in the gap, one of which is connected to the sub-pixel of the first color, and the other data line 1013 is connected to the sub-pixel of the second color.

[0189] In the embodiment of the present application, for a plurality of target sub-pixels (taking 1012a in the figure as an example) of the same color and arranged along the first direction A1 included in the pixel 1012, the plurality of target sub-pixels have corresponding at least two target data lines (taking 1013a and 1013b in the figure as an example). At least one of the at least two target data lines is located at a first side of the plurality of sub-pixels 1012 along the second direction A2, and at least one target data line 1013 is located at a second side of the plurality of sub-pixels 1012 along the second direction A2.

[0190] Among the corresponding at least two target data lines, at least one target data line is used to connect to a part of the target sub-pixels of the plurality of target sub-pixels, and at least one target data line is used to connect to another part of the target sub-pixels of the plurality of target sub-pixels. That is, the plurality of sub-pixels arranged along the first direction A1 can be connected to at least two data lines 1013, and the at least two data lines are used to provide data signals for the plurality of sub-pixels.

[0191] refer to Figure 5 , the target sub-pixels connected to two target data lines providing data signals for multiple target sub-pixels are arranged alternately. Figure 5 Taking the 12 first sub-pixels 10121 included in the pixel 1012 as 12 target sub-pixels as an example, a target data line 1013a located on the first side (the left side in the figure) of the 12 first sub-pixels 10121 is connected to the first sub-pixels 10121 numbered 2, 4, 6, 8, 10 and 12 among the 12 first sub-pixels 10121, and a target data line 1013b located on the second side (the right side in the figure) of the 12 first sub-pixels 10121 is connected to the first sub-pixels 10121 numbered 1, 3, 5, 7, 9 and 11 among the 12 first sub-pixels 10121.

[0192] By means of this design, a column of sub-pixels can be connected to at least two data lines 1013, and data signals can be provided to the sub-pixels in the same column through at least two data lines 1013. By means of this design, the number of gate lines 1014 required for each pixel 1012 can be reduced, and the number of gate lines 1014 included in the entire display panel 10 can be reduced, and gate signals can be provided to the pixels 1012 included in the display panel 10 through a smaller number of gate lines 1014.

[0193] For example, the number of gate lines 1014 that the display panel 10 provides gate signals for each pixel 1012 may be equal to the number of sub-pixels of any color included in the pixel 1012 divided by the number of data lines 1013 designed with gaps. Assuming that the pixel 1012 includes 12 first sub-pixels 10121, 12 second sub-pixels 10122, and 12 third sub-pixels 10123, and the gap is designed with two data lines 1013, the number of gate lines 1014 connected to the sub-pixels included in the pixel 1012 is 12÷2=6.

[0194] And because the number of gate lines 1014 included in the display panel 10 is less than the number of sub-pixels arranged along the first direction A1 (ie, the number of rows of sub-pixels 1012 ), each gate line 1014 can be connected to at least two sub-pixels arranged along the first direction A1 .

[0195] Optional, reference Figure 5 , taking the case where a pixel 1012 includes 12 first sub-pixels 10121, 12 second sub-pixels 10122, and 12 third sub-pixels 10123, and two data lines 1013 are provided in each gap, the display panel 10 includes 6 gate lines 1014 connected to the sub-pixels in the pixel 1012. Moreover, the 6 gate lines 1014 are arranged along the first direction A1, and each gate line 1014 is connected to two adjacent sub-pixels of the 12 sub-pixels arranged along the first direction A1 included in the pixel 1012.

[0196] For each pixel 1012, each gate line 1014 may be connected to two first sub-pixels 10121, two second sub-pixels 10122, and two third sub-pixels 10123 in the pixel 1012. Moreover, among the two first sub-pixels 10121 connected to each gate line 1014, one of the first sub-pixels 10121 is connected to a data line 1013 disposed in a gap between the first side of the two first sub-pixels 10121, and the other first sub-pixel 10121 is connected to a data line 1013 disposed in a gap between the second side of the two first sub-pixels 10121. Among the two second sub-pixels 10122 connected to each gate line 1014, one of the second sub-pixels 10122 is connected to a data line 1013 disposed in a gap between the first side of the two second sub-pixels 10122, and the other second sub-pixel 10122 is connected to a data line 1013 disposed in a gap between the second side of the two second sub-pixels 10122. Among the two third sub-pixels 10123 connected to each gate line 1014, one of the third sub-pixels 10123 is connected to a data line 1013 set in the gap on the first side of the two third sub-pixels 10123, and the other third sub-pixel 10123 is connected to a data line 1013 set in the gap on the second side of the two third sub-pixels 10123.

[0197] In the embodiment of the present application, each black matrix structure 10211 covers at least two data lines 1013 located in the same gap. That is, the orthographic projection of each black matrix structure 10211 on the first substrate 1011 covers the orthographic projections of all data lines 1013 in the same gap on the first substrate 1011. For example, assuming that each gap is designed with two data lines 1013, the orthographic projection of each black matrix structure 10211 on the first substrate 1011 covers the orthographic projections of the two data lines 1013 in the same gap on the first substrate 1011. Alternatively, assuming that each gap is designed with three data lines 1013, the orthographic projection of each black matrix structure 10211 on the first substrate 1011 covers the orthographic projections of the three data lines 1013 in the same gap on the first substrate 1011.

[0198] In the embodiment of the present application, by connecting each column of sub-pixels to at least two data lines 1013 (this solution may be referred to as a Mutil Source solution), the number of data lines 1013 corresponding to the pixel 1012 may be increased, thereby reducing the number of gate lines 1014 required for the pixel 1012. In addition, the charging time H of each row of pixels may satisfy:

[0199] H=1 / (f×(m+r)×k) Formula (2)

[0200] Wherein, in the above formula (2), f is the refresh frequency, m is the gate row resolution, r is the number of dummy gate lines, and k is the number of gate lines 1014 in each pixel 1012. When the number k of gate lines 1014 required by the pixel 1012 is reduced, the charging time H is increased, thereby ensuring that each sub-pixel is fully charged. Wherein, the gate row resolution may refer to the number of rows of pixels 1012, or may refer to the number of pixels 1012 included in each column of pixels 1012.

[0201] As an optional implementation, refer to Figure 5 , the gap between the adjacent sub-pixels of the first target color and the second target color has two data lines 1013. One of the data lines 1013 located in the same gap is connected to the sub-pixel of the first target color, and the other data line 1013 is connected to the sub-pixel of the second target color. Figure 5 In the illustrated embodiment, the number of gate lines 1014 included in the display panel 10 is half the number of sub-pixels included in the display panel 10 and arranged along the first direction A1.

[0202] As another optional implementation, refer to Figure 6 , the gap between the adjacent sub-pixels of the first target color and the sub-pixels of the second target color has three data lines 1013. Two of the data lines (1013a and 1013c) located in the same gap are connected to the sub-pixels of the first target color, and another data line (1013b) is connected to the sub-pixel of the second target color. Alternatively, two of the data lines located in the same gap are connected to the sub-pixels of the first target color, and another data line is connected to the sub-pixel of the second target color. Figure 6 In the illustrated embodiment, the number of the gate lines 1014 included in the display panel 10 is 1 / 3 of the number of the sub-pixels included in the display panel 10 and arranged along the first direction A1.

[0203] In addition, the gap between the adjacent sub-pixels of the first target color and the sub-pixels of the second target color may have a greater number of data lines 1013. Part of the data lines 1013 located in the same gap are connected to the sub-pixels of the first target color, and another part of the data lines 1013 are connected to the sub-pixels of the second target color. The embodiment of the present application does not limit the number of data lines 1013 set in the gap.

[0204] It should be noted that the more data lines 1013 are provided with gaps, the more complicated the layout design of the display panel 10 will be, so the number of gaps provided cannot be too large. Generally, two or three data lines 1013 are provided with gaps.

[0205] refer to Figure 7The array substrate 101 further includes a common (com) electrode layer b2. The liquid crystal molecules in the liquid crystal layer 103 included in the display panel 10 can be deflected under the common drive of the pixel electrode layer b1 and the common electrode layer b2, thereby making the display panel 10 emit light. Figure 7 The common electrode layer b2 includes: a plurality of first electrode portions b21 arranged along the second direction A2, and a plurality of second electrode portions b22 arranged along the second direction A2. The plurality of first electrode portions b21 and the plurality of second electrode portions b22 are arranged alternately.

[0206] The orthographic projection of the first electrode portion b21 on the first substrate 1011 is located within the orthographic projection of the black matrix structure 10211 on the first substrate 1011. The second electrode portion b22 includes a plurality of common electrode patterns b221 arranged and spaced apart along the first direction A1. One end of each common electrode pattern b221 is connected to one of the two adjacent first electrode portions b21, and the other end is connected to the other of the two adjacent first electrode portions b21.

[0207] The orthographic projection of each common electrode pattern b221 on the first substrate 1011 is in the shape of a strip, and the extension direction of the common electrode pattern b221 is parallel to the extension direction of the pixel electrode b1a. The orthographic projection of the common electrode pattern b221 on the first substrate 1011 and the orthographic projection of the pixel electrode b1a on the first substrate 1011 at least partially overlap. Optionally, the distance between adjacent common electrode patterns b221 ranges from 3 μm to 10 μm.

[0208] refer to Figure 7 The first electrode portion b21 is an integral structure, and the plurality of common electrode patterns b221 of the second electrode portion b22 are connected through the first electrode portion b21, thereby realizing that the common electrode layer b2 transmits the common electrode signal.

[0209] It should be noted that the second electrode portion b22 of the common electrode layer b2 may also be an integral structure, that is, the common electrode layer b2 may be an entire electrode layer covering the display area of ​​the display panel 10. The specific design of the common electrode layer b2 is not limited in the present embodiment.

[0210] refer to Figure 2 , Figure 5 and Figure 6 Each sub-pixel further includes a switch transistor T. The switch transistor T includes a source electrode, a drain electrode, and a channel located between the source electrode and the drain electrode. The source electrode is connected to the data line 1013, and the drain electrode is connected to the pixel electrode b1a.

[0211] In the embodiment of the present application, since the gate line 1014 is not covered by the black matrix structure 10211, in order to reduce the influence of the gate line 1014 on the display effect, the width of the gate line 1014 can be appropriately reduced (i.e., the length of the orthographic projection of the gate line 1014 on the first substrate 1011 along the fourth direction A4 is reduced). Wherein, the width reduction of the gate line 1014 will cause the length of the channel of the switching transistor T to be smaller. However, the length of the channel will affect the electrical characteristics and working performance of the switching transistor T, so the length of the channel cannot be designed to be smaller. The fourth direction A4 is perpendicular to the third direction A3. Figure 2 , Figure 5 and Figure 6 In the embodiment, the fourth direction A4 is the pixel column direction.

[0212] Figure 8 is a partial cross-sectional view of an array substrate provided in an embodiment of the present application. Figure 8 , the array substrate 101 includes a gate layer b3 and a transparent electrode layer b4 in contact with the gate layer b3. The gate line 1014 is located on the gate layer b3. The transparent electrode layer b4 includes a plurality of transparent electrode patterns b41. In the fourth direction A4, the orthographic projection of the transparent electrode pattern b41 on the first substrate 1011 covers the orthographic projection of the gate line 1014 on the first substrate 1011. In addition, the length of the orthographic projection of the transparent electrode pattern b41 on the first substrate 1011 along the fourth direction A4 is greater than the length of the orthographic projection of the gate line 1014 on the first substrate 1011 along the fourth direction A4.

[0213] Since the transparent electrode pattern b41 is in direct contact with the gate line 1014, the length of the orthographic projection of the transparent electrode pattern b41 on the first substrate 1011 along the fourth direction A4 is the length of the channel. Thus, when the width of the gate line 1014 is small, the length of the channel can be increased by the transparent electrode pattern b41 to ensure the electrical characteristics and working performance of the switching transistor. Furthermore, since the transparent electrode pattern b41 is made of a transparent material, even though the width of the transparent electrode pattern b41 is wide, it will not affect the size of the opening area 10a of the display panel 10, and the display effect of the display panel 10 can be ensured.

[0214] refer to Figure 8The array substrate 101 includes: a buffer layer (buffer) b5, an active layer (poly) b6, a gate insulating layer (gate insulator, GI) b7, a gate layer b3, a transparent electrode layer b4, an interlayer dielectric layer (inter level dielectric, ILD) b8, a source and drain layer b9, a first passivation layer (passivation layer, PVX) b10, a first planarization layer (planarization layer, PLN) b11, a pixel electrode layer b1, a second passivation layer b12, a second planarization layer b13 and a common electrode layer b2.

[0215] The active layer b6 includes a plurality of active patterns b61, each of which includes a source region b61a, a drain region b61b and a channel region b61c. Each active pattern b61 is used to form a partial structure of a switch transistor T.

[0216] The interlayer dielectric layer b8 and the gate insulating layer b7 have a first via hole g1 for exposing the source region b61a of the active pattern b61. Figure 8 Since the gate insulating layer b is only located in the channel region b61c and does not cover the source region b61a, the first via hole g1 is only located in the interlayer dielectric layer b8.

[0217] The source-drain layer b9 includes a plurality of data lines 1013 and a plurality of source-drain patterns. Each source-drain pattern is connected to one data line 1013, and each source-drain pattern is connected to a source region b61a of an active pattern b61 through a first via hole g1. Figure 8 The source / drain pattern and the data line 1013 are represented by the same pattern.

[0218] The gate insulating layer b7, the interlayer dielectric layer b8, the first passivation layer b10 and the first planar layer b11 have a second via hole g2. The second via hole g2 is used to expose the drain region b61b.

[0219] Each pixel electrode b1a in the pixel electrode layer b1 has a first portion b1a1 located in the second via hole g2, and a second portion b1a2 located on the side of the first flat layer b11 away from the first substrate 1011. The first portion b1a1 and the drain region b61b of the active pattern b61 are connected through the second via hole g2, and the distance between the first portion b1a1 and the first substrate 1011 is smaller than the distance between the second portion b1a2 and the first substrate 1011. That is, the surface of the pixel electrode b1a away from the first substrate 1011 is a non-flat surface.

[0220] At least part of the second flat layer b13 is located on the side of the first portion b1a1 away from the first substrate 1011 , that is, the second flat layer b13 may be filled in the second via hole g2 , so that the surface of the common electrode layer b2 close to the first substrate 1011 is a flat surface.

[0221] Normally, if the surface of the common electrode layer b2 near the first substrate 1011 is not flat, it will cause the surface of the array substrate 101 near the color filter substrate 102 to be not flat, which will in turn cause the liquid crystal layer 103 to be filled unevenly, affecting the display effect of the display panel 10. Therefore, in order to avoid affecting the display effect due to the uneven surface, the orthographic projection of the black matrix structure 10211 on the first substrate 1011 can cover the orthographic projection of the second via g2 on the first substrate 1011, so that the area where the second via g2 is located is a non-opening area. However, this design will cause the width of the black matrix structure 10211 along the second direction A2 to be wider, affecting the aperture ratio of the display panel 10.

[0222] In the embodiment of the present application, the second flat layer b13 is used to fill the second via hole g2 to improve the flatness of the surface of the common electrode layer b2 close to the first substrate 1011. In this way, the filling uniformity of the liquid crystal layer 103 can be improved, and the controllability of the liquid crystal molecules in the liquid crystal layer 103 can be ensured, so that the black matrix structure 10211 does not need to be used to cover the second via hole g2. Furthermore, the width of the black matrix structure 10211 along the second direction A2 can be small, thereby improving the aperture ratio of the display panel 10. Figure 8 In the figure, the second flat layer b13 is only located at the second via hole g2 . In fact, the second flat layer b13 may also be located at a side of the second passivation layer b12 away from the first substrate 1011 .

[0223] Fig. 9 is a partial cross-sectional view of another array substrate provided in an embodiment of the present application. Fig. 9 The array substrate 101 includes: a buffer layer b5, an active layer b6, a gate insulating layer b7, a gate layer b3, a transparent electrode layer b4, an interlayer dielectric layer b8, a source and drain layer b9, a first passivation layer b10, an electrode transfer layer b14, a first planarization layer b11, a pixel electrode layer b1, a second passivation layer b12, and a common electrode layer b2, which are located on the first substrate 1011 and stacked in sequence.

[0224] The active layer b6 includes a plurality of active patterns b61, each of which includes a source region b61a, a drain region b61b and a channel region b61c. Each active pattern b61 is used to form a partial structure of a switch transistor T.

[0225] The interlayer dielectric layer b8 and the gate insulating layer b7 have a first via hole g1 for exposing the source region b61a of the active pattern b61.

[0226] The source-drain layer b9 includes a plurality of data lines 1013 and a plurality of source-drain patterns. Each source-drain pattern is connected to one data line 1013, and each source-drain pattern is connected to a source region b61a of an active pattern b61 through a first via hole g1.

[0227] The gate insulating layer b7, the interlayer dielectric layer b8 and the first passivation layer b10 have a third via hole g3, and the third via hole g3 is used to expose the drain region b61b. Fig. 9 Since the gate insulating layer b is only located in the channel region b61c and does not cover the drain region b61b, the third via hole g3 is only located in the interlayer dielectric layer b8 and the first passivation layer b10.

[0228] The electrode switching layer b14 includes a plurality of electrode switching patterns b141. The electrode switching patterns b141 are connected to a drain region b61b of an active pattern b61 through a third via g3. Moreover, the orthographic projection of the electrode switching patterns b141 on the first substrate 1011 at least partially overlaps with the orthographic projection of the data line 1013 on the first substrate 1011.

[0229] The first planar layer b11 has a fourth via hole g4 for exposing the electrode switching pattern b141 , and an orthographic projection of the fourth via hole g4 on the first substrate 1011 at least partially overlaps with an orthographic projection of the data line 1013 on the first substrate 1011 .

[0230] Each pixel electrode b1a in the pixel electrode layer b1 has a third portion b1a3 located in the fourth via hole g4, and a fourth portion b1a4 located on the side of the first flat layer b11 away from the first substrate 1011. The third portion b1a3 and the drain region b61b of the active pattern b61 are connected through the fourth via hole g4, and the distance between the third portion b1a3 and the first substrate 1011 is smaller than the distance between the fourth portion b1a4 and the first substrate 1011. That is, the surface of the pixel electrode b1a away from the first substrate 1011 is a non-flat surface.

[0231] exist Fig. 9 In the array substrate 101 shown, the active pattern b61 and the pixel electrode b1a are connected via the electrode switching pattern b141. Furthermore, the orthographic projection of the connection position (the fourth via g4) between the electrode switching pattern b141 and the pixel electrode b1a on the first substrate 1011 overlaps with the positive pixel 1012 of the data line 1013 on the first substrate 1011.

[0232] Normally, the orthographic projection of the black matrix structure 10211 on the first substrate 1011 covers the orthographic projection of the data line 1013 on the first substrate 1011. Therefore, the orthographic projection of the fourth via hole g4 on the first substrate 1011 partially overlaps with the positive pixel 1012 of the data line 1013 on the first substrate 1011, so that the orthographic projection of the black matrix structure 10211 on the first substrate 1011 can also cover the orthographic projection of the fourth via hole g4 on the first substrate 1011. Therefore, although the liquid crystal layer 103 at the fourth via hole g4 is filled unevenly, the black matrix structure 10211 covers the fourth via hole g4, so the display effect of the display panel 10 will not be affected.

[0233] exist Fig. 9 In the array substrate 101, since an additional electrode transfer layer b14 is provided, and the electrode transfer layer b14 is connected to the pixel electrode b1a (the electrode transfer layer b14 and the pixel electrode b1a transmit the same signal), the distance between the electrode transfer layer b14 and the source-drain electrode layer b9 in the film thickness direction is relatively close. Furthermore, the electrode transfer layer b14 and the source-drain electrode layer b9 are relatively close, so that the data signal transmitted by the data line 1013 of the source-drain electrode layer b9 interferes with the pixel 1012.

[0234] For the above reasons, reference Fig.10 The first passivation layer b10 includes a first sub-passivation layer b101 and a second sub-passivation layer b102. The array substrate 101 also includes a shielding layer b15 located between the first sub-passivation layer b101 and the second sub-passivation layer b102. The shielding layer b15 includes a plurality of shielding patterns b151. The shielding patterns b151 are located between the data lines 1013 and the electrode switching patterns b141.

[0235] In which, in the second direction A2, the orthographic projection of the shielding pattern b151 on the first substrate 1011 covers the orthographic projections of at least two data lines 1013 on the first substrate 1011, and the length of the shielding pattern b151 along the second direction A2 is less than the length of the black matrix structure 10211 along the second direction A2.

[0236] Since the shielding pattern b151 covers at least two data lines 1013 in the second direction A2, it is possible to prevent the data line 1013 located in the source-drain electrode layer b9 from interfering with the electrode transfer pattern b141 located in the electrode transfer layer b14, thereby ensuring the display effect of the display panel 10. In addition, the length of the shielding pattern b151 along the second direction A2 is less than the length of the black matrix structure 10211 along the second direction A2, so the design of the shielding pattern b151 will not affect the size of the opening area 10a of the display panel 10. However, the distance between the shielding pattern b151 and the data line 1013 in the source-drain electrode layer b9 in the thickness direction is relatively close, which will generate a certain capacitive load on the data line 1013.

[0237] For further reference, Fig.11 , the array substrate 101 further includes: a spacer layer b16 located between the first sub-passivation layer b101 and the shielding layer b15. The orthographic projection of the spacer layer b16 on the first substrate 1011 at least covers the orthographic projection of the shielding pattern b151 on the first substrate 1011. In this way, the distance between the shielding layer b15 and the source-drain electrode layer b9 in the thickness direction can be increased, and the capacitance loading generated by the shielding layer b15 on the data line 1013 can be reduced.

[0238] Fig.12 FIG. 1 is a partial cross-sectional view of another array substrate provided in an embodiment of the present application. Fig.12 The array substrate 101 includes: a source and drain layer b9, a buffer layer b5, an active layer b6, a gate insulating layer b7, a transparent electrode layer b4, a gate layer b3, a first passivation layer b10, a first flat layer b11, an electrode transfer layer b14, a second passivation layer b12, a second flat layer b13, a pixel electrode layer b1, a third passivation layer b17 and a common electrode layer b2, which are located on the first substrate 1011 and stacked in sequence. Fig.12 The connection mode of the array substrate 101 shown may be a top gate bottom connection (TGBC).

[0239] The source-drain electrode layer b9 includes a plurality of data lines 1013 and a plurality of source-drain patterns, each of which is connected to one data line 1013 .

[0240] The buffer layer b5 has a fifth via hole g5, and the fifth via hole g5 is used to expose a partial area of ​​the source-drain pattern. The fifth via hole g5 is used for connecting the subsequent active pattern b61 and the source-drain pattern.

[0241] The active layer b6 includes a plurality of active patterns b61, each of the active patterns b61 includes a source region b61a, a drain region b61b and a channel region b61c, and the source region b61a and the source-drain patterns are connected through a fifth via hole g5.

[0242] The first passivation layer b10 and the first planar layer b11 have a sixth via hole g6 , and the sixth via hole g6 is used to expose the drain region b61 b . The sixth via hole g6 is used for connecting the subsequent electrode transfer pattern b141 and the drain region b61 b .

[0243] The electrode transfer layer b14 includes a plurality of electrode transfer patterns b141, each of which has a fifth portion b141a located in the sixth via hole g6, and a sixth portion b141b located on the side of the first flat layer b11 away from the first substrate 1011. The fifth portion b141a and the drain region b61b of the active pattern b61 are connected through the sixth via hole g6, and the distance between the fifth portion b141a and the first substrate 1011 is smaller than the distance between the sixth portion b141b and the first substrate 1011. That is, the surface of the electrode transfer layer b14 away from the first substrate 1011 is a non-flat surface.

[0244] At least a portion of the second flat layer b13 is located in the sixth via hole g6, and a surface of the pixel electrode layer b1 close to the first substrate 1011 is a flat surface.

[0245] The second passivation layer b12 and the second planar layer b13 have a seventh via hole g7, and the seventh via hole g7 is used to expose a partial area of ​​the sixth portion b141b. The seventh via hole g7 is used for connecting the subsequent pixel electrode b1a and the electrode switching pattern b141.

[0246] Each pixel electrode b1a in the pixel electrode layer b1 and one sixth portion b141b are connected through a seventh via hole g7.

[0247] Normally, if the surface of the pixel electrode layer b1 near the first substrate 1011 is uneven, it will cause the surface of the array substrate 101 near the color filter substrate 102 to be uneven, which will in turn cause the filling of the liquid crystal layer 103 to be uneven, affecting the display effect of the display panel 10. Therefore, in order to avoid affecting the display effect due to the uneven surface, the orthographic projection of the black matrix structure 10211 on the first substrate 1011 can cover the orthographic projection of the sixth via g6 on the first substrate 1011, so that the area where the sixth via g6 is located is a non-opening area. However, this design will cause the width of the black matrix structure 10211 along the second direction A2 to be wider, affecting the aperture ratio of the display panel 10.

[0248] In the embodiment of the present application, the second flat layer b13 is used to fill the sixth via hole g6 to improve the flatness of the surface of the pixel electrode layer b1 close to the first substrate 1011. In this way, the filling uniformity of the liquid crystal layer 103 can be improved, and the controllability of the liquid crystal molecules in the liquid crystal layer 103 can be ensured, so that the sixth via hole g6 does not need to be covered with a black matrix structure 10211. Furthermore, the width of the black matrix structure 10211 along the second direction A2 can be small, thereby improving the aperture ratio of the display panel 10.

[0249] In the embodiments of the present application, Fig.13 FIG. 1 is a partial cross-sectional view of another array substrate provided in an embodiment of the application. Fig.13 The array substrate 101 includes: a source and drain layer b9, a buffer layer b5, an active layer b6, a gate insulating layer b7, a transparent electrode layer b4, a gate layer b3, a first passivation layer b10, an electrode transfer layer b14, a first flat layer b11, a pixel electrode layer b1, a second passivation layer b12 and a common electrode layer b2, which are located on the first substrate 1011 and stacked in sequence. Fig.13 The connection mode of the array substrate 101 shown may be TGBC.

[0250] The source-drain electrode layer b9 includes a plurality of data lines 1013 and a plurality of source-drain patterns, each of which is connected to one data line 1013 .

[0251] The buffer layer b5 has a fifth via hole g5, and the fifth via hole g5 is used to expose a partial area of ​​the source-drain pattern. The fifth via hole g5 is used for connecting the subsequent active pattern b61 and the source-drain pattern.

[0252] The active layer b6 includes a plurality of active patterns b61, each of the active patterns b61 includes a source region b61a, a drain region b61b and a channel region b61c, and the source region b61a and the source-drain patterns are connected through a fifth via hole g5.

[0253] The first passivation layer b10 has an eighth via hole g8, and the eighth via hole g8 is used to expose the drain region b61b. The eighth via hole g8 is used for connecting the subsequent electrode transfer pattern b141 and the drain region b61b.

[0254] The electrode switching layer b14 includes a plurality of electrode switching patterns b141 , and each electrode switching pattern b141 is connected to the drain region b61 b through an eighth via hole g8 .

[0255] The first planar layer b11 has a ninth via hole g9 , and the ninth via hole g9 is used to expose a partial area of ​​the electrode switching pattern b141 .

[0256] The pixel electrode b1a has a seventh portion b1a7 located in the ninth via hole g9, and an eighth portion b1a8 located on the side of the first flat layer b11 away from the first substrate 1011. The seventh portion b1a7 and the electrode transfer pattern b141 are connected through the ninth via hole g9, and the distance between the seventh portion b1a7 and the first substrate 1011 is smaller than the distance between the eighth portion b1a8 and the first substrate 1011. That is, the surface of the pixel electrode b1a away from the first substrate 1011 is a non-flat surface.

[0257] This solution can be applied to a case where two data lines 1013 are arranged in each gap, and the orthographic projection of the ninth via g9 on the first substrate 1011 can be located between the two data lines 1013. Since the black matrix structure 10211 itself covers the two data lines 1013, it can also cover the ninth via g9 located between the two data lines 1013. Therefore, although the liquid crystal layer 103 at the ninth via g9 is filled unevenly, since the black matrix structure 10211 will cover the ninth via g9, the uneven position of the ninth via g9 will not affect the display effect of the display panel 10.

[0258] In the embodiment of the present application, the stacking relationship of the transparent electrode layer b4 and the gate layer b3 can be exchanged, for example Figures 8 to 11 In the embodiment, the transparent electrode layer b4 is located on a side of the gate layer b3 away from the first substrate 1011. Fig.12 and Fig.13 In the embodiment, the gate layer b3 is located on a side of the transparent electrode layer b4 away from the first substrate 1011. The embodiment of the present application does not limit the stacking relationship between the transparent electrode layer b4 and the gate layer b3.

[0259] In the embodiments of the present application, in order to clearly indicate each film layer, Fig.12 Taking the array substrate 101 shown as an example, the following briefly introduces each film layer of the array substrate 101 in the form of each single layer and a step-by-step stacking method.

[0260] Fig.14 is a partial schematic diagram of a source and drain layer provided in an embodiment of the present application. Fig.14 It can be seen that the source-drain electrode layer b9 includes multiple data lines 1013 and source-drain patterns. The source-drain patterns are patterns protruding from the sides of the data lines 1013 and are an integrated structure with the data lines 1013 .

[0261] Fig.15 It is a partial schematic diagram of a buffer layer provided in an embodiment of the present application. Fig.16 Schematic diagram of partial superposition of a source / drain layer and a buffer layer provided in an embodiment of the present application. Fig.15 and Fig.16The buffer layer b5 may have a fifth via hole g5, which is used to expose at least part of the source-drain pattern, and the fifth via hole g5 is used for connecting the subsequent active pattern b61 with the source-drain pattern. In order to facilitate the illustration of each fifth via hole g5 of the buffer layer b5, Fig.13 and Fig.14 The fifth via hole g5 is represented by a filling pattern. Other areas without a filling pattern are used to represent areas where the buffer layer b5 has solid material.

[0262] Fig.17 It is a partial schematic diagram of an active layer provided in an embodiment of the present application. Fig.18 Schematic diagram of partial superposition of a source / drain layer, a buffer layer and an active layer provided in an embodiment of the present application. Fig.17 and Fig.18 The active layer b6 includes a plurality of active patterns b61, and for the plurality of active patterns b61 corresponding to a data line 1013, a portion of the active patterns b61 is located on a first side of the data line 1013, and another portion of the active patterns b61 is located on a second side of the data line 1013.

[0263] Each active pattern b61 is connected to a corresponding data line 1013 through a fifth via hole g5 in the buffer layer b5.

[0264] In the embodiment of the present application, the display panel 10 includes a gate insulating layer b7 located on the side of the active layer b6 away from the first substrate 1011, which is used to insulate the active layer b6 from the subsequently formed gate layer b3. The gate insulating layer b7 can be a film layer covering the entire layer, which is not illustrated in the figure.

[0265] Fig.19 It is a partial schematic diagram of a transparent electrode layer provided in an embodiment of the present application. Fig. 20 This is a schematic diagram of a partial superposition of a source / drain layer, a buffer layer, an active layer, and a transparent electrode layer provided in an embodiment of the present application. Fig.19 and Fig. 20 The transparent electrode layer b4 includes a plurality of transparent electrode patterns b41 , and the positive projection of each transparent electrode pattern b41 on the first substrate 1011 partially overlaps with the positive pixel 1012 of the active pattern b61 on the first substrate 1011 .

[0266] Fig.21 It is a partial schematic diagram of a gate layer provided in an embodiment of the present application. Fig. 22 This is a schematic diagram of a partial superposition of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer and a gate layer provided in an embodiment of the present application. Fig.21 and Fig. 22The gate layer b3 includes a plurality of gate lines 1014, and the positive projection of each gate line 1014 on the first substrate 1011 partially overlaps with the positive pixel 1012 of the transparent electrode pattern b41 on the first substrate 1011. The gate line 1014 and the transparent electrode pattern b41 are in direct contact, and are used to form a channel region b61c of the switch transistor.

[0267] Fig.23 It is a partial schematic diagram of a first passivation layer and a first planarization layer provided in an embodiment of the present application. Fig.24 This is a schematic diagram of a partial superposition of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer and a first planar layer provided in an embodiment of the present application. Fig.23 and Fig.24 The first passivation layer b10 and the first planar layer b11 have a sixth via hole g6, and the sixth via hole g6 is used to expose the drain region b61b. The sixth via hole g6 is used for connecting the subsequent electrode transfer pattern b141 and the drain region b61b of the active pattern b61.

[0268] The first passivation layer b10 and the first flat layer b11 have the same film structure, so only Fig.23 and Fig.24 Furthermore, in order to conveniently illustrate the sixth via holes g6 of the first passivation layer b10 and the first planar layer b11, Fig.23 and Fig.24 The sixth via hole g6 is represented by a filling pattern. Other areas where no filling pattern is drawn are used to represent areas where the first passivation layer b10 and the first planarization layer b11 have solid materials.

[0269] Fig.25 It is a partial schematic diagram of an electrode transfer layer provided in an embodiment of the present application. Fig.26 This is a schematic diagram of the partial superposition of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, a first flat layer and an electrode transfer layer provided in an embodiment of the present application. Fig.25 and Fig.26 The electrode transfer layer b14 includes a plurality of electrode transfer patterns b141, and the fifth portion b141a of each electrode transfer pattern b141 is connected to the drain region b61b of the active pattern b61 through a sixth via g6. The electrode transfer pattern b141 also includes a sixth portion b141b that is an integral structure with the fifth portion b141a, and the sixth portion b141b is located on a side of the first flat layer b11 away from the first substrate 1011.

[0270] Fig. 27 It is a partial schematic diagram of a second planar layer provided in an embodiment of the present application. Fig.28This is a partial superposition diagram of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, a first flat layer, an electrode transfer layer and a second flat layer provided in an embodiment of the present application. Fig. 27 and Fig.28 The second planar layer b13 at least includes a filling portion for filling into the sixth via hole g6. For example, Fig. 27 and Fig.28 Only the portion filled to the sixth via hole g6 is shown by the filling pattern, and the remaining area without the pattern is used to represent the area without solid material. Of course, the second planar layer b13 can also be located in other areas, which is not limited in the embodiment of the present application.

[0271] Since the second planar layer b13 is located in the sixth via hole g6, the location of the sixth via hole g6 can be planarized, thereby ensuring that the surface close to the first substrate 1011 for forming the pixel electrode layer b1 is a flat surface.

[0272] Fig.29 It is a partial schematic diagram of a second passivation layer provided in an embodiment of the present application. Fig.30 This is a schematic diagram of a partial superposition of a source and drain electrode layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, a first flat layer, an electrode transfer layer, a second flat layer and a second passivation layer provided in an embodiment of the present application. Fig.29 and Fig.30 The second passivation layer b12 has a seventh via hole g7, and the seventh via hole g7 is used for connecting the subsequent pixel electrode b1a and the electrode switching pattern b141.

[0273] In order to facilitate the illustration of each seventh via hole g7 of the second passivation layer b12, Fig.29 and Fig.30 The seventh via hole g7 is represented by a filling pattern. Other areas without a filling pattern are used to represent areas where the second passivation layer b12 has solid material.

[0274] Fig.31 It is a partial schematic diagram of a pixel electrode layer provided in an embodiment of the present application. Fig.32 This is a schematic diagram of partial superposition of a source and drain electrode layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, a first flat layer, an electrode transfer layer, a second flat layer, a second passivation layer and a pixel electrode layer provided in an embodiment of the present application. Fig.31 and Fig.32The pixel electrode layer b1 includes a plurality of pixel electrode b1a patterns, and the orthographic projection of each pixel electrode b1a pattern on the first substrate 1011 is in the shape of a strip, and the extending direction of the pixel electrode b1a intersects both the first direction A1 and the second direction A2. Furthermore, each pixel electrode b1a can be connected to the electrode transfer pattern b141 through the seventh via g7.

[0275] A third passivation layer b17 may be formed on the pixel electrode layer b1 to insulate the pixel electrode layer b1 from a common electrode layer b2 to be formed subsequently.

[0276] Fig.33 It is a partial schematic diagram of a common electrode layer provided in an embodiment of the present application. Fig.34 This is a partial superposition diagram of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, a first flat layer, an electrode transfer layer, a second flat layer, a second passivation layer, a pixel electrode layer and a common electrode layer provided in an embodiment of the present application. Fig.33 and Fig.34 The common electrode layer b2 includes: a plurality of first electrode portions b21 arranged along the second direction A2, and a plurality of second electrode portions b22 arranged along the second direction A2. The plurality of first electrode portions b21 and the plurality of second electrode portions b22 are arranged alternately.

[0277] The orthographic projection of the first electrode portion b21 on the first substrate 1011 covers the orthographic projection of a data line 1013 on the first substrate 1011. The second electrode portion b22 includes a plurality of common electrode patterns b221 arranged and spaced apart along the first direction A1. One end of each common electrode pattern b221 is connected to one of the two adjacent first electrode portions b21, and the other end is connected to the other of the two adjacent first electrode portions b21.

[0278] The orthographic projection of each common electrode pattern b221 on the first substrate 1011 is in the shape of a strip, and the extension direction of the common electrode pattern b221 is parallel to the extension direction of the pixel electrode b1a. The orthographic projection of the common electrode pattern b221 on the first substrate 1011 and the orthographic projection of the pixel electrode b1a on the first substrate 1011 at least partially overlap.

[0279] Optionally, the length of the overlapping area of ​​the common electrode pattern b221 and the pixel electrode b1a along the direction perpendicular to the extension direction of the common electrode pattern b221 and the pixel electrode b1a is greater than or equal to 0.5 μm (micrometer), for example, 1 μm, so that the common electrode pattern b221 and the pixel electrode b1a can generate an electric field to drive the liquid crystal molecules in the liquid crystal layer 103 to deflect.

[0280] refer to Fig.33 The first electrode portion b21 is an integral structure, and the plurality of common electrode patterns b221 of the second electrode portion b22 are connected through the first electrode portion b21, thereby realizing that the common electrode layer b2 transmits the common electrode signal.

[0281] Fig.35 It is a partial schematic diagram of a black matrix layer provided in an embodiment of the present application. Fig.36 This is a partial superposition diagram of a source and drain electrode layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, a first flat layer, an electrode transfer layer, a second passivation layer, a second flat layer, a pixel electrode layer, a common electrode layer and a black matrix layer provided in an embodiment of the present application. Fig.35 and Fig.36 It can be seen that the black matrix layer 1021 includes a plurality of black matrix structures 10211 , and the orthographic projection of each black matrix structure 10211 on the first substrate 1011 covers the orthographic projection of the first electrode portion b21 on the first substrate 1011 .

[0282] Optionally, the orthographic projection of the black matrix structure 10211 on the first substrate 1011 covers the orthographic projection of a data line 1013 on the first substrate 1011, and the distance between the edge of the orthographic projection of the black matrix structure 10211 on the first substrate 1011 and the edge of the orthographic projection of the source-drain pattern on the first substrate 1011 is greater than or equal to 1 μm. This ensures that the black matrix structure 10211 completely covers the data line 1013 and the source-drain pattern, thereby avoiding affecting the display of the display panel 10.

[0283] In addition, Fig.13 Taking the array substrate 101 shown as an example, the following briefly introduces each film layer of the array substrate 101 in the form of each single layer and a step-by-step stacking method.

[0284] Fig.37 is a partial schematic diagram of a source and drain layer provided in an embodiment of the present application. Fig.37 It can be seen that the source-drain electrode layer b9 includes a plurality of data lines 1013, a source-drain pattern ( Fig.12 The data line 1013 and the source / drain pattern are in one piece, and the data line 1013 and the source / drain pattern are in a straight line.

[0285] Fig.38 It is a partial schematic diagram of a buffer layer provided in an embodiment of the present application. Fig.39 Schematic diagram of partial superposition of a source / drain layer and a buffer layer provided in an embodiment of the present application. Fig.38 and Fig.39The buffer layer b5 may have a fifth via hole g5, which is used to expose at least part of the source-drain pattern, and the fifth via hole g5 is used for connecting the subsequent active pattern b61 with the source-drain pattern. In order to facilitate the illustration of each fifth via hole g5 of the buffer layer b5, Fig.38 and Fig.39 The fifth via hole g5 is represented by a filling pattern. Other areas without a filling pattern are used to represent areas where the buffer layer b5 has solid material.

[0286] Fig.40 It is a partial schematic diagram of an active layer provided in an embodiment of the present application. Fig.41 Schematic diagram of partial superposition of a source / drain layer, a buffer layer and an active layer provided in an embodiment of the present application. Fig.40 and Fig.41 The active layer b6 includes a plurality of active patterns b61. For the plurality of active patterns b61 corresponding to the two data lines 1013, a portion of the active patterns b61 is located at a first side of the two data lines 1013, and another portion of the active patterns b61 is located at a second side of the two data lines 1013.

[0287] Each active pattern b61 and the data line 1013 closest to the active pattern b61 are connected through a fifth via hole g5 in the buffer layer b5.

[0288] In the embodiment of the present application, the display panel 10 includes a gate insulating layer located on the side of the active layer b6 away from the first substrate 1011, which is used to insulate the active layer b6 from the subsequently formed gate layer b3. The gate insulating layer b7 can be a film layer covering the entire layer, which is not illustrated in the figure.

[0289] Fig.42 It is a partial schematic diagram of a transparent electrode layer provided in an embodiment of the present application. Fig.43 This is a schematic diagram of a partial superposition of a source / drain layer, a buffer layer, an active layer, and a transparent electrode layer provided in an embodiment of the present application. Fig.42 and Fig.43 The transparent electrode layer b4 includes a plurality of transparent electrode patterns b41, and a positive projection of each transparent electrode pattern b41 on the first substrate partially overlaps with a positive pixel 1012 of the active pattern b61 on the first substrate.

[0290] Fig.44 It is a partial schematic diagram of a gate layer provided in an embodiment of the present application. Fig.45 This is a schematic diagram of a partial superposition of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer and a gate layer provided in an embodiment of the present application. Fig.44 and Fig.45The gate layer b3 includes a plurality of gate lines 1014, and the positive projection of each gate line 1014 on the first substrate 1011 partially overlaps with the positive pixel 1012 of the transparent electrode pattern b41 on the first substrate 1011. The gate line 1014 and the transparent electrode pattern b41 are directly structured to form the channel region b61c of the switch transistor.

[0291] Fig.46 It is a partial schematic diagram of a first passivation layer provided in an embodiment of the present application. Fig.47 This is a schematic diagram of a partial superposition of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer and a first passivation layer provided in an embodiment of the present application. Fig.46 and Fig.47 The first passivation layer b10 has an eighth via hole g8, and the eighth via hole g8 is used to expose the drain region b61b. The eighth via hole g8 is used for connecting the subsequent electrode transfer pattern b141 and the drain region b61b of the active pattern b61.

[0292] In order to facilitate the illustration of each eighth via hole g8 of the first passivation layer b10, Fig.46 and Fig.47 The eighth via hole g8 is represented by a filling pattern. Other areas without a filling pattern are used to represent areas where the first passivation layer b10 has solid material.

[0293] Fig.48 It is a partial schematic diagram of an electrode transfer layer provided in an embodiment of the present application. Fig.49 This is a schematic diagram of the partial superposition of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer and an electrode transfer layer provided in an embodiment of the present application. Fig.48 and Fig.49 The electrode transfer layer b14 is connected to the drain region b61b of the active pattern b61 through the eighth via hole g8.

[0294] Fig.50 It is a partial schematic diagram of a first planar layer provided in an embodiment of the present application. Fig.51 This is a schematic diagram of the partial superposition of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, an electrode transfer layer and a first flat layer provided in an embodiment of the present application. Fig.50 and Fig.51 It can be seen that the first flat layer b11 has a ninth via hole g9, which is used to expose a portion of the electrode transfer pattern b141. The ninth via hole g9 is used for connecting the subsequent pixel electrode b1a and the electrode transfer pattern b141.

[0295] In order to facilitate the illustration of each ninth via hole g9 of the first planar layer b11, Fig.50 and Fig.51The ninth via hole g9 is represented by a filling pattern. Other areas without a filling pattern are used to represent areas where the first planar layer b11 has solid material.

[0296] Fig.52 It is a partial schematic diagram of a pixel electrode layer provided in an embodiment of the present application. Fig.53 This is a schematic diagram of partial superposition of a source and drain electrode layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, an electrode transfer layer, a first flat layer and a pixel electrode layer provided in an embodiment of the present application. Fig.52 and Fig.53 The pixel electrode layer b1 includes a plurality of pixel electrode b1a patterns, and the orthographic projection of each pixel electrode b1a pattern on the first substrate 1011 is in the shape of a strip, and the extending direction of the pixel electrode b1a intersects both the first direction A1 and the second direction A2. Furthermore, each pixel electrode b1a can be connected to the electrode transfer pattern b141 through the ninth via g9.

[0297] A second passivation layer b12 may be formed on the pixel electrode layer b1 to insulate the pixel electrode layer b1 from a common electrode layer b2 to be formed subsequently.

[0298] Fig.54 It is a partial schematic diagram of a common electrode layer provided in an embodiment of the present application. Fig.55 This is a partial superposition diagram of a source and drain layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, an electrode transfer layer, a first flat layer, a pixel electrode layer, a second passivation layer and a common electrode layer provided in an embodiment of the present application. Fig.55 and Fig.55 The common electrode layer b2 includes: a plurality of first electrode portions b21 arranged along the second direction A2, and a plurality of second electrode portions b22 arranged along the second direction A2. The plurality of first electrode portions b21 and the plurality of second electrode portions b22 are arranged alternately.

[0299] The orthographic projection of the first electrode portion b21 on the first substrate 1011 covers the orthographic projections of the two data lines 1013 on the first substrate 1011. The second electrode portion b22 includes a plurality of common electrode patterns b221 arranged and spaced apart along the first direction A1. One end of each common electrode pattern b221 is connected to one of the two adjacent first electrode portions b21, and the other end is connected to the other of the two adjacent first electrode portions b21.

[0300] The orthographic projection of each common electrode pattern b221 on the first substrate 1011 is in the shape of a strip, and the extension direction of the common electrode pattern b221 is parallel to the extension direction of the pixel electrode b1a. The orthographic projection of the common electrode pattern b221 on the first substrate 1011 and the orthographic projection of the pixel electrode b1a on the first substrate 1011 at least partially overlap.

[0301] Optionally, the length of the overlapping area of ​​the common electrode pattern b221 and the pixel electrode b1a along the direction perpendicular to the extension direction of the common electrode pattern b221 and the pixel electrode b1a is greater than or equal to 0.5 μm (micrometer), for example, 1 μm, so that the common electrode pattern b221 and the pixel electrode b1a can generate an electric field to drive the liquid crystal molecules in the liquid crystal layer 103 to deflect.

[0302] Fig.56 It is a partial schematic diagram of a black matrix layer provided in an embodiment of the present application. Fig.57 This is a partial superposition diagram of a source and drain electrode layer, a buffer layer, an active layer, a transparent electrode layer, a gate layer, a first passivation layer, an electrode transfer layer, a first flat layer, a pixel electrode layer, a second passivation layer, a common electrode layer and a black matrix layer provided in an embodiment of the present application. Fig.56 and Fig.57 It can be seen that the black matrix layer 1021 includes a plurality of black matrix structures 10211 , and the orthographic projection of each black matrix structure 10211 on the first substrate 1011 covers the orthographic projection of the first electrode portion b21 on the first substrate 1011 .

[0303] Optionally, the orthographic projection of the black matrix structure 10211 on the first substrate 1011 covers the orthographic projection of the two data lines 1013 on the first substrate 1011, and the distance between the edge of the orthographic projection of the black matrix structure 10211 on the first substrate 1011 and the edge of the orthographic projection of the two data lines 1013 on the first substrate 1011 is greater than or equal to 1 μm. This ensures that the black matrix structure 10211 completely covers the two data lines 1013, thereby preventing the data lines 1013 from affecting the display of the display panel 10.

[0304] In an embodiment of the present application, the pixel electrode b1a has a first pixel portion b1aa, a second pixel portion b1ab and a third pixel portion b1ac. Among them, the first pixel portion b1aa, the second pixel portion b1ab and the third pixel portion b1ac are an integrated structure. The orthographic projection of the first pixel portion b1aa on the first substrate 1011 is located within the orthographic projection of the first target black matrix structure on the first substrate 1011, and the first pixel portion b1aa is used to connect to the electrode transfer pattern b141. The orthographic projection of the second pixel portion b1ab on the first substrate 1011 is located between the first target black matrix structure and the second target black matrix structure. The orthographic projection of the third pixel portion b1ac on the first substrate 1011 is located within the orthographic projection of the second target black matrix structure on the first substrate 1011. The first target black matrix structure and the second target black matrix structure are two black matrix structures 10211 adjacent to each other in the second direction A2.

[0305] Optionally, the length of the first pixel portion b1aa in the second direction A2 and the length of the third pixel portion b1ac in the second direction A2 are both greater than or equal to 1 μm. That is, the length of the portions of both ends of the pixel electrode b1a covered by the black matrix structure 10211 along the second direction A2 are both greater than or equal to 1 μm. Thus, light leakage from the edge of the pixel electrode b1a can be avoided, and the display effect of the display panel 10 can be ensured.

[0306] In the embodiment of the present application, the array substrate 101 included in the display panel 10 is designed as above, so that the display panel 10 can realize continuous light emission at each gray scale, and the effect is as follows: Fig.58 In the three cases where the gray scale is Lv64, Lv127 and Lv255, the brightness curve is approximately a straight line, that is, the brightness at different pixel electrodes is approximately the same, and the display panel 10 can achieve continuous light emission.

[0307] And, reference Fig.59 If the grayscales of adjacent pixel electrodes b1a are different, the brightness of the positions of adjacent pixel electrodes b1a in the display panel 10 is different. That is, the brightness of the light emitted by adjacent sub-pixels 1012 does not affect each other.

[0308] in, Fig.58 and Fig.59 It is only used to illustrate the brightness relationship between the positions of different pixel electrodes b1a in the display panel 10, and is not used to represent the film layer relationship of the actual product.

[0309] In the examples of this application, refer to Figure 1The display panel 10 further includes: a lens layer 104 located on a side of the color filter substrate 102 away from the array substrate 101. The lens layer 104 includes a plurality of lens structures 1041, and the surface of each lens structure 1041 away from the array substrate 101 is a curved surface.

[0310] Fig.60 is a partial schematic diagram of a display panel provided in an embodiment of the present application. Fig.60 The shape of the orthographic projection of the lens structure 1041 on the array substrate 101 is a strip. Fig.60 The extending direction of the lens structure 1041 is parallel to the extending direction of the pixel electrode b1a. That is, the extending direction of the lens structure 1041 intersects the first direction A1, the second direction A2 and the third direction A3.

[0311] The lens structure 1041 and the pixel electrode b1a included in the array substrate 101 constitute a display unit of the display panel 10, which can form a multi-directional 3D display effect and can meet the requirements of a horizontal or vertical 3D display screen. At the same time, the pixel electrode b1a and the lens structure 1041 in the display unit can span multiple opening areas 10a, so that a continuous display screen can be formed, achieving a display effect similar to continuous light emission.

[0312] For the solution in which the extending direction of the lens structure 1041 is parallel to the extending direction of the pixel electrode b1a, refer to Fig.61 During the display process of the display panel 10, when a sub-pixel is lit, the internal brightness distribution of the sub-pixel is uneven, and the electric field lines at the boundary position of the common electrode pattern b221 are more densely distributed, which will cause the brightness to have a peak at the boundary position of the common electrode pattern b221.

[0313] Among them, the internal brightness unevenness of a single sub-pixel usually has no effect on 2D display, but Fig.62 In 3D display, this microscopic unevenness phenomenon will form moiré patterns when projected at different angles after being magnified by the lens structure 1041, and the display effect of the display panel 10 is poor.

[0314] refer to Fig.63The reason why the scheme in which the extension direction of the lens structure 1041 is parallel to the extension direction of the pixel electrode b1a produces moiré is that the auxiliary lines of the lens structure 1041 (the auxiliary lines are lines at any position parallel to the extension direction of the lens structure 1041) will be parallel to the light bars of the pixel electrode b1a, which will cause the light beams of the pixel 1012 at the position of the auxiliary lines to be projected in the same direction. As a result, when the user is watching, sometimes they will see bright bars and sometimes they will see dark bars, which will cause changes in light and dark under different viewing angles, thereby producing moiré. The light bars of the pixel electrode b1a are parallel to the extension direction of the pixel electrode b1a. The position of the pixel electrode b1a constitutes a bright bar, and the gap between adjacent pixel electrodes b1a constitutes a dark bar.

[0315] For the above reasons, reference Fig.64 The extension direction of the lens structure 1041 intersects with the extension direction of the pixel electrode b1a, so that the auxiliary line of the lens structure 1041 can cross the bright strip and the dark strip at the same time as much as possible, so that the brightness felt by the user at different positions is as similar as possible, thereby solving the moiré problem caused by the uneven light emission of the factor pixel 1012.

[0316] For further reference, Fig.65 In order to completely avoid the moiré problem, the first condition that needs to be met is that the length of the portion of the lens structure 1041 located in the opening area 10a in the first direction A1 is equal to the maximum distance between the two ends of the sub-pixel 1012 in the first direction A1. That is, the auxiliary line of the lens structure 1041 passes through the first target point and the second target point of the array substrate 101 at the same time. The first target point and the second target point are two diagonal points among the four corner points of the sub-pixel 1012, and the distance between the two diagonal points is greater than the distance between the other two diagonal points.

[0317] Under the first condition, the first direction A1 is the pixel column direction of the display panel 10, the second direction A2 is the pixel row direction of the display panel 10, and the first condition angle α1 between the extension direction of the pixel electrode b1a and the second direction A2 satisfies:

[0318] tanα1=(db) / (ac) Formula (3)

[0319] The angle β between the extension direction of the lens structure 1041 and the second direction A2 satisfies:

[0320] tanβ=d / (ac) Formula (4)

[0321] Wherein, in the above formula (3) and formula (4), a is the length of the sub-pixel along the second direction A2, b is the length of the sub-pixel along the first direction A1, c is the length of the black matrix structure 10211 along the second direction A2, and d is the length of the portion of the lens structure 1041 located between two adjacent black matrix structures 10211 along the first direction A1. Wherein, the length a of the sub-pixel along the second direction A2 is equal to: the sum of the length of the black matrix structure 10211 along the second direction A2 and the distance between adjacent black matrix structures 10211 in the second direction A2. The length c of the sub-pixel along the first direction A1 is equal to: the sum of the length of the pixel electrode b1a along the first direction A1 and the distance between adjacent pixel electrodes b1a in the first direction A1.

[0322] In the embodiment of the present application, in the above formula (3) and formula (4), a, b and c are all known quantities. By first determining the angle β between the extension direction of the lens structure 1041 and the second direction A2, d is calculated according to formula (4). Afterwards, a, b, c and d can be substituted into formula (3) to calculate the first conditional angle α1. Among them, the angle β can be the angle α selected according to formula (2).

[0323] In the embodiment of the present application, due to the inclined design of the pixel electrode b1a, the overlapping areas of different pixel electrodes b1a and the gate lines 1014 between adjacent black matrix structures 10211 are designed differently (the integrated brightness caused by the gate lines 1014 on the opening area 10a is different), which will produce moiré patterns of alternating light and dark.

[0324] Option 1, reference Fig.66 In order to eliminate the influence of the gate line 1014, if the extension direction of the gate line 1014 (the third direction A3) is the pixel row direction, the second condition that needs to be met is: the length of the portion of the pixel electrode b1a located between adjacent black matrix structures 10211 in the first direction A1 is equal to the distance between the adjacent gate lines 1014 along the first direction A1.

[0325] Under the second condition, a second conditional angle α2 between the extending direction of the pixel electrode b1a and the second direction A2 satisfies:

[0326] tanα2=e / (ac) Formula (5)

[0327] Wherein, in the above formula (5), e is the distance between two adjacent gate lines 1014 along the first direction A1. In addition, in order to simultaneously eliminate the moiré caused by the influence of the lens structure 1041 and the gate line 1014, the above first condition and the second condition can be satisfied at the same time, and then the angle between the extension direction of the pixel electrode b1a and the second direction A2 can be a common multiple of the angle under the first condition and the angle under the second condition.

[0328] Option 2, reference Fig.67 In order to eliminate the influence of the gate line 1014, the extension direction of the gate line 1014 can be appropriately adjusted (that is, the gate line 1014 can be set obliquely relative to the pixel row direction). Optionally, the third condition satisfied after adjusting the extension direction of the gate line 1014 is: the sum of the length of the portion of the pixel electrode b1a located between the adjacent black matrix structures 10211 in the first direction A1 and the length of the portion of the gate line 1014 located between the adjacent black matrix structures 10211 in the first direction A1 is equal to the distance between the adjacent gate lines 1014 along the first direction A1. In addition, the overlapping position of the pixel electrode b1a and the gate line 1014 is located at the junction of the black matrix structure 10211 and the opening area 10a.

[0329] refer to Fig.67 , under the third condition, the third direction A3 and the second direction A2 intersect, and the third condition angle γ1 between the third direction A3 and the second direction A2 satisfies:

[0330] tanγ1=(|e-(ac)tanα1|) / (ac) Formula (6)

[0331] In the above formula (6), e is the distance between two adjacent grid lines 1014 along the first direction A1. In addition, α1 in formula (6) can be determined based on the above first condition. Thus, by determining the third condition angle γ1 through the above formula (6), the influence of the lens structure 1041 and the grid lines 1014 on the moiré pattern can be eliminated at the same time.

[0332] Option 3, reference Fig.68 , if the first condition angle α1 calculated based on the above first condition can make the pixel electrode b1a cross a gate line 1014. In order to eliminate the influence of the gate line 1014, the fourth condition to be satisfied is: the sum of the length of the portion of the pixel electrode b1a located between the adjacent black matrix structures 10211 in the first direction A1 and the length of the portion of the gate line 1014 located between the adjacent black matrix structures 10211 in the first direction A1 is equal to the distance between the first target gate line 1014a and the second target gate line 1014b along the first direction A1. There is also a third target gate line 1014c between the first target gate line 1014a and the second target gate line 1014b, and the third target gate line 1014c is the gate line 1014 crossed by the pixel electrode b1a. The orthographic projection of the pixel electrode b1a on the first substrate 1011 and the orthographic projection of the third target gate line 1014c on the first substrate 1011 partially overlap. Furthermore, the overlapping position of the pixel electrode b1a and the gate line 1014 is located at the boundary between the black matrix structure 10211 and the opening area 10a.

[0333] refer to Fig.68, under the fourth condition, the third direction A3 (the extension direction of the gate line 1014) intersects with the second direction A2, and the fourth condition angle γ2 between the third direction A3 and the second direction A2 satisfies:

[0334] tanγ2=(|2e-(ac)tanα1|) / (ac) Formula (7)

[0335] In the above formula (7), e is the distance between two adjacent grid lines 1014 along the first direction A1. In addition, α1 in formula (7) can be determined based on the above first condition. Thus, the fourth condition angle γ2 is determined by the above formula (7), which can eliminate the influence of the lens structure 1041 and the grid lines 1014 to generate moiré patterns.

[0336] In the embodiment of the present application, a larger number of pixel electrodes b1a can be placed on the first substrate 1011 as much as possible to increase the storage capacitance of the display panel 10. In addition, by designing the transparent electrode layer b4, the length of the channel of the switch transistor can be increased, thereby avoiding the gate line 1014 from being designed too wide, and the aperture ratio of the display panel 10 can be increased. The arrangement of pixels in the display panel 10 provided in the embodiment of the present application can ensure low power consumption.

[0337] Optionally, the materials of the pixel electrode layer b1, the common electrode layer b2, the transparent electrode layer b4 and the electrode transfer layer b14 may all be transparent materials, such as indium tin oxide (ITO).

[0338] In summary, an embodiment of the present application provides a display panel, in which pixels in an array substrate of the display panel include a plurality of sub-pixels of different colors, each data line is connected to a column of sub-pixels arranged along a first direction, and each gate line is connected to at least one sub-pixel arranged along the first direction. In addition, the light-emitting area of ​​the sub-pixel is located on both sides of the gate line, that is, it can cross two opening areas located on both sides of the gate line, so as to facilitate the continuous display of the two opening areas arranged in the first direction. In addition, since the black matrix structure does not cover the target line segment of the gate line, the influence of the black matrix structure on the continuous display in the first direction can be avoided, so as to ensure that the display panel realizes continuous display in the first direction, and the display effect of the display panel is better.

[0339] Fig.69 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. Fig.69 The display device includes: a power supply component 20 and a display panel 10 provided in the above embodiment. The power supply component 20 is used to supply power to the display panel 10.

[0340] Optionally, the display device may be a liquid crystal display (LCD) display device. The display device may be any appropriate display device, including but not limited to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, and an e-book.

[0341] Since the display device can have substantially the same technical effects as the display panel described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.

[0342] The terms used in the embodiments of this application are only used to explain the embodiments of this application, and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should be the common meanings understood by people with general skills in the field to which this application belongs.

[0343] The terms used in the implementation mode of the present application are only used to explain the embodiments of the present application, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the implementation mode of the present application should be the common meanings understood by people with ordinary skills in the field to which the present application belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limit, but indicate that there is at least one. Words such as "include" or "include" and similar words mean that the elements or objects appearing in front of "include" or "include" include the elements or objects listed after "include" or "include" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0344] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, It is characterized in that The display panel (10) comprises: an array substrate (101) and a color film substrate (102) arranged opposite to each other, and a liquid crystal layer (103) located between the array substrate (101) and the color film substrate (102); the array substrate (101) comprises: A first substrate (1011); A plurality of pixels (1012) located on the first substrate (1011), each of the pixels (1012) comprising: a plurality of first sub-pixels (10121) of a first color, a plurality of second sub-pixels (10122) of a second color, and a plurality of third sub-pixels (10123) of a third color, the plurality of sub-pixels of each color being arranged along a first direction (A1), and the plurality of first sub-pixels (10121), the plurality of second sub-pixels (10122), and the plurality of third sub-pixels (10123) being arranged along a second direction (A2), and the second direction (A2) intersects with the first direction (A1); A plurality of data lines (1013) extending along a first direction (A1) and arranged along a second direction (A2), each of the data lines (1013) being connected to a column of sub-pixels arranged along the first direction (A1); and, a plurality of gate lines (1014) extending along a third direction (A3) and arranged along the first direction (A1), each of the gate lines (1014) being connected to at least one sub-pixel arranged along the first direction (A1), and light-emitting areas of at least some of the sub-pixels included in the pixel being located on both sides of the gate line, and the third direction (A3) intersecting with the first direction (A1); The color film substrate (102) comprises: a second substrate and a black matrix layer (1021) located on the second substrate, the black matrix layer (1021) comprising a plurality of black matrix structures (10211) extending along the first direction (A1) and arranged along the second direction (A2), each of the black matrix structures (10211) covering at least one of the data lines (1013), and the black matrix layer (1021) does not overlap with a target line segment of the gate line (1014), and the target line segment is a line segment located between adjacent sub-pixels along the first direction (A1) and does not overlap with the data line (1013).

2. The display panel according to claim 1, It is characterized in that The array substrate (101) further comprises: a pixel electrode layer (b1) located on the first substrate (1011), the pixel electrode layer (b1) comprising a plurality of pixel electrodes (b1a) arranged at intervals; The shape of the positive projection of the pixel electrode (b1a) on the first substrate (1011) is a strip, the extension direction of the pixel electrode (b1a) intersects with the first direction (A1), the second direction (A2) and the third direction (A3), and each sub-pixel (10121), the second sub-pixel (10122) and the third sub-pixel (10123) includes: one pixel electrode (b1a).

3. The display panel according to claim 2, It is characterized in that The orthographic projection of the pixel electrode (b1a) on the first substrate (1011) overlaps with a positive pixel (1012) portion of at least one gate line (1014) on the first substrate (1011).

4. The display panel according to claim 1, It is characterized in that In the second direction (A2), there is a gap between any two adjacent sub-pixels of the colors, and at least two of the plurality of data lines (1013) are located in the same gap, wherein at least one of the data lines (1013) located in the same gap is connected to a sub-pixel of one of the two adjacent sub-pixels of the colors, and at least one of the data lines (1013) located in the same gap is connected to a sub-pixel of another of the two adjacent sub-pixels of the colors; Each of the gate lines (1014) is connected to at least two sub-pixels adjacent to each other along the first direction (A1), and the third direction (A3) intersects with the first direction (A1); Each of the black matrix structures (10211) covers at least two of the data lines (1013) located in the same gap.

5. The display panel according to claim 4, It is characterized in that Two of the plurality of data lines (1013) are located in the same gap; one of the data lines (1013) is connected to a sub-pixel of one color among two adjacent sub-pixels of different colors, and the other data line (1013) is connected to a sub-pixel of the other color among the two adjacent sub-pixels of different colors; or, Three of the multiple data lines (1013) are located in the same gap; one of the data lines (1013) is connected to a sub-pixel of one of two adjacent sub-pixels of different colors, and the other two of the data lines (1013) are connected to a sub-pixel of the other of two adjacent sub-pixels of different colors; or, two of the data lines (1013) located in the same gap are connected to a sub-pixel of one of two adjacent sub-pixels of different colors, and the other data line (1013) is connected to a sub-pixel of the other of two adjacent sub-pixels of different colors.

6. The display panel according to claim 1, It is characterized in that The display panel (10) further comprises a common electrode layer (b2), wherein the common electrode layer (b2) comprises: a plurality of first electrode portions (b21) arranged along the second direction (A2), and a plurality of second electrode portions (b22) arranged along the second direction (A2), wherein the plurality of first electrode portions (b21) and the plurality of second electrode portions (b22) are arranged in a staggered manner; The orthographic projection of the first electrode portion (b21) on the first substrate (1011) is located within the orthographic projection of the black matrix structure (10211) on the first substrate (1011); The second electrode portion (b22) comprises a plurality of common electrode patterns (b221) arranged along the first direction (A1) and spaced apart, one end of each of the common electrode patterns (b221) being connected to one of the two adjacent first electrode portions (b21), and the other end of each of the common electrode patterns (b221) being connected to the other of the two adjacent first electrode portions (b21); The orthographic projection of each common electrode pattern (b221) on the first substrate (1011) is in the shape of a strip, and the extension direction of the common electrode pattern (b221) is parallel to the extension direction of the pixel electrode (b1a) included in the sub-pixel, and the orthographic projection of the common electrode pattern (b221) on the first substrate (1011) and the orthographic projection of the pixel electrode (b1a) on the first substrate (1011) at least partially overlap.

7. The display panel according to claim 1, It is characterized in that Each of the sub-pixels (1012) further comprises: a switch transistor, the switch transistor comprising a source, a drain and a channel located between the source and the drain, the source being connected to the data line (1013), and the drain being connected to a pixel electrode (b1a) included in the sub-pixel; The array substrate (101) comprises: a gate layer (b3) and a transparent electrode layer (b4) in contact with the gate layer (b3), and the gate line (1014) is located on the gate layer (b3); The transparent electrode layer (b4) comprises a plurality of transparent electrode patterns (b41); in a fourth direction (A4), an orthographic projection of the transparent electrode pattern (b41) on the first substrate (1011) covers an orthographic projection of the gate line (1014) on the first substrate (1011); and a length of the orthographic projection of the transparent electrode pattern (b41) on the first substrate (1011) along the fourth direction (A4) is greater than a length of the orthographic projection of the gate line (1014) on the first substrate (1011) along the fourth direction (A4); a length of the orthographic projection of the transparent electrode pattern (b41) on the first substrate (1011) along the fourth direction (A4) is equal to a length of the channel; and the fourth direction (A4) is perpendicular to the third direction (A3).

8. The display panel according to claim 7, It is characterized in that The array substrate (101) comprises: a buffer layer (b5), an active layer (b6), a gate insulating layer (b7), the gate layer (b3), the transparent electrode layer (b4), an interlayer dielectric layer (b8), a source-drain electrode layer (b9), a first passivation layer (b10), a first flat layer (b11), the pixel electrode layer (b1), a second passivation layer (b12), a second flat layer (b13), and the common electrode layer (b2) which are located on the first substrate (1011) and stacked in sequence; The active layer (b6) includes a plurality of active patterns (b61), each of the active patterns (b61) includes a source region (b61a), a drain region (b61b) and a channel region (b61c); The interlayer dielectric layer (b8) and the gate insulating layer (b7) have a first via hole (g1), and the first via hole (g1) is used to expose the source region (b61a); The source-drain electrode layer (b9) comprises the plurality of data lines (1013) and a plurality of source-drain patterns, each of the source-drain patterns is connected to one of the data lines (1013), and each of the source-drain patterns is connected to a source region (b61a) of the active pattern (b61) through the first via hole (g1); The gate insulating layer (b7), the interlayer dielectric layer (b8), the first passivation layer (b10) and the first planar layer (b11) have a second via hole (g2), and the second via hole (g2) is used to expose the drain region (b61b); Each pixel electrode (b1a) in the pixel electrode layer (b1) has a first portion (b1a1) located in the second via hole (g2), and a second portion (b1a2) located on a side of the first flat layer (b11) away from the first substrate (1011), the first portion (b1a1) and the drain region (b61b) of the active pattern (b61) are connected through the second via hole (g2), and a distance between the first portion (b1a1) and the first substrate (1011) is smaller than a distance between the second portion (b1a2) and the first substrate (1011); At least a portion of the second flat layer (b13) is located on a side of the first portion (b1a1) away from the first substrate (1011), and a surface of the common electrode layer (b2) close to the first substrate (1011) is a flat surface.

9. The display panel according to claim 7, It is characterized in that The array substrate (101) comprises: a buffer layer (b5), an active layer (b6), a gate insulating layer (b7), the gate layer (b3), the transparent electrode layer (b4), an interlayer dielectric layer (b8), a source-drain electrode layer (b9), a first passivation layer (b10), an electrode transfer layer (b14), a first flat layer (b11), the pixel electrode layer (b1), a second passivation layer (b12), and the common electrode layer (b2) which are located on the first substrate (1011) and stacked in sequence; The active layer (b6) includes a plurality of active patterns (b61), each of the active patterns (b61) includes a source region (b61a), a drain region (b61b) and a channel region (b61c); The interlayer dielectric layer (b8) and the gate insulating layer (b7) have a first via hole (g1), and the first via hole (g1) is used to expose the source region (b61a); The source-drain electrode layer (b9) comprises the plurality of data lines (1013) and a plurality of source-drain patterns, each of the source-drain patterns is connected to one of the data lines (1013), and each of the source-drain patterns is connected to a source region (b61a) of the active pattern (b61) through the first via hole (g1); The gate insulating layer (b7), the interlayer dielectric layer (b8) and the first passivation layer (b10) have a third via hole (g3), and the third via hole (g3) is used to expose the drain region (b61b); The electrode switching layer (b14) comprises a plurality of electrode switching patterns (141), the electrode switching patterns (141) and a drain region (b61b) of the active pattern (b61) are connected via the third via hole (g3), and an orthographic projection of the electrode switching pattern (141) on the first substrate (1011) at least partially overlaps with an orthographic projection of the data line (1013) on the first substrate (1011); The first flat layer (b11) has a fourth via hole (g4), the fourth via hole (g4) is used to expose the electrode switching pattern (141), and the orthographic projection of the fourth via hole (g4) on the first substrate (1011) and the orthographic projection of the data line (1013) on the first substrate (1011) at least partially overlap; Each pixel electrode (b1a) in the pixel electrode layer (b1) has a third portion (b1a3) located in the fourth via hole (g4), and a fourth portion (b1a4) located on a side of the first flat layer (b11) away from the first substrate (1011), the third portion (b1a3) and the electrode transfer pattern (141) are connected through the fourth via hole (g4), and the distance between the third portion (b1a3) and the first substrate (1011) is smaller than the distance between the fourth portion (b1a4) and the first substrate (1011).

10. The display panel (10) according to claim 9, It is characterized in that The first passivation layer (b10) comprises a first sub-passivation layer (b101) and a second sub-passivation layer (b102); the array substrate (101) further comprises: a shielding layer (b15) located between the first sub-passivation layer (b101) and the second sub-passivation layer (b102), the shielding layer (b15) comprising a plurality of shielding patterns (b151), and the shielding patterns (b151) are located between the data lines (1013) and the electrode switching patterns (141); In the second direction (A2), the orthographic projection of the shielding pattern (b151) on the first substrate (1011) covers the orthographic projection of the at least two data lines (1013) on the first substrate (1011), and the length of the shielding pattern (b151) along the second direction (A2) is less than the length of the black matrix structure (10211) along the second direction (A2).

11. The display panel (10) according to claim 10, It is characterized in that The array substrate (101) further comprises: a spacer layer (b16) located between the first sub-passivation layer (b101) and the shielding layer (b15); The orthographic projection of the spacer layer (b16) on the first substrate (1011) at least covers the orthographic projection of the shielding pattern (b151) on the first substrate (1011).

12. The display panel according to claim 7, It is characterized in that The array substrate (101) comprises: a source-drain electrode layer (b9), a buffer layer (b5), an active layer (b6), a gate insulating layer (b7), the transparent electrode layer (b4), the gate layer (b3), a first passivation layer (b10), a first flat layer (b11), an electrode transfer layer (b14), a second passivation layer (b12), a second flat layer (b13), the pixel electrode layer (b1), a third passivation layer (b17), and the common electrode layer (b2), which are located on the first substrate (1011) and stacked in sequence; The source-drain electrode layer (b9) includes the plurality of data lines (1013) and a plurality of source-drain patterns, each of the source-drain patterns being connected to one of the data lines (1013); The buffer layer (b5) has a fifth via hole (g5), and the fifth via hole (g5) is used to expose a partial area of ​​the source and drain pattern; The active layer (b6) includes a plurality of active patterns (b61), each of the active patterns (b61) includes a source region (b61a), a drain region (b61b) and a channel region (b61c), and the source region (b61a) and the source-drain pattern are connected through the fifth via hole (g5); The first passivation layer (b10) and the first planar layer (b11) have a sixth via hole (g6), and the sixth via hole (g6) is used to expose the drain region (b61b); The electrode switching layer (b14) comprises a plurality of electrode switching patterns (b141), each of the electrode switching patterns (b141) having a fifth portion (b141a) located in the sixth via hole (g6), and a sixth portion (b141b) located on a side of the first flat layer (b11) away from the first substrate (1011), the fifth portion (b141a) and the drain region (b61b) of the active pattern (b61) are connected via the sixth via hole (g6), and a distance between the fifth portion (b141a) and the first substrate (1011) is smaller than a distance between the sixth portion (b141b) and the first substrate (1011); At least a portion of the second flat layer (b13) is located in the sixth via hole (g6), and a surface of the pixel electrode layer (b1) close to the first substrate (1011) is a flat surface; The second passivation layer (b12) and the second planar layer (b13) have a seventh via hole (g7), and the seventh via hole (g7) is used to expose a partial area of ​​the sixth portion (b141b); Each pixel electrode (b1a) in the pixel electrode layer (b1) and one of the sixth portions (b141b) are connected via the seventh via hole (g7).

13. The display panel according to claim 7, It is characterized in that The array substrate (101) comprises: a source-drain electrode layer (b9), a buffer layer (b5), an active layer (b6), a gate insulating layer (b7), the transparent electrode layer (b4), the gate layer (b3), a first passivation layer (b10), an electrode transfer layer (b14), a first flat layer (b11), the pixel electrode layer (b1), a second passivation layer (b12), and the common electrode layer (b2) which are located on the first substrate (1011) and are stacked in sequence; The source-drain electrode layer (b9) includes the plurality of data lines (1013) and a plurality of source-drain patterns, each of the source-drain patterns being connected to one of the data lines (1013); The buffer layer (b5) has a fifth via hole (g5), and the fifth via hole (g5) is used to expose a partial area of ​​the source and drain pattern; The active layer (b6) includes a plurality of active patterns (b61), each of the active patterns (b61) includes a source region (b61a), a drain region (b61b) and a channel region (b61c), and the source region (b61a) and the source-drain pattern are connected through the fifth via hole (g5); The first passivation layer (b10) has an eighth via hole (g8), and the eighth via hole (g8) is used to expose the drain region (b61b); The electrode switching layer (b14) includes a plurality of electrode switching patterns (b141), and each of the electrode switching patterns (b141) and the drain region (b61b) are connected via the eighth via hole (g8); The first flat layer (b11) has a ninth via hole (g9), and the ninth via hole (g9) is used to expose a partial area of ​​the electrode transfer pattern (b141); The pixel electrode (b1a) comprises a seventh portion (b1a7) located in the ninth via hole (g9), and an eighth portion (b1a8) located on a side of the first flat layer (b11) away from the first substrate (1011), the seventh portion (b1a7) and the electrode transfer pattern (b141) are connected via the ninth via hole (g9), and the distance between the seventh portion (b1a7) and the first substrate (1011) is smaller than the distance between the eighth portion (b1a8) and the first substrate (1011); Wherein, the black matrix structure (10211) covers the ninth via hole (g9).

14. The display panel according to any one of claims 2 to 13, It is characterized in that The pixel electrode (b1a) comprises a first pixel portion (b1aa), a second pixel portion (b1ab) and a third pixel portion (b1ac); an orthographic projection of the first pixel portion (b1aa) on the first substrate (1011) is located within an orthographic projection of a first target black matrix structure on the first substrate (1011); an orthographic projection of the second pixel portion (b1ab) on the first substrate (1011) is located between the first target black matrix structure and the second target black matrix structure; an orthographic projection of the third pixel portion (b1ac) on the first substrate (1011) is located within an orthographic projection of the second target black matrix structure on the first substrate (1011); and the first target black matrix structure and the second target black matrix structure are two black matrix structures (10211) adjacent to each other in the second direction (A2); A length of the first pixel portion (b1aa) in the second direction (A2) and a length of the third pixel portion (b1ac) in the second direction (A2) are both greater than or equal to 1 μm.

15. The display panel according to any one of claims 1 to 13, It is characterized in that The display panel (10) further comprises a lens layer (104) located on a side of the color film substrate (102) away from the array substrate (101); the lens layer (104) comprises a plurality of lens structures (1041), and a surface of each lens structure (1041) away from the array substrate (101) is a curved surface; The shape of the orthographic projection of the lens structure (1041) on the array substrate (101) is a strip, and the extension direction of the lens structure (1041) intersects with the first direction (A1), the second direction (A2) and the third direction (A3).

16. The display panel according to claim 15, It is characterized in that An extension direction of the lens structure (1041) intersects with an extension direction of a pixel electrode (b1a) included in the sub-pixel.

17. The display panel according to claim 16, It is characterized in that Under a first condition, the first direction (A1) is the pixel column direction of the display panel (10), the second direction (A2) is the pixel row direction of the display panel (10), and a first conditional angle α1 between the extension direction of the pixel electrode (b1a) and the second direction (A2) satisfies: tanα1=(db) / (ac); The angle β between the extension direction of the lens structure (1041) and the second direction (A2) satisfies: tanβ=d / (ac); Wherein, a is the length of the sub-pixel (1012) along the second direction (A2), b is the length of the sub-pixel (1012) along the first direction (A1), c is the length of the black matrix structure (10211) along the second direction (A2), and d is the length of a portion of the lens structure (1041) located between two adjacent black matrix structures (10211) along the first direction (A1); The first condition is that the length of the portion of the lens structure (1041) located in the opening area (10a) in the first direction (A1) is equal to the maximum distance between the two ends of the sub-pixel (1012) in the first direction (A1).

18. The display panel according to claim 17, It is characterized in that Under the second condition, the third direction (A3) is parallel to the second direction (A2), and a second conditional angle α2 between the extension direction of the pixel electrode (b1a) and the second direction (A2) satisfies: tanα2=e / (ac); Wherein, the e is the distance between two adjacent gate lines (1014) along the first direction (A1); the angle between the extension direction of the pixel electrode (b1a) and the second direction (A2) is a common multiple of the first condition angle and the second condition angle; The second condition is that the length of the portion of the pixel electrode (b1a) located between adjacent black matrix structures (10211) in the first direction (A1) is equal to the distance between adjacent gate lines (1014) along the first direction (A1).

19. The display panel according to claim 17, It is characterized in that Under the third condition, the third direction (A3) and the second direction (A2) intersect, and a third condition angle γ1 between the third direction (A3) and the second direction (A2) satisfies: tanγ1=(e-(ac)tanα1) / (ac); Wherein, the distance e is the distance between two adjacent gate lines (1014) along the first direction (A1); The third condition is that the sum of the length of the portion of the pixel electrode (b1a) located between adjacent black matrix structures (10211) in the first direction (A1) and the length of the portion of the gate line (1014) located between adjacent black matrix structures (10211) in the first direction (A1) is equal to the distance between adjacent gate lines (1014) along the first direction (A1).

20. The display panel according to claim 17, It is characterized in that Under the fourth condition, the third direction (A3) and the second direction (A2) intersect, and a fourth condition angle γ2 between the third direction (A3) and the second direction (A2) satisfies: tanγ2=(2e-(ac)tanα1) / (ac); Wherein, the distance e is the distance between two adjacent gate lines (1014) along the first direction (A1); The fourth condition is: the sum of the length of the portion of the pixel electrode (b1a) located between adjacent black matrix structures (10211) in the first direction (A1) and the length of the portion of the gate line (1014) located between adjacent black matrix structures (10211) in the first direction (A1) is equal to the distance between the first target gate line (1014a) and the second target gate line (1014b) along the first direction (A1), there is also a third target gate line (1014c) between the first target gate line (1014a) and the second target gate line (1014b), and the orthographic projection of the pixel electrode (b1a) on the first substrate (1011) and the orthographic projection of the third target gate line (1014c) on the first substrate (1011) partially overlap.

21. The display panel according to claim 15, It is characterized in that The extension directions of the multiple lens structures (1041) in the display panel (10) are parallel, and the extension directions of the multiple pixel electrodes (b1a) included in the pixel electrode layer (b1) in the display panel (10) are parallel.

22. A display device, It is characterized in that The display device comprises: a power supply component (20) and a display panel (10) according to any one of claims 1 to 21; Wherein, the power supply component (20) is used to supply power to the display panel (10).

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