A display panel, a display device and a manufacturing method of a display panel

Abstract

The application discloses a display panel, a display device and a manufacturing method of the display panel, and aims at solving the scratch clouding problem of the prior art display panel. The display panel comprises an array substrate and a counter substrate arranged oppositely, wherein the array substrate comprises a gate line, a data line, a plurality of pixel electrodes, a plurality of transistors and a plurality of first vias; when the display panel is powered on, it comprises a first dark line, a second dark line connected to one end of the first dark line and extending along the first direction, and a third dark line connected to the other end of the first dark line and extending along the first direction; wherein in the region of the same pixel electrode, the second dark line is located on the side of the third dark line close to the first via; the orthographic projection of the first via on the substrate is at least partially different from the orthographic projection of the second dark line on the substrate, and both are located on different sides of the orthographic projection of the first dark line on the substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel, a display device and a manufacturing method of the display panel. BACKGROUND

[0002] With the development of display technology, flat panel display devices such as liquid crystal display (LCD) are widely used in mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, desktop computers and other consumer electronic products due to their high image quality, power saving, thin body and wide application range, and have become the mainstream of display devices.

[0003] However, the liquid crystal display of the prior art has the problem of trace mura, that is, when a customer slides the liquid crystal display panel with a finger on a white screen, dark stripes appear in the area where the customer slides, affecting the customer's experience. SUMMARY

[0004] The present application provides a display panel, a display device and a manufacturing method of the display panel to solve the problem of trace mura in the display panel of the prior art.

[0005] The present application provides a display panel, comprising: an array substrate and a counter substrate arranged opposite to each other; the array substrate comprises: a substrate, a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction on one side of the substrate, a plurality of pixel electrodes, a plurality of transistors and a plurality of first vias; the transistor comprises: a first electrode and a second electrode; wherein the first electrode is electrically connected to the data line; the second electrode is electrically connected to the pixel electrode through the first via;

[0006] When the display panel is powered on, it includes: a first dark stripe extending in the second direction and passing through the center area of the pixel electrode, a second dark stripe connected to one end of the first dark stripe and extending in the first direction, and a third dark stripe connected to the other end of the first dark stripe and extending in the first direction; wherein in the same area of the pixel electrode, the second dark stripe is located on the side of the third dark stripe close to the first via;

[0007] The first via is at least partially projected on the substrate, and the second dark stripe is projected on the substrate, respectively located on different sides of the first dark stripe in the projection of the substrate.

[0008] In a possible implementation, the display panel when powered on further includes a fourth dark line extending along the first direction and passing through the center region of the pixel electrode, and a fifth dark line connected to one end of the fourth dark line and extending along the second direction; the fifth dark line is located on the same side of the fourth dark line as the second dark line.

[0009] The first via is located in at least part of the substrate orthographic projection, in a region between the first dark line extension line and the fifth dark line extension line in the substrate orthographic projection.

[0010] In a possible implementation, the data line includes a first data line and a second data line adjacent to the pixel electrode and located on different sides of the pixel electrode.

[0011] The pixel electrode, and the first data line and the second data line adjacent to the pixel electrode satisfy: the fifth dark line is located on a side of the first dark line close to the first data line, the pixel electrode is electrically connected to the second data line, and the second dark line is located in a region between the first dark line and the second data line.

[0012] In a possible implementation, the data line includes a first data line and a second data line adjacent to the pixel electrode and located on different sides of the pixel electrode.

[0013] The pixel electrode, and the first data line and the second data line adjacent to the pixel electrode satisfy: the pixel electrode is electrically connected to the first data line, the fifth dark line is located on a side of the first dark line close to the second data line, and the second dark line is located in a region between the first dark line and the first data line.

[0014] In a possible implementation, the array substrate has a first insulating layer between the pixel electrode and the layer where the second electrode is located, and a second insulating layer located on a side of the layer where the second electrode is located facing the substrate; the first via is located in the first insulating layer.

[0015] The first via partially exposes a part of the surface of the second electrode away from the substrate, and partially exposes a part of the surface of the second insulating layer away from the substrate.

[0016] In a possible implementation, in the same region where the pixel electrode is located, the second electrode has a first outer edge away from a side of the fourth dark line.

[0017] The first via covers part of the first outer edge in the substrate orthographic projection.

[0018] In a possible implementation, the pixel electrode comprises: a pixel electrode body, and a pixel electrode extension; wherein the pixel electrode extension is located on a side of the pixel electrode body facing the gate line electrically connected by the transistor;

[0019] The pixel electrode extension comprises: a first extension extending along the first direction, and a second extension connected to one end of the first extension and extending away from the side of the pixel electrode body; the pixel electrode is electrically connected to the second electrode through the second extension and the first via.

[0020] In a possible implementation, the pixel electrode extension and the pixel electrode body have a first gap extending along the first direction.

[0021] In a possible implementation, the display panel further comprises: a first spacer located on a side of the layer where the pixel electrode is located away from the substrate;

[0022] The pixel electrode has a first recess in the region where the first via is located; the first spacer is filled in the first recess.

[0023] In a possible implementation, in a direction perpendicular to the substrate, the height of the first spacer is equal to the depth of the first recess.

[0024] In a possible implementation, the array substrate further comprises: a first alignment film layer located on a side of the pixel electrode facing the counter substrate;

[0025] The counter substrate further comprises: a common electrode layer, and a second alignment film layer located on a side of the common electrode layer facing the array substrate.

[0026] Embodiments of the present application also provide a display device comprising the display panel provided by the embodiments of the present application.

[0027] Embodiments of the present application also provide a manufacturing method of the display panel provided by the embodiments of the present application, the manufacturing method comprising:

[0028] forming an array substrate having a plurality of gate lines, a plurality of data lines, a plurality of pixel electrodes, a plurality of transistors, and a first alignment film layer, and performing alignment on the array substrate by using ultraviolet light;

[0029] forming a counter substrate having a common electrode and a second alignment film layer, and performing alignment on the counter substrate by using ultraviolet light;

[0030] assembling the array substrate and the counter substrate.

[0031] In a possible implementation, the first alignment film layer comprises: a plurality of first alignment units corresponding to the pixel electrodes; and the alignment of the array substrate by the ultraviolet light comprises:

[0032] The first region of the first alignment unit is aligned by a first mask plate in a first light alignment direction, and the second region of the first alignment unit is aligned by a second mask plate in a second light alignment direction, wherein the first region and the second region extend along the second direction and are arranged along the first direction, and in the region of the same pixel electrode, the first region is located between the first dark line and the data line, the first light alignment direction is a direction from the third dark line to the second dark line, and the second light alignment direction is a direction from the second dark line to the third dark line.

[0033] In a possible implementation, the first alignment film layer comprises: a plurality of first alignment units corresponding to the pixel electrodes; and the alignment of the array substrate by the ultraviolet light comprises:

[0034] The third region of the second alignment unit is aligned by a third mask plate in a third light alignment direction, and the fourth region of the second alignment unit is aligned by a fourth mask plate in a fourth light alignment direction, wherein the third region and the fourth region extend along the first direction and are arranged along the second direction, and in the region of the same pixel electrode, the third region is located on a side of the fourth dark line away from the gate line to which the pixel electrode is electrically connected, the third light alignment direction is a direction from the first dark line to the side of the data line to which the pixel electrode is electrically connected, and the fourth light alignment direction is opposite to the third light alignment direction.

[0035] The first via hole in the substrate orthographic projection and the second dark line in the substrate orthographic projection are respectively located on different sides of the first dark line extension line in the substrate orthographic projection, that is, the transverse second dark line and the first via hole are staggered at the position of the first via hole, the second dark line and the first via hole are far away from each other, on the one hand, the liquid crystal at the position of the first via hole can smoothly transition with the liquid crystal in the pixel area, the difference in azimuth angle of the liquid crystal in the two regions is reduced, the stability of the liquid crystal alignment is improved, and the liquid crystal disorder is reduced; on the other hand, the second dark line and the first via hole are far away from each other, when the liquid crystal at the position of the first via hole is disordered after being pressed, the distance from the position of the first via hole to the pixel area is farther, the shape of the dark line in the pixel area is less affected and is not easy to be disordered, and thus the Trace Mura is improved. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1Schematic diagrams showing dark patterns affected by liquid crystal at vias and those not affected by liquid crystal at vias;

[0037] Figure 2 This is one of the schematic diagrams of a display panel structure provided in an embodiment of the present invention;

[0038] Figure 3 for Figure 2 A schematic diagram of the cross-section along the dashed line e1;

[0039] Figure 4 This is a second schematic diagram of the display panel structure provided in an embodiment of the present invention;

[0040] Figure 5 This is the third schematic diagram of the display panel structure provided in the embodiment of the present invention;

[0041] Figure 6 This is the fourth schematic diagram of the display panel structure provided in the embodiment of the present invention;

[0042] Figure 7 This is one of the schematic diagrams of the first via provided in an embodiment of the present invention;

[0043] Figure 8A This is one of the schematic diagrams of UV2A light alignment in related technologies;

[0044] Figure 8B This is the second schematic diagram of UV2A light alignment in related technologies;

[0045] Figure 9A This is a diagram showing the correspondence between the UV2A mask and the display substrate in related technologies;

[0046] Figure 9B This is a design for the splicing of mass-produced UV2A photomasks in related technologies;

[0047] Figure 10 This is a schematic diagram of the alignment direction and dark pattern of mass-produced UV2A in related technologies;

[0048] Figure 11 This is a schematic diagram of the UV2A alignment direction and dark pattern provided in an embodiment of the present invention;

[0049] Figure 12 This is a schematic diagram of the display panel manufacturing process provided in an embodiment of the present invention. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0051] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0052] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0053] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0054] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0055] Most liquid crystal display devices on the market are backlit liquid crystal displays, which consist of a liquid crystal display panel and a backlight module. Typically, a liquid crystal display panel comprises a color filter (CF) substrate, a thin film transistor (TFT) substrate, liquid crystal (LC) sandwiched between the CF and TFT substrates, and a sealant. However, this type of liquid crystal display panel often suffers from misalignment between the CF and TFT substrates, leading to pixel light leakage or low aperture ratio. To solve this problem, a technique called Color Filter on Array (COA) was developed. Because COA liquid crystal display panels do not have the alignment problem between the CF and TFT substrates, the difficulty of the cell alignment process during display panel manufacturing is reduced, avoiding errors during cell alignment. Therefore, the black matrix can be designed with a narrow linewidth, improving the aperture ratio, and it is widely used in high-end monitor (MNT) products.

[0056] In related technologies, the liquid crystal at the pixel via location is distorted by the electric field direction, resulting in an azimuth angle different from that of the liquid crystal in the pixel area. When the azimuth angle of the liquid crystal at the pixel via is opposite to that of the pixel area, it can easily affect the normal orientation of the liquid crystal in the pixel area. When pressed, the electric field in the disordered area of ​​the liquid crystal becomes stronger, and the range of the disordered area increases, affecting the normal alignment of the liquid crystal in the pixel area and causing disordered dark lines, such as... Figure 1 As shown on the left side, where, Figure 1 The attached diagram on the right shows a schematic diagram when the liquid crystal at the via is not affected.

[0057] See Figure 2 and Figure 3 As shown, where, Figure 3 It can be Figure 2 A cross-sectional view along the dashed line e shows that an embodiment of the present invention provides a display panel, including: an array substrate and a counter substrate disposed opposite to each other; the array substrate includes: a substrate 1, and a plurality of gate lines 2 extending along a first direction X, a plurality of data lines 3 extending along a second direction Y, a plurality of pixel electrodes 4, a plurality of transistors T, and a plurality of first vias K1; the transistors T include: a first electrode TA and a second electrode TB; wherein, the first electrode TA is electrically connected to the data lines 3; the second electrode TB is electrically connected to the pixel electrodes 4 through the first vias K1;

[0058] When the display panel is powered on, it includes: a first dark ridge 51 extending along the second direction Y and passing through the central region of the pixel electrode 4; a second dark ridge 52 connected to one end of the first dark ridge 51 and extending along the first direction X; and a third dark ridge 53 connected to the other end of the first dark ridge 51 and extending along the first direction X; wherein, in the same region where the pixel electrode 4 is located, the second dark ridge 52 is located on the side of the third dark ridge 53 closer to the first via K1.

[0059] At least a portion of the first via K1 projected onto the substrate 1 and the second dark ripple 52 projected onto the substrate 1 are located on different sides of the extension line e2 of the first dark ripple 51 projected onto the substrate 1, respectively.

[0060] In this embodiment of the invention, at least a portion of the first via K1 projected onto the substrate 1 and the second dark ripple 52 projected onto the substrate 1 are located on different sides of the extension line of the first dark ripple 51 projected onto the substrate 1. That is, at the periphery of the first via K1, the second dark ripple 52 is staggered from the first via K1, making the positions of the second dark ripple 52 and the first via K1 relatively far apart. On the one hand, this allows for a smooth transition between the liquid crystal at the position of the first via K1 and the liquid crystal in the pixel area, reducing the difference in the azimuth angle of the liquid crystal in the two areas, improving the stability of liquid crystal orientation, and thus reducing liquid crystal disturbance. On the other hand, the relatively far position of the second dark ripple 52 from the first via K1 means that when the liquid crystal at the first via K1 is disturbed under pressure, the distance from the position of the first via K1 to the pixel area is greater, reducing the impact on the morphology of the dark ripple in the pixel area and making it less prone to disturbance, thereby improving trace mura.

[0061] In one possible implementation, see Figure 2 As shown, when the display panel is powered on, it further includes: a fourth dark stencil 54 extending along the first direction X and passing through the central region of the pixel electrode, and a fifth dark stencil 55 connected to one end of the fourth dark stencil 54 and extending along the second direction Y; the fifth dark stencil 55 and the second dark stencil 52 are located on the same side of the fourth dark stencil 54; at least a portion of the first via K1 projected onto the substrate 1 is located in the region between the extension line e2 of the first dark stencil 51 and the extension line e3 of the fifth dark stencil 55 projected onto the substrate 1.

[0062] In one possible implementation, see Figure 2As shown, the data line 3 includes a first data line 31 and a second data line 32 adjacent to the pixel electrode 4 and located on different sides of the pixel electrode 4; the pixel electrode 4, and the first data line 31 and the second data line 32 adjacent to the pixel electrode 4 satisfy the following: the fifth dark ripple 55 is located on the side of the first dark ripple 51 close to the first data line 31, the pixel electrode 4 is electrically connected to the second data line 32, and the second dark ripple 52 is located in the area between the first dark ripple 51 and the second data line 32. That is, in this embodiment of the invention, the second dark ripple 52 is located close to the data line 3 (i.e., the second data line 32) electrically connected (through transistor T) to the pixel electrode 4 where the second dark ripple 52 is located, thereby making the second dark ripple 52 laterally staggered from the first via K1, making the position of the second dark ripple 52 far from the first via K1, so that the liquid crystal at the position of the first via K1 and the liquid crystal in the pixel area transition smoothly, reducing liquid crystal disorder, and reducing the impact on the morphology of the dark ripples in the pixel area, making them less prone to disorder, thereby improving trace mura.

[0063] It should be noted that for a pixel electrode 4, among the first data line 31 and the second data line 32 adjacent to it, the second data line 32 is electrically connected to the pixel electrode 4; however, for another pixel electrode 4 adjacent to the pixel electrode 4, the second data line 32 can also serve as the first data line 31 of the other pixel electrode 4. That is, for any data line 3, it is both the first data line 31 and the second data line 32. However, for a specific pixel electrode 4, the data line 3 electrically connected to the pixel electrode 4 is fixed, that is, for the pixel electrode 4, the second data line 32 is fixed.

[0064] In one possible implementation, see Figure 4 As shown, the data line 3 includes a first data line 31 and a second data line 32 that are adjacent to the pixel electrode 4 and located on different sides of the pixel electrode 4; the pixel electrode 4, and the first data line 31 and the second data line 32 adjacent to the pixel electrode 4 satisfy the following: the pixel electrode 4 is electrically connected to the first data line 31, the fifth dark ripple 55 is located on the side of the first dark ripple 51 close to the second data line 32, and the second dark ripple 52 is located in the area between the first dark ripple 51 and the first data line 31. In this embodiment, the mask can be adjusted during the light alignment process of the display panel to rotate the swastika pattern into a swastika pattern. Alternatively, the second dark pattern 52 can be positioned close to the data line 3 (i.e., the first data line 31) that is electrically connected (via transistor T) to the pixel electrode 4 where the second dark pattern 52 is located. This allows the second dark pattern 52 to be staggered from the first via K1, making the positions of the second dark pattern 52 and the first via K1 more distant. This results in a smooth transition between the liquid crystal at the position of the first via K1 and the liquid crystal in the pixel area, reducing liquid crystal disturbance and minimizing the impact on the shape of the dark pattern in the pixel area, thus improving trace mura.

[0065] The UV2A photo-alignment technology is a pixel-level scanning exposure technology. Through the light-shielding areas and light-transmitting areas configured on the mask plate, the photo-alignment of the alignment films on the array substrate and the color filter substrate is carried out in the opposite polarization directions in the corresponding pixel areas, and after pairing, a four-domain or multi-domain display effect is achieved. Specifically, as shown in Figure 8A- Figure 8B The mask plate is mounted on two platforms (Stages). One sub-pixel unit corresponds to the light-shielding areas and light-transmitting areas on different platforms (Stages). The sizes of the light-shielding area 101 and the light-transmitting area 102 configured on the mask plate are both approximately 1 / 2 of the sub-pixel size. An adjacent light-shielding area + light-transmitting area corresponds to one sub-pixel unit; the photo-alignment polarization direction is horizontal to the pixel scanning (Scan) direction, and the photo-alignment polarization directions of the two platforms are opposite; the photo-alignment methods of the array substrate TFF and the color filter substrate CF are the same, but the sub-pixel photo-alignment directions are different. After pairing and bonding, the liquid crystal orientations on the array substrate TFF and the color filter substrate CF sides between different domains are all different, and the liquid crystal rotates orderly in the cell, forming a unique UV2A display mode; the theoretical integrated light quantity of the array substrate TFF and the color filter substrate CF is the same, and the azimuth angles of the liquid crystal in different domains are all 45° with respect to the polarizing axis of the TFT / CF. At this time, the transmittance of the product is the highest.

[0066] Specifically, in the related art of the UV2A photo-alignment technology, due to the limited size of the mask plate, multiple mask plates are required to expose the display substrate in a splicing manner. The mask plate splicing method and the corresponding method of the display substrate are as shown in Figure 9A and Figure 9B Among them, the mask plates of the first platform Stage1 and the second platform Stage2 are arranged in an interleaved splicing manner; in the first platform Stage1 and the second platform Stage2, the photo-alignment directions of column A are the same, the photo-alignment directions of column B are the same, and the photo-alignment direction of column B is horizontally opposite to that of column A. The four-domain exposure of the pixels is completed through the Scan method. The mass production UV2A alignment method in the related art is as shown in Figure 10 The array substrate TFT is left A / right B, and the color filter substrate CF is upper B / lower A. After bonding, the alignment dark line is in the shape of a "卍". At the pixel via, it interferes with the horizontal dark line in the lower right corner. At the pixel via part, due to the existence of complex electric fields such as the hole taper and metal cushion layer, the alignment dark line is distorted under the action of the electric field; when swiping forcefully, the liquid crystal in the display area is affected by the complex electric field around the pixel via and cannot return to the original regular arrangement state in time, and the light flux through the pixel decreases, thus showing TraceMura.

[0067] In the embodiments of the present invention, the A / B column exposure positions of the array substrate TFT and the color filter substrate CF can be exchanged, as shown in Figure 11As shown, the array substrate TFT is B on the left and A on the right, and the color filter substrate CF is A on the top and B on the bottom. After bonding, the dark lines are in the shape of a swastika. There are no lateral alignment dark lines between the pixel via (i.e., the first via K1) and the display area. The random electric field around the pixel via (i.e., the first via K1) has no effect on the dark lines at the vertical edge. When swiping, it will not affect the liquid crystal arrangement in the display area, thereby improving the trace mura.

[0068] In one possible implementation, see Figure 3 As shown, the array substrate has a first insulating layer 91 between the pixel electrode 4 and the layer containing the second electrode TB, and a second insulating layer 92 located on the side of the layer containing the second electrode TB facing the substrate 1; a first via K1 is located in the first insulating layer 91; the first via K1 partially exposes a portion of the surface of the second electrode TB facing away from the substrate 1, and partially exposes a portion of the surface of the second insulating layer 92 facing away from the substrate 1. In this embodiment of the invention, the first via K1 partially exposes a portion of the surface of the second electrode TB facing away from the substrate 1, and partially exposes a portion of the surface of the second insulating layer 92 facing away from the substrate 1, that is, the first via K1 is set as a half-overlapping hole structure, which can also increase the distance between the second dark pattern 52 and the first via K1, so that the liquid crystal at the position of the first via K1 and the liquid crystal in the pixel area transition smoothly, reducing liquid crystal disturbance, and reducing the impact on the morphology of the dark pattern in the pixel area, making it less prone to disturbance, thereby improving trace mura.

[0069] In one possible implementation, combined with Figure 2 As shown, in the same region where pixel electrode 4 is located, the second electrode TB has a first outer edge w1 on the side away from the fourth dark sm 54; the orthographic projection of the first via K1 onto substrate 1 covers the portion of the first outer edge w1 projected onto substrate 1. That is, by moving the first via K1 upwards, it can be partially moved to the region above the second electrode TB, so that the distance between the first via K1 and the second dark sm 52 is larger.

[0070] In one possible implementation, see Figure 5As shown, the pixel electrode 4 includes: a pixel electrode body 41 and a pixel electrode epitaxial portion 42; wherein, the pixel electrode epitaxial portion 42 is located on the side of the pixel electrode body 41 facing the gate line 2 electrically connected through the transistor T; the pixel electrode epitaxial portion 42 includes: a first epitaxial portion 421 extending along the first direction X, and a second epitaxial portion 422 connected to one end of the first epitaxial portion 421 and extending away from the pixel electrode body 41; the pixel electrode 4 is electrically connected to the second electrode TB through the second epitaxial portion 422 via the first via K1. In this embodiment of the invention, the pixel electrode 4 further includes a first epitaxial portion 421 and a second epitaxial portion 422. The pixel electrode 4 is electrically connected to the second electrode TB through the second epitaxial portion 422 via the first via K1. That is, the pixel electrode 4 overlaps with the first via K1 in a finger-connected manner, isolating the influence of the first via K1 on the alignment dark lines (dark patterns), thereby achieving a smooth transition between the liquid crystal at the position of the first via K1 and the liquid crystal in the pixel area, reducing liquid crystal disorder, and reducing the impact on the morphology of the dark patterns in the pixel area, making them less prone to disorder, thereby improving Trace Mura.

[0071] In one possible implementation, see Figure 5 As shown, a first gap F extending along the first direction X is provided between the pixel electrode epitaxial portion 42 and the pixel electrode body 41. This isolates the influence of the first via K1 on alignment dark lines (dark patterns), enabling a smooth transition between the liquid crystal at the location of the first via K1 and the liquid crystal in the pixel area, reducing liquid crystal disturbance, and minimizing the impact on the morphology of dark patterns in the pixel area, thus improving trace mura.

[0072] In one possible implementation, see Figure 6 and Figure 7 As shown, the display panel further includes: a first spacer PS1 located on the side of the layer where the pixel electrode 4 is located away from the substrate 1; the pixel electrode 4 has a first recess Q in the area where the first via K1 is located; the first spacer PS1 fills the first recess Q. In this embodiment of the invention, the display panel further includes: a first spacer PS1 located in the first recess Q of the pixel electrode 4, that is, the first spacer PS1 is used to fill the recess at the position of the first via K1. After filling, the influence of the first via K1 on the liquid crystal molecule arrangement can be effectively controlled, the interference of the first via K1 on the liquid crystal arrangement of the display area can be weakened, and the trace mura can be improved.

[0073] In one possible implementation, the material of the first spacer PS1 can be the same as the material of the main spacer or the secondary spacer in the display panel, and the first spacer PS1 can be formed at the same time as the main spacer or the secondary spacer is formed.

[0074] In one possible implementation, see Figure 6 and Figure 7As shown, in the direction perpendicular to the substrate 1, the height h1 of the first spacer PS1 is equal to the depth h2 of the first recess Q.

[0075] In one possible implementation, combined with Figure 2 or Figure 3 As shown, transistor T also includes an active pattern 6; the first insulating layer 91 may include a first sub-insulating layer 911 and a second sub-insulating layer 912 located between the first sub-insulating layer 911 and the layer containing the second electrode TB; wherein, the first sub-insulating layer 911 may be an organic insulating layer; the second sub-insulating layer 912 may be a passivation layer; a color resist layer 7 may also be present between the first sub-insulating layer 911 and the second sub-insulating layer 912; the second insulating layer 92 may specifically be a gate insulating layer; optionally, the layer containing the gate line 2 may also include multiple first traces 20, the first traces 20 may be common traces, and a storage capacitor may be formed with the second electrode (such as the drain) of the transistor in the layer containing the data line, and each first trace 20 may be connected to... They can be independent of each other or interconnected; the layer where the pixel electrode 4 is located can also include multiple second traces 40, which can include a first sub-trace 401 extending along the first direction X and a second sub-trace 402 extending along the second direction Y; wherein, the orthographic projection of the second sub-trace 402 on the substrate can overlap with the orthographic projection of the data line 3 on the substrate, and can be used to shield the coupling capacitance between the data line 3 and the pixel electrode 4; the first sub-trace 401 can be used to electrically connect the second sub-trace 402 to each other to form an interconnected structure; the first sub-trace 401 and the second sub-trace 402 can be loaded with a common voltage, and the materials of the two can be the same as the material of the pixel electrode 4, for example, both are indium tin oxide.

[0076] In one possible implementation, the array substrate further includes a first alignment film layer located on the side of the pixel electrode 4 facing the opposing substrate; the opposing substrate further includes a common electrode layer and a second alignment film layer located on the side of the common electrode layer facing the array substrate.

[0077] Based on the same inventive concept, embodiments of the present invention also provide a display device, including a display panel as provided in the embodiments of the present invention. Implementation of this display device can refer to the embodiments of the display panel described above, and repeated details will not be repeated.

[0078] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0079] Based on the same inventive concept, embodiments of the present invention also provide a method for manufacturing a display panel as provided in embodiments of the present invention, see [link to relevant documentation]. Figure 12 As shown, the manufacturing method includes:

[0080] Step S100: Form an array substrate having multiple gate lines, multiple data lines, multiple pixel electrodes, multiple transistors, and a first alignment film layer, and align the array substrate using ultraviolet light;

[0081] Step S200: Form a counter substrate having a common electrode and a second alignment film layer, and align the counter substrate using ultraviolet light;

[0082] Step S300: Align the array substrate with the opposing substrate.

[0083] In one possible implementation, the first alignment film layer includes: a plurality of first alignment units corresponding to pixel electrodes; combined with Figure 11 As shown, in step S100, aligning the array substrate with ultraviolet light includes:

[0084] A first mask (Mask1) is used to align the first region S1 of the first alignment unit PP1 in a first photoalignment direction (V1), and a second mask (Mask2) is used to align the second region S2 of the first alignment unit PP1 in a second photoalignment direction (V2). The first region S1 and the second region S2 extend along the second direction (Y) and are arranged along the first direction (X). Within the same region containing the pixel electrode, the first region S1 is located on the side of the first dark ripple 51 facing the data line 3 electrically connected to the pixel electrode. The first photoalignment direction (V1) points from the third dark ripple 53 to the second dark ripple 52, and the second photoalignment direction (V2) points from the second dark ripple 52 to the third dark ripple 53. The light-transmitting area of ​​the first mask (Mask1) corresponds to the first region S1, and the light-transmitting area of ​​the second mask (Mask2) corresponds to the second region S2. That is, the first mask (Mask1) transmits light in the first region S1 and blocks light in the second region S2; the second mask (Mask2) transmits light in the second region S2 and blocks light in the first region S1.

[0085] In one possible implementation, the second alignment film layer includes: a plurality of first alignment units PP2 corresponding to the pixel electrodes, combined with Figure 11 As shown, in step S200, the alignment of the opposing substrates using ultraviolet light includes:

[0086] The third region S3 of the second alignment unit PP2 is aligned in the third photoalignment direction V3 using a third mask 3, and the fourth region S4 of the second alignment unit PP2 is aligned in the fourth photoalignment direction V4 using a fourth mask 4. The third region S3 and the fourth region S4 extend along the first direction X and are arranged along the second direction Y. In the same region where the pixel electrode is located, the third region S3 is located on the side of the fourth dark fringe 54 away from the gate line 2 electrically connected to the pixel electrode. The third photoalignment direction V3 is the direction from the first dark fringe 51 to the side of the data line 3 electrically connected to the pixel electrode. The fourth photoalignment direction V4 is opposite to the third photoalignment direction V3. The light-transmitting area of ​​the third mask (Mask3) corresponds to the third region S3, and the light-transmitting area of ​​the fourth mask (Mask4) corresponds to the fourth region S4. That is, the third mask (Mask3) transmits light in the third region S3 and blocks light in the fourth region S4; the fourth mask (Mask4) transmits light in the fourth region S4 and blocks light in the third region S3.

[0087] In one possible implementation, the first, second, third, and fourth masks can be independent masks. In another possible implementation, the first, second, third, and fourth masks can be the same mask, except that the areas that do not need to be aligned are blocked. Therefore, by adjusting the blocking of the areas that do not need to be aligned, the alignment of different positions or regions of the array substrate and the color filter substrate can be achieved.

[0088] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0089] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A display panel, characterized by, The display panel comprises: oppositely arranged array substrate and counter substrate; the array substrate comprises: a substrate, and a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction on one side of the substrate, a plurality of pixel electrodes, a plurality of transistors, and a plurality of first vias; the transistor comprises: a first electrode and a second electrode; wherein the first electrode is electrically connected with the data line; the second electrode is electrically connected with the pixel electrode through the first via; wherein the display panel when powered on comprises: a first dark line extending along the second direction and passing through the center region of the pixel electrode, a second dark line connected to one end of the first dark line and extending along the first direction, and a third dark line connected to the other end of the first dark line and extending along the first direction; wherein in the same region of the pixel electrode, the second dark line is located on the side of the third dark line close to the first via; the first via is located on the opposite side of the second dark line in the orthogonal projection of the substrate, and the first via and the second dark line are staggered in the first direction; the array substrate has a first insulating layer between the pixel electrode and the second electrode, and a second insulating layer on the side of the second electrode facing the substrate; the first via is located in the first insulating layer; the first via partially exposes the surface of the second electrode on the side away from the substrate, and partially exposes the surface of the second insulating layer on the side away from the substrate.

2. The display panel of claim 1, wherein, The display panel when powered on further comprises: a fourth dark line extending along the first direction and passing through the center region of the pixel electrode, and a fifth dark line connected to one end of the fourth dark line and extending along the second direction; the fifth dark line and the second dark line are located on the same side of the fourth dark line; the first via is located in the region between the first dark line and the fifth dark line in the orthogonal projection of the substrate.

3. The display panel of claim 2, wherein, The data line comprises: a first data line and a second data line adjacent to the pixel electrode and located on different sides of the pixel electrode; the pixel electrode and the first data line and the second data line adjacent to the pixel electrode satisfy: the fifth dark line is located on the side of the first dark line close to the first data line, the pixel electrode is electrically connected to the second data line, and the second dark line is located in the region between the first dark line and the second data line.

4. The display panel of claim 2, wherein, The data line comprises: a first data line and a second data line adjacent to the pixel electrode and located on different sides of the pixel electrode; the pixel electrode and the first data line and the second data line adjacent to the pixel electrode satisfy: the pixel electrode is electrically connected to the first data line, the fifth dark line is located on the side of the first dark line close to the second data line, and the second dark line is located in the region between the first dark line and the first data line.

5. The display panel of claim 1, wherein, The second electrode has a first outer edge away from a fourth dark line on a region where the pixel electrode is located; the fourth dark line is a dark line extending along the first direction and passing through a central region of the pixel electrode when the display panel is powered on. The first via hole covers a part of the first outer edge in the orthographic projection of the substrate.

6. The display panel of claim 1, wherein, The pixel electrode comprises a pixel electrode main body and a pixel electrode extension; the pixel electrode extension is located on a side of the pixel electrode main body facing the gate line electrically connected by the transistor; The pixel electrode extension comprises a first extension extending along the first direction and a second extension connected to one end of the first extension and extending away from the pixel electrode main body; the pixel electrode is electrically connected to the second electrode through the second extension and the first via hole.

7. The display panel of claim 6, wherein, The pixel electrode extension and the pixel electrode main body have a first gap extending along the first direction.

8. The display panel of claim 1, wherein, The display panel further comprises a first spacer on a side of the layer where the pixel electrode is located away from the substrate; The pixel electrode has a first recess in a region where the first via hole is located; the first spacer is filled in the first recess.

9. The display panel of claim 8, wherein, In a direction perpendicular to the substrate, the height of the first spacer is equal to the depth of the first recess.

10. The display panel of claim 1, wherein, The array substrate further comprises a first alignment film layer on a side of the pixel electrode facing the counter substrate; The counter substrate further comprises a common electrode layer and a second alignment film layer on a side of the common electrode layer facing the array substrate.

11. A display device, characterized by comprising: The display panel comprises any one of claims 1-10.

12. A method of manufacturing a display panel as claimed in any one of the claims 1-10, characterized in that The manufacturing method comprises: forming an array substrate with a plurality of gate lines, a plurality of data lines, a plurality of pixel electrodes, a plurality of transistors, and a first alignment film layer, and aligning the array substrate by using ultraviolet light; forming a counter substrate with a common electrode layer and a second alignment film layer, and aligning the counter substrate by using ultraviolet light; assembling the array substrate and the counter substrate.

13. The manufacturing method as described in claim 12, characterized in that, The first alignment film layer comprises a plurality of first alignment units corresponding to the pixel electrodes; the step of aligning the array substrate by using ultraviolet light comprises: aligning a first region of the first alignment unit in a first light alignment direction by using a first mask plate and aligning a second region of the first alignment unit in a second light alignment direction by using a second mask plate, wherein the first region and the second region extend along the second direction and are arranged along the first direction, and in a region where the same pixel electrode is located, the first region is located between the first dark line and the data line, the first light alignment direction is a direction from the third dark line to the second dark line, and the second light alignment direction is a direction from the second dark line to the third dark line.

14. The manufacturing method as described in claim 13, characterized in that, The first alignment film layer comprises a plurality of second alignment units corresponding to the pixel electrodes; the step of aligning the counter substrate by using ultraviolet light comprises: The third mask plate is used to align the third area of the second alignment unit in a third light alignment direction, and the fourth mask plate is used to align the fourth area of the second alignment unit in a fourth light alignment direction, wherein the third area and the fourth area extend along the first direction and are arranged along the second direction, and in the area of the same pixel electrode, the third area is located on the side of the fourth dark line away from the gate line to which the pixel electrode is electrically connected, the third light alignment direction is a direction from the first dark line to the side of the data line to which the pixel electrode is electrically connected, the fourth light alignment direction is opposite to the third light alignment direction, and the fourth dark line is a dark line extending along the first direction and passing through the central area of the pixel electrode when the display panel is powered on.

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