Voltage regulating module, electronic device and voltage adjusting method

Abstract

The application discloses a voltage regulating module, an electronic device and a voltage regulating method. The voltage regulating module comprises a target module, a PMIC module and a voltage detection module. The voltage detection module is located between the target module and the PMIC module. The PMIC module comprises a voltage output port and a GPIO port. The voltage output port of the PMIC module is connected with the target module through a power supply wire. The voltage detection module has a first input end, a second input end and an output end. The first input end of the voltage detection module and the second input end of the voltage detection module are both connected with the target module through a power supply wire. The output end of the voltage detection module is connected with the GPIO port of the PMIC module.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of electronics, and particularly relates to a voltage regulation module, an electronic device, and a voltage adjustment method. BACKGROUND

[0002] At present, in order to save power consumption, an AVS (Adaptive Voltage Scaling, self-adaptive voltage regulation) voltage regulation system is used in electronic devices such as mobile phones and tablets, and it is very common to adjust the output voltage of a PMIC (Power Management Integrated Circuit, power management integrated circuit) module according to the load.

[0003] In the process of voltage regulation by using the AVS voltage regulation system, a voltage detection loop is used, and the voltage detection loop often causes voltage regulation delay due to a large number of components (such as AVS sensors and AVS controllers) contained therein, which causes the AVS voltage regulation system to have a slow response speed in the voltage regulation process. SUMMARY

[0004] The present application provides a voltage regulation module, an electronic device, and a voltage adjustment method, and at least solves the problem of slow response speed of the AVS voltage regulation system in the voltage regulation process in the related art.

[0005] In a first aspect, the present application provides a voltage regulation module, comprising: a target module, a PMIC module, and a voltage detection module; the voltage detection module is located between the target module and the PMIC module.

[0006] The PMIC module comprises a voltage output port and a GPIO port; the voltage output port of the PMIC module is connected to the target module through a power supply line; the voltage detection module has a first input end, a second input end, and an output end, the first input end of the voltage detection module and the second input end of the voltage detection module are both connected to the target module through the power supply line, and the output end of the voltage detection module is connected to the GPIO port of the PMIC module.

[0007] In a second aspect, the present application provides an electronic device comprising the voltage regulation module of the first aspect.

[0008] In a third aspect, the present application provides a voltage adjustment method applied to the voltage regulation module of the first aspect, comprising:

[0009] When the voltage detection module detects that the output voltage of the PMIC module drops below a preset value, a target signal is output to the PMIC module.

[0010] The PMIC module increases an output voltage of a voltage output port of the PMIC module based on the target signal.

[0011] In the embodiment of the present application, the voltage regulating module includes a target module, a PMIC module and a voltage detection module; the voltage detection module is located between the target module and the PMIC module; the PMIC module includes a voltage output port and a GPIO port; the voltage output port of the PMIC module is connected with the target module through a power supply wire; the voltage detection module has a first input end, a second input end and an output end, the first input end of the voltage detection module and the second input end of the voltage detection module are both connected with the target module through the power supply wire, and the output end of the voltage detection module is connected with the GPIO port of the PMIC module. In this way, the voltage detection module is arranged between the target module and the PMIC module in the present application, and the voltage on the power supply wire between the target module and the PMIC module is detected through the voltage detection module. Since the power supply voltage of the target module can be quickly detected through the voltage detection module, the PMIC module can directly obtain the power supply voltage detected by the voltage detection module, thereby avoiding the delay caused by the detection loop of the AVS voltage regulating system in the related art, and further improving the response speed of the voltage regulating module. BRIEF DESCRIPTION OF DRAWINGS

[0012] The above and / or additional aspects and advantages of the present application will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings in which:

[0013] Figure 1 a schematic diagram of a voltage regulating module provided in the related art;

[0014] Figure 2 a schematic diagram of a voltage regulating module provided in the embodiment of the present application;

[0015] Figure 3 a schematic diagram of another voltage regulating module provided in the embodiment of the present application;

[0016] Figure 4 a schematic diagram of another voltage regulating module provided in the embodiment of the present application;

[0017] Figure 5 a schematic diagram of another voltage regulating module provided in the embodiment of the present application;

[0018] Figure 6 a schematic diagram of another voltage regulating module provided in the embodiment of the present application;

[0019] Figure 7-1 a schematic diagram of another voltage regulating module provided in the embodiment of the present application;

[0020] Figure 7-2 a schematic diagram of another voltage regulating module provided in the embodiment of the present application;Figure 7-1 The simulation circuit diagram corresponding to the voltage regulation module shown;

[0021] Figure 7-3 The input waveform diagram of the two input terminals P and N of the operational amplifier in the simulation circuit shown; Figure 7-2

[0022] Figure 7-4 The output waveform diagram of the first GPIO port GPIO1-1 and the second GPIO port GPIO1-2 in the simulation circuit shown; Figure 7-2

[0023] Figure 7-5 The output waveform diagram of the first GPIO port GPIO1-1 and the second GPIO port GPIO1-2 in the simulation circuit shown; Figure 7-2

[0024] Figure 8 The schematic diagram of another voltage regulation module provided by the embodiment of the present application;

[0025] Figure 9 The schematic diagram of an electronic device provided by the embodiment of the present application;

[0026] Figure 10 The schematic flow chart of a voltage adjustment method provided by the embodiment of the present application;

[0027] Figure 11 The schematic flow chart of a voltage adjustment method provided by the embodiment of the present application;

[0028] Figure 12 The schematic flow chart of a voltage adjustment method provided by the embodiment of the present application.

[0029] Legend:

[0030] 10-electronic device; 100-voltage regulation module; 110-target module; 1101-first target module; 1102-second target module; 1103-third target module; 120-PMIC module; 1201 control unit; 1202-P voltage regulation unit; BUCK-voltage output port; BUCK1-voltage output port; BUCK2-voltage output port; BUCK3-voltage output port; GPIO-GPIO port; GPIO1-GPIO port; GPIO2-GPIO port; GPIO3-GPIO port; GPIO1-1-first GPIO port; GPIO1-2-second GPIO port; 130-voltage detection module; 1301-comparator; 1302-operational amplifier; R1-first resistor; R2-second resistor; C1-first capacitor; C2-second capacitor; N1-first inverter; N2-second inverter; N3-third inverter. ​​​DETAILED DESCRIPTION

[0031] The embodiments of the present application will be described in detail below with reference to the drawings, in which the same or similar components have the same or similar reference numbers throughout the several figures. The embodiments described below are exemplary only, and are not intended to limit the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of the present application.

[0032] The terms "first", "second" in the specification and claims of the present application can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / ", generally means that the front and rear associated objects are in an "or" relationship.

[0033] In the description of the present application, it should be understood that the terms "in", "out" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0034] In the description of the present application, it should be noted that unless otherwise specified and limited, the terms "connected", "connected" should be broadly understood, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0035] Currently, in the process of voltage regulation by using the AVS voltage regulation system, a voltage detection circuit is used, and the voltage detection circuit often causes voltage regulation delay due to the many components (such as AVS sensor and AVS controller) contained therein, which causes the AVS voltage regulation system to have a slow response speed in the voltage regulation process. For example, referring to Figure 1In the related art, the AVS voltage regulation system in the electronic device can include a SoC chip and a PMIC module, the SoC chip includes a central processor, a memory, an arbiter, an AVS sensor and an AVS controller, and the PMIC module includes a voltage regulation unit. The voltage regulation scheme based on the AVS voltage regulation system includes: the central processor reads an initial voltage value pre-stored in the memory and gives the initial voltage value to the arbiter; the arbiter can send a voltage regulation command to the PMIC module through an SPMI (Serial Peripheral Management Interface) bus, the voltage regulation command including a power-on instruction and the initial voltage value; the PMIC module outputs a power supply voltage VDD to the SoC chip according to the voltage regulation command; the AVS sensor on the SoC chip detects the current power supply voltage VDD and current sensor data such as load and temperature in the SoC chip and outputs to the AVS controller; the AVS controller outputs a more suitable voltage value to the arbiter to update the voltage value according to the value of the current power supply voltage VDD and the current sensor data such as load and temperature in the SoC chip; the arbiter sends a voltage regulation command to the PMIC module through the SPMI bus again, the voltage regulation command including updated voltage value information; the voltage regulation unit in the PMIC module adjusts the current power supply voltage VDD output by the PMIC module according to the updated voltage value information, and thus the power supply voltage VDD output by the PMIC module can be regulated multiple times until the power supply voltage VDD output by the PMIC module reaches the expected voltage value. It should be noted that in one round of voltage regulation, the AVS sensor detection, the AVS controller, the arbiter and the SPMI bus transmission of the voltage regulation command are required, causing voltage regulation delay and thus slow response speed of the AVS voltage regulation system.

[0036] Therefore, in the embodiments of the present application, a voltage detection module is arranged between the target module and the PMIC module, and the voltage detection module is used to detect the voltage on the power supply line between the target module and the PMIC module. Since the voltage detection module can quickly detect the power supply voltage of the target module, the PMIC module can directly obtain the power supply voltage detected by the voltage detection module, thereby avoiding the voltage regulation delay caused by the long voltage detection loop of the AVS voltage regulation system in the related art and further improving the response speed of the voltage regulation module.

[0037] For example, in actual application, such as instantaneous load increase, external interference, etc. may cause the voltage of the functional module to drop, and if it drops below the lower limit of the voltage acceptable by the functional module, the functional module will work abnormally, and stability problems may occur. The traditional AVS scheme needs to pass through AVS sensor detection, AVS controller, arbitrator, SPMI bus transmission voltage regulation command, causing voltage regulation delay, thereby causing the response speed of the AVS voltage regulation system to be slow, and the stability problem caused by voltage drop in these scenarios cannot be solved. The voltage detection module is arranged between the target module and the PMIC module in the embodiment of the application, and the voltage drop on the power supply line between the target module and the PMIC module is detected through the voltage detection module. Since the voltage drop of the target module can be quickly detected through the voltage detection module, the voltage regulation delay caused by the voltage detection loop of the AVS voltage regulation system in the related art is avoided, the response speed of the voltage regulation module is further improved, and thus the stability problem caused by the voltage drop of the target module can be solved.

[0038] The voltage regulation module, the electronic device and the voltage adjustment method provided by the embodiment of the application will be described in detail below with reference to the drawings.

[0039] As shown in Figure 2 The voltage regulation module 100 provided by the embodiment of the application can include: a target module 110, a PMIC module 120 and a voltage detection module 130; the voltage detection module 130 is located between the target module 110 and the PMIC module 120.

[0040] The PMIC module 120 includes a voltage output port BUCK and a GPIO port; the voltage output port BUCK of the PMIC module 120 is connected with the target module 110 through a power supply line; the voltage detection module 130 has a first input end, a second input end and an output end, and the first input end of the voltage detection module 130 and the second input end of the voltage detection module 130 are both connected with the target module 110 through a power supply line, and the output end of the voltage detection module 130 is connected with the GPIO port of the PMIC module 120.

[0041] In the embodiment of the application, the target module 110 can be a module provided with working voltage by the PMIC module 120.

[0042] The target module 110 can be located inside the SoC chip or outside the SoC chip, and the specific arrangement position of the target module 110 is not limited in the application.

[0043] The target module 110 can include, but is not limited to, a graphic processing module (GPU), a memory module (DDR), a multi-media module (Multi-media), a display module (DISPLAY), a communication module (Modem), a display processing unit (DPU), a video processing unit (VPU), and the like. The specific function of the target module 110 is not limited in the present application.

[0044] The target module 110 can include one functional module or multiple functional modules, and the specific number of the target module 110 is not limited in the present application.

[0045] In the embodiment of the present application, the PMIC module 120 can provide an output voltage to the target module 110 through the voltage output port BUCK. The PMIC module 120 can also adjust the output voltage provided to the target module 110 according to actual needs.

[0046] The PMIC module 120 can realize power supply management of each functional module in the electronic device, and the PMIC module 120 can include at least one chip.

[0047] In the embodiment of the present application, the voltage detection module 130 can be understood as a hardware identification circuit, which can quickly detect the voltage on the power supply line between the target module 110 and the PMIC module 120, and directly output the detection result to the GPIO port of the PMIC module 120.

[0048] In the embodiment of the present application, the voltage detection module 130 is arranged between the target module 110 and the PMIC module 120. The voltage on the power supply line between the target module 110 and the PMIC module 120 is detected through the voltage detection module 130. Since the power supply voltage VDD of the target module 110 can be quickly detected through the voltage detection module 130, the PMIC module 120 can directly obtain the power supply voltage VDD of the target module detected by the voltage detection module 130. The delay caused by the detection loop of the AVS voltage regulation system in the related art is avoided, and the response speed of the voltage regulation module is further improved.

[0049] According to the voltage regulation module provided in the embodiment of the present application, the voltage regulation module comprises a target module, a PMIC module and a voltage detection module; the voltage detection module is located between the target module and the PMIC module; the PMIC module comprises a voltage output port and a GPIO port; the voltage output port of the PMIC module is connected with the target module through a power supply wire; the voltage detection module has a first input end, a second input end and an output end; the first input end of the voltage detection module and the second input end of the voltage detection module are both connected with the target module through a power supply wire; and the output end of the voltage detection module is connected with the GPIO port of the PMIC module. In this way, the voltage detection module is arranged between the target module and the PMIC module, and the voltage on the power supply wire between the target module and the PMIC module is detected through the voltage detection module. Since the power supply voltage of the target module can be quickly detected through the voltage detection module, the PMIC module can directly obtain the power supply voltage detected by the voltage detection module, thereby avoiding the delay caused by the detection loop of the AVS voltage regulation system in the related art, and further improving the response speed of the voltage regulation module.

[0050] In particular, in the scenario where the voltage of the target module drops due to instantaneous load increase, external interference, etc., the voltage detection module is arranged between the target module and the PMIC module, and the voltage drop on the power supply wire between the target module and the PMIC module is detected through the voltage detection module. Since the voltage drop of the target module can be quickly detected through the voltage detection module, the delay caused by the detection loop of the adaptive voltage regulation sensor in the related art is avoided, the response speed of the voltage regulation module is further improved, and thus the stability problem caused by the voltage drop of the target module can be solved.

[0051] For example, in the scenario where the voltage of the target module drops due to instantaneous load increase, external interference, etc., the voltage detection module 130 is arranged between the target module 110 and the PMIC module 120, and the voltage drop on the power supply wire between the target module 110 and the PMIC module 120 is detected through the voltage detection module 130. Since the voltage drop of the target module 110 can be quickly detected through the voltage detection module 130, the delay caused by the detection loop of the adaptive voltage regulation sensor in the related art is avoided, the response speed of the voltage regulation module is further improved, and thus the output voltage drop of the PMIC module 120 can be quickly and timely detected by the voltage detection module 130, so that the PMIC module 120 can timely adjust the output voltage provided to the target module 110 through the voltage output port BUCK of the PMIC module 120, avoid the abnormal operation of the target module 110, improve the system stability, solve the stability problem caused by the voltage drop of the target module, and improve the anti-interference ability of the system.

[0052] In actual application, in case that the voltage drop on the power supply line between the target module 110 and the PMIC module 120 is detected by the voltage detection module 130, in order to avoid the stability problem caused by the voltage drop of the target module, the PMIC module 120 further includes a voltage regulating unit inside, so as to timely adjust the output voltage provided by the voltage output port BUCK of the PMIC module 120 to the target module 110. The following is an example.

[0053] For example, in a specific embodiment, as shown in Figure 3 The PMIC module 120 further includes a control unit 1201 and a voltage regulating unit 1202, the GPIO port is connected with the control unit 1201, the control unit 1201 is connected with the voltage regulating unit 1202, and the voltage regulating unit 1202 is connected with the voltage output port BUCK.

[0054] The output of the voltage detection module 130 includes a target signal. In response to the voltage detection module 130 detecting that the output voltage of the voltage output port BUCK of the PMIC module drops below the preset value, the voltage detection module 130 outputs the target signal to the GPIO port of the PMIC module 120; the GPIO port transmits the target signal to the control unit 1201, the control unit 1201 generates a voltage boosting instruction based on the target signal, and transmits the voltage boosting instruction to the voltage regulating unit 1202, and the voltage regulating unit 1202 increases the output voltage provided by the voltage output port BUCK to the target module 110.

[0055] In this way, in response to the voltage detection module 130 outputting the target signal to the GPIO port of the PMIC module 120 in case of quickly detecting the output voltage drop of the PMIC module 120, the control unit 1201 and the voltage regulating unit 1202 of the PMIC module 120 can timely adjust the output voltage provided by the voltage output port BUCK to the target module 110 based on the target signal, avoid the abnormal work of the target module 110, improve the system stability, and solve the stability problem caused by the voltage drop of the target module.

[0056] In actual application, the PMIC module can supply power to multiple target modules through multiple power supply lines, and many target modules have stability problems caused by voltage drop. Based on this, the application can further set multiple voltage detection modules to monitor the voltage drop of the multiple power supply lines, and solve the stability problems of multiple target modules caused by voltage drop. The following is an example.

[0057] In a specific embodiment, the target module can include multiple target modules, and the voltage output port includes multiple voltage output ports, one voltage output port being connected with one target module through one power supply line;

[0058] The voltage detection module includes multiple modules, and the GPIO port includes multiple ports. The first and second input terminals of a voltage detection module are connected to a target module via a power supply line, and the output terminal of a voltage detection module is connected to a GPIO port.

[0059] For example, such as Figure 4 As shown, taking three target modules as an example, the target modules may include a first target module 1101, a second target module 1102, and a third target module 1103; the voltage output port BUCK1 is connected to the first target module 1101 through a power supply line, the voltage output port BUCK2 is connected to the second target module 1102 through a power supply line, and the voltage output port BUCK3 is connected to the third target module 1103 through a power supply line.

[0060] The three target modules can be different modules. For example, the first target module 1101 can be a graphics processing module (GPU), the second target module 1102 can be a memory module (DDR), and the third target module 1103 can be a display module. Of course, the three target modules can also be other modules, and this application does not limit the specific functions of the target modules.

[0061] Among them, such as Figure 4 As shown, the voltage detection module also includes three modules, and the GPIO ports include three ports.

[0062] The first input terminal and the second input terminal of the first voltage detection module 130 are connected to the first target module 1101 via a power supply line, and the output terminal of the first voltage detection module is connected to the first GPIO port GPIO1.

[0063] The first and second input terminals of the second voltage detection module 130 are connected to the second target module 1102 via a power supply line, and the output terminal of the second voltage detection module 130 is connected to the second GPIO port GPIO2.

[0064] The first and second input terminals of the third voltage detection module 130 are connected to the third target module 1103 via a power supply line, and the output terminal of the third voltage detection module 130 is connected to the third GPIO port GPIO3.

[0065] The PMIC module 120 can also store the mapping relationship between the target module, GPIO ports, and voltage output ports, as shown in Table 1:

[0066]

[0067] Table 1

[0068] Referring to Table 1, in response to the first voltage detection module 130 detecting that the voltage output interface BUCK1 of the PMIC module 120 outputs a voltage drop, a first target signal is output to the GPIO1 port of the PMIC module 120, and the PMIC module 120 can adjust the output voltage provided to the first target module 1101 through the voltage output port BUCK1 in time based on the first target signal, so as to avoid the first target module 1101 from working abnormally.

[0069] Similarly, in response to the second voltage detection module 130 detecting that the voltage output interface BUCK2 of the PMIC module 120 outputs a voltage drop, a second target signal is output to the GPIO2 port of the PMIC module 120, and the PMIC module 120 can adjust the output voltage provided to the second target module 1102 through the voltage output port BUCK2 in time based on the second target signal, so as to avoid the second target module 1102 from working abnormally.

[0070] Similarly, in response to the third voltage detection module 130 detecting that the voltage output interface BUCK3 of the PMIC module 120 outputs a voltage drop, a third target signal is output to the GPIO3 port of the PMIC module 120, and the PMIC module 120 can adjust the output voltage provided to the third target module 1103 through the voltage output port BUCK3 in time based on the third target signal, so as to avoid the third target module 1103 from working abnormally.

[0071] In this way, the embodiment of the present application solves the stability problem of the multiple target modules caused by voltage drop by using multiple voltage detection modules to monitor the voltage drop of multiple power supply lines, respectively.

[0072] In actual application, the voltage detection module can use various types of circuits to monitor the voltage drop, such as comparator circuit or operational amplifier circuit, etc., and the specific structure of the voltage detection module is not limited in the present application. The following is an example.

[0073] In a specific embodiment, as shown in Figure 5 The voltage detection module 130 can include a comparator 1301, a first capacitor C1 and a first resistor R1. The comparator 1301 has a first input end, a second input end and an output end. The first input end of the comparator 1301 is connected with the target module 110 through a power supply line. The second input end of the comparator 1301 is connected with the target module 110 through the first resistor R1 and the power supply line. The second input end of the comparator 1301 is also connected with the ground through the first capacitor C1. The output end of the comparator 1301 is connected with the GPIO port.

[0074] The first input end of the comparator 1301 can be a reverse input end, and the second input end can be a same direction input end. The same phase input end and the reverse phase input end of the comparator 1301 are connected with the target module 110 through the power supply wire, and the same phase input end of the comparator 1301 is also connected with the first capacitor C1.

[0075] The comparator 1301 can monitor the voltage fluctuation on the power supply wire and output a high level signal to the GPIO port of the PMIC module 120 in the case of voltage drop. For example, in the case of transient load increase of the target module 110, the output voltage of the voltage output port BUCK is instantaneously pulled down by the target module, for example, from 800 mV to 750 mV. At this time, the same phase input end of the comparator 1301 has the first capacitor C1 and the first resistor R1 to maintain the input voltage at 800 mV for a period of time, and the input voltage of the reverse input end of the comparator 1301 instantaneously decreases to 750 mV. At this time, the input voltage of the same phase input end of the comparator 1301 is 800 mV, which is greater than the input voltage of the reverse phase input end of the comparator 1301, that is, 750 mV. Therefore, the output end of the comparator 1301 outputs a high level signal to the GPIO port. After a period of time, when the load does not have transient increase, the voltage of the same phase input end of the comparator 1301 is the same as that of the reverse input end of the comparator 1301. At this time, the output end of the comparator 1301 outputs a low level signal to the GPIO port.

[0076] The output of the comparator 1301 contains a first level signal, and the first level signal indicates that the PMIC module 120 increases the output voltage provided to the target module 110 through the voltage output port BUCK.

[0077] The first level signal can be a high level signal. For example, the PMIC module 120 recognizes the high level signal of the GPIO1 port, which indicates that the output voltage of the voltage output port BUCK is instantaneously pulled down by the target module 110 due to the transient load increase of the target module 110. Therefore, the PMIC module 120 can increase the output voltage output to the target module 110 through the voltage output port BUCK.

[0078] Therefore, compared with the voltage regulation scheme of the AVS voltage regulation system shown in Figure 1 Therefore, compared with the voltage regulation scheme of the AVS voltage regulation system shown in

[0079] In another specific embodiment, as shown in Figure 6As shown, the voltage detection module 130 includes an operational amplifier 1302, a second resistor R2, a second capacitor C2, a first inverter N1 and a second inverter N2; the operational amplifier 1302 has a first input end, a second input end and an output end, the first input end of the operational amplifier 1302 is connected with the target module 110 through a power supply wire, the second input end of the operational amplifier 1302 is connected with the target module 110 through the second resistor R2 and the power supply wire, and the second input end of the operational amplifier 1302 is also grounded through the second capacitor C2; the output end of the operational amplifier 1302 is connected with the GPIO port through the first inverter N1 and the second inverter N2.

[0080] Compared with the voltage detection module shown in Figure 5 Compared with the voltage detection module shown in, the operational amplifier 1302 is used instead of the comparator 1301, the speed of the operational amplifier 1302 outputting a high level is slower, the output is an analog signal, and there is a signal from low to high climbing process. The non-inverting input end and the inverting input end of the operational amplifier 1302 are connected with the target module 110 through a power supply wire, the non-inverting input end of the operational amplifier 1302 is also connected with the second capacitor C2 and the second resistor R2 in series, and the output end of the operational amplifier 1302 is connected with the GPIO port GPIO1-1 through the first inverter N1 and the second inverter N2. The operational amplifier 1302 can be used to monitor the voltage fluctuation on the power supply wire.

[0081] The first inverter N1 is used to convert the analog signal output by the operational amplifier 1302 into a digital signal. The second inverter N2 is used to output a high level signal to the GPIO port GPIO1-1 of the PMIC module 120 in the case of voltage drop.

[0082] The output of the second inverter N2 contains a second level signal, and the second level signal indicates that the PMIC module 120 increases the output voltage provided to the target module 110 through the voltage output port BUCK1.

[0083] The second level signal can be a high level signal. For example, the PMIC module 120 recognizes the high level signal of the GPIO1-1 port, which means that the output voltage of the voltage output port BUCK is pulled down by the target module instantaneously due to the transient increase of the load of the target module 110, and then the PMIC module 120 can increase the output voltage output to the target module 110 through the voltage output port BUCK.

[0084] In this way, compared with Figure 1Compared with the voltage regulation scheme of the AVS voltage regulation system shown, the embodiment of the present application does not need to detect the voltage regulation command through the AVS sensor, the AVS controller, the arbitrator and the SPMI bus again, but can directly adjust the high voltage in the case that the PMIC module 120 identifies the high level signal of the GPIO1 port, so as to realize the effect of quickly increasing the voltage.

[0085] In a specific example, in order to avoid the increase of power consumption caused by the continuous high voltage, the PMIC module 120 can be configured to detect the high voltage and the low voltage of the GPIO1 port, and the PMIC module 120 can be configured to adjust the output voltage of the BUCK1 port according to the high voltage and the low voltage of the GPIO1 port. Figure 7-1 As shown in the voltage detection module shown in the prior art, the voltage detection module 130 can further include a third inverter N3, and the GPIO port includes a first GPIO port GPIO1-1 and a second GPIO port GPIO1-2. Figure 6 As shown in the voltage detection module shown in the prior art, the voltage detection module 130 can further include a third inverter N3, and the GPIO port includes a first GPIO port GPIO1-1 and a second GPIO port GPIO1-2.

[0086] The output end of the operational amplifier 1302 is connected with the first GPIO port GPIO1-1 in sequence via the first inverter N1 and the second inverter N2.

[0087] The output end of the operational amplifier 1302 is further connected with the second GPIO port GPIO1-2 via the third inverter N3.

[0088] The working threshold voltage of the first inverter N1 is the same as that of the second inverter N2, and the working threshold voltage of the second inverter N2 is greater than that of the third inverter N3.

[0089] The two groups of inverters N1 & N2 and N3 with different working threshold voltages Vth are respectively connected with the GPIO1-1 and the GPIO1-2 of the PMIC module, and there is a time difference in the output of the high level of the second inverter N2 and the third inverter N3 due to the different working threshold voltages Vth.

[0090] The output of the third inverter N3 contains a third level signal, and the third level signal indicates that the PMIC module 120 adjusts the output voltage provided by the BUCK1 voltage output port to the target module 110.

[0091] It can be understood that the PMIC adjusts the high voltage and restores the voltage by detecting the high / low state of the output level of the second inverter N2 / third inverter N3 respectively, adjusts the high voltage when the second inverter N2 outputs the high level signal, and restores the voltage when the third inverter outputs the high level signal.

[0092] For example, if the PMIC module 120 detects a high-level signal at the GPIO1-1 port, it indicates that the load transient of the target module 110 has increased, causing the output voltage of the voltage output port BUCK to be pulled down momentarily by the target module. In this case, the PMIC module 120 can increase the output voltage output to the target module 110 through the voltage output port BUCK1 to avoid stability problems caused by the load transient.

[0093] For example, if the PMIC module 120 detects a high-level signal at the GPIO1-2 port, it means that after a period of time, the load of the target module 110 has not increased transiently, and the output voltage of the voltage output port BUCK has returned to normal. Then, the PMIC module 120 can reduce the output voltage output to the target module 110 through the voltage output port BUCK1 to avoid increased power consumption caused by continuous high voltage.

[0094] The following simulation example illustrates the signal conversion process of the voltage detection module.

[0095] Figure 7-2 Showing a kind of Figure 7-1 The simulation circuit corresponding to the voltage detection module is shown. The power supply for the voltage output path of the PMIC module 120 is Vdc, and its internal resistance is R. The load-discharge model of the target module 110 can be equivalent to a current source It.

[0096] The PMIC module 120 outputs Vdc of 800mV, and the target module 110 can output a square wave with a pump frequency of 100kHz. R2 = 1kΩ, C2 = 1pF (or 10pF). During transient pump-off, the power supply drops from 800mV to 780mV for 2 microseconds. The output waveforms of the first input terminal N and the second input terminal P of the operational amplifier 1302 at this time can be referenced. Figure 7-3 .

[0097] like Figure 7-3 As shown, since R2 and C2 connected to the second input terminal P (non-inverting input terminal) of operational amplifier 1302 can maintain the voltage, when the voltage on the power supply line drops, the input voltage of the second input terminal P (non-inverting input terminal) is slightly higher than the input voltage of the first input terminal N (inverting input terminal), and when the voltage rises, the input voltage of the second input terminal P (non-inverting input terminal) is slightly lower than the input voltage of the first input terminal N (inverting input terminal).

[0098] The operational amplifier 1302 works by proportionally amplifying the voltage difference between the input voltage at the second input terminal P (non-inverting input) and the input voltage at the first input terminal N (inverting input) before outputting the result. The output waveform of the operational amplifier 1302's output terminal AMP_OUT can be referenced here. Figure 7-4 .like Figure 7-4As shown, when the output voltage of the PMIC module 120 drops due to the transient load of the target module 110, the output waveform of the AMP_OUT has an upward pulse signal; after a period of time, the load of the target module 110 does not have a transient increase, and when the output voltage of the voltage output port BUCK returns to normal, the output waveform of the AMP_OUT has a downward pulse signal.

[0099] Then, the operating threshold voltage of the first inverter N1 and the second inverter N2 can be 510mV, and the operating threshold voltage of the third inverter N3 is 500mV. Then, the output waveform of the output end AMP_OUT of the operational amplifier 1302 after passing through the two groups of inverters can be referred to as Figure 7-5 .

[0100] As shown in Figure 7-5 , when the output end AMP_OUT of the operational amplifier 1302 is above 510mV, the second inverter N2 outputs a high level of 1.8V, and the GPIO1-1 port of the PMIC module detects a high level signal, so that the PMIC module adjusts the output voltage output by the voltage output port BUCK1 to the target module 110, thereby avoiding the stability problem caused by the transient increase of the load.

[0101] As shown in Figure 7-5 , when the output end AMP_OUT of the operational amplifier 1302 is between 510mV and 500mV, the second inverter N2 outputs a low level of 0V, and the third inverter N3 outputs a low level of 0V.

[0102] As shown in Figure 7-5 , when the output end AMP_OUT of the operational amplifier 1302 is below 500mV, the second inverter N2 outputs a low level of 0V, and the third inverter N3 outputs a high level of 1.8V, and the GPIO1-2 port of the PMIC module detects a high level signal, so that the PMIC module adjusts the output voltage output by the voltage output port BUCK1 to the target module 110, thereby recovering the voltage value before the voltage is raised, and avoiding the increase of power consumption caused by the continuous high voltage.

[0103] In addition, referring to Figure 8In actual application, the voltage regulation module provided in the embodiments of the present application can further include a central processing unit, a memory, an arbitrator, an AVS sensor and an AVS controller. The central processing unit, the memory, the arbitrator, the AVS sensor, the AVS controller and the target module 110 can all be located inside an SoC chip. The voltage regulation scheme based on the voltage regulation module includes that the central processing unit reads an initial voltage value pre-stored in the memory and sends the initial voltage value to the arbitrator; the arbitrator sends a voltage regulation command to a PMIC module through an SPMI (Serial Peripheral Management Interface) bus, the voltage regulation command including a power-on instruction and the initial voltage value; the PMIC module outputs a power voltage VDD to the SoC chip according to the voltage regulation command; an AVS sensor on the SoC chip detects the current power voltage VDD and current sensor data such as load and temperature inside the SoC chip and outputs them to the AVS controller; the AVS controller outputs a more suitable voltage value to the arbitrator to update the voltage value according to the value of the current power voltage VDD and the current sensor data such as load and temperature inside the SoC chip; the arbitrator sends a voltage regulation command to the PMIC module through the SPMI bus again, the voltage regulation command including the updated voltage value information; and a voltage regulation unit in the PMIC module adjusts the power voltage VDD currently output by the PMIC module according to the updated voltage value information, so that the voltage can be regulated multiple times until the power voltage VDD output by the PMIC module reaches an expected voltage value.

[0104] In addition, in the scenario where the load of the target module 110 is transiently increased, the PMIC module 120 identifies the high-level signal of the GPIO port, which indicates that the output voltage of the voltage output port BUCK is instantaneously pulled down by the target module due to the transient increase of the load of the target module 110, and then the PMIC module 120 can increase the output voltage output to the target module 110 through the voltage output port BUCK to avoid the stability problem caused by the transient increase of the load.

[0105] In addition, since the voltage does not need to be adjusted through the AVS sensor detection, the AVS controller, the arbitrator and the SPMI bus transmission of the voltage regulation command, but can be directly increased by the PMIC module 120 in the case where the high-level signal of the GPIO port is identified, the effect of rapidly increasing the voltage is achieved.

[0106] Based on the same concept as the voltage regulation module provided in any of the above embodiments, the embodiments of the present application further provide an electronic device.

[0107] As shown in Figure 9 , the embodiments of the present application provide an electronic device 10, which includes a voltage regulation module 100.

[0108] It should be noted that the electronic device 10 provided in this application embodiment includes the voltage regulating module provided in any of the above embodiments, and can realize all the functions of the voltage regulating module. To avoid repetition, it will not be described again here.

[0109] In the embodiments of this application, the electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a smartwatch, mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), etc. The embodiments of this application do not specifically limit the scope.

[0110] Based on a concept similar to the voltage regulating module provided in any of the above embodiments, this application also provides a voltage adjustment method, which is applied to the voltage regulating module provided in any of the above embodiments.

[0111] For example, such as Figure 10 As shown, this application provides a voltage adjustment method, applied to the voltage regulating module provided in any of the above embodiments. The voltage adjustment method may include:

[0112] Step 1010: When the voltage detection module detects that the output voltage of the PMIC module has dropped below a preset value, it outputs a target signal to the PMIC module;

[0113] Step 1020: Based on the target signal, the PMIC module increases the output voltage supplied to the target module through the voltage output port of the PMIC module.

[0114] The target signal can be, for example, Figure 5 The first level signal output by comparator 1301 in the detection circuit shown can also be as follows: Figure 6 The second level signal output by the second inverter N2 in the detection circuit shown is not specifically limited in this application.

[0115] The first level signal can be a high level signal, and the second level signal can be a high level signal.

[0116] The PMIC module 120 recognizes the high level signal of the GPIO port, indicating that the load transient increase of the target module 110 causes the output voltage of the voltage output port BUCK to be instantaneously pulled down by the target module, and the PMIC module 120 can increase the output voltage output to the target module 110 through the voltage output port BUCK to avoid the stability problem caused by the load transient increase.

[0117] According to the voltage adjustment method provided in the embodiment of the present application, the voltage detection module outputs a target signal to the PMIC module when detecting that the output voltage of the PMIC module drops below a preset value; and the PMIC module increases the output voltage provided to the target module through the voltage output port of the PMIC module based on the target signal. In this way, the voltage detection module is used to detect the power supply voltage output by the PMIC module to the target module, and since the voltage detection module can quickly detect the power supply voltage of the target module, the PMIC module can directly obtain the power supply voltage detected by the voltage detection module, avoiding the delay caused by the detection loop of the AVS voltage regulation system in the related art, and further improving the response speed of the voltage regulation module.

[0118] In particular, the voltage detection module 130 is used to detect the voltage drop on the power supply line between the target module 110 and the PMIC module 120, and since the voltage detection module 130 can quickly detect the voltage drop of the target module 110, the delay caused by the detection loop of the adaptive voltage sensor in the related art is avoided, and the response speed of the voltage regulation module is further improved, so that the voltage detection module 130 can quickly and timely detect the output voltage drop of the PMIC module 120, so that the PMIC module 120 can timely increase the output voltage provided to the target module 110 through the voltage output port BUCK of the PMIC module 120, avoid the abnormal operation of the target module 110, improve the system stability, and solve the stability problem caused by the voltage drop of the target module.

[0119] In actual application, if the voltage detection module 130 detects the voltage drop on the power supply line between the target module 110 and the PMIC module 120, the voltage drop on the power supply line may be caused by the load transient increase of the target module 110, or may be caused by the buck command sent by the arbiter to the PMIC module through the SPMI bus. In order to avoid false buck action, the embodiment of the present application can further detect whether the buck command is received before triggering the buck action, if the buck command is not received, it indicates that the voltage drop on the power supply line is caused by the load transient increase of the target module 110, and if the buck command is received, it indicates that the voltage drop on the power supply line is caused by the buck command.

[0120] Based on this, in one specific embodiment, after step 1010, the voltage adjustment method can further include: determining whether the PMIC module receives a voltage reduction command.

[0121] The voltage reduction command can be sent by an arbitrator inside the SoC chip to the PMIC module through an SPMI bus, or can be sent by other control modules or processing modules inside the SoC chip to the PMIC module through the SPMI bus, and the specific source of the voltage reduction command is not limited in the present application.

[0122] Further, in step 1020, the PMIC module adjusts the output voltage of the voltage output port of the PMIC module based on the target signal, and specifically includes:

[0123] In the case where the PMIC module does not receive the voltage reduction command from the arbitrator, the PMIC module adjusts the output voltage provided by the voltage output port of the PMIC module to the target module based on the target signal;

[0124] The arbitrator and the target module can be arranged in the SoC chip. For example, as shown in the voltage regulation module, the arbitrator and the target module can be arranged in the SoC chip, and the arbitrator can send the voltage reduction command to the PMIC module through the SPMI bus. Figure 8

[0125] For example, in actual applications, for DVFS (Dynamic Voltage Frequency Scaling, dynamic voltage frequency scaling) power supply and AVS power supply, the voltage regulation system will automatically adjust the voltage according to the working frequency and temperature and other factors, and the following two cases will occur:

[0126] Case one: when switching from low frequency and low voltage to high frequency and high voltage, the voltage at the non-inverting input of the comparator is lower than that at the inverting input, and the output is low, which will not mis-trigger the PMIC module to raise the voltage;

[0127] Case two: when switching from high frequency and high voltage to low frequency and low voltage, the voltage at the non-inverting input of the comparator is higher than that at the inverting input, and the output is high, which will mis-trigger the PMIC module to raise the voltage. Since the action of actively switching the frequency and voltage is accompanied by an SPMI control signal, it can be determined by software logic whether the system actively reduces the voltage or the voltage drop caused by transient load, thereby avoiding mis-triggering the voltage raising.

[0128] The specific voltage adjustment process can refer to Figure 11 The steps of the voltage adjustment include:

[0129] Step 1110: obtaining the voltage value corresponding to the working frequency from the memory;

[0130] ​Wherein, each SoC chip completes the FT (Final Test) test when the SoC chip is shipped, for ensuring the SoC chip function is normal. The FT test can test the working voltage value suitable for each SoC chip internal CPU, GPU, DDR and other functional modules respectively, and record the voltage value and store it in the memory. Based on this, after the electronic device is powered on, the voltage value corresponding to the working frequency can be obtained from the memory.

[0131] Step 1120: sending a voltage adjustment command to the PMIC module through the SPMI bus to output a voltage;

[0132] Wherein, the voltage adjustment command can be obtained by the arbitrator through comprehensive consideration, for example, if it is the first round of voltage regulation, the voltage adjustment command can be generated directly based on the voltage value obtained from the memory, and sent to the PMIC module through the SPMI bus, so as to ensure that the system is quickly initialized and enters the working state; if it is not the first round of voltage regulation, the updated voltage value can be determined based on the current voltage value detected by the AVS sensor and the load and temperature of each module in the current SoC chip, and the voltage adjustment command can be generated based on the updated voltage value, and sent to the PMIC module through the SPMI bus, so as to realize adaptive voltage regulation or dynamic voltage frequency regulation.

[0133] Step 1130: the voltage output port BUCK of the PMIC module outputs a voltage value;

[0134] Wherein, the PMIC module can adjust the power voltage based on the voltage adjustment command from the SPMI bus and output the voltage value to the target module through the voltage output port BUCK.

[0135] Step 1140: the GPIO port of the PMIC module receives a high level signal;

[0136] Wherein, the GPIO port of the PMIC module receives a high level signal, which means that the output voltage of the voltage output port BUCK is reduced.

[0137] Step 1150: judging whether the SPMI receives a voltage reduction command:

[0138] If the SPMI does not receive the voltage reduction command, step 1160 is executed to increase the voltage:

[0139] If the SPMI receives the voltage reduction command, step 1170 is executed without triggering the voltage increase action.

[0140] Wherein, if the SPMI does not receive the voltage reduction command, it means that the voltage drop on the power supply line is caused by the load transient increase of the target module 110, and if the voltage reduction command is received, it means that the voltage drop on the power supply line is caused by the voltage reduction command.

[0141] Further, in the case that the SPMI does not receive the buck command, it indicates that the load transient of the target module 110 increases, causing the output voltage of the voltage output port BUCK to be pulled down by the target module instantaneously. The PMIC module 120 can increase the output voltage output to the target module 110 through the voltage output port BUCK to avoid the stability problem caused by the load transient increase. In the case that the SPMI receives the buck command, it indicates that the voltage drop on the power supply line is caused by the buck command, and the buck action is not triggered, which can avoid triggering the buck action.

[0142] In this way, the PMIC module, in the case that no buck command is received, increases the output voltage provided to the target module through the voltage output port of the PMIC module based on the target signal, which can avoid triggering the buck action.

[0143] In another specific embodiment, in order to avoid the increase of power consumption caused by the continuous high voltage, as shown in the voltage adjustment method, the voltage adjustment method further includes: Figure 12

[0144] Step 1210: The voltage detection module outputs a target signal to the PMIC module in the case that the output voltage of the PMIC module is detected to be below a preset value.

[0145] Step 1220: The PMIC module increases the output voltage provided to the target module through the voltage output port of the PMIC module based on the target signal.

[0146] Step 1230: In the case that the voltage detection module includes a third inverter, in response to the voltage detection module detecting that the output voltage of the voltage output port of the PMIC module recovers to the preset value, the third inverter outputs a third level signal to the PMIC module.

[0147] Step 1240: The PMIC module decreases the output voltage output to the target module by the voltage output port of the PMIC module based on the third level signal.

[0148] Wherein, the steps 1210 to 1220 can refer to the specific content of the steps 1010 to 1020.

[0149] It can be understood that in the steps 1210 to 1220, the PMIC module recognizes the target signal (high level signal) of the GPIO port, which indicates that the load transient of the target module 110 increases, causing the output voltage of the voltage output port BUCK to be pulled down by the target module instantaneously. The PMIC module 120 can increase the output voltage output to the target module 110 through the voltage output port BUCK1 to avoid the stability problem caused by the load transient increase.

[0150] ​In steps 1230 to 1240, the PMIC module identifies the third level signal (high level signal) output by the third inverter, indicating that the load of the target module 110 has no transient increase after a period of time, the output voltage of the voltage output port BUCK returns to normal, and then the PMIC module 120 can lower the output voltage output to the target module 110 through the voltage output port BUCK1, thereby restoring the voltage value before the voltage is lifted, and avoiding the increase in power consumption caused by the sustained high voltage.

[0151] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the exemplary description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0152] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and purposes of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A voltage regulating module, characterized by, The application relates to a voltage detection module for a PMIC module and a target module. The voltage detection module is located between the target module and the PMIC module. The PMIC module comprises a voltage output port and a general input-output (GPIO) port. The voltage detection module comprises an operational amplifier, a second resistor, a second capacitor, a first inverter and a second inverter.

2. The pressure regulating module of claim 1, wherein, The PMIC module further comprises a control unit and a voltage regulating unit.

3. The pressure regulating module of claim 1, wherein, The target module comprises a plurality of target modules, and the voltage output port comprises a plurality of voltage output ports. One first input end and one second input end of one voltage detection module are connected to one target module via one power supply line, and one output end of one voltage detection module is connected to one GPIO port.

4. The pressure regulating module of any one of claims 1-3, wherein, The output of the comparator comprises a first level signal, which indicates that the PMIC module increases the output voltage provided to the target module via the voltage output port.

5. The pressure regulating module of claim 4, wherein, The voltage detection module further comprises a third inverter.

6. The pressure regulating module of claim 1, wherein, The output end of the operational amplifier is connected to the first GPIO port via the first inverter and the second inverter. The output end of the operational amplifier is further connected to the second GPIO port via the third inverter. ​ The first inverter and the second inverter have the same working threshold voltage, and the working threshold voltage of the second inverter is greater than the working threshold voltage of the third inverter.

7. The voltage regulation module of claim 6, wherein, the output of the second inverter comprises a second level signal, and the second level signal indicates that the PMIC module increases the output voltage provided to the target module through the voltage output port; the output of the third inverter comprises a third level signal, and the third level signal indicates that the PMIC module decreases the output voltage provided to the target module through the voltage output port.

8. An electronic device, comprising: The voltage regulation module comprises any one of claims 1-7.

9. A voltage adjustment method applied to the voltage adjustment module of any one of claims 1-7, characterized in that, The method comprises: the voltage detection module outputs a target signal to the PMIC module when detecting that the output voltage of the PMIC module drops below a preset value; the PMIC module increases the output voltage provided to the target module through the voltage output port of the PMIC module based on the target signal.

10. The method of claim 9, wherein, The PMIC module increases the output voltage of the voltage output port of the PMIC module based on the target signal, comprising: the PMIC module increases the output voltage provided to the target module through the voltage output port of the PMIC module based on the target signal when no voltage decrease command is received from the arbitrator; The arbitrator and the target module are arranged in a system on chip (SoC) chip.

11. The method of claim 10, wherein, After the PMIC module increases the output voltage of the voltage output port of the PMIC module based on the target signal, the method further comprises: when the voltage detection module comprises a third inverter, the third inverter outputs a third level signal to the PMIC module in response to the voltage detection module detecting that the output voltage of the voltage output port of the PMIC module returns to the preset value; the PMIC module decreases the output voltage output by the voltage output port of the PMIC module to the target module based on the third level signal.

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