An under-voltage generating circuit

Abstract

The present invention belongs to the field of radio frequency circuits and relates to an undershoot voltage generating circuit. A resistor R1 and a capacitor C1 are used to stabilize the circuit, and a current source Ib provides the bias current for the operational amplifier. The MOS transistor P5 serves as a current-voltage conversion transistor, with its drain connected to four serially connected voltage-regulating resistors and its gate connected to the output terminal of the clamping operational amplifier. The clamping operational amplifier correlates the node voltage VX with the reference voltage VREF and dynamically regulates the gate voltage of the MOS transistor P5 through a feedback loop. The MOS transistor P6, the MOS transistor Q6, and the MOS transistor Q7 form a current mirror circuit for replicating the gate voltage of the MOS transistor P5, thereby generating a reference current. The reference current is injected into the RC low-pass circuit, and finally an undershoot voltage is generated. It solves the problem of difficult-to-test overshoot fluctuations existing in circuits such as power amplifiers.

Description

Technical Field

[0001] The present invention belongs to the field of radio frequency circuits, and particularly relates to an undershoot voltage generation circuit. Background Art

[0002] Analog LDO (low dropout linear regulator) is widely used in low-input and high-precision power supply circuits due to its advantages of low power consumption, high integration, low noise, adjustable temperature coefficient, etc. Especially in the receiving and transmitting parts of radio frequency circuits, analog LDOs with low noise, high power supply rejection ratio and built-in temperature coefficient are required for low-noise amplifiers, power amplifiers, mixers, etc. to optimize the temperature characteristics of the circuit and improve the circuit linearity. Among them, circuits such as power amplifiers have overshoot fluctuations that are difficult to test, and it is easier to solve this problem in the analog LDO used for power supply than in the power amplifier.

[0003] Therefore, how to make the output voltage of the analog LDO generate an undershoot at the initial start-up and return to the default value after a period of time has become a technical problem that needs to be solved urgently. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an undershoot voltage generation circuit to introduce an undershoot voltage that can be maintained for a certain period of time when the analog LDO circuit starts up, and solve the problem of overshoot fluctuations that are difficult to test in circuits such as power amplifiers.

[0005] The present invention is implemented as follows:

[0006] An undershoot voltage generation circuit, the undershoot voltage generation circuit includes:

[0007] Resistors RT1, RT2, RT3, and RT4 are connected in series in sequence and then connected to one end of capacitor C2 to form an RC low-pass circuit. The other end of capacitor C2 is grounded. The voltage output terminal VOUT is between resistor RT4 and capacitor C2. The other end of resistor RT1 is connected to the reference voltage VREF;

[0008] The MOS transistors P7, P8, P4 and the MOS transistors Q8, Q9, Q10, and Q11 form an enable control circuit. Among them, the gate of the MOS transistor Q10 is connected to the gate of the MOS transistor P7 and is connected to the control signal EN. The drain of the MOS transistor Q10 is connected to the drain of the MOS transistor P7 and is connected to the gate of the MOS transistor P4. The source of the MOS transistor Q10 is grounded. The sources of the MOS transistors P7 and P4 are connected to the power supply VDD. The drain of the MOS transistor P4 is connected to the gate of the MOS transistor P5 to control the on / off of the MOS transistor P5. The drain of the MOS transistor P4 is connected to the gate of the MOS transistor P6. The source of the MOS transistor P6 is connected to the power supply VDD. The drain of the MOS transistor P6 is connected to the drain and gate of the MOS transistor Q7. The gate of the MOS transistor Q7 is connected to the gate of the MOS transistor Q6. The source of the MOS transistor Q6 is grounded. The drain of the MOS transistor Q6 is connected to the reference voltage VREF. The source of the MOS transistor Q7 is grounded;

[0009] The drain of the MOS transistor Q11 is connected to the drain of the MOS transistor P8 and is connected to the gates of the MOS transistors Q8 and Q9 to control the on / off of the MOS transistors Q8 and Q9. The source of the MOS transistor Q11 is grounded. The source of the MOS transistor P8 is connected to the power supply VDD. The gates of the MOS transistors P8 and Q11 are connected and then connected to the gate of the MOS transistor P4;

[0010] The MOS transistors P1, P2, P3, the MOS transistors Q3, Q4, Q5, the current source Ib, the resistor R1, and the capacitor C1 form a clamping operational amplifier. Among them, the gate of the MOS transistor P1 is connected to the reference voltage VREF. The source of the MOS transistor P1 is connected to the current source Ib. The current source Ib is connected to the power supply VDD. The gate of the MOS transistor P2 is connected to the drain of the MOS transistor P5. The source of the MOS transistor P2 is connected to the current source Ib. The drain of the MOS transistor P1 is connected to the drain and gate of the MOS transistor Q4 and is also connected to the drain of the MOS transistor Q9. The drain of the MOS transistor P2 is connected to the drain of the MOS transistor Q5. The gate of the MOS transistor Q5 is connected to the gate of the MOS transistor Q4. The sources of the MOS transistor Q5, the MOS transistor Q9, and the MOS transistor Q4 are grounded;

[0011] The gate of MOS transistor Q8 is connected to the gate of MOS transistor Q9. The drain of MOS transistor Q8 is connected to one end of resistor R1 and the drain of MOS transistor Q5. The other end of resistor R1 is connected to one end of capacitor C1. The other end of capacitor C1 is connected to the drain of MOS transistor Q3. The gate of MOS transistor Q3 is connected to the drain of MOS transistor Q8. The source of MOS transistor Q3 is grounded. The drain of MOS transistor Q3 is connected to the drain of MOS transistor P3. The gate of MOS transistor Q3 is connected to the drain of MOS transistor Q5;

[0012] The gate of MOS transistor P3 is powered by the bias voltage Vb provided by an external circuit. The source of MOS transistor P3 is connected to power supply VDD. The drain of MOS transistor P3 is connected to the gate of MOS transistor P5. The source of MOS transistor P5 is connected to power supply VDD; The drain of MOS transistor P5 is connected to four series-connected voltage regulating resistors RV1, voltage regulating resistor RV2, resistor R3, and voltage regulating resistor RV4. The other end of voltage regulating resistor RV4 is grounded. The drain of MOS transistor P5 is the node voltage VX.

[0013] Further, the resistor R1 and capacitor C1 are used to stabilize the circuit, and the current source Ib provides the operational amplifier bias current; MOS transistor P5 serves as a current-voltage conversion transistor, and its gate is connected to the output terminal of the clamping operational amplifier; The clamping operational amplifier correlates the node voltage VX with the reference voltage VREF and dynamically regulates the gate voltage of MOS transistor P5 through a feedback loop; MOS transistor P6, MOS transistor Q6, and MOS transistor Q7 form a current mirror circuit for replicating the gate voltage of MOS transistor P5, thereby generating a reference current.

[0014] Further, the reference current is injected into the RC low-pass circuit to generate an undershoot voltage.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: The structure of the circuit is simple, facilitating transplantation. The undershoot voltage has high precision, and the circuit has low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is the schematic diagram of the circuit structure provided by the embodiment of the present invention;

[0017] Figure 2 is Figure 1 the waveform schematic diagram of the undershoot voltage generation circuit shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0019] In view of the fact that in the prior art, the power amplifier itself has a certain temperature coefficient, which will affect its gain and power linearity, it is easier to solve this problem in the analog LDO used for power supply than in the power amplifier.

[0020] The present invention provides an undershoot voltage generating circuit. After the undershoot voltage generating circuit is connected to a main circuit, when the main circuit is started, an undershoot voltage that can last for a period of time is introduced into the output voltage. After the startup is completed, the undershoot voltage generating circuit will be closed and the output voltage will return to a normal value.

[0021] Please refer to Figure 1 The embodiment of the present invention provides an undershoot voltage generating circuit. The undershoot voltage generating circuit includes an RC low-pass circuit and an enable control circuit.

[0022] Resistors RT1, RT2, RT3 and RT4 are connected in series in sequence and connected to one end of capacitor C2 to form an RC low-pass circuit. The other end of capacitor C2 is connected to the ground GND. A voltage output terminal VOUT is between resistor RT4 and capacitor C2. The other end of resistor RT1 is connected to a reference voltage VREF.

[0023] MOS transistor P7, MOS transistor P8, MOS transistor P4, MOS transistor Q8, MOS transistor Q9, MOS transistor Q10 and MOS transistor Q11 constitute an enable control circuit, wherein the gate of MOS transistor Q10 is connected to the gate of MOS transistor P7 and to the control signal EN. Figure 1 The two nodes a in the diagram represent connection. The drain of the MOS transistor Q10 is connected to the drain of the MOS transistor P7 and to the gate of the MOS transistor P4. The source of the MOS transistor Q10 is connected to the ground line GND. The sources of the MOS transistors P7 and P4 are connected to the power supply VDD. The drain of the MOS transistor P4 is connected to the gate of the MOS transistor P5 for controlling the on and off of the MOS transistor P5. The drain of the MOS transistor P4 is connected to the gate of the MOS transistor P6. The source of the MOS transistor P6 is connected to the power supply VDD. The drain of the MOS transistor P6 is connected to the drain and gate of the MOS transistor Q7. The gate of the MOS transistor Q7 is connected to the gate of the MOS transistor Q6. The source of the MOS transistor Q6 is grounded. The drain of the MOS transistor Q6 is connected to the reference voltage VREF. The source of the MOS transistor Q7 is grounded.

[0024] The drain of MOS transistor Q11 is connected to the drain of MOS transistor P8, Figure 1 which is marked as node b in Figure 1 and connected to the gates of MOS transistor Q8 and MOS transistor Q9 to control the on / off states of MOS transistor Q8 and MOS transistor Q9. The source of MOS transistor Q11 is grounded to GND, and the source of MOS transistor P8 is connected to power supply VDD; the gates of MOS transistor P8 and MOS transistor Q11 are connected and then connected to the gate of MOS transistor P4.

[0025] MOS transistors P1, P2, P3, Q3, Q4, Q5, current source Ib, resistor R1 and capacitor C1 form a clamping operational amplifier; among them, the gate of MOS transistor P1 is connected to reference voltage VREF, the source of MOS transistor P1 is connected to current source Ib, and current source Ib is connected to power supply VDD; the gate of MOS transistor P2 is connected to the drain of MOS transistor P5, that is, node voltage VX; the source of MOS transistor P2 is connected to current source Ib, and current source Ib is connected to power supply VDD; the drain of MOS transistor P1 is connected to the drain and gate of MOS transistor Q4, and at the same time connected to the drain of MOS transistor Q9; the drain of MOS transistor P2 is connected to the drain of MOS transistor Q5, the gate of MOS transistor Q5 is connected to the gate of MOS transistor Q4, and the source of MOS transistor Q5, the source of MOS transistor Q9 and the source of MOS transistor Q4 are grounded;

[0026] The gate of MOS transistor Q8 is connected to the gate of MOS transistor Q9, the drain of MOS transistor Q8 is connected to one end of resistor R1 and the drain of MOS transistor Q5, the other end of resistor R1 is connected to one end of capacitor C1, the other end of capacitor C1 is connected to the drain of MOS transistor Q3, the gate of MOS transistor Q3 is connected to the drain of MOS transistor Q8, the source of MOS transistor Q3 is grounded, and the drain of MOS transistor Q3 is connected to the drain of MOS transistor P3. The gate of MOS transistor Q3 is connected to the drain of MOS transistor Q5.

[0027] The gate of MOS transistor P3 is powered by bias voltage Vb provided by an external circuit, the source of MOS transistor P3 is connected to power supply VDD, the drain of MOS transistor P3 is connected to the gate of MOS transistor P5, the source of MOS transistor P5 is connected to power supply VDD, the drain of MOS transistor P5 is connected to four series-connected voltage-regulating resistors RV1, voltage-regulating resistor RV2, voltage-regulating resistor R3 and voltage-regulating resistor RV4, the other end of voltage-regulating resistor RV4 is grounded, and the drain of MOS transistor P5 is node voltage VX.

[0028] Among them, resistor R1 and capacitor C1 are used to stabilize the circuit, and current source Ib provides the bias current for the operational amplifier. MOS transistor P5 serves as a current-voltage conversion transistor, with its drain connected to four series-connected voltage-regulating resistors RV1, voltage-regulating resistor RV2, voltage-regulating resistor R3, and voltage-regulating resistor RV4, and its gate connected to the output terminal of the clamping operational amplifier. The clamping operational amplifier correlates the node voltage VX with the reference voltage VREF and dynamically regulates the gate voltage of MOS transistor P5 through a feedback loop. MOS transistors P6, Q6, and Q7 form a current mirror circuit, which is used to copy the gate voltage of MOS transistor P5, thereby generating a reference current. The reference current is injected into the RC low-pass circuit, and finally an undershoot voltage is generated. In addition, MOS transistors P7, P8, P4, and Q8-Q11 form an enable control circuit. The timing of the control signal EN is set to be the same as the enable signal of the main circuit, which is used to correlate the main circuit with the undershoot voltage generation circuit. Thus, when the main circuit starts, the undershoot voltage generation circuit is turned on accordingly, causing the output voltage of the main circuit to have an undershoot. After the main circuit completes startup, the undershoot voltage generation circuit is turned off.

[0029] Figure 2 is a waveform schematic diagram of the undershoot voltage generation circuit. Among them, V REF is the transient reference voltage generated after the reference current is injected into the resistor. V OUT is the output voltage of the undershoot voltage generation circuit. LDO_VOUT is the LDO output voltage applied with the undershoot voltage generation circuit.

[0030] Please refer to Figure 2 , in the initial stage of startup, VOUT experiences a slow rise. Since the analog LDO output voltage follows the trend of VOUT, an undershoot voltage that can last for a period of time is introduced in the analog LDO output voltage.

[0031] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An undershoot voltage generating circuit, characterized in that: The undershoot voltage generating circuit comprises: Resistors RT1, RT2, RT3 and RT4 are connected in series in sequence and connected to one end of capacitor C2 to form an RC low-pass circuit. The other end of capacitor C2 is grounded. A voltage output end VOUT is between resistor RT4 and capacitor C2. The other end of resistor RT1 is connected to a reference voltage VREF. MOS transistor P7, MOS transistor P8, MOS transistor P4 and MOS transistor Q8, MOS transistor Q9, MOS transistor Q10 and MOS transistor Q11 constitute an enable control circuit, wherein the gate of MOS transistor Q10 is connected to the gate of MOS transistor P7 and to the control signal EN, the drain of MOS transistor Q10 is connected to the drain of MOS transistor P7 and to the gate of MOS transistor P4, the source of MOS transistor Q10 is grounded, the sources of MOS transistor P7 and MOS transistor P4 are connected to the power supply VDD, the drain of MOS transistor P4 is connected to the gate of MOS transistor P5, and is used to control the on and off of MOS transistor P5; the drain of MOS transistor P4 is connected to the gate of MOS transistor P6, the source of MOS transistor P6 is connected to the power supply VDD, the drain of MOS transistor P6 is connected to the drain and gate of MOS transistor Q7, the gate of MOS transistor Q7 is connected to the gate of MOS transistor Q6, the source of MOS transistor Q6 is grounded, the drain of MOS transistor Q6 is connected to the reference voltage VREF, and the source of MOS transistor Q7 is grounded; The drain of the MOS transistor Q11 is connected to the drain of the MOS transistor P8, and is connected to the gates of the MOS transistor Q8 and the MOS transistor Q9, and is used to control the on and off of the MOS transistor Q8 and the MOS transistor Q9. The source of the MOS transistor Q11 is grounded, and the source of the MOS transistor P8 is connected to the power supply VDD. The gates of the MOS transistor P8 and the MOS transistor Q11 are connected and then connected to the gate of the MOS transistor P4. MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor Q3, MOS transistor Q4, MOS transistor Q5, current source Ib, resistor R1 and capacitor C1 form a clamping operational amplifier; wherein, the gate of MOS transistor P1 is connected to reference voltage VREF, the source of MOS transistor P1 is connected to current source Ib, and current source Ib is connected to power supply VDD; the gate of MOS transistor P2 is connected to the drain of MOS transistor P5; the source of MOS transistor P2 is connected to current source Ib; the drain of MOS transistor P1 is connected to the drain and gate of MOS transistor Q4, and is also connected to the drain of MOS transistor Q9; the drain of MOS transistor P2 is connected to the drain of MOS transistor Q5, the gate of MOS transistor Q5 is connected to the gate of MOS transistor Q4, and the source of MOS transistor Q5, the source of MOS transistor Q9, and the source of MOS transistor Q4 are grounded; The gate of the MOS transistor Q8 is connected to the gate of the MOS transistor Q9, the drain of the MOS transistor Q8 is connected to one end of the resistor R1 and the drain of the MOS transistor Q5, the other end of the resistor R1 is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to the drain of the MOS transistor Q3, the gate of the MOS transistor Q3 is connected to the drain of the MOS transistor Q8, the source of the MOS transistor Q3 is grounded, the drain of the MOS transistor Q3 is connected to the drain of the MOS transistor P3, and the gate of the MOS transistor Q3 is connected to the drain of the MOS transistor Q5; The gate of the MOS transistor P3 is powered by a bias voltage Vb provided by an external circuit, the source of the MOS transistor P3 is connected to the power supply VDD, the drain of the MOS transistor P3 is connected to the gate of the MOS transistor P5, and the source of the MOS transistor P5 is connected to the power supply VDD; the drain of the MOS transistor P5 is connected to four voltage control resistors RV1, RV2, R3 and RV4 connected in series, the other end of the voltage control resistor RV4 is grounded, and the drain of the MOS transistor P5 is the node voltage VX.

2. The undershoot voltage generating circuit according to claim 1, characterized in that: The resistor R1 and the capacitor C1 are used to stabilize the circuit, and the current source Ib provides an operational amplifier bias current; the MOS transistor P5 is used as a current-voltage conversion tube, and the gate is connected to the output end of the clamping operational amplifier; the clamping operational amplifier associates the node voltage VX with the reference voltage VREF, and dynamically adjusts the gate voltage of the MOS transistor P5 through a feedback loop; the MOS transistor P6 and the MOS transistor Q6 and the MOS transistor Q7 form a current mirror circuit, which is used to copy the gate voltage of the MOS transistor P5, and then generate a reference current.

3. The undershoot voltage generating circuit according to claim 2, characterized in that: The reference current is injected into the RC low-pass circuit to generate an undershoot voltage.

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