Direct memory access method and system

Abstract

A method and apparatus are described. The method includes receiving a data packet and address data, the data packet including data to be written to the memory of the computing system, the address data including addresses in a set of addresses of a first address space of the computing system, identifying a subset of the set of addresses identified by a subset of addresses in a second address space associated with the memory of the computing system, and writing the data packet to the memory of the computing system. Determining an address from another subset of addresses in the second address space, writing the data to a region of the memory associated with the determined address, and updating an address translation table on the computing system based on the determined address.

Description

[0001] This application is a divisional application. The application number of the original application is 202080042864.3, and the original application date is May 28, 2020. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to a system and method for writing data to a memory of a computing system. In particular, the present disclosure relates to a system and method for performing direct memory access operations on a memory of a computing system. Background Art

[0003] Direct memory access (DMA) enables a device or subsystem in a computing system to read data directly from and write data to the physical memory of the computing system. DMA can be implemented in a computing system through devices such as a graphics processing unit or a sound card, or other processor cores in a multi-core system. DMA frees up computing resources in the computing system. In particular, DMA operations can be performed simultaneously while a program is running on the main processor.

[0004] Remote direct memory access (RDMA) enables a computing system to read data from or write data to the memory of another computing system over a network. RDMA can improve network performance, resulting in higher throughput and lower network latency on systems that do not implement RDMA. Summary of the invention

[0005] The present disclosure is directed to a method for a computing system, such as may be used to perform direct memory access operations on a memory of the computing system.

[0006] The aforementioned and other objects are achieved by the features of the independent claims. Further implementations are evident from the dependent claims, the description and the drawings.

[0007] In a first aspect, a method is provided. The method includes receiving a data packet and address data, the data packet including data to be written to the memory of a computing system, the address data including an address in a set of addresses in a first address space of the computing system. The method includes identifying a subset of the set of addresses identified by a subset of addresses in a second address space associated with the memory of the computing system; determining an address from another subset of addresses in the second address space; writing the data to a region of the memory associated with the determined address; and updating an address translation table on the computing system based on the determined address.

[0008] The method according to the first aspect writes data to the memory of the computing system, for example, when the destination address of the data packet is not mapped and has not yet been assigned an address in the second address space. The method improves latency and reduces overhead of performing direct memory access operations in the computing system.

[0009] According to a second aspect, there is provided an apparatus for a computing system. The apparatus is arranged to identify an address in a set of addresses in a first address space of a computing system from a data packet and address data, the data packet comprising data to be written to a memory of the computing system, the address data comprising the address; identify a subset of the set of addresses identified by a subset of addresses in a second address space associated with the memory of the computing system. The apparatus is arranged to determine an address from another subset of addresses in the second address space; write the data to a region of the memory associated with the determined address; and send a message to the computing system to update an address translation table on the computing system based on the determined address.

[0010] In one implementation, identifying the subset of addresses identified by the subset of addresses in the second address includes accessing the address translation table; and identifying the subset based on the address translation table.

[0011] In another implementation, the second address space is a physical address space of a physical memory of the computing system.

[0012] In another implementation, the first address space is a virtual address space.

[0013] In another implementation, determining an address from another subset of addresses in the second address space includes storing address data in one or more addresses of the another subset; and determining an address from the another subset of the stored address data.

[0014] The method described in the present implementation provides a method for selecting an address from a storage address pool to map an unmapped address in a first address space to the address.

[0015] In another implementation, determining an address from another subset of addresses in the second address space includes sending a query including a request to the computing system to identify an address from the another subset; and receiving a response including address data for the address from the another subset of the computing system.

[0016] The method described in accordance with the present implementation provides an alternative method for determining an address from an available address pool to map an unmapped address into the address.

[0017] In another implementation, the method includes removing certain addresses from the other subset of the second address space.

[0018] The method according to the present implementation provides a method to remove the determined address from the further subset of the second address space and thus no longer be available for mapping an unmapped address thereto.

[0019] In another implementation, the method includes determining a number of addresses of the second address space in the other subset; and replenishing the other subset when the number of addresses is below a threshold number.

[0020] The method described in the present implementation replenishes the address pool to ensure that there are enough addresses in the pool to withstand a large number of requests including unmapped addresses in the first address space.

[0021] In another implementation, supplementing the another subset includes determining the availability of addresses in the second address space based on a criterion; and including the addresses in the another subset based on the determination.

[0022] In another implementation, the criteria include criteria for use of the address by the computing system.

[0023] The method according to the present implementation provides a criterion based on the usage of memory addresses for determining the availability of addresses to replenish the address pool. The present implementation of the method ensures that addresses that are not fully used by the computing system are recycled and included in the pool for mapping unmapped addresses.

[0024] In another implementation, the method includes storing address data for the other subset.

[0025] In another implementation, the address of the data packet is a destination address of a direct memory access (DMA) request.

[0026] In another implementation, the address of the data packet is a destination address of a direct memory access (DMA) request.

[0027] In another implementation, the method includes accessing at least one other address translation table, each table including an entry for each address in the set, and updating the entry of the at least one other address translation table corresponding to the address of the data packet to use the determined address to identify the address of the data packet.

[0028] In another implementation, the address translation table is stored in the computing system.

[0029] In another implementation, the address translation table is stored in a device that performs a direct memory access or remote direct memory access request on the computing system.

[0030] The above aspects and other aspects of the present application will be apparent from the embodiments described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0032] Figure 1 A computing system according to an example is shown.

[0033] Figure 2A is a schematic diagram of a remote direct memory access request according to an example.

[0034] Figure 2B is a schematic diagram of a remote direct memory access request according to an example.

[0035] Figure 3 A flow chart of a method for a computing system according to an example is shown. DETAILED DESCRIPTION

[0036] The following will describe the exemplary embodiments in sufficient detail to enable those skilled in the art to embody and implement the systems and processes described herein. It should be understood that the embodiments may be embodied in many different forms and should not be construed to be limited to the examples described herein.

[0037] Therefore, the embodiments may be modified in various ways and in various alternative forms, specific embodiments of which are shown in the drawings and described in detail below in an exemplary form. It is not intended to limit the specific forms disclosed herein. On the contrary, all modifications, equivalents and alternative forms falling within the scope of the appended claims should be included. In the drawings and appropriate detailed descriptions, the elements of the exemplary embodiments are always represented by the same reference numerals.

[0038] The terms used herein to describe the embodiments are not intended to limit the scope. The articles "a", "an" and "the" are singular and therefore have a single reference, but the use of the singular in this article should not exclude the presence of multiple references. In other words, unless the context clearly indicates otherwise, elements represented in the singular may be numbered as one or more. It should be further understood that when used in this specification, the terms "comprises", "includes" and / or "comprises" specify the presence of the described features, items, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, items, steps, operations, elements, parts and / or combinations thereof.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used in this article should be interpreted according to the conventions of the art. It should be further understood that, unless explicitly defined herein, commonly used terms should also be interpreted as customary terms in the relevant field, rather than idealized or overly formalized meanings.

[0040] Figure 1 1 is a block diagram of an apparatus 100. The apparatus 100 includes a computing system 110. The apparatus 100 may be used with the methods and systems described herein. The computing system 110 includes a central processing unit (CPU) 120. The CPU 120 includes logic for reading or writing data to memory and executing processes on the computing system 110. The CPU 120 is connected to other components of the computing system 110 via a bus 130. The bus 130 enables data transfer between interconnected components of the computing system 110.

[0041] The computing system 110 includes a storage device 140. The storage device 140 may include any type of non-transitory storage device for storing data, programs, and other information and making them accessible via the bus 130. The storage device 140 may include at least one such as a solid state drive, a hard disk drive, a magnetic disk drive, or an optical disk drive. The storage device 140 is connected to other components of the computing system 110 via the bus 130.

[0042] The computing system 110 includes physical memory 150. The memory 150 may include any type of non-temporary system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), or a combination thereof. The memory 150 includes a plurality of memory cells. Each memory cell has an address for identifying the location of the memory cell in the memory 150. The discrete address range of the memory 150 is called a physical address space.

[0043] Typically, only system software such as BIOS and the operating system in the boot state directly access physical memory 150. For other processes, the computing system 110 maintains a virtual address space. The virtual address space is similar to the physical address space, but the addresses do not correspond to locations in physical memory 150. The virtual address space provides a continuous address space appearance to the process. The mapping of virtual addresses to physical addresses is stored in a data structure called a page table. Each entry in the page table can be called a page table entry. A page, memory page, or virtual page is a fixed-length continuous block of virtual memory, represented by a single page table entry. A frame is a fixed-length continuous block of a page mapped to physical memory.

[0044] In addition to providing the appearance of a continuous address space, virtual addressing can also create a virtual partition of memory 150 in two non-contiguous areas. The first area, called kernel space, is reserved for protected processes, such as the BIOS and operating system. The second area, called user space, is allocated to other processes. The computing system 110 maintains the separation of kernel space and user space by preventing processes executing in user space from addressing kernel space.

[0045] Figure 1 The CPU 120 is shown including a memory management unit (MMU) 160. The MMU 160 performs address translation to map virtual addresses of pages addressed by a process to physical addresses of corresponding frames in the memory 150. The MMU 160 also performs virtual memory management for processes running on the computing system 110. When pages are moved between different physical memory locations, the MMU 160 manages the corresponding page table entries, updating the page table as necessary.

[0046] Data stored at virtual addresses is moved between physical memory 150 and other memory, such as storage device 140, using a virtual memory management process called paging. When a process requests a page in the virtual address space, MMU 160 determines whether the requested page is available in memory 150 by performing an address translation. When the page is available, a physical address is returned, and a calculation is performed on CPU 120. When the page is not available in memory 150, MMU 160 returns a page fault. Software running on the operating system (called a page manager) accesses storage device 140, restores the frame corresponding to the virtual address of the page that caused the page fault, and updates the page table in MMU 160 with the new mapping between the virtual address and the physical address, where the page has been restored to memory 150.

[0047] Paging allows a computing system to allocate a continuous virtual address range to a process that exceeds the available space in physical memory 150 by extending the virtual address space into a secondary storage device such as storage device 140. However, when all frames are used in physical memory 150, the operating system must select a frame to reuse as a page required by the process. The paging manager can use a page replacement algorithm such as Least Recently Used (LRU) or First In First Out (FIFO) to determine which memory location in memory 150 to release the requested page. The paging manager can page out or "swap" pages from memory 150 to storage device 140 according to the page replacement algorithm. The paging manager updates the page table so that the page requested by the process points to the released location in memory. The area of ​​storage device 140 reserved for this purpose is called swap space. In some cases, a page can be locked or "pinned" in memory 150 to prevent the page from being swapped out to storage device 140.

[0048] The computing system 110 also includes a direct memory access (DMA) device 170. The DMA device 170 may be a disk drive, a graphics card, a sound card, or other hardware device. In other examples, the DMA device 170 may be another processing core similar to the CPU 120. The DMA device 170 is connected to the bus 130 and may interact with other components of the computing system 110 through the bus 130. The DMA device 170 may perform DMA requests to the memory 150. A DMA request from the device 170 to the memory 150 is an operation such as a data write operation that is independent of the CPU 120 and is performed directly to a location in the memory 150. Without DMA, when the CPU 120 uses programmed input / output, the CPU 120 will be completely occupied during the entire process of the read or write operation and cannot perform other work. DMA allows the CPU 120 to perform other operations while processing DMA requests from the device 170. DMA is useful for performing large data transfers such as between the device 170 and the memory 150. Once the DMA operation to memory 150 is completed, device 170 sends an interrupt request back to CPU 120 so that CPU 120 can process the data from device 170 that was written to memory 150 after the DMA operation.

[0049] Similar to processes running on computing system 110, DMA requests from DMA device 170 may specify addresses in a virtual address space. In some examples, DMA device 170 is arranged to perform address translation of addresses specified in DMA requests. For example, in some cases, DMA device 170 and / or computing system 110 include an input-output memory management unit (IOMMU) ( Figure 1 1 ), the input-output memory management unit performs address translation for I / O devices in the computing system 110 in a manner similar to the manner in which the MMU 160 performs address translation for the CPU 120. In other examples, the DMA device 170 uses a remote procedure call to the operating system to track or query page table entries.

[0050] The computing system 110 further includes a network interface controller (NIC) 180 that connects the computing system 110 to a network 190. The NIC 180 may include a wired or wireless link to the network 190, such as Ethernet or a wireless transmitter and receiver. In some examples, the network 190 may be a local area network (LAN). In other examples, the network 190 is a wide area network. The network 190 may enable communication between the computing system 110 and remote devices, such as other computing systems, network servers, and remote storage and data processing devices.

[0051] exist Figure 1 1, computing system 110 communicates with remote computing device 195 across network 190. According to an example, NIC 180 supports remote direct memory access (RDMA) requests from remote device 195 to memory 150. Similar to DMA requests from DMA device 170, RDMA requests from remote device 195 are requests to perform operations directly on locations in memory 150, bypassing the operating system of computing system 110. RDMA enables high throughput, low latency networking between computing system 110 and remote device 195 by using zero copy of data to memory 150 without requiring CPU 120 to copy data to other memory locations.

[0052] Similar to processes running on computing system 110 and DMA requests from DMA device 170, RDMA requests received at NIC 180 may include addresses of a virtual address space. In some examples, NIC 180 is arranged to perform address translation of addresses specified in the RDMA request. In other examples, NIC 180 uses, for example, an onboard IOMMU to track or query page table entries. Once the physical address is determined, NIC 180 can write the data in the RDMA request directly to memory 150.

[0053] The methods and systems described herein may be used to perform DMA (or RDMA) operations because a DMA request sent to an unmapped virtual address does not have a corresponding physical address in the memory 150 .

[0054] One approach to addressing the problem of (R)DMA requests to unmapped virtual addresses is to pin a subset of virtual addresses that can be used by the DMA device 170 or NIC 180 to physical addresses in the memory 150. This ensures that (R)DMA operations never encounter unmapped memory. However, there is a significant cost in that the pinned memory is not available for use by other processes or devices in the computing system 120. In addition, the memory consumption in this case can hurt performance because other memory must be swapped from the memory 150 to the storage device 140 more frequently to accommodate the required space.

[0055] Another approach to using pinning to permanently allocate memory for DMA operations is to provide temporary pinned buffers in memory 150 for the purpose of DMA operations. Each buffer can be reused once the last DMA request is completed. For example, input data for an RDMA request from device 195 can first be placed in a pinned buffer in memory 150 and then copied to another buffer in the virtual address space subspace addressed by the process. The original pinned buffer can then be reused in further DMA requests.

[0056] Unfortunately, this approach also has many disadvantages. First, the latency is significantly reduced due to the extra copy operation of the fixed buffer. However, this operation is necessary, otherwise the buffer will not be available for other DMA requests. In addition, a dedicated fixed buffer pool needs to be allocated, which results in management overhead in the computing system 110, similar to the fixed approach described previously. Other similar approaches also have latency penalties or cause large memory usage due to the excessive number of fixed areas in the memory 150 area.

[0057] The method and system described herein writes data from a (R)DMA request into a buffer and then remaps the virtual address to point to the buffer address. The method does not require stalling or further copying of data into the buffer.

[0058] Figure 2A is a simplified diagram of an example 200 of an RDMA request according to the methods described herein. Figure 2A The example 200 shown is composed of Figure 1 NIC 180 is shown processing RDMA requests. Figure 1 DMA requests for the DMA device 170 shown are processed in a similar manner, and Figure 2A The examples shown are not intended to limit other methods and examples described herein to RDMA requests.

[0059] In the example 200 shown in FIG2A , Figure 1 NIC 180 is shown receiving RDMA request 210. RDMA request 210 may be received by, for example, Figure 1 Received by remote device 195 as shown. RDMA request 210 includes destination (virtual) address 211, such as an address in the virtual address space of a target process running on computing system 110, and data 212 to be written to memory 150 of computing system 110. In some cases, data 212 may be divided into one or more packets, where the virtual address of each packet is determined by an offset from the virtual address of the first packet, which is represented by virtual address 211 of RDMA request 210. When NIC 180 receives RDMA request 210, NIC 180 performs address translation (by itself, or using, for example, an onboard IOMMU as described above) to identify the address in memory 150 for destination virtual address 211.

[0060] An example of translating the destination address 211 is shown in box 220. Three examples are shown herein. When the virtual address 211 of the RDMA request has been mapped to the physical memory 150, the NIC 180 only needs to perform the address translation and write the data 212 to the corresponding location in the memory 150. For example, in Figure 2A, if virtual address 211 is mapped to physical address 221 or 223, NIC 180 writes data 212 to location 221 or 223 in memory 150, respectively. If NIC 180 determines that the page of destination address 211 is not mapped, NIC 180 determines address 222 to write data 212 from an available address pool corresponding to physical memory locations in memory 150, and writes the data to buffer 230 located at physical address 222 in memory 150.

[0061] Figure 2B Shown with Figure 2A The same example 200 is shown. Figure 2B , a virtual address space 240 and a process 241 for addressing an address range in the virtual address space 240 are shown. Once the NIC 180 determines the write Figure 2A NIC 180 notifies CPU 120 to update the address translation table of process 241 based on the address 222 of data 212 of RDMA request 210 in the buffer 230. In some examples, CPU 120 (re)maps the virtual address in address translation table 250 of process 241 to point to physical address 222 of buffer 230. As an illustrative example, Figure 2B The remapping of a virtual address that previously pointed to a location in the swap space of storage device 140 to address 222 is shown in FIG.

[0062] Figure 3 is a block diagram of a method 300 shown according to an example. Figure 3 The method 300 shown can be used in conjunction with other methods and systems described herein. In particular, the method 300 can be used in conjunction with Figure 1 The illustrated computing system 110 is implemented to handle DMA and RDMA requests to the memory 150 .

[0063] At block 310, a data packet includes data to be written to a memory of a computing system, and address data is used to receive an address from a set of addresses in a first address space of the computing system. According to an example, the data packet may be a data packet for a DMA request or an RDMA request. The computing system and the memory may be Figure 1 The computing system 110 and the memory 150 are shown. According to an example, the first address space is a virtual address space of the computing system.

[0064] At block 320, a subset of the set of addresses is identified by a subset of addresses in a second address space associated with a memory of the computing system. The second address space may be a physical address space associated with the memory of the computing system. According to an example, the subset may be identified from an address translation table that identifies a subset of the set of addresses from the first address space by a subset of addresses in the second address space. The address translation table includes an entry for each address in the set. In other examples, identification of the subset may be determined by accessing an output of a function that maps addresses in the first address space to addresses in the second address space.

[0065] At block 330, an address from another subset of addresses in the second address space is determined. According to an example, determining an address in another subset of the second address space includes accessing stored address data to obtain at least one address in another subset, and determining an address in another subset from the stored address data. For example, when method 300 is Figure 1 When implemented on the computing system 110 shown in , the NIC 180 can store a pool of addresses that are used as data for writing RDMA requests when the requests contain unmapped virtual addresses.

[0066] At block 340, data is written to a memory region associated with the determined address in the second address space. At block 350, an entry of an address translation table is updated based on the determined address. For example, when method 300 is performed at Figure 1 When implemented on the device shown, NIC 180 notifies CPU 120 to update the address translation table. In some examples, CPU 120 (re)maps the virtual address in the address translation table to point to the buffer address in the second (physical) address space.

[0067] According to an example, determining an address from another subset in the second address space may include sending a request to a computing system to identify an address from another subset, receiving a response from the computing system, the response including address data of data from another subset of addresses. For example, NIC 180 may determine the buffer address of the IOMMU without storing the address locally.

[0068] In some examples, method 300 also includes removing determined addresses of another subset of addresses from the second address space. Method 300 may also include determining the number of addresses in the second address space in another subset, and supplementing the other subset when the number of addresses is below a threshold number. Supplementing the other subset may include determining the availability of addresses in the second address space based on criteria, and including the addresses in the other subset based on the determination. According to an example, the criteria may include criteria for the computing system to use the addresses. These examples enable the computing system to maintain a supply of buffers and write data in DMA requests to the system on demand in a non-pausing manner without copying the data to other buffers.

[0069] The method and example described herein provide resource-friendly, efficient (R)DMA operations. In particular, the method provides a control flow for processing (R)DMA operations, with the destination being an unmapped memory location. In addition, the method and system described herein utilize a removable buffer that serves as a clear destination for (R)DMA operations. (R)DMA operations that have been mapped to memory are not affected.

[0070] The methods described herein can be implemented on any device with (R)DMA capabilities and are not limited to certain device types. The methods and systems can also be used with virtual machines as well as regular process pages. The performance of a system implementing the methods described herein approaches that of a system that pins the entire address space into memory while also allowing for memory oversubscription and paging.

[0071] It should be understood that one or more steps of the embodiment method provided herein can be performed by corresponding units or modules. Each unit or module can be hardware, software, or a combination thereof. For example, one or more units or modules in these units or modules can be integrated circuits, for example, field programmable gate arrays (FPGA) or application-specific integrated circuits (ASIC).

[0072] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

[0073] The present application may be embodied in other specific devices and / or methods. The described embodiments should be considered to be illustrative and not restrictive in all respects. In particular, the scope of the present application is specified by the attached claims rather than the description and drawings herein. Any changes within the meaning and equivalent range of the claims should be included within their scope.

Claims

1. A memory access method, characterized in that: include: receiving a data packet and address data, the data packet comprising data to be written into a memory of a computing system, the address data comprising an address in a set of addresses in a first address space of the computing system; identifying a subset of the set of addresses based on a subset of addresses in a second address space associated with a memory of the computing system; determining an address from another subset of addresses in the second address space; writing the data into a region of the memory associated with the determined address; as well as An address translation table on the computing system is updated based on the determined address.

2. The method according to claim 1, characterized in that: Identifying the subset of addresses identified by the subset of addresses in the second address comprises: accessing the address translation table; and The subset is identified based on the address translation table.

3. The method according to claim 1, characterized in that The second address space is a physical address space of a physical memory of the computing system.

4. The method according to claim 1, characterized in that: The first address space is a virtual address space.

5. The method according to claim 1, characterized in that Determining a subset from another subset of addresses in the second address space comprises: accessing stored address data for one or more addresses in the other subset; and An address from the another subset of the stored address data is determined.

6. The method according to claim 1, characterized in that Determining an address from another subset of addresses in the second address space includes: sending a request to the computing system to identify an address from the other subset; and A response including address data is received for an address in another subset of the computing systems.

7. The method according to claim 1, characterized in that This includes removing a certain address from another subset of addresses in the second address space.

8. The method according to claim 1, characterized in that include: determining the number of addresses in the second address space in the another subset; as well as When the number of addresses is lower than a threshold number, the another subset is supplemented.

9. The method according to claim 8, characterized in that Supplementing the another subset includes: determining the availability of addresses in the second address space based on a criterion; and The address is included in the another subset based on the determination.

10. The method according to claim 9, characterized in that The criteria include criteria for use of the address by the computing system.

11. The method according to claim 1, characterized in that: The address of the data packet is a destination address of a direct memory access (DMA) request.

12. The method according to claim 1, characterized in that The address of the data packet is a destination address of a remote direct memory access (RDMA) request.

13. The method according to claim 1, characterized in that include: accessing one or more further address translation tables, each table comprising an entry for each address in the set; as well as The entries of the one or more other address translation tables corresponding to the address of the data packet are updated to identify the address of the data packet by the determined address.

14. The method according to claim 1, characterized in that The address translation table is stored in the computing system.

15. The method according to claim 1, characterized in that The address translation table is stored in a device that performs a direct memory access or remote direct memory access request on the computing system.

16. An apparatus for a computing system, characterized in that: Arranged as: identifying an address from a set of addresses in a first address space of a computing system from a data packet and address data, the data packet including data to be written to a memory of the computing system, the address data including the address; a subset of the set of addresses identified based on a subset of addresses of a second address space associated with a memory of the computing system; determining an address from another subset of addresses in the second address space; writing the data into a region of the memory associated with the determined address; as well as A message is sent to the computing system to update an address translation table on the computing system based on the determined address.

17. The device according to claim 16, characterized in that In order to identify the subset of addresses identified by the subset of addresses in the second address, the apparatus is arranged to: accessing the address translation table; and The subset is identified based on the address translation table.

18. The device according to claim 16, characterized in that The second address space is a physical address space of a physical memory of the computing system.

19. The device according to claim 16, characterized in that The first address space is a virtual address space of the computing system.

20. The device according to claim 16, characterized in that To determine an address from another subset of addresses in the second address space, the apparatus is arranged to: storing the address data in one or more addresses of the another subset; as well as An address from the another subset of the stored address data is determined.

21. The device according to claim 16, characterized in that To determine an address from another subset of addresses in the second address space, the apparatus is arranged to: sending a query including a request to the computing system to identify an address from the other subset; and A response including address data is received for an address from another subset of the computing systems.

22. The device according to claim 16, characterized in that The apparatus is arranged to send a message comprising a request to the computing system to remove the determined address from the further subset of the second address space.

23. The device according to claim 16, characterized in that The device is arranged to: determining the number of addresses in the second address space in the another subset; and When the number of addresses is lower than a threshold number, the another subset is updated.

24. The device according to claim 16, characterized in that The device is arranged to: accessing one or more further address translation tables, each table comprising an entry for each address in the set; and The entries of the one or more other address translation tables corresponding to the address of the data packet are updated to identify the address of the data packet by the determined address.

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