Mask pattern optimization method, computer equipment, readable storage medium and program product

Abstract

The invention relates to the field of chip design, in particular to a mask graph optimization method, computer equipment, a readable storage medium and a program product, and provides a neural network model comprising a mask graph generation module and a photoetching simulation module in the mask graph optimization method. The mask pattern generation module outputs a corresponding mask pattern based on an input original design layout, the photoetching simulation module simulates according to the mask pattern to obtain a corresponding simulated photoetching pattern, a loss function is constructed according to the corresponding relation between the simulated photoetching pattern and the original design layout, parameters in the neural network model are adjusted by the loss function, and the mask pattern is obtained. The mask plate graph output by the mask plate graph generation module is iteratively optimized, so that the accuracy of the obtained mask plate graph is improved; and meanwhile, the model can accurately obtain graphic information, so that a relatively good optimization result can be obtained even if a low-resolution original design layout is adopted, and the precision of the mask plate graph output based on the original design layout is ensured.

Description

[Technical field]

[0001] The present invention relates to the field of chip design, and in particular to a mask layout optimization method, computer equipment, readable storage medium and program product. [Background technology]

[0002] Inverse Lithography Technology (ILT) is an advanced lithography technology used in chip design and manufacturing. It aims to improve the resolution and accuracy of the lithography process in order to achieve more complex patterns on the chip. Unlike the traditional method of using regular masks, inverse lithography calculates an optimized mask pattern to better control the propagation and interference of light, thereby more accurately realizing the desired pattern on the silicon wafer.

[0003] ILT is often used to process high-resolution images, especially in modern semiconductor manufacturing, where feature sizes are very small. Therefore, the input image needs to have sufficient resolution to capture subtle features and complex patterns.

[0004] ILT requires high-quality input image data for effective mask optimization and pattern reconstruction by comprehensively considering the propagation characteristics of light.

[0005] In modern semiconductor processes, for high-end designs, whether using inverse lithography or other technologies, the quality and resolution of the input image are usually given priority to ensure that the subsequent lithography process can accurately achieve the design goals. However, a higher-resolution input image will consume a lot of computing resources / computing time for the mask layout generated by inverse lithography, while if a lower-resolution input image is used, the accuracy of the resulting mask layout will be lower. [Summary of the invention]

[0006] In order to solve the problem that the optimization result accuracy of the existing mask layout optimization technology is not high enough, the present invention provides a mask layout optimization method, which includes the following steps:

[0007] Providing a neural network model, the neural network model includes a mask layout generation module and a lithography simulation module, providing an original design layout containing a number of design graphics, inputting the original design layout into the mask layout generation module to output a corresponding mask layout, and the lithography simulation module obtains a corresponding simulated lithography pattern according to the mask layout simulation;

[0008] Providing an assignment map corresponding to the original design layout, and defining the assignment of corresponding pixel grid points based on the area ratio of the design graphics in the original design layout in the corresponding pixel grid points of the assignment map;

[0009] Define the corresponding relationship between the assignment of pixel grid points on the assignment map and the corresponding pixel grid points on the simulated lithography pattern to construct a loss function;

[0010] The parameters in the neural network model are adjusted using the loss function to iteratively optimize the mask layout output by the mask layout generation module; the mask layout corresponding to the simulated lithography pattern obtained after the iteration is completed is output as the optimized mask layout.

[0011] Preferably, defining the correspondence between the values ​​of the pixel grid points on the value map and the corresponding pixel grid points on the simulated lithography pattern includes:

[0012] The original design layout is mapped onto the assignment map. In each pixel grid of the assignment map, when the design pattern in the original design layout occupies more than half of the area of ​​the pixel grid and the center of the pixel grid in the assignment map is located within the mapped design pattern, the pixel grid is assigned a value of 1; when the design pattern occupies less than half of the area of ​​the pixel grid and the center of the pixel grid in the assignment map is located outside the mapped design pattern, the pixel grid is assigned a value of 0; when the pixel grid is assigned a value of 1 or 0, one indicates that the design pattern exists at the pixel grid and the other indicates that the design pattern does not exist at the pixel grid, and a binary map of the design pattern is defined as the assignment map; a loss function is constructed according to the correspondence between the binary map of the design pattern and the corresponding pixel grid on the simulated lithography pattern.

[0013] Preferably, a grayscale threshold is set, and a pixel grid point whose value is 1 and whose grayscale value in the corresponding simulated lithography pattern is less than the grayscale threshold is taken as a first bad pixel;

[0014] The pixel grid point whose value is 0 and whose gray value in the corresponding simulated photolithography pattern is greater than the gray threshold is regarded as the second bad pixel;

[0015] The error between the grayscale value of the first bad pixel and the second bad pixel and the preset grayscale threshold is calculated in the loss function, and the parameters in the neural network model are adjusted according to the loss function to reduce the error of the bad pixel.

[0016] Preferably, assuming that the simulated lithography pattern obtained by the lithography simulation module is D, and the corresponding assignment map of the original design layout is B, and the grayscale threshold is set to τ, the loss function is defined as:

[0017]

[0018] Among them, i and j represent D ij and B ij In the coordinate positions in B and D, otherwise refers to the remaining pixel grid points in the simulated lithography pattern except for the bad pixels.

[0019] Preferably, defining the correspondence between the values ​​of the pixel grid points on the value map and the corresponding pixel grid points on the simulated lithography pattern includes:

[0020] The original design layout is mapped to the assignment map. In each pixel grid of the assignment map, the ratio of the design figure in the original design layout to the area of ​​the pixel grid is used as the target floating-point value of the pixel grid. The floating-point map of the design figure is constructed through the target floating-point values ​​of each pixel grid as the assignment map; the loss function is constructed according to the correspondence between the floating-point map of the design figure and the corresponding pixel grid on the simulated lithography pattern.

[0021] Preferably, a first floating point value, a second floating point value and a third floating point value are set, the first floating point value is greater than the second floating point value, and the second floating point value is greater than the third floating point value;

[0022] The grayscale threshold and the deviation threshold are set at the same time, and the pixel grid point whose target floating point value is greater than the second floating point value and whose grayscale value in the corresponding simulated lithography pattern is less than the grayscale threshold is regarded as the third bad pixel;

[0023] A pixel grid point whose target floating point value is less than the second floating point value and whose grayscale value in the corresponding simulated photolithography pattern is greater than the grayscale threshold is regarded as a fourth bad pixel;

[0024] A pixel grid point whose target floating-point value is greater than the first floating-point value and whose grayscale value in the corresponding simulated lithography pattern is less than the sum of the grayscale threshold and the deviation threshold is regarded as a fifth bad pixel;

[0025] A pixel grid point whose target floating-point value is less than the third floating-point value and whose grayscale value in the corresponding simulated lithography pattern is greater than the difference between the grayscale threshold and the deviation threshold is taken as a sixth bad pixel;

[0026] In the loss function, the error between the grayscale value of the third bad pixel and the grayscale threshold, the error between the grayscale value of the fourth bad pixel and the grayscale threshold, the error between the grayscale value of the fifth bad pixel and the sum of the grayscale threshold and the deviation threshold, and the error between the grayscale value of the sixth bad pixel and the difference between the grayscale threshold and the deviation threshold are calculated respectively, and the parameters in the neural network model are adjusted according to the loss function to reduce the error.

[0027] Preferably, assuming that the simulated lithography pattern obtained by the lithography simulation module is D, the floating-point image of the original design layout is F, and the grayscale threshold τ and the deviation threshold σ are set, the loss function is defined as:

[0028]

[0029] Among them, i and j represent D ij and F ijIn the coordinate positions in B and F, otherwise refers to the remaining pixel grid points in the simulated lithography pattern except for the bad pixels.

[0030] In order to solve the above technical problems, the present invention also provides a computer device, which includes a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the steps of the above mask layout optimization method.

[0031] In order to solve the above technical problems, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above mask layout optimization method are implemented.

[0032] In order to solve the above technical problem, the present invention also provides a computer program product, which includes a computer program / instructions, and when the computer program / instructions are executed by a processor, the steps of the above mask layout optimization method are implemented.

[0033] Compared with the prior art, the mask layout optimization method, computer device, readable storage medium and program product provided by the present invention have the following advantages:

[0034] 1. The neural network model provided by the present invention includes a mask layout generation module and a lithography simulation module. The mask layout generation module outputs a corresponding mask layout based on the input original design layout, and the mask layout can be quickly obtained through the mask layout generation module; at the same time, the lithography simulation module obtains a corresponding simulated lithography pattern according to the mask layout simulation, and uses the simulated lithography pattern as the supervision information of the mask layout generation module. A loss function is constructed through the correspondence between the simulated lithography pattern and the original design layout, and the parameters in the neural network model are adjusted by the loss function. The simulated lithography pattern is used as a dynamic benchmark for iterative element judgment, and the mask layout output by the mask layout generation module is iteratively optimized, so that the optimized mask layout meets the lithography requirements, so that the output mask layout has higher accuracy, that is, the simulated lithography pattern obtained by lithography of the mask layout is closer to the design pattern, and the accuracy of the obtained mask layout is improved;

[0035] At the same time, the loss function is constructed based on the assignment of pixel grids on the assignment map of the original design layout and the corresponding relationship between the pixel grids on the simulated lithography pattern. The assignment map defines the assignment of corresponding pixel grids according to the area ratio of the design graphics in the original design layout within the corresponding pixel grids of the assignment map. By assigning values ​​to the original design layout, the design graphics in the original design layout are more accurately represented, so that the model can accurately obtain graphic information, so that even if a low-resolution original design layout is used, better optimization results can be obtained, thereby ensuring the accuracy of the mask layout output based on the original design layout. At the same time, in a low-resolution environment, the computing resources required by the model can be reduced, thereby improving the working efficiency of the model.

[0036] 2. The present invention maps the original design layout onto an assignment map. In each pixel grid point of the assignment map, when the design graphic in the original design layout occupies more than half of the area of ​​the pixel grid point, the pixel grid point is assigned a value of 1; when the design graphic occupies less than half of the area of ​​the pixel grid point, the pixel grid point is assigned a value of 0; when the pixel grid point is assigned a value of 1 or 0, one indicates that the design graphic exists at the pixel grid point, and the other indicates that the design graphic does not exist at the pixel grid point, and a binary map of the design graphic is defined as the assignment map; a loss function is constructed according to the correspondence between the binary map of the design graphic and the corresponding pixel grid points on the simulated lithography pattern; the binary map only uses two states to represent the graphic, and compared with color or grayscale images, the amount of data is greatly reduced, and the storage and processing efficiency is higher. The operation speed of processing the binary map is usually faster than that of processing the color or grayscale image, because each pixel grid point only needs to consider two states, which reduces the complexity of the loss function constructed by the binary map, and improves the adjustment and optimization efficiency of the loss function for the mask layout generation module.

[0037] 3. When the center of a pixel point in the assignment map of the present invention is located within the mapped design graphic and the design graphic in the original design layout occupies more than half of the area of ​​the pixel point, the pixel point is assigned a value of 1; when the center of a pixel point in the assignment map is located outside the mapped design graphic and the design graphic occupies less than half of the area of ​​the pixel point, the pixel point is assigned a value of 0; whether the center of the pixel point is located within the design graphic is used as a prerequisite for the assignment. If the center point of the pixel point is not within the design graphic, isolated noise points can be quickly determined and removed, thereby improving the quality and accuracy of the binary image. Judging whether the center point is within the design graphic can ensure that the generated mask layout matches the photolithography process requirements, thereby preventing the mask layout from being too large or too small, leading to errors in the manufacturing process.

[0038] 4. The present invention is also provided with a grayscale threshold, by setting the pixel value of 1 and the pixel point whose grayscale value in the corresponding simulated photolithography pattern is less than the grayscale threshold as the first bad pixel; setting the pixel value of 0 and the pixel point whose grayscale value in the corresponding simulated photolithography pattern is greater than the grayscale threshold as the second bad pixel; by using an assignment graph to accurately represent the design graphics in the original design layout, the model can accurately obtain graphic information, and then the difference between the simulated photolithography pattern and the design graphics, i.e., the first bad pixel and the second bad pixel, can be quickly and accurately obtained through the assignment graph; then, the error between the grayscale value of the first bad pixel and the second bad pixel and the preset grayscale threshold is calculated in the loss function, and the parameters in the neural network model are adjusted according to the loss function to reduce the error of the bad pixel, and the pixel points that need to be optimized and adjusted are further represented in the loss function, thereby reducing the amount of data calculation and improving the optimization efficiency.

[0039] 5. The mask layout generation module of the present invention is set as a mask layout generation model, and the lithography simulation module is set as a lithography simulation model; the lithography simulation model is connected to the mask layout generation model, and the lithography simulation model generates a simulated lithography pattern according to the mask layout output by the mask layout generation model, and uses the loss function constructed according to the assignment graph of the simulated lithography pattern and the original design layout as supervision information to guide the mask layout generation model to generate an optimized mask layout. By setting the mask layout generation module and the lithography simulation module as a complete model respectively, different types of mask layout generation modules and lithography simulation modules can be adjusted and used according to different usage requirements. The two can run independently to realize their respective functions, and can also be linked to optimize the output results.

[0040] 6. The present invention maps the original design layout onto an assignment map. In each pixel grid point of the assignment map, the ratio of the design graphic in the original design layout to the area of ​​the pixel grid point is used as the target floating-point value of the pixel grid point. A floating-point map of the design graphic is constructed as the assignment map through the target floating-point values ​​of each pixel grid point. A loss function is constructed according to the correspondence between the floating-point map of the design graphic and the corresponding pixel grid points on the simulated lithography pattern. Compared with the assignment map in the form of a binary map, the floating-point map constructed by area ratio represents the design graphic more accurately, further improving the optimization accuracy of the mask layout.

[0041] 7. The present invention further limits the correspondence between the floating-point image of the design graphic and the corresponding pixel grid points on the simulated lithography pattern in the loss function by setting grayscale thresholds and deviation thresholds, and dividing the floating-point values ​​into intervals, and specifically defines the bad pixels in the pixel grid points that need to be supervised in the loss function, thereby reducing the amount of data calculation originally required and improving the guidance and optimization efficiency of the loss function on the mask layout generation module.

[0042] 8. The present invention also provides a computer device, which includes a memory, a processor and a computer program stored on the memory. The processor executes the computer program to implement the steps of the above-mentioned mask layout optimization method, which has the same beneficial effects as the above-mentioned mask layout optimization method and will not be repeated here.

[0043] 9. The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed, the above-mentioned mask layout optimization method is implemented, and it has the same beneficial effects as the above-mentioned mask layout optimization method, which will not be elaborated here.

[0044] 10. The present invention also provides a computer program product having a computer program stored thereon. The computer program product includes a computer program / instructions. When the computer program / instructions are executed by a processor, the steps of the above-mentioned mask layout optimization method are implemented, and the computer program / instructions have the same beneficial effects as the above-mentioned mask layout optimization method, which will not be elaborated here.

Brief Description of the Drawings

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0046] Figure 1 It is a step flow chart of a mask optimization method provided by the first embodiment of the present invention.

[0047] Figure 2 It is an example diagram of an assignment diagram in a mask optimization method provided in the first embodiment of the present invention.

[0048] Figure 3 It is a schematic diagram of the structure of a computer device provided by the second embodiment of the present invention.

[0049] Figure 4 It is a schematic diagram of the structure of a computer-readable storage medium provided by the third embodiment of the present invention.

[0050] Figure 5 It is a schematic diagram of the structure of a computer program product provided by the fourth embodiment of the present invention.

[0051] Description of the accompanying drawings:

[0052] 10. Computer device; 20. Computer readable storage medium; 30. Computer program product. [Specific implementation method]

[0053] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and implementation examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0054] To solve the problem that the optimization results of existing mask layout optimization technology are not accurate enough, please refer to Figure 1 The present invention provides a mask layout optimization method, which comprises the following steps:

[0055] S1: providing a neural network model, the neural network model including a mask layout generation module and a lithography simulation module, providing an original design layout including a plurality of design graphics, inputting the original design layout into the mask layout generation module to output a corresponding mask layout, and the lithography simulation module obtains a corresponding simulated lithography pattern according to the mask layout simulation;

[0056] S2: providing an assignment map corresponding to the original design layout, and defining the assignment of corresponding pixel grid points based on the area ratio of the design graphics in the original design layout in the corresponding pixel grid points of the assignment map;

[0057] S3: defining the corresponding relationship between the assignment of pixel grid points on the assignment map and the corresponding pixel grid points on the simulated lithography pattern to construct a loss function;

[0058] S4: Adjust the parameters in the neural network model with the loss function to iteratively optimize the mask layout output by the mask layout generation module; output the mask layout corresponding to the simulated lithography pattern obtained after the iteration as the optimized mask layout.

[0059] The neural network model provided by the present invention can quickly obtain a mask layout through a mask layout generation module, and at the same time, a photolithography simulation module obtains a corresponding simulated photolithography pattern according to the mask layout simulation, and uses the simulated photolithography pattern as the supervision information of the mask layout generation module. A loss function is constructed through the correspondence between the simulated photolithography pattern and the original design layout, and the parameters in the neural network model are adjusted by the loss function. The simulated photolithography pattern is used as a dynamic benchmark for iterative element judgment, and the mask layout output by the mask layout generation module is iteratively optimized, so that the optimized mask layout meets the photolithography requirements, and the output mask layout has higher accuracy, that is, the simulated photolithography pattern obtained by photolithography of the mask layout is closer to the design pattern, and the accuracy of the obtained mask layout is improved;

[0060] At the same time, the loss function is constructed based on the assignment of pixel grids on the assignment map of the original design layout and the corresponding relationship between the pixel grids on the simulated lithography pattern. The assignment map defines the assignment of corresponding pixel grids according to the area ratio of the design graphics in the original design layout within the corresponding pixel grids of the assignment map. By assigning values ​​to the original design layout, the design graphics in the original design layout are more accurately represented, so that the model can accurately obtain graphic information, so that even if a low-resolution original design layout is used, better optimization results can be obtained, thereby ensuring the accuracy of the mask layout output based on the original design layout. At the same time, in a low-resolution environment, the computing resources required by the model can be reduced, thereby improving the working efficiency of the model.

[0061] It should be noted that in modern semiconductor processes, for high-end designs, whether using inverse lithography or other technologies, the quality and resolution of the input image are usually given priority to ensure that the subsequent lithography process can accurately achieve the design goals. However, higher-resolution input images will consume a lot of computing resources / computing time for the mask layout generated by inverse lithography.

[0062] Specifically, Inverse Lithography Technology (ILT) is an advanced lithography technology used in chip design and manufacturing. It aims to improve the resolution and accuracy of the lithography process in order to achieve more complex patterns on the chip. Unlike the traditional method of using regular masks, inverse lithography calculates an optimized mask pattern to better control the propagation and interference of light, so as to more accurately realize the desired pattern on the silicon wafer. ILT is often used to process high-resolution images, especially in modern semiconductor manufacturing, where the feature size is very small. Therefore, the input image needs to have sufficient resolution to capture subtle features and complex patterns.

[0063] It can be understood that the mask layout generation module is obtained based on historical design graphics and mask layout training corresponding to the historical design graphics.

[0064] Specifically, a design graphic and a mask layout optimized by inverse lithography technology corresponding to the design graphic are provided, and a mask layout generation module is trained by the design graphic and the corresponding mask layout, so that the mask layout generation module can output the corresponding mask layout optimized by inverse lithography technology according to the input design graphic.

[0065] ILT technology is designed to provide higher resolution and smaller feature sizes for complex patterns, and is suitable for the manufacture of high-density integrated circuits. It can usually generate more effective mask patterns to improve the overall quality of finished products, but ILT technology usually requires more computing resources and design cycles. Through deep training and learning, the mask layout generation module can quickly obtain a mask layout with higher accuracy after ILT technology optimization.

[0066] It is understandable that the ILT technology requires high-quality input image data for effective mask optimization and pattern reconstruction by comprehensively considering the propagation characteristics of light. However, a higher-resolution input image will require a lot of computing resources / computing time to generate the mask layout using the ILT technology. The original design layout containing several design graphics provided in the present invention is characterized in a low-resolution scenario. The resolution of the original design layout is lower than the resolution originally required for using the ILT technology. In the present invention, the model can accurately obtain graphic information through the assignment graph. At the same time, the loss function guides and supervises the optimization process of the mask layout generation module, so that even if a low-resolution original design layout is used, better optimization results can be obtained. The low-resolution original design layout also reduces the calculation time required for the model, thereby improving the working efficiency of the model.

[0067] It can be understood that in step S2, defining the corresponding relationship between the values ​​of the pixel grid points on the value graph and the corresponding pixel grid points on the simulated lithography pattern includes:

[0068] The original design layout is mapped onto the assignment map. In each pixel grid of the assignment map, when the design graphic in the original design layout occupies more than half of the area of ​​the pixel grid, the pixel grid is assigned a value of 1; when the design graphic occupies less than half of the area of ​​the pixel grid, the pixel grid is assigned a value of 0; when the pixel grid is assigned a value of 1 or 0, one indicates that the design graphic exists at the pixel grid, and the other indicates that the design graphic does not exist at the pixel grid, and a binary map of the design graphic is defined as the assignment map; a loss function is constructed according to the correspondence between the binary map of the design graphic and the corresponding pixel grid on the simulated lithography pattern.

[0069] When constructing the loss function based on the correspondence between the binary image of the design figure and the corresponding pixel grid points on the simulated lithography pattern, the binary Figure 1 Generally, two states are used to represent graphics. Compared with color or grayscale images, the amount of data is greatly reduced, and the storage and processing efficiency is higher. The operation speed of processing binary images is usually faster than that of processing color or grayscale images, because each pixel grid only needs to consider two states, which reduces the complexity of the loss function constructed by the binary image and improves the adjustment and optimization efficiency of the loss function for the mask generation module.

[0070] Furthermore, step S2 further includes: when the center of a pixel grid point in the assignment map is located within the mapped design pattern, and the design pattern in the original design layout occupies more than half of the area of ​​the pixel grid point, assigning the pixel grid point a value of 1, indicating that the design pattern exists at the pixel grid point;

[0071] When the center of a pixel grid point in the assignment map is outside the mapped design pattern and the design pattern occupies less than half of the area of ​​the pixel grid point, the pixel grid point is assigned a value of 0, indicating that there is no design pattern at the pixel grid point.

[0072] Whether the center of the pixel grid is within the design pattern is used as the premise for assigning values. If the center of the pixel grid is not within the design pattern, those isolated noise points can be quickly determined and removed, thereby improving the quality and accuracy of the binary image. Judging whether the center point is within the design pattern can ensure that the generated mask layout matches the requirements of the lithography process, thereby preventing the mask layout from being too large or too small, leading to errors in the manufacturing process.

[0073] Specifically, see Figure 2 First, we can define a bitmap that represents the design graphics in the original design layout in a low-resolution scenario. Bitmap is a format for storing images, usually used to represent the pixel information of an image. It stores the color or grayscale value of each pixel in the form of a matrix. Figure 2 As shown in the left figure a, the orange polygon in Figure a represents a circuit mapped into the bitmap of the design graphic; and the blue 6*6 grid represents a 6-pixel*6-pixel bitmap, which will need to record the information of the represented design graphic, and each blue dot represents the center position of each pixel.

[0074] Next, we define the values ​​of the pixel grid in the bitmap to obtain the corresponding assignment diagram: when the center point of a pixel is inside the orange polygon, and the area of ​​the orange part inside the pixel grid is greater than 1 / 2, we assign the pixel a value of 1; when the center point of the pixel is outside the orange polygon, and the area of ​​the blue part inside the pixel grid is greater than 1 / 2, we assign the pixel a value of 0; we assign the other pixels a value of -2, indicating that the situation there is complicated; in summary, we get the following Figure 2 The assignment diagram corresponding to the original design layout shown in Figure b on the middle right.

[0075] Further, in step S3, a loss function is defined based on the above-mentioned assignment graph, assuming that the simulated lithography pattern obtained by the lithography simulation module is D, and the corresponding assignment graph of the original design layout is B. A grayscale threshold τ is set, and the pixel grid point whose value is 1 and whose grayscale value in the corresponding simulated lithography pattern is less than the grayscale threshold is taken as the first bad pixel;

[0076] The pixel grid point whose value is 0 and whose gray value in the corresponding simulated photolithography pattern is greater than the gray threshold is regarded as the second bad pixel;

[0077] The error between the grayscale value of the first bad pixel and the second bad pixel and the preset grayscale threshold is calculated in the loss function, and the parameters in the neural network model are adjusted according to the loss function to reduce the error of the bad pixel.

[0078] Specifically, the loss function is defined as:

[0079]

[0080] Among them, i and j represent D ij and B ij In the coordinate positions in B and D, otherwise refers to the situation except the above two rows, in which case no loss or error will be caused.

[0081] By using the assignment graph to accurately represent the design graphics in the original design layout, the model can accurately obtain graphic information, and then the differences between the simulated lithography pattern and the design graphics, namely the first bad pixel and the second bad pixel, can be quickly and accurately obtained through the assignment graph; then the error between the grayscale value of the first bad pixel and the second bad pixel and the preset grayscale threshold is calculated in the loss function, and the parameters in the neural network model are adjusted according to the loss function to reduce the error of the bad pixels. The specific pixel grid points that need to be optimized and adjusted are further represented in the loss function, which reduces the amount of data calculation and improves the optimization efficiency.

[0082] It can be understood that the mask layout generation module is set as a mask layout generation model, and the lithography simulation module is set as a lithography simulation model; the lithography simulation model is connected to the mask layout generation model, and the lithography simulation model generates a simulated lithography pattern according to the mask layout output by the mask layout generation model, and uses the loss function constructed according to the assignment graph of the simulated lithography pattern and the original design layout as supervision information to guide the mask layout generation model to generate an optimized mask layout.

[0083] The lithography simulation model generates a simulated lithography pattern according to the mask layout output by the mask layout generation model, and inputs the simulated lithography pattern into the mask layout generation model. The simulated lithography pattern serves as supervisory information to guide the mask layout generation model to generate an optimized mask layout. By setting the mask layout generation module and the lithography simulation module as a complete model respectively, different types of mask layout generation modules and lithography simulation modules can be adjusted and used according to different usage requirements. The two can run independently to realize their respective functions, and can also be linked to optimize the output results.

[0084] Optionally, in step S3, defining the corresponding relationship between the values ​​of the pixel grid points on the value graph and the corresponding pixel grid points on the simulated lithography pattern may further include:

[0085] The original design layout is mapped to the assignment map. In each pixel grid of the assignment map, the ratio of the design figure in the original design layout to the area of ​​the pixel grid is used as the target floating-point value of the pixel grid. The floating-point map of the design figure is constructed through the target floating-point values ​​of each pixel grid as the assignment map; the loss function is constructed according to the correspondence between the floating-point map of the design figure and the corresponding pixel grid on the simulated lithography pattern.

[0086] A loss function is constructed based on the correspondence between the floating-point image of the design graphic and the corresponding pixel grid on the simulated lithography pattern. Compared with the assignment map in the form of a binary map, the floating-point image constructed by area ratio represents the design graphic more accurately, further improving the optimization accuracy of the mask layout.

[0087] Specifically, a first floating point value, a second floating point value, and a third floating point value are set, the first floating point value is greater than the second floating point value, and the second floating point value is greater than the third floating point value;

[0088] The grayscale threshold and the deviation threshold are set at the same time, and the pixel grid point whose target floating point value is greater than the second floating point value and whose grayscale value in the corresponding simulated lithography pattern is less than the grayscale threshold is regarded as the third bad pixel;

[0089] A pixel grid point whose target floating point value is less than the second floating point value and whose grayscale value in the corresponding simulated photolithography pattern is greater than the grayscale threshold is regarded as a fourth bad pixel;

[0090] A pixel grid point whose target floating-point value is greater than the first floating-point value and whose grayscale value in the corresponding simulated lithography pattern is less than the sum of the grayscale threshold and the deviation threshold is regarded as a fifth bad pixel;

[0091] A pixel grid point whose target floating-point value is less than the third floating-point value and whose grayscale value in the corresponding simulated lithography pattern is greater than the difference between the grayscale threshold and the deviation threshold is taken as a sixth bad pixel;

[0092] In the loss function, the error between the grayscale value of the third bad pixel and the grayscale threshold, the error between the grayscale value of the fourth bad pixel and the grayscale threshold, the error between the grayscale value of the fifth bad pixel and the sum of the grayscale threshold and the deviation threshold, and the error between the grayscale value of the sixth bad pixel and the difference between the grayscale threshold and the deviation threshold are calculated respectively, and the parameters in the neural network model are adjusted according to the loss function to reduce the error.

[0093] Assuming that the simulated lithography pattern obtained by the lithography simulation module is D, the floating-point image of the original design layout is F, and the grayscale threshold τ and the deviation threshold σ are set, the loss function is defined as:

[0094]

[0095] The present invention sets a grayscale threshold and a deviation threshold, and divides the floating-point value into intervals, thereby further limiting the correspondence between the floating-point image of the design graphic and the corresponding pixel grid points on the simulated lithography pattern in the loss function, and specifically defines the bad pixels in the pixel grid points that need to be supervised in the loss function, thereby reducing the amount of data calculation originally required and improving the guidance and optimization efficiency of the loss function on the mask layout generation module.

[0096] In summary, the neural network model provided by the first embodiment of the present invention includes a mask layout generation module and a lithography simulation module. The mask layout generation module outputs a corresponding mask layout based on the input original design layout, and the mask layout can be quickly obtained through the mask layout generation module; at the same time, the lithography simulation module obtains a corresponding simulated lithography pattern according to the mask layout simulation, and uses the simulated lithography pattern as the supervision information of the mask layout generation module. A loss function is constructed through the correspondence between the simulated lithography pattern and the original design layout, and the parameters in the neural network model are adjusted by the loss function. The simulated lithography pattern is used as a dynamic benchmark for iterative factor judgment, and the mask layout output by the mask layout generation module is iteratively optimized. The template diagram makes the optimized mask layout meet the lithography requirements and makes the output mask layout more accurate, that is, the simulated lithography pattern obtained by lithography of the mask layout is closer to the design pattern, thereby improving the accuracy of the obtained mask layout; the loss function can more accurately represent the design pattern in the original design layout, so that the model can accurately obtain the graphic information, so that even if the original design layout with low resolution is used, better optimization results can be obtained, which ensures the accuracy of the mask layout output based on the original design layout, and solves the problem that reducing the resolution of the original design layout can reduce the time required for model calculation but also reduces the accuracy of the mask layout output by the model.

[0097] To solve the above technical problems, please refer to Figure 3 The second embodiment of the present invention further provides a computer device 10, which includes a memory, a processor and a computer program stored in the memory. The processor executes the computer program to implement the steps of the above-mentioned mask layout optimization method, which has the same beneficial effects as the above-mentioned mask layout optimization method and will not be repeated here.

[0098] To solve the above technical problems, please refer to Figure 4 The third embodiment of the present invention further provides a computer-readable storage medium 20, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned mask layout optimization method are implemented, and the above-mentioned mask layout optimization method has the same beneficial effects, which will not be repeated here.

[0099] To solve the above technical problems, please refer to Figure 5The fourth embodiment of the present invention further provides a computer program product 30, which includes a computer program / instruction. When the computer program / instruction is executed by a processor, the steps of the above-mentioned mask layout optimization method are implemented, and the steps have the same beneficial effects as the above-mentioned mask layout optimization method, which will not be elaborated here.

[0100] It is understandable that, according to the embodiments disclosed in the present invention, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present invention include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part, and / or installed from a removable medium. When the computer program is executed by the central processing unit (CPU), the above functions defined in the method of the present application are executed. It should be noted that the computer-readable medium described in the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. Computer-readable storage media, for example, include but are not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection with one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, an apparatus or a device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in combination with an instruction execution system, an apparatus or a device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0101] The computer program code for performing the operation of the present application can be written in one or more programming languages ​​or a combination thereof, and the programming language includes object-oriented programming languages ​​such as Java, Smalltalk, C++, and also includes conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on the remote computer, or completely on the remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (for example, using an Internet service provider to connect through the Internet).

[0102] In the embodiments provided by the present invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0103] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. Those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0104] In various embodiments of the present invention, it should be understood that the size of the serial numbers of the above-mentioned processes does not mean the necessary order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0105] The flow chart and block diagram in the accompanying drawings of the present invention illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which is determined based on the functions involved. It should be particularly noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs a specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0106] The above is a detailed introduction to a mask layout optimization method, a computer device, a readable storage medium and a program product disclosed in an embodiment of the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea: At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention. Any modifications, equivalent substitutions and improvements made within the principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A mask layout optimization method, It is characterized in that The following steps are involved: Providing a neural network model, the neural network model includes a mask layout generation module and a lithography simulation module, providing an original design layout containing a number of design graphics, inputting the original design layout into the mask layout generation module to output a corresponding mask layout, and the lithography simulation module obtains a corresponding simulated lithography pattern according to the mask layout simulation; Providing an assignment map corresponding to the original design layout, and defining the assignment of corresponding pixel grid points based on the area ratio of the design graphics in the original design layout in the corresponding pixel grid points of the assignment map; Define the corresponding relationship between the assignment of pixel grid points on the assignment map and the corresponding pixel grid points on the simulated lithography pattern to construct a loss function; The parameters in the neural network model are adjusted by using the loss function, so as to iteratively optimize the mask layout output by the mask layout generation module; The mask layout corresponding to the simulated lithography pattern obtained after the iteration is completed is output as the optimized mask layout.

2. A mask layout optimization method according to claim 1, It is characterized in that Defining the correspondence between the assignment of pixel grid points on the assignment graph and the corresponding pixel grid points on the simulated lithography pattern to construct the loss function includes: The original design layout is mapped onto the assignment map. In each pixel grid of the assignment map, when the design pattern in the original design layout occupies more than half of the area of ​​the pixel grid and the center of the pixel grid in the assignment map is located within the mapped design pattern, the pixel grid is assigned a value of 1; when the design pattern occupies less than half of the area of ​​the pixel grid and the center of the pixel grid in the assignment map is located outside the mapped design pattern, the pixel grid is assigned a value of 0; when the pixel grid is assigned a value of 1 or 0, one indicates that the design pattern exists at the pixel grid and the other indicates that the design pattern does not exist at the pixel grid, and a binary map of the design pattern is defined as the assignment map; a loss function is constructed according to the correspondence between the binary map of the design pattern and the corresponding pixel grid on the simulated lithography pattern.

3. A mask layout optimization method according to claim 2, It is characterized in that Also includes: Setting a grayscale threshold, taking a pixel point whose value is 1 and whose grayscale value in the corresponding simulated photolithography pattern is less than the grayscale threshold as a first bad pixel; The pixel grid point whose value is 0 and whose gray value in the corresponding simulated photolithography pattern is greater than the gray threshold is regarded as the second bad pixel; The error between the grayscale value of the first bad pixel and the second bad pixel and the preset grayscale threshold is calculated in the loss function, and the parameters in the neural network model are adjusted according to the loss function to reduce the error of the bad pixel.

4. A mask layout optimization method according to claim 3, Features: Assuming that the simulated lithography pattern obtained by the lithography simulation module is D, and the corresponding assignment map of the original design layout is B, and the grayscale threshold is set to τ, the loss function is defined as: Among them, i and j represent D ij and B ij In the coordinate positions in B and D, otherwise refers to the remaining pixel grid points in the simulated lithography pattern except for the bad pixels.

5. A mask layout optimization method according to claim 1, It is characterized in that Defining the correspondence between the assignment of pixel grid points on the assignment graph and the corresponding pixel grid points on the simulated lithography pattern to construct the loss function includes: The original design layout is mapped to the assignment map. In each pixel grid of the assignment map, the ratio of the design figure in the original design layout to the area of ​​the pixel grid is used as the target floating-point value of the pixel grid. The floating-point map of the design figure is constructed through the target floating-point values ​​of each pixel grid as the assignment map; the loss function is constructed according to the correspondence between the floating-point map of the design figure and the corresponding pixel grid on the simulated lithography pattern.

6. A mask layout optimization method according to claim 5, It is characterized in that Also includes: Set a first floating point value, a second floating point value and a third floating point value, the first floating point value is greater than the second floating point value, and the second floating point value is greater than the third floating point value; The grayscale threshold and the deviation threshold are set at the same time, and the pixel grid point whose target floating point value is greater than the second floating point value and whose grayscale value in the corresponding simulated lithography pattern is less than the grayscale threshold is regarded as the third bad pixel; A pixel grid point whose target floating point value is less than the second floating point value and whose grayscale value in the corresponding simulated photolithography pattern is greater than the grayscale threshold is regarded as a fourth bad pixel; A pixel grid point whose target floating-point value is greater than the first floating-point value and whose grayscale value in the corresponding simulated lithography pattern is less than the sum of the grayscale threshold and the deviation threshold is regarded as a fifth bad pixel; A pixel grid point whose target floating-point value is less than the third floating-point value and whose grayscale value in the corresponding simulated lithography pattern is greater than the difference between the grayscale threshold and the deviation threshold is taken as a sixth bad pixel; In the loss function, the error between the grayscale value of the third bad pixel and the grayscale threshold, the error between the grayscale value of the fourth bad pixel and the grayscale threshold, the error between the grayscale value of the fifth bad pixel and the sum of the grayscale threshold and the deviation threshold, and the error between the grayscale value of the sixth bad pixel and the difference between the grayscale threshold and the deviation threshold are calculated respectively, and the parameters in the neural network model are adjusted according to the loss function to reduce the error.

7. A mask layout optimization method according to claim 6, Features: Assuming that the simulated lithography pattern obtained by the lithography simulation module is D, the floating-point image of the original design layout is F, and the grayscale threshold τ and the deviation threshold σ are set, the loss function is defined as: Among them, i and j represent D ij and F ij In the coordinate positions in B and F, otherwise refers to the remaining pixel grid points in the simulated lithography pattern except for the bad pixels.

8. A computer device comprising a memory, a processor and a computer program stored in the memory, Features : The processor executes the computer program to implement the steps of a mask layout optimization method as described in any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, Features :When the computer program is executed by a processor, the steps of a mask layout optimization method as described in any one of claims 1 to 7 are implemented.

10. A computer program product comprising a computer program / instructions, Features :When the computer program / instruction is executed by a processor, the steps of a mask layout optimization method as described in any one of claims 1 to 7 are implemented.

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