Manufacturing method of display panel, display panel and manufacturing device of display panel

Abstract

The application discloses a manufacturing method of a display panel, a display panel and a manufacturing device of the display panel, and generally relates to the technical field of display panels. The method comprises the following steps: through first etching and second etching, at least one metal wiring area is connected in parallel between two perforations formed by etching and the first metal layer and the second metal layer, and the polycrystalline silicon layer is connected in parallel between one perforation formed by etching and the metal wiring area corresponding to the polycrystalline silicon layer; wherein, the first metal layer is partially overlapped with one metal wiring area in the orthographic projection of the substrate, and the second metal layer is partially overlapped with one metal wiring area in the orthographic projection of the substrate, or the second metal layer is partially overlapped with one metal wiring area in the orthographic projection of the substrate.

Description

Technical Field

[0001] This disclosure generally relates to the field of display device technology, and more particularly to a method for manufacturing a display panel, a display panel, and an apparatus for manufacturing a display panel. Background Technology

[0002] With the continuous development of display panels, their display performance is getting better and better; for example, display panels are getting larger and larger.

[0003] To maximize the effective display area while maintaining the same size of the display panel, non-display areas are minimized. For example, the area occupied by the bezel in the orthographic projection direction is reduced; that is, a narrow bezel increases the effective display area. In related technologies, display panels are generally composed of multiple layers of film. When wiring is required between different layers, wiring areas are created on two different layers, and holes are etched through the orthographic projection direction between the two layers to connect them.

[0004] However, in the above solution, during the process of etching through holes from certain film layers of the display panel as starting layers to other film layers, if the number of holes is large and the number of layers of the corresponding spacing film layers are different, it is easy for some film layers corresponding to holes to be over-etched or under-etched, which will lead to poor subsequent wiring effect. Summary of the Invention

[0005] In view of the above-mentioned defects or deficiencies in the related technologies, it is desirable to provide a method for manufacturing a display panel, a display panel, and an apparatus for manufacturing a display panel, which can solve the problem that when there are more holes to be etched, and the number of holes is large and the number of corresponding spacer film layers is different, some of the film layers corresponding to the holes are easily over-etched or under-etched, which leads to poor subsequent wiring effect. In this way, the consumables required for the wiring process of the display panel can be reduced while ensuring the wiring quality of the display panel.

[0006] Firstly, a method for manufacturing a display panel is provided, the method comprising:

[0007] The display panel includes a display area and a non-display area in the orthographic projection direction, and the display area is at least partially surrounded by the non-display area; the display panel includes a substrate, a buffer film layer is disposed on one side of the substrate, a GI film layer is disposed on the side of the buffer film layer away from the substrate, an interlayer dielectric layer is disposed on the side of the GI film layer away from the substrate, a PLN film layer is disposed on the side of the interlayer dielectric layer away from the substrate, a polysilicon layer is disposed in a portion of the buffer film layer of the display area near the substrate, and at least two metal connection areas are disposed on the side of the PLN film layer near the substrate;

[0008] A first metal layer is disposed on the side of the buffer film layer corresponding to the non-display area near the substrate, and a second metal layer is disposed on the side of the interlayer dielectric layer corresponding to the non-display area near the substrate. The method includes:

[0009] Through the first etching and the second etching, at least one of the metal connection areas is connected to the first metal layer and the second metal layer through two through holes formed by etching, and the polysilicon layer is connected to the metal connection area corresponding to the polysilicon layer through one through hole formed by etching.

[0010] Wherein, the orthographic projection of the first metal layer on the substrate partially overlaps with a metal wiring area and the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area, or the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area.

[0011] In this application, the aforementioned display panel is divided into a display area and a non-display area in the orthographic projection direction. The display area is surrounded by the non-display area. The display area includes a substrate, a buffer film layer is disposed on one side of the substrate, a GI film layer is disposed on the side of the buffer film layer away from the substrate, an interlayer dielectric layer is disposed on the side of the GI film layer away from the substrate, and a planarization film layer PLN is disposed on the side of the interlayer dielectric layer away from the substrate. A polysilicon layer is disposed in a portion of the buffer film layer of the display area near the substrate. The side of the planarization film layer near the substrate is used to provide at least two metal connection areas. A first metal layer is disposed on the side of the buffer film layer corresponding to the non-display area near the substrate, and a second metal layer is disposed on the side of the interlayer dielectric layer corresponding to the non-display area near the substrate. Through two etching processes (the first and second etching), at least one metal connection area is etched to form two vias that connect to the first and second metal layers, respectively. The polysilicon layer is also etched to form a via that connects to the corresponding metal connection area (the projection of the first metal layer onto the substrate partially overlaps with a metal connection area, and the projection of the second metal layer onto the substrate partially overlaps with a metal connection area, or vice versa). Thus, through these two etching processes, the three vias located between different film layers are made interconnected according to the required overlap pattern. Furthermore, because of the batch etching, there is no risk of under-etching or over-etching of one or more of the three vias. Therefore, while ensuring etching and connection quality, the increased number of vias also reduces wiring material consumption.

[0012] In a second aspect, a display panel is provided, the display panel including a display area and a non-display area in the orthographic projection direction, the display area being at least partially surrounded by the non-display area; the display panel includes a substrate, a buffer film layer disposed on one side of the substrate, a GI film layer disposed on the side of the buffer film layer away from the substrate, an interlayer dielectric layer disposed on the side of the GI film layer away from the substrate, a planarization film layer disposed on the side of the interlayer dielectric layer away from the substrate, a polysilicon layer disposed in a portion of the buffer film layer of the display area near the substrate, and at least two metal wiring areas disposed on the side of the planarization film layer near the substrate;

[0013] A first metal layer is provided on the side of the buffer film layer corresponding to the non-display area that is close to the substrate, and a second metal layer is provided on the side of the interlayer dielectric layer corresponding to the non-display area that is close to the substrate.

[0014] The at least one metal connection area is connected to the first metal layer and the second metal layer through two through holes formed by etching, and the polysilicon layer is connected to the metal connection area corresponding to the polysilicon layer through one through hole formed by etching.

[0015] Wherein, the orthographic projection of the first metal layer on the substrate partially overlaps with a metal wiring area and the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area, or the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area.

[0016] Thirdly, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the method described in the first aspect.

[0017] Fourthly, a computer-readable storage medium is provided having a computer program stored thereon, characterized in that the program, when executed by a processor, implements the method described in the first aspect above.

[0018] Fifthly, a computer program product is provided, which includes instructions that, when executed by a processor, implement the method described in the first aspect above.

[0019] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0020] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0021] Figure 1 This is one of the schematic diagrams of a display panel in related technologies;

[0022] Figure 2 This is the second schematic diagram of a display panel in related technologies;

[0023] Figure 3 This is the third schematic diagram of a display panel in related technologies;

[0024] Figure 4 A schematic flowchart illustrating the manufacturing method of the display panel provided in this application embodiment;

[0025] Figure 5 This is one of the structural schematic diagrams of the display panel provided in the embodiments of this application;

[0026] Figure 6 This is a second schematic diagram of the structure of the display panel provided in the embodiments of this application;

[0027] Figure 7 This is the third schematic diagram of the structure of the display panel provided in the embodiments of this application;

[0028] Figure 8 A schematic diagram of the structure of the display panel manufacturing apparatus provided in the embodiments of this application;

[0029] Figure 9 A schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0030] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0031] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The applicable scenarios of this application will be described below.

[0032] To maximize the effective display area while maintaining the same size of the display panel, a narrow bezel can be used. The bezel is often used for wiring. Display panels are typically composed of multiple layers of film. When wiring is required between different layers, overlapping methods can be used to connect the wires of different layers from the outside of the display panel. Alternatively, wiring areas can be created on different layers, with holes etched through the orthographic projection of the layers to connect the wiring between them.

[0033] In related technologies, a display panel, when viewed in cross-section from the orthographic projection direction, comprises multiple film layers, such as nine film layers. Figure 1 As shown, Figure 1 The display panel is divided into a non-display area (Fanout area) and a display area (AA area) by a dashed line 10, with the display area to the left of the dashed line and the non-display area to the right. In the display area, an LS film layer 11 serves as a light-shielding layer for the thin-film transistors (TFTs) 12 in the AA area, reducing the illumination Ioff of the TFTs and improving the panel's voltage holding capability. Verification showed that the illumination Ioff is minimized when the LS film layer 11 blocks the perforations in the ILD film layer corresponding to the TFTs in the orthogonal projection direction of the substrate 13. The non-display area only has two overlapping metal layers: the SD layer 14 and the Gate layer 15. In the AA area, there is an overlap between the SD film layer 16 and the polysilicon layer 17. Both types of perforation require perforation in the ILD film layer. Therefore, in the process of fabricating the ILD film layer 18 of the display film layer, the process is as follows: after the entire layer is coated to form the ILD film layer, the ILD layer 18 is etched through the mask in one step to etch through the Gate layer 15, and at the same time, the ILD and GI layers 19 are etched through the Poly layer 17.

[0034] To reduce the bezel size, overlaps between different metal layers can be added in the non-display area, thereby reducing wiring materials and saving space occupied by wiring, thus significantly reducing the volume of the non-display area, i.e., reducing the bezel size. To achieve this, LS layer 1 and SD layer 2 can be added to the non-display area, and etched vias can be added to the ILD layer 18 of the non-display area. The newly added LS layer 1 and SD layer 2 in the non-display area are then overlapped for conductivity. This means that three vias need to be etched simultaneously in the ILD layer 18, forming a three-layer wiring configuration.

[0035] To ensure the overlap between the three metal film layers, such as Figure 2 and Figure 3 As shown, the ILD layer 18 needs to be etched into the LS layer and Gate layer in the non-display area, involving both deep and shallow via etching. Simultaneously, to ensure the TFT device's illumination Ioff remains at a low level, the TFT LS11 in the AA area needs to block the vias in the ILD layer 18. A poly layer 17 exists between the ILD layer 18 and the LS layer 11, which hinders the etching of the vias in the ILD layer 18, thus leading to… Figure 2 Some layers of the SD layer 17 can be etched down to the LS layer 11, while others cannot. This means that... Figure 3 Some areas are etched to the LS layer 11, while others are not. Both cases of etching to and not etching to the LS layer 11 essentially represent uneven and inaccurate etching of the ILD layer 18, due to the numerous etched holes in the ILD layer within the display panel. Figure 1 and Figure 2 The image shows only one hole in the ILD18 layer of the display area. In such an unevenly etched ILD18 hole, the SD layer set in the hole overlaps and conducts with the poly layer 17. If the same brightness and the same color are required to be displayed, different Vcom needs to be set for different overlapping areas. However, the display panel usually has only one Vcom. Therefore, this uneven etching makes the Vcom of the entire display area of ​​the display panel uneven, which ultimately leads to uneven display and poor display effect.

[0036] Based on this, this application proposes a method, apparatus, equipment, and medium for manufacturing a display panel, which can solve the problem that when there are more holes to be etched, and the number of holes is large and the number of corresponding spacer film layers is different, some holes may be over-etched or under-etched, which will lead to poor subsequent wiring effect. Thus, while ensuring the wiring quality of the display panel, the consumables required in the wiring process of the display panel are reduced.

[0037] Figure 4This is a schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application. The display panel includes a display area and a non-display area in the orthographic projection direction, with the display area surrounded by the non-display area. The display panel includes a substrate, a buffer film layer on one side of the substrate, a GI film layer on the side of the buffer film layer away from the substrate, an interlayer dielectric layer on the side of the GI film layer away from the substrate, a planarization film layer on the side of the interlayer dielectric layer away from the substrate, a polysilicon layer on a portion of the buffer film layer near the substrate in the display area, and at least two metal connection areas on the side of the planarization film layer near the substrate.

[0038] In this embodiment, the display panel includes a display area and a non-display area.

[0039] In one example, the display area can be a pixel area.

[0040] In one example, the aforementioned non-display area may include a trace fanout area. Generally, the aforementioned non-display area is located in the area where the border of the display panel is situated, that is, the border area includes the trace fanout area.

[0041] In this embodiment of the application, the above-mentioned at least two metal wiring areas are respectively disposed in the display area and the non-display area.

[0042] In one example, the aforementioned metal wiring area can be an SD layer.

[0043] like Figure 5 As shown, Figure 5 The image shows a longitudinal cross-section of the display film layer in an embodiment of this application. As can be seen from this display film layer, the display panel is divided into a pixel area (i.e., the aforementioned AA area) and a fanout area (i.e., the aforementioned non-display area). The display panel includes a substrate 21. A buffer layer 22 is disposed on one side of the substrate. A GI layer 23 is disposed on the side of the buffer layer 22 away from the substrate 21. An interlayer dielectric layer (ILD) 24 is disposed on the side of the GI layer 23 away from the substrate 21. A planarization layer 25 (PLN) is disposed on the side of the ILD 24 away from the substrate 21. In the orthographic projection direction of the aforementioned AA area, a polysilicon layer 26 is disposed in a portion of the buffer layer 22 near the substrate 21.

[0044] In this embodiment, a first metal layer is provided on the side of the buffer film layer corresponding to the non-display area that is close to the substrate, and a second metal layer is provided on the side of the interlayer dielectric layer corresponding to the non-display area that is close to the substrate.

[0045] In one example, the first metal layer described above can be an LS layer. The second metal layer described above can be a Gate layer.

[0046] The method includes the following steps 301:

[0047] Step 301: Through the first etching and the second etching, at least one of the metal connection areas is connected to the first metal layer and the second metal layer by two through holes formed by etching, and the polysilicon layer is connected to the metal connection area corresponding to the polysilicon layer by one through hole formed by etching.

[0048] In the embodiments of this application, the orthographic projection of the first metal layer on the substrate partially overlaps with a metal wiring area and the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area, or the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area.

[0049] It is understandable that, since the etching process involves vertically penetrating the film layer, when it is necessary to connect at least one of the aforementioned metal connection areas to the first metal layer and the second metal layer through two through holes formed by etching, at least one metal connection area needs to at least partially overlap with the first metal layer or the second metal layer on the orthogonal projection of the substrate.

[0050] In this embodiment, in order to ensure that the metal wiring area is connected to the first metal layer and the second metal layer through two through holes, the second metal layer may be composed of one or more overlapping areas located on the side of the interlayer dielectric layer close to the substrate. Therefore, the distribution area of ​​the second metal layer corresponds to the distribution pattern of the metal wiring area, as detailed in the following description.

[0051] Furthermore, the number of the aforementioned metal wiring areas also corresponds to the number of overlapping areas of the aforementioned second metal layer. For example, when there are 3 metal wiring areas, the number of overlapping areas of the aforementioned second metal layer is 1; when there are 2 metal wiring areas, the number of overlapping areas of the aforementioned second metal layer is 2. For details, please refer to the subsequent description, which will not be repeated here.

[0052] In the embodiments of this application, different masks are used in the first and second etching processes. It can be understood that in order to ensure that the etching process does not result in over-etching or under-etching, two masks are set to etch the three perforations through the two masks respectively, so that the perforations etched each time can ensure successful metal overlap and conduction between different film layers.

[0053] In the method provided in this application embodiment, the display panel is divided into a display area and a non-display area in the orthographic projection direction. The display area is surrounded by the non-display area. The display area includes a substrate, a buffer film layer is disposed on one side of the substrate, a GI film layer is disposed on the side of the buffer film layer away from the substrate, an interlayer dielectric layer is disposed on the side of the GI film layer away from the substrate, and a planarization film layer PLN is disposed on the side of the interlayer dielectric layer away from the substrate. A polysilicon layer is disposed in a portion of the buffer film layer of the display area near the substrate. The side of the planarization film layer near the substrate is used to provide at least two metal connection areas. A first metal layer is disposed on the side of the buffer film layer corresponding to the non-display area near the substrate, and a second metal layer is disposed on the side of the interlayer dielectric layer corresponding to the non-display area near the substrate. Through two etching processes (the first and second etching), at least one metal connection area is etched to form two vias that connect to the first and second metal layers, respectively. The polysilicon layer is also etched to form a via that connects to the corresponding metal connection area (the projection of the first metal layer onto the substrate partially overlaps with a metal connection area, and the projection of the second metal layer onto the substrate partially overlaps with a metal connection area, or vice versa). Thus, through these two etching processes, the three vias located between different film layers are made interconnected according to the required overlap pattern. Furthermore, because of the batch etching, there is no risk of under-etching or over-etching of one or more of the three vias. Therefore, while ensuring etching and connection quality, the increased number of vias also reduces wiring material consumption.

[0054] Optionally, in the embodiments of this application, all three perforations can be through the interlayer dielectric layer. Based on this, the first and second etching processes connect at least one of the metal connection areas to the first metal layer and the second metal layer via two perforations, and the polysilicon layer connects to the corresponding metal connection area via one perforation. The method for manufacturing the display panel disclosed in this application includes: etching the interlayer dielectric layer through a first mask to generate two perforations, and etching the interlayer dielectric layer through a second mask to generate one perforation; or, etching the interlayer dielectric layer through a first mask to generate one perforation, and etching the interlayer dielectric layer through a second mask to generate two perforations.

[0055] For example, the three vias include: a via from the interlayer dielectric layer to the polysilicon layer in the display area, a via from the interlayer dielectric layer to the second metal layer in the non-display area, and a via from the interlayer dielectric layer to the first metal layer in the non-display area.

[0056] It is understandable that the above-described process of creating vias using masks all requires etching through the interlayer dielectric layer. That is, although the three vias have different depths, they all need to be etched perpendicularly towards the substrate, starting from the interlayer dielectric layer. Therefore, to ensure that the etching process does not result in over-etching or under-etching, one can either use a first mask to etch two vias first, and then use a second mask to etch one via; or use a first mask to generate one via, and then use a second mask to generate two vias.

[0057] Optionally, in this embodiment, a third metal layer is provided on the side of the buffer film layer corresponding to the display area near the substrate, and a metal connection area is provided on the side of the PLN film layer of the display area near the substrate. The third metal layer and the thin film transistor of the display area overlap in the orthographic projection direction.

[0058] For example, the third metal layer is used to block the light transmission of the ILD hole in the display area for mounting thin film transistors (TFTs), thereby reducing the light exposure caused by illumination.

[0059] For example, the third metal layer described above can be an LS layer.

[0060] like Figures 5 to 7 As shown, an LS layer 29 (i.e., the aforementioned third metal layer) is provided on the side of the display area near the substrate.

[0061] For example, the metal wiring area of ​​the aforementioned display area can be an SD layer.

[0062] For example, the metal wiring area of ​​the display area and the polysilicon layer overlap in the orthographic projection direction. The metal wiring area of ​​the display area and the thin-film transistor overlap in the orthographic projection direction.

[0063] It is understandable that the metal wiring area of ​​the aforementioned display area can conduct with the thin-film transistor and also with the polysilicon layer.

[0064] For example, during the etching process to generate the above three vias, the etching methods can be combined arbitrarily, and this application embodiment does not limit this.

[0065] like Figure 5 As shown, Figure 5The structure includes three through-holes: one between the interlayer dielectric layer ILD24 and the polysilicon layer 26 in the display area (hereinafter referred to as the first hole 31, the location outlined by the dashed box 31); one between the interlayer dielectric layer ILD24 and the second metal layer GATE layer 27 in the non-display area (hereinafter referred to as the second hole 32, the location outlined by the dashed box 32); and one between the interlayer dielectric layer ILD24 and the first metal layer LS layer 28 in the non-display area (hereinafter referred to as the third hole 33, the location outlined by the dashed box 33). The first metal layer LS layer 28 is disposed on the side of the buffer film layer 22 corresponding to the non-metallic area near the substrate, and the second metal layer GATE layer 27 is disposed on the side of the interlayer dielectric layer ILD24 corresponding to the non-metallic area near the substrate. It can be seen that the through-hole between the interlayer dielectric layer ILD24 and the second metal layer GATE layer 27 in the non-display area is a single-layer through-hole in the interlayer dielectric layer ILD24. It should be noted that the display area and the non-display area are separated by a dashed line 30. The area to the left of the dashed line 30 is the display area, and the area to the right of the dashed line 30 is the non-display area.

[0066] The different perforation sequences and methods described above will be illustrated with various examples below:

[0067] It is understood that in the following examples, at least two metal connection areas include three SD areas in the planar film layer PLN25 near the display substrate, and these three SD areas overlap with the display area GI layer in the orthographic projection position of the polysilicon layer 26 on the substrate, overlap with the non-display area GATE layer 27 in the orthographic projection portion of the substrate, and overlap with the non-display area LS layer 28 in the orthographic projection portion of the substrate:

[0068] Example 1: such as Figure 5 As shown, after coating and generating the ILD layer 24, an etching process is first performed using a first mask to etch the second hole 32 and the third hole 33 at positions corresponding to the orthographic projection of the ILD layer and the two SD regions in the non-display area, ensuring that the second hole 32 and the third hole 33 are etched according to the overlap requirements. Then, an etching process is performed using a second mask to etch the first hole 31 at positions corresponding to the orthographic projection of the ILD layer and one SD region in the display area, ensuring that the first hole 31 is etched according to the overlap requirements.

[0069] Example 2: such as Figure 5As shown, after coating and generating the ILD layer 24, an etching process is first performed using a first mask to etch the first hole 31 at the position corresponding to the orthographic projection of the ILD layer and an SD area in the display area, ensuring that the first hole 31 is etched according to the overlap requirements. Then, an etching process is performed using a second mask to etch the second hole 32 and the third hole 33 at the position corresponding to the orthographic projection of the ILD layer and two SD areas in the non-display area, ensuring that the second hole 32 and the third hole 33 are etched according to the overlap requirements.

[0070] Example 3: such as Figure 6 As shown, after coating and forming the ILD layer 24, an etching process is first performed using a first mask to etch the ILD layer in the non-display area. The etching location is the region corresponding to the SD region that overlaps with the orthographic projection of the GATE layer 27 in the non-display area onto the substrate, i.e., the second hole 32 is etched first. Then, using a second mask, the first hole 31 is etched at the location where the SD region and the polysilicon layer 26 overlap in the orthographic projection onto the substrate in the ILD layer of the display area, and the third hole 33 is etched at the location where the LS layer 28 overlaps in the orthographic projection onto the substrate in the ILD layer of the non-display area. The first hole 31 and the third hole 33 are etched simultaneously according to the overlap requirements.

[0071] Example 4: Figure 6 As shown, after coating and forming the ILD layer 24, an etching process is first performed using a first mask to etch the first hole 31 in the ILD layer in the display area where it overlaps with the SD region and the polysilicon layer 26 in the substrate orthographic projection, and the third hole 33 in the ILD layer in the non-display area where it overlaps with the LS layer 28 in the substrate orthographic projection. The first hole 31 and the third hole 33 are etched simultaneously according to the overlap requirements, that is, the first hole 31 and the third hole 33 are etched first. Then, using a second mask, etching is performed in the ILD layer in the non-display area, and the etching position is the area corresponding to the SD region that overlaps with the non-display area GATE layer 27 in the substrate orthographic projection, that is, the aforementioned second hole 32 is etched again.

[0072] It should be noted that during the etching of the first hole 31 and the third hole 33, etching is required into the buffer layer. However, since the LS layer 28 is composed of three Mo / Al / Mo layers, the Mo layer is harder and often difficult to etch through, thus preventing etching into the Al layer. Therefore, although the first hole 31, like the third hole 33, is etched into the buffer layer and overlaps with the LS layer 28 in the display area and the LS layer 29 in the non-display area, the first hole 31 actually only enables the subsequent SD layer to conduct through the polysilicon layer 26, and not through the LS layer 29 in the display area.

[0073] Meanwhile, since both the first hole 31 and the third hole 33 are etched into the LS layer in the buffer, the first hole 31 does not suffer from the problem in the prior art where some holes are etched into the LS layer 29 while others are not, leading to uneven depth of the first hole 31. This uneven depth results in inconsistent front coupling of the display panel, inconsistent Vcom voltage required at different locations, and ultimately, uneven display and poor display effect. By unifying the etching depth of the first hole 31, a uniform Vcom voltage can also ensure the uniformity of the display panel, thereby improving the display effect.

[0074] Optionally, the method for manufacturing a display panel provided in this application embodiment further includes: during the first etching and the second etching process, using the shielding material to shield the perforations generated corresponding to the first etching.

[0075] Understandably, before the first etching begins, a shielding material can be placed at the perforation area corresponding to the second etching to protect areas other than the perforation area to be generated in the first etching, thus preventing over-etching of areas outside the first etching range during the first etching process. After the first etching ends and before the second etching begins, for the holes that have been etched in the first etching, a shielding material can be placed at the perforation area corresponding to the first etching to protect the perforations generated after the first etching, thus preventing the perforations that have already been etched from being etched again during the second etching process.

[0076] In one example, the aforementioned masking material can be PR adhesive.

[0077] Furthermore, the aforementioned shielding material is applied in the process of including three vias in the interlayer dielectric layer ILD24. It is understood that when the same film layer, i.e., the interlayer dielectric layer ILD24, includes three vias, these three vias are not etched at the same time, but rather sequentially through two masks. Therefore, the two etching processes cannot interfere with each other. Based on this, a shielding material needs to be placed on the side of the interlayer dielectric layer ILD24 away from the substrate before both the first and second etching processes begin.

[0078] Example 5: In conjunction with Example 1 above, before performing the etching process through the first mask, on the side of the first mask away from the substrate, the area other than the area where the second hole 32 and the third hole 33 are etched is covered with PR adhesive, and the first etching is performed; then after the first etching is completed, the PR adhesive is peeled off, and PR adhesive is covered in the area other than the area of ​​the first hole 31, and then the second etching is performed.

[0079] Example 6: In conjunction with Example 2 above, before performing the etching process through the first mask, on the side of the first mask away from the substrate, the area other than the area where the first hole 31 is etched is covered with PR adhesive, and the first etching is performed; then after the first etching is completed, the PR adhesive is peeled off, and PR adhesive is covered in the area other than the areas of the second hole 32 and the third hole 33, and then the second etching is performed.

[0080] Example 7: In conjunction with Example 3 above, before performing the etching process through the first mask, on the side of the first mask away from the substrate, the area other than the area where the first hole 31 and the third hole 33 are etched is covered with PR adhesive, and the first etching is performed; then after the first etching is completed, the PR adhesive is peeled off, and PR adhesive is covered in the area other than the area where the second hole 32 is located, and then the second etching is performed.

[0081] Example 8: In conjunction with Example 4 above, before performing the etching process through the first mask, on the side of the first mask away from the substrate, the area other than the area where the second hole 32 is etched is covered with PR adhesive, and the first etching is performed; then after the first etching is completed, the PR adhesive is peeled off, and PR adhesive is covered in the area other than the areas of the first hole 31 and the third hole 33, and then the second etching is performed.

[0082] Optionally, in this embodiment, the perforations in the non-display area among the three perforations can be made sequentially in different film layers, ultimately allowing the metal layers between different film layers to overlap. The first and second etching processes connect at least one of the metal connection areas to the first and second metal layers via two perforations, and the polysilicon layer connects to the corresponding metal connection area via one perforation. In the display panel manufacturing method of this embodiment, the method includes: two second metal layers are disposed on the side of the interlayer dielectric layer corresponding to the non-display area near the substrate; the first second metal layer partially overlaps the metal connection area in the orthogonal projection direction of the substrate, and the second second metal layer partially overlaps the first metal layer in the orthogonal projection direction of the substrate; the GI layer in the non-display area is etched using a third mask to generate a perforation from the GI layer to the first metal layer in the non-display area; and two perforations are generated by etching the interlayer dielectric layer in the non-display area using a fourth mask.

[0083] For example, the two perforations corresponding to the fourth mask are: the perforation from the interlayer dielectric layer to the polysilicon layer in the display area, and the perforation from the interlayer dielectric layer to the second metal layer in the non-display area.

[0084] It is understood that, in the embodiments of this application, the purpose of adding a first metal layer and a second metal layer in the non-display area compared to the previous one is to reduce the peripheral wiring in the non-display area. In this way, the wiring is reduced by overlapping between the inner film layers.

[0085] Furthermore, in order to make the metal wiring area located in the planar film layer in the non-display area interconnected and conductive between the second metal layer of the interlayer dielectric layer and the first metal layer of the buffer film layer, two second metal regions can be provided in the interlayer dielectric layer. One second metal region is interconnected with the metal wiring area in the planar film layer, and the other second metal region is interconnected with the first metal layer in the buffer film layer. In this way, the above-mentioned three-layer wiring in the non-display area is realized.

[0086] like Figure 7 As shown, Figure 7 The device includes three vias: a via from the interlayer dielectric layer ILD24 to the polysilicon layer 26 in the display area (hereinafter referred to as the first via 31); a via from the interlayer dielectric layer ILD24 to the second metal layer GATE layer 27 in the non-display area (hereinafter referred to as the second via 32); and a via from the GI film layer 23 in the non-display area to the first metal layer LS layer 28 in the non-display area (hereinafter referred to as the third via 33).

[0087] The first metal layer LS layer 28 is disposed on the side of the buffer film layer 22 corresponding to the non-metallic region, close to the substrate, and the second metal layer GATE layer 27 is disposed on the side of the interlayer dielectric layer ILD 24 corresponding to the non-metallic region, close to the substrate. It can be seen that the perforation between the interlayer dielectric layer ILD 24 in the non-display region and the second metal layer GATE layer 27 in the non-display region is a single-layer perforation in the interlayer dielectric layer ILD 24.

[0088] The different perforation sequences and methods described above will be illustrated with various examples below:

[0089] It is understood that in the following examples, at least two metal connection areas include two SD areas in the planar film layer PLN25 near the display substrate, and these two SD areas overlap with the display area GI layer at the orthographic projection position of the polysilicon layer 26 on the substrate, and overlap with the non-display area GATE layer 27 at the orthographic projection portion of the substrate:

[0090] Example 9: (e.g.) Figure 7As shown, after coating and forming the GI film layer 23, an etching process is first performed using the mask of the GI layer through a first mask. A third hole 33 is etched at the position where the GI film layer 23 in the non-display area overlaps with the LS layer 28 in the non-display area's orthogonal projection region. This ensures that the third hole 33 is etched according to the requirement that the GATE layer 27 and the LS layer 28 in the non-display area can overlap and conduct. Next, an interlayer dielectric layer (ILD layer) 24 is coated and formed. An etching process is then performed using the mask of the ILD layer through a second mask. A first hole 31 is etched in the interlayer dielectric layer (ILD layer) 24 in the display area, overlapping with the polysilicon layer 26 in the orthogonal projection region of the substrate. Etching is also performed in the ILD layer in the non-display area, specifically in the region corresponding to the SD region that overlaps with the orthogonal projection region of the GATE layer 27 in the non-display area, i.e., the aforementioned second hole 32 is etched again.

[0091] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the training rule determination method described in this application. For example, it can execute... Figure 4 The steps of the method shown are as follows.

[0092] This application provides a computer program product containing instructions that are implemented by a processor at runtime. Figure 4 The steps of the method shown are as follows.

[0093] It should be noted that although the operation of the method of the present invention is described in a specific order in the accompanying drawings, this does not require or imply that the operations must be performed in that specific order, or that all the operations shown must be performed in order to achieve the desired result.

[0094] This application also discloses a display panel, which includes a display area and a non-display area in the orthographic projection direction. The display area is at least partially surrounded by the non-display area. The display panel includes a substrate, a buffer film layer is disposed on one side of the substrate, a GI film layer is disposed on the side of the buffer film layer away from the substrate, an interlayer dielectric layer is disposed on the side of the GI film layer away from the substrate, a planarization film layer is disposed on the side of the interlayer dielectric layer away from the substrate, a polysilicon layer is disposed in a portion of the buffer film layer of the display area near the substrate, and at least two metal connection areas are disposed on the side of the planarization film layer near the substrate.

[0095] A first metal layer is provided on the side of the buffer film layer corresponding to the non-display area that is close to the substrate, and a second metal layer is provided on the side of the interlayer dielectric layer corresponding to the non-display area that is close to the substrate.

[0096] The at least one metal connection area is connected to the first metal layer and the second metal layer through two through holes formed by etching, and the polysilicon layer is connected to the metal connection area corresponding to the polysilicon layer through one through hole formed by etching.

[0097] Wherein, the orthographic projection of the first metal layer on the substrate partially overlaps with a metal wiring area and the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area, or the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area.

[0098] In one example, the three vias include: a via from the interlayer dielectric layer to the polysilicon layer in the display area, a via from the interlayer dielectric layer to the second metal layer in the non-display area, and a via from the interlayer dielectric layer to the first metal layer in the non-display area.

[0099] In one example, two second metal layers are disposed on the side of the interlayer dielectric layer corresponding to the non-display area near the substrate. The first second metal layer partially overlaps with the metal wiring area in the orthographic projection direction of the substrate, and the second second metal layer partially overlaps with the first metal layer in the orthographic projection direction of the substrate.

[0100] The three vias include: a via from the GI layer to the first metal layer in the non-display area, a via from the interlayer dielectric layer to the polysilicon layer in the display area, and a via from the interlayer dielectric layer to the second metal layer in the non-display area.

[0101] Figure 8 The present application also discloses a display panel manufacturing apparatus, including an execution unit 601: the display panel includes a display area and a non-display area in the orthographic projection direction, the display area being at least partially surrounded by the non-display area; the display panel includes a substrate, a buffer film layer is disposed on one side of the substrate, a GI film layer is disposed on the side of the buffer film layer away from the substrate, an interlayer dielectric layer is disposed on the side of the GI film layer away from the substrate, a planarization film layer is disposed on the side of the interlayer dielectric layer away from the substrate, a polysilicon layer is disposed in a portion of the buffer film layer of the display area near the substrate, and at least two metal connection areas are disposed on the side of the planarization film layer near the substrate; a first metal layer is disposed on the side of the buffer film layer corresponding to the non-display area near the substrate, and a second metal layer is disposed on the side of the interlayer dielectric layer corresponding to the non-display area near the substrate; the execution unit 601 is used for:

[0102] Through the first etching and the second etching, at least one of the metal connection areas is connected to the first metal layer and the second metal layer through two through holes formed by etching, and the polysilicon layer is connected to the metal connection area corresponding to the polysilicon layer through one through hole formed by etching.

[0103] Wherein, the orthographic projection of the first metal layer on the substrate partially overlaps with a metal wiring area and the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area, or the orthographic projection of the second metal layer on the substrate partially overlaps with a metal wiring area.

[0104] In one possible example, execution unit 601 is specifically used for:

[0105] Two vias are generated by etching the interlayer dielectric layer using a first mask, and one via is generated by etching the interlayer dielectric layer using a second mask.

[0106] or,

[0107] A first mask is used to etch the interlayer dielectric layer to generate a via, and a second mask is used to etch the interlayer dielectric layer to generate two vias.

[0108] The three vias include: a via from the interlayer dielectric layer to the polysilicon layer in the display area, a via from the interlayer dielectric layer to the second metal layer in the non-display area, and a via from the interlayer dielectric layer to the first metal layer in the non-display area.

[0109] In one possible example, execution unit 601 is specifically used for:

[0110] During the first and second etching processes, the shielding material is used to shield the perforations generated by the first etching.

[0111] In one possible example, execution unit 601 is specifically used for:

[0112] The first etching and the second etching process connect at least one of the metal connection areas to the first metal layer and the second metal layer through two through-holes formed by etching, and the polysilicon layer connects to the metal connection area corresponding to the polysilicon layer through one through-hole formed by etching, including:

[0113] Two second metal layers are disposed on the side of the interlayer dielectric layer corresponding to the non-display area near the substrate. The first second metal layer overlaps with the metal wiring area in the orthogonal projection direction of the substrate, and the second second metal layer overlaps with the first metal layer in the orthogonal projection direction of the substrate.

[0114] The GI layer in the non-display area is etched using a third mask to generate a perforation from the GI layer to the first metal layer in the non-display area.

[0115] Two perforations are generated by etching the interlayer dielectric layer in the non-display area using a fourth mask.

[0116] The two perforations corresponding to the fourth mask are: the perforation from the interlayer dielectric layer to the polysilicon layer in the display area, and the perforation from the interlayer dielectric layer to the second metal layer in the non-display area.

[0117] In one possible example, a third metal layer is provided on the side of the buffer film layer corresponding to the display area closer to the substrate, and a metal connection area is provided on the side of the PLN film layer of the display area closer to the substrate. The third metal layer and the thin film transistor of the display area overlap in the orthographic projection direction.

[0118] It should be understood that the units described in the display panel manufacturing apparatus correspond to the various steps in the method described in the accompanying drawings. Therefore, the operations and features described above for the method also apply to the display panel manufacturing apparatus and the units contained therein, and will not be repeated here. The display panel manufacturing apparatus can be pre-implemented in a computer device's browser or other security applications, or it can be loaded into a computer device's browser or its security applications through download or other means. The corresponding units in the display panel manufacturing apparatus can cooperate with the units in the computer device to implement the solutions of the embodiments of this application.

[0119] The division of modules or units mentioned in the detailed description above is not mandatory. In fact, according to the embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0120] It should be noted that for details not disclosed in the display panel manufacturing apparatus of this application embodiment, please refer to the details disclosed in the above embodiments of this application, which will not be repeated here.

[0121] The following is for reference. Figure 9 , Figure 9 A schematic diagram of a computer device suitable for implementing embodiments of this application is shown. For example... Figure 9As shown, the computer system 1700 includes a central processing unit (CPU) 1701, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 1702 or programs loaded from storage section 1708 into random access memory (RAM) 1703. RAM 1703 also stores various programs and data required for the system's operating instructions. CPU 1701, ROM 1702, and RAM 1703 are interconnected via bus 1704. Input / output (I / O) interface 1705 is also connected to bus 1704.

[0122] The following components are connected to I / O interface 1705: an input section 1706 including a keyboard, mouse, etc.; an output section 1707 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 1708 including a hard disk, etc.; and a communication section 1709 including a network interface card such as a LAN card, modem, etc. The communication section 1709 performs communication processing via a network such as the Internet. Drive 1710 is also connected to I / O interface 1705 as needed. Removable media 1711, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 1710 as needed so that computer programs read from them can be installed into storage section 1708 as needed.

[0123] Specifically, according to embodiments of this application, the flowchart above refers to... Figure 4 The described process can be implemented as a computer software program. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowchart. In such an embodiment, the computer program contains program code for performing the methods shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via communication section 1709, and / or installed from removable medium 1711. When the computer program is executed by central processing unit (CPU) 1701, it performs the functions defined in the system of this application.

[0124] It should be noted that the computer-readable medium shown in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0125] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operational instructions of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two connected blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified functions or operational instructions, or using a combination of dedicated hardware and computer instructions.

[0126] The units or modules described in the embodiments of this application can be implemented in software or hardware. The described units or modules can also be housed in a processor; for example, a processor can be described as including a first receiving module, a second receiving module, and a transmitting module. The names of these units or modules do not, in certain circumstances, constitute a limitation on the unit or module itself.

[0127] In another aspect, this application also provides a computer-readable storage medium, which may be included in the electronic device described in the above embodiments, or may exist independently and not assembled into the electronic device. The aforementioned computer-readable storage medium stores one or more programs that, when used by one or more processors, execute the method for manufacturing a display panel described in this application.

[0128] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the foregoing disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for manufacturing a display panel, characterized in that, The display panel comprises a display area and a non-display area in the orthographic projection direction, the display area is at least partially surrounded by the non-display area; the display panel comprises a substrate, a buffer film layer is arranged on one side of the substrate, a GI film layer is arranged on the side of the buffer film layer away from the substrate, an interlayer dielectric layer is arranged on the side of the GI film layer away from the substrate, and a planarization film layer is arranged on the side of the interlayer dielectric layer away from the substrate; a polysilicon layer is arranged in a partial region of the buffer film layer on the side of the display area close to the substrate, and at least two metal wiring areas are arranged on the side of the planarization film layer close to the substrate; The buffer film layer on the side of the non-display area close to the substrate is provided with a first metal layer, and the interlayer dielectric layer on the side of the non-display area close to the substrate is provided with a second metal layer, and the method comprises: Through first etching and second etching, at least one metal wiring area is connected between the two perforations formed by etching and the first metal layer and the second metal layer, and the polysilicon layer is connected between the one perforation formed by etching and the metal wiring area corresponding to the polysilicon layer; Wherein, the first metal layer partially overlaps with one metal wiring area in the orthographic projection of the substrate, and the second metal layer partially overlaps with one metal wiring area in the orthographic projection of the substrate, or the second metal layer partially overlaps with one metal wiring area in the orthographic projection of the substrate.

2. The method of claim 1, wherein, The method comprises: Through a first mask, the interlayer dielectric layer is etched to form two perforations, and through a second mask, the interlayer dielectric layer is etched to form one perforation; Or, Through a first mask, the interlayer dielectric layer is etched to form one perforation, and through a second mask, the interlayer dielectric layer is etched to form two perforations; The three perforations comprise: a perforation from the interlayer dielectric layer to the polysilicon layer in the display area, a perforation from the interlayer dielectric layer to the second metal layer in the non-display area, and a perforation from the interlayer dielectric layer to the first metal layer in the non-display area.

3. The method of claim 2, wherein, The method further comprises: During the second etching, the perforation generated by the first etching is shielded by a shielding material.

4. The method of claim 1, wherein, The method comprises: The second metal layer of the non-display area corresponding interlayer dielectric layer is arranged on the side close to the substrate, the first second metal layer partially overlaps the metal wiring area in the orthographic projection direction of the substrate, and the second second metal layer partially overlaps the first metal layer in the orthographic projection direction of the substrate. The GI layer in the non-display area is etched through a third mask to generate a through hole of the GI layer in the non-display area to the first metal layer. The interlayer dielectric layer in the non-display area is etched through a fourth mask to generate two through holes. The two through holes corresponding to the fourth mask are a through hole of the interlayer dielectric layer in the display area to the polysilicon layer and a through hole of the interlayer dielectric layer in the non-display area to the second metal layer.

5. The method of claim 1, wherein, The third metal layer is arranged on the side of the buffer film layer corresponding to the display area close to the substrate, and the PLN film layer of the display area is arranged on the side close to the substrate to form a metal wiring area, and the third metal layer and the thin film transistor of the display area overlap in the orthographic projection direction.

6. A display panel, characterized by, The display panel includes a substrate, a buffer film layer arranged on one side of the substrate, a GI film layer arranged on the side of the buffer film layer away from the substrate, an interlayer dielectric layer arranged on the side of the GI film layer away from the substrate, and a planar film layer arranged on the side of the interlayer dielectric layer away from the substrate, a polysilicon layer arranged in a partial region of the buffer film layer of the display area close to the substrate, and at least two metal wiring areas arranged on the side of the planar film layer close to the substrate. The first metal layer is arranged on the side of the buffer film layer corresponding to the non-display area close to the substrate, and the second metal layer is arranged on the side of the interlayer dielectric layer corresponding to the non-display area close to the substrate. The at least one metal wiring area is connected to the first metal layer and the second metal layer through two through holes formed by etching, and the polysilicon layer is connected to the metal wiring area corresponding to the polysilicon layer through a through hole formed by etching. The first metal layer partially overlaps one metal wiring area in the orthographic projection of the substrate, and the second metal layer partially overlaps one metal wiring area in the orthographic projection of the substrate, or the second metal layer partially overlaps one metal wiring area in the orthographic projection of the substrate.

7. The display panel of claim 6, wherein, The three through holes include a through hole of the interlayer dielectric layer in the display area to the polysilicon layer, a through hole of the interlayer dielectric layer in the non-display area to the second metal layer, and a through hole of the interlayer dielectric layer in the non-display area to the first metal layer.

8. The display panel of claim 6, wherein, The second metal layer of the non-display area corresponding interlayer dielectric layer is arranged on the side close to the substrate, the first second metal layer partially overlaps the metal wiring area in the orthographic projection direction of the substrate, and the second second metal layer partially overlaps the first metal layer in the orthographic projection direction of the substrate. The three through holes include: a through hole from the GI layer to the first metal layer in the non-display area, a through hole from the interlayer dielectric layer to the polysilicon layer in the display area, and a through hole from the interlayer dielectric layer to the second metal layer in the non-display area.

9. An apparatus for manufacturing a display panel, characterized in that, An execution module is included for executing and implementing the method of any of claims 1-5.

10. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the program to implement the method of any of claims 1-5.

11. A computer readable storage medium having stored thereon a computer program, characterized in that The program is executed by the processor to implement the method of any of claims 1-5.

12. A computer program product, the computer program product comprising instructions embodied therein, wherein: The instructions are executed by the processor to implement the method of any of claims 1-5.

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