Display panel and display device

Abstract

The invention provides a display panel and a display device, and the display panel comprises a plurality of repeating units which comprise at least two sub-pixels. The sub-pixel includes a light emitting device, a driving transistor configured to drive the light emitting device to emit light, and a switching transistor configured to control signal transmission between the light emitting device and the driving transistor according to a first light emission control signal. Wherein at least one sub-pixel comprises a multiplexing transistor, and the multiplexing transistor is configured to control signal transmission between the plurality of driving transistors and the multiplexing signal line according to a multiplexing control signal. In the same repeating unit, the number of the multiplexing transistors electrically connected with the same multiplexing signal line is smaller than the number of the sub-pixels. Therefore, the driving transistors of the plurality of sub-pixels are all connected with the multiplexing signal lines through the multiplexing transistors, so that the number of transistors included in the display panel can be reduced, and the high-resolution design of the display panel is facilitated.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In order to realize the display of sub-pixels in the display area, the sub-pixels need to include pixel driving circuits. The sub-pixels are arranged in the display area, so that the pixel driving circuits included in the sub-pixels are also arranged in the display area. However, the pixel driving circuit includes a large number of transistors, which will occupy a large layout space, resulting in a reduction in the number of sub-pixels that can be arranged in the display area, which is not conducive to realizing the high-resolution design of the display panel. Summary of the invention

[0003] The embodiments of the present invention provide a display panel and a display device, which can support the display panel to realize high-resolution design.

[0004] An embodiment of the present invention provides a display panel, comprising a plurality of repeating units, wherein the repeating units include at least two sub-pixels, wherein the sub-pixels include a light-emitting device, a driving transistor configured to drive the light-emitting device to emit light, and a switch transistor configured to control signal transmission between the light-emitting device and the driving transistor according to a first light-emitting control signal. At least one sub-pixel includes a multiplexing transistor, wherein the multiplexing transistor is configured to control signal transmission between the plurality of driving transistors and a multiplexing signal line according to a multiplexing control signal; in the same repeating unit, the number of the multiplexing transistors electrically connected to the same multiplexing signal line is less than the number of the sub-pixels.

[0005] The present invention provides a display device, comprising any one of the above-mentioned display panels.

[0006] The present invention provides a display panel and a display device, including a plurality of repeating units, wherein the repeating units include at least two sub-pixels, wherein the sub-pixels include a light-emitting device, a driving transistor configured to drive the light-emitting device to emit light, and a switch transistor configured to control signal transmission between the light-emitting device and the driving transistor according to a first light-emitting control signal. At least one sub-pixel includes a multiplexing transistor, and the multiplexing transistor is configured to control signal transmission between a plurality of driving transistors and a multiplexing signal line according to a multiplexing control signal. In the same repeating unit, the number of multiplexing transistors electrically connected to the same multiplexing signal line is less than the number of sub-pixels. By making the driving transistors of the plurality of sub-pixels connected to the multiplexing signal line via the multiplexing transistor, the number of transistors included in the display panel is reduced, thereby facilitating the display panel to achieve a high-resolution design. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0008] Figure 1A to Figure 1B is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0009] Figure 2A to Figure 2C is a schematic diagram of the circuit structure of a repeating unit provided in an embodiment of the present invention;

[0010] Figure 3A to Figure 3B is a timing diagram of a corresponding sub-pixel provided by an embodiment of the present invention;

[0011] Figure 4A to Figure 4L It corresponds to Figure 2A A schematic diagram of the wiring structure of the repeating unit shown;

[0012] Figure 5A to Figure 5L It corresponds to Figure 2B A schematic diagram of the wiring structure of the repeating unit shown;

[0013] Figure 6 It is a schematic diagram of the structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device.

[0015] Specifically, Figure 1A to Figure 1B is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. An embodiment of the present invention provides a display panel, and the display panel includes a plurality of repeating units RU.

[0016] The repeating unit RU includes at least two sub-pixels Spi, and the sub-pixel Spi includes a light emitting device LD and a pixel driving circuit.

[0017] Optionally, the light-emitting colors of the plurality of sub-pixels Spi included in the same repeating unit RU may be the same or different.

[0018] Optionally, the light emitting device LD includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, or the like.

[0019] Figure 2A to Figure 2C is a schematic diagram of the circuit structure of a repeating unit provided in an embodiment of the present invention, wherein the pixel driving circuit includes a driving module and a switch control module.

[0020] The driving module is electrically connected to the light emitting device LD, and is configured to drive the light emitting device LD to emit light. The driving module includes a driving transistor Tdr configured to generate a driving current to drive the light emitting device LD to emit light.

[0021] The switch control module is electrically connected to the driving transistor Tdr and the light emitting device LD, and is configured to control the on and off of the driving current flow path according to the light emitting control signal. The switch control module includes a switch transistor Ts configured to control the signal transmission between the light emitting device LD and the driving transistor Tdr according to the first light emitting control signal EM1.

[0022] Please continue reading Figure 1A to Figure 1B and Figure 2A to Figure 2C At least one sub-pixel Spii includes a multiplexing transistor Tm, and the multiplexing transistor Tm is configured to control the signal transmission between multiple driving transistors Tdr and the multiplexing signal line according to a multiplexing control signal; in the same repetitive unit RU, the number of multiplexing transistors Tm electrically connected to the same multiplexing signal line is less than the number of sub-pixels Spi, so that the driving transistors Tdr of the multiple sub-pixels Spi are connected to the multiplexing signal line via the multiplexing transistor Tm, so as to reduce the number of transistors included in the display panel, thereby facilitating the display panel to achieve high-resolution design.

[0023] Optionally, in the same repeating unit RU, different sub-pixels Spi may include a plurality of multiplexing transistors Tm with different functions, so as to further reduce the number of transistors included in the display panel. Figure 1A and Figure 2A to Figure 2C As shown, in the same repeating unit RU, the multiplexing signal lines electrically connected to the multiplexing transistors Tm included in different sub-pixels Spii transmit different signals, and the multiplexing control signals corresponding to the multiplexing transistors Tm included in different sub-pixels Spii are different, so that different sub-pixels Spi in the same repeating unit RU include multiplexing transistors Tm with different functions, so that the multiple sub-pixels Spi included in the same repeating unit RU share the multiplexing transistors Tm with different functions, so as to further reduce the number of transistors included in the display panel.

[0024] That is, the same repeating unit RU may include X sub-pixels Spi and Y multiplexing transistors Tm, where X≥2 and X≥Y. That is, the same repeating unit RU may include only one multiplexing transistor Tm or multiple multiplexing transistors Tm.

[0025] For example, in the same repeating unit RU, a sub-pixel Spi includes a first multiplexing transistor Tm1, a multiplexing control signal received by a control end of the first multiplexing transistor Tm1 is a second light-emitting control signal EM2, a multiplexing signal line electrically connected to a first source-drain end of the first multiplexing transistor Tm1 is a first power line VDL electrically connected to a first voltage end VDD, and a second source-drain end of the first multiplexing transistor Tm1 is electrically connected to a first source-drain end of a plurality of driving transistors Tdr of sub-pixels Spi in the same repeating unit RU, so that the plurality of sub-pixels Spi in the same repeating unit RU share the first multiplexing transistor Tm1, so as to realize the electrical connection of the driving transistors Tdr of the plurality of sub-pixels Spi with the first voltage end VDD according to the second light-emitting control signal EM2 transmitted by the same multiplexing control line. The above-mentioned multiplexing transistor Tm includes a first multiplexing transistor Tm1.

[0026] Alternatively, in the same repetition unit RU, a sub-pixel Spi includes a second multiplexing transistor Tm2, ​​the multiplexing control signal received by the control end of the second multiplexing transistor Tm2 is the first gate control signal Pscan1, the multiplexing signal line electrically connected to the first source and drain end of the second multiplexing transistor Tm2 is the first reset line VL1, and the second source and drain end of the second multiplexing transistor Tm2 is electrically connected to the first source and drain end of the driving transistor Tdr of multiple sub-pixels Spi in the same repetition, so that multiple sub-pixels Spi in the same repetition unit RU share the second multiplexing transistor Tm2, ​​so as to realize the electrical connection between the driving transistors Tdr of multiple sub-pixels Spi and the first reset line VL1 according to the first gate control signal Pscan1 transmitted by the same multiplexing control line. Wherein, the above-mentioned multiplexing transistor Tm includes the second multiplexing transistor Tm2.

[0027] Alternatively, in the same overlapping unit, one sub-pixel Spi may include a first multiplexing transistor Tm1, and another sub-pixel Spi may include a second multiplexing transistor Tm2.

[0028] It should be noted that, for each sub-pixel Spi, the corresponding working principle when the multiplexing transistor Tm is shared is the same as the working principle when the multiplexing transistor Tm is not shared, so as to reduce the number of transistors included in the display panel while keeping the working principle of each sub-pixel Spi unaffected. Therefore, in some embodiments, the multiplexing transistor Tm may not be limited to the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2 mentioned above, but may also be other transistors in the pixel driving circuit (such as the reset transistor Tr described below). Among them, not sharing the multiplexing transistor Tm means that the multiplexing transistor Tm is independently set in each sub-pixel Spi.

[0029] Please continue reading Figure 2A to Figure 2C In order to make the luminous brightness of the light-emitting device LD meet the design requirements, the sub-pixel Spi includes a data transistor Tda, and the data transistor Tda includes a control terminal configured to receive a first scan signal Nscan1, a first source-drain terminal electrically connected to the data line DL, and a second source-drain terminal.

[0030] In addition, the sub-pixel Spi may also include an initial transistor Ti, a first capacitor C1 and a second capacitor C2, the initial transistor Ti includes a control terminal for receiving a second scan signal Nscan2, a first source-drain terminal electrically connected to the first initial line VIL, and a second source-drain terminal electrically connected to the second source-drain terminal of the data transistor Tda.

[0031] The first capacitor C1 is connected in series between the second source-drain terminal of the data transistor Tda and the control terminal of the driving transistor Tdr, and the second capacitor C2 is connected in series between the first voltage terminal VDD and the second source-drain terminal of the data transistor Tda.

[0032] Optionally, in order to compensate for the influence of the threshold voltage of the driving transistor Tdr on the driving current, the sub-pixel Spi also includes a compensation transistor Tc, and the compensation transistor Tc includes a control end for receiving the second scanning signal Nscan2, a first source-drain end electrically connected to the first source-drain end of the switching transistor Ts and the second source-drain end of the driving transistor Tdr, and a second source-drain end electrically connected to the control end of the driving transistor Tdr.

[0033] Optionally, in order to reset the anode potential of the light-emitting device LD, the sub-pixel Spi can include a reset transistor Tr, which includes a control end for receiving a second gate control signal Pscan2, a first source-drain end electrically connected to the second reset line VL2, and a second source-drain end electrically connected to the anode of the light-emitting device LD and the second source-drain end of the switching transistor Ts.

[0034] Since both the switch transistor Ts and the first multiplexing transistor Tm1 can realize the control of the on-off of the driving current flow path, the switch control module can include the first multiplexing transistor Tm1.

[0035] Optionally, in order to reset the potential of the control terminal of the driving transistor Tdr, the sub-pixel Spi further includes a reset transistor Tre, such as Figure 2C As shown. The reset transistor Tre includes a control terminal for receiving a third scan signal, a first source-drain terminal electrically connected to a third reset line VL3, and a second source-drain terminal electrically connected to a control terminal of the driving transistor Tdr. The third scan signal corresponding to the reset transistor Tre may be the same as the second scan signal Pscan2, and when the reset transistor Tre is turned on, the switch transistor Ts may be in a cut-off state.

[0036] In addition, the reset transistor Tr can also reset the anode potential of the light emitting device LD while resetting the control terminal potential of the driving transistor Tdr, so as to omit the reset transistor Tre, thereby reducing the number of transistors included in the display panel. Accordingly, when the reset transistor Tr is electrically connected to the second reset line VL2 and the anode of the light emitting device LD according to the second gate control signal Pscan2, the switch transistor Ts can be configured to be turned on according to the first light control signal EM1, so as to reset the anode potential of the light emitting device LD while resetting the control terminal potential of the driving transistor Tdr.

[0037] When the anode potential of the light-emitting device LD and the control terminal potential of the driving transistor Tdr are reset at the same time, in order to avoid the light-emitting device LD from emitting light by mistake, when the reset transistor Tr is electrically connected to the second reset line VL2 and the anode of the light-emitting device LD according to the second gate control signal Pscan2, the switching transistor Ts is turned on according to the first light-emitting control signal EM1, and the first multiplexing transistor Tm1 is configured to be turned off according to the second light-emitting control signal EM2.

[0038] Optionally, in order to save the border width of the display panel, the display panel includes a gate driving circuit, and the gate driving circuit includes a plurality of gate driving sub-circuits. Among them, the control ends of the second multiplexing transistor Tm2 and the reset transistor Tr are electrically connected to the gate driving sub-circuits of different levels, so that the second multiplexing transistor Tm2 and the reset transistor Tr can be controlled by the signal generated by the same gate driving circuit. For example, the control end of the second multiplexing transistor Tm2 receives the gate control signal generated by the nm-th level gate driving sub-circuit, and the control end of the reset transistor Tr receives the gate control signal generated by the n-th level gate driving sub-circuit. Among them, n>m, m≥1.

[0039] Optionally, the driving transistor Tdr, the switching transistor Ts, the first multiplexing transistor Tm1, the second multiplexing transistor Tm2, ​​the reset transistor Tr, the data transistor Tda, the compensation transistor Tc and the initial transistor Ti may be P-type transistors or N-type transistors, and the driving transistor Tdr, the switching transistor Ts, the first multiplexing transistor Tm1, the second multiplexing transistor Tm2, ​​the reset transistor Tr, the data transistor Tda, the compensation transistor Tc and the initial transistor Ti may be silicon transistors or oxide transistors. Among them, the oxide transistor includes oxide semiconductor materials such as indium gallium zinc oxide.

[0040] like Figure 3A to Figure 3B : is a timing diagram of a corresponding sub-pixel provided in an embodiment of the present invention, taking the driving transistor Tdr, the switch transistor Ts, the first multiplexing transistor Tm1, the second multiplexing transistor Tm2 and the reset transistor Tr as P-type transistors, and the data transistor Tda, the compensation transistor Tc and the initial transistor Ti as N-type transistors as an example, Figure 2A to Figure 2B The working principle of the sub-pixel Spi shown is explained.

[0041] The first stage t1: the first light emitting control signal EM1, the second light emitting control signal EM2, and the second gate control signal Pscan2 are at a high level, and the first scanning signal Nscan1, the second scanning signal Nscan2, and the first gate control signal Pscan1 are at a low level. The second multiplexing transistor Tm2 is turned on, and the first reset signal transmitted by the first reset line VL1 is transmitted to the first source and drain terminals of the plurality of driving transistors Tdr.

[0042] Second stage t2: the second light-emitting control signal EM2, the second scanning signal Nscan2, and the first gate control signal Pscan1 are at high level, and the first light-emitting control signal EM1, the first scanning signal Nscan1, and the second gate control signal Pscan2 are at low level. The switching transistor Ts, the initial transistor Ti, the compensation transistor Tc, and the reset transistor Tr are turned on, the first initial signal transmitted by the first initial line VIL is transmitted to one end of the first capacitor C1 and the second capacitor C2, and the second reset signal transmitted by the second reset line VL2 is transmitted to the anode of the light-emitting device LD, and the potential of the control end of the driving transistor Tdr is reset.

[0043] The third stage t3: the first light-emitting control signal EM1, the second scanning signal Nscan2, the first gate control signal Pscan1, and the second gate control signal Pscan2 are at a high level, and the second light-emitting control signal EM2 and the first scanning signal Nscan1 are at a low level. The first multiplexing transistor Tm1, the initial transistor Ti, and the compensation transistor Tc are turned on, the first voltage terminal VDD supply voltage is transmitted to the first source-drain terminal of the driving transistor Tdr, and the first capacitor C1 is charged so that the first capacitor C1 stores the threshold voltage information of the driving transistor Tdr, and the first initial signal transmitted by the first initial line VIL is transmitted to one end of the first capacitor C1 and the second capacitor C2.

[0044] Fourth stage t4: the first light emitting control signal EM1, the second light emitting control signal EM2, the first scanning signal Nscan1, the first gate control signal Pscan1, and the second gate control signal Pscan2 are at a high level, and the second scanning signal Nscan2 is at a low level. The data transistors Tda in the first sub-pixel Spi1 and the second sub-pixel Spi2 are turned on, and the data signal transmitted by the data line DL is coupled to the control end of the driving transistor Tdr via the first capacitor C1.

[0045] Fifth stage t5: the first light emitting control signal EM1, the second light emitting control signal EM2, and the second gate control signal Pscan2 are at a high level, and the first scanning signal Nscan1, the second scanning signal Nscan2, and the first gate control signal Pscan1 are at a low level. The second multiplexing transistor Tm2 is turned on, and the first reset signal transmitted by the first reset line VL1 is transmitted to the first source and drain terminals of the plurality of driving transistors Tdr.

[0046] The sixth stage t6: the first light-emitting control signal EM1 and the first gate control signal Pscan1 are at a high level, the first scanning signal Nscan1, the second scanning signal Nscan2, the second light-emitting control signal EM2, and the second gate control signal Pscan2 are at a low level. The reset transistor Tr is turned on, and the second reset signal transmitted by the second reset line VL2 is transmitted to the anode of the light-emitting device LD.

[0047] The seventh stage t7: the first gate control signal Pscan1 and the second gate control signal Pscan2 are at a high level, the first light-emitting control signal EM1, the second light-emitting control signal EM2, the first scan signal Nscan1, and the second scan signal Nscan2 are at a low level. The switch transistor Ts and the second multiplexing transistor Tm2 are turned on, and the driving transistor Tdr generates a driving current to control the light-emitting device LD to emit light.

[0048] Optionally, the same first light-emitting control signal EM1 can simultaneously control the on and off of the switching transistors Ts of multiple rows of sub-pixels Spi. The same second light-emitting control signal EM2 can simultaneously control the on and off of the first multiplexing transistor Tm1 of multiple rows of sub-pixels Spi, and the same first gate control signal Pscan1 can simultaneously control the on and off of the second multiplexing transistor Tm2 of multiple rows of sub-pixels Spi. A first scanning signal Nscan1 can correspondingly control the on and off of the data transistor Tda of a row of sub-pixels Spi, and a second scanning signal Nscan2 can correspondingly control the on and off of the initial transistor Ti and the compensation transistor Tc of a row of sub-pixels Spi. Therefore, the time period corresponding to the execution of the fourth stage t4 by two adjacent rows of sub-pixels Spi can correspond to the invalid level time period of the same second light-emitting control signal EM2. Figure 2B and Figure 3B As shown, the first scanning signal received by the control end of the data transistor Tda of the first sub-pixel Spi1 and the second sub-pixel Spi2 is the n-level scanning signal Nscan1(n) generated by the n-level gate driving sub-circuit of another gate driving circuit in the display panel, and the first scanning signal received by the control end of the data transistor Tda of the third sub-pixel Spi3 and the fourth sub-pixel Spi4 is the n+1-th level scanning signal Nscan1(n+1) generated by the n+1-th level gate driving sub-circuit of the other gate driving circuit. The time period during which the first sub-pixel Spi1 and the second sub-pixel Spi2 execute the fourth stage t4 correspondingly and the time period during which the third sub-pixel Spi3 and the fourth sub-pixel Spi4 execute the fourth stage t4 correspondingly correspond to the invalid level time period of the same second light-emitting control signal EM2.

[0049] It should be noted that the circuit structure of the sub-pixel Spi is not limited to Figure 2A to Figure 2C The design form shown. For example, in some embodiments, the second source-drain terminal of the data transistor Tda can be connected to the first source-drain terminal of the driving transistor Tdr, the second source-drain terminal of the initial transistor Ti is electrically connected to the control terminal of the driving transistor Tdr, the first capacitor C1 is connected in series between the first voltage terminal VDD and the control terminal of the driving transistor Tdr, and the second capacitor C2 is connected in series between the control terminal of the driving transistor Tdr and the control terminal of the data transistor Tda. The connection method of the first multiplexing transistor Tm1, the second multiplexing transistor Tm2, ​​the reset transistor Tr, the switch transistor Ts, the driving transistor Tdr and the light emitting device LD is as follows. Figure 2A to Figure 2C set up.

[0050] It should be noted that the control terminal of the transistor may correspond to a gate, and the first source-drain terminal and the second source-drain terminal of the transistor may correspond to a source and a drain, respectively.

[0051] Optionally, in order to enable multiple sub-pixels Spi in the same repeating unit RU to share the multiplexing transistor Tm to save layout space, the multiple sub-pixels Spi in the same repeating unit RU may be symmetrically arranged based on the design of the multiplexing transistor Tm.

[0052] like Figure 4A to Figure 4L It corresponds to Figure 2A Schematic diagram of the wiring structure of the repeating unit shown, Figure 5A to Figure 5L It corresponds to Figure 2B The wiring structure diagram of the repeating unit is shown. The example in which the same repeating unit RU includes both the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2 is used for explanation.

[0053] The repeating unit RU includes a first sub-pixel Spi1 and a second sub-pixel Spi2 arranged in a mirror image. The first sub-pixel Spi1 includes a first multiplexing transistor Tm1, and the second sub-pixel Spi2 includes a second multiplexing transistor Tm2. Figure 1A , Figure 2A to Figure 2B , Figure 4A to Figure 4B and Figure 5A to Figure 5B shown.

[0054] Since the first sub-pixel Spi1 and the second sub-pixel Spi2 share the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2, ​​the first sub-pixel Spi1 and the second sub-pixel Spi2 respectively adopt Figure 2A The structure shown in the design includes 14 transistors in total, which reduces two transistors compared to the design in which the first sub-pixel Spi1 and the second sub-pixel Spi2 include the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2 respectively. Therefore, it is beneficial to reduce the number of transistors included in the display panel.

[0055] In addition, the repeating unit RU may further include a third sub-pixel Spi3 and a fourth sub-pixel Spi4 that are arranged in a mirror image, the third sub-pixel Spi3 is symmetrical with the first sub-pixel Spi1 about the first multiplexing transistor Tm1, and the fourth sub-pixel Spi4 is symmetrical with the second sub-pixel Spi2 about the second multiplexing transistor Tm2. The second source-drain terminals of the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2 are electrically connected to the first source-drain terminals of the driving transistors Tdr of the third sub-pixel Spi3 and the fourth sub-pixel Spi4, as shown in FIG. Figure 1A , Figure 2B , Figure 4B and Figure 5B shown.

[0056] Since the first sub-pixel Spi1 to the fourth sub-pixel Spi4 share the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2, ​​the first sub-pixel Spi1 and the second sub-pixel Spi2 respectively adopt Figure 2BThe structure shown in the design includes 26 transistors in total, which reduces six transistors compared to the design in which the first sub-pixel Spi1 to the fourth sub-pixel Spi4 include the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2 respectively. Therefore, it is beneficial to reduce the number of transistors included in the display panel.

[0057] Optionally, the first sub-pixel Spi1 and the second sub-pixel Spi2 have different luminous colors, so that the sub-pixels Spi with different luminous colors share the multiplexing transistor Tm. Optionally, the luminous colors of the first sub-pixel Spi1 to the fourth sub-pixel Spi4 include red, green, blue, etc. For example, if the luminous color of the first sub-pixel Spi1 is red, the luminous color of the second sub-pixel Spi2 may be green, the luminous color of the third sub-pixel Spi3 may be blue, and the luminous color of the fourth sub-pixel Spi4 may be green.

[0058] Please continue reading Figure 1B , Figure 4A to Figure 4L and Figure 5A to Figure 5L , taking the repeating unit RU including two sub-pixels Spi or four sub-pixels Spi as an example, the wiring structure of the sub-pixel Spi for saving layout space is described.

[0059] The display panel includes a substrate 100 , a first active layer 201 , a first metal layer 301 , a second metal layer 302 , a first source-drain layer 401 , and a second source-drain layer 402 .

[0060] Alternatively, the substrate 100 may include glass, polyimide, or the like.

[0061] Optionally, the substrate 100 may include a base plate 1001 , a barrier layer 1002 located on the base plate 1001 , and a buffer layer 1003 located on the barrier layer 1002 .

[0062] Optionally, the substrate 100 further includes a light shielding layer 101 located between the buffer layer 1003 and the barrier layer 1002 .

[0063] Please continue reading Figure 1B , Figure 4C and Figure 5C, the first active layer 201 is located on the substrate 100, and the first active layer 201 includes a first connection portion Ca, a first active pattern P1 of a driving transistor Tdr, a second active pattern P2 of a switch transistor Ts, a third active pattern P3 of a first multiplexing transistor Tm1, and a fourth active pattern P4 of a second multiplexing transistor Tm2. In the same repeating unit RU, the first connection portion Ca is connected between the first doped portions of the plurality of first active patterns P1, the second active pattern P2 is connected to an end of the corresponding first active pattern P1 away from the first connection portion Ca (that is, the second active pattern P2 is connected to the second doped portion of the corresponding first active pattern P1), and the third active pattern P3 and the fourth active pattern P4 are connected to the first connection portion Ca, so as to realize the connection between the plurality of first active patterns P1 and the third active pattern P3 and the fourth active pattern P4 through the first connection portion Ca, thereby providing a basis for the plurality of sub-pixels Spi to share the multiplexing transistor Tm.

[0064] Please continue reading Figure 1B , Figure 4D and Figure 5D , the first metal layer 301 is located on the first active layer 201, and the first metal layer 301 includes a first electrode C1a, a first light-emitting control line EML1a, a first light-emitting control connection line EML2a, and a first gate control line Pscan1a. The first electrode C1a corresponds to the channel portion of the first active pattern P1 to serve as the gate of the driving transistor Tdr. Among them, the channel portion of the first active pattern P1 is located between the first doped portion and the second doped portion of the first active pattern P1. Part of the first light-emitting control line EML1a overlaps with the channel portion of the second active pattern P2 to serve as the gate of the switching transistor Ts. Part of the first light-emitting control connection line EML2a overlaps with the channel portion of the third active pattern P3 to serve as the gate of the first multiplexing transistor Tm1. Part of the first gate control line Pscan1a overlaps with the channel portion of the fourth active pattern P4 to serve as the gate of the second multiplexing transistor Tm2.

[0065] Please continue reading Figure 1B , Figure 4E and Figure 5E The second metal layer 302 is located on the first metal layer 301, and the second metal layer 302 includes a second electrode C12b, and a portion of the second electrode C12b overlaps with the first electrode C1a. The first electrode C1a and the second electrode C12b can serve as two electrodes of the first capacitor C1.

[0066] Please continue reading Figure 1B , Figure 4H and Figure 5H, the first source-drain layer 401 is located on the second metal layer 302, and the first source-drain layer 401 includes a first power connection portion VDa and a second light-emitting control connection line EML2b. The first power connection portion VDa is connected between the third active pattern P3 and the first voltage terminal VDD to realize the electrical connection between the first multiplexing transistor Tm1 and the first voltage terminal VDD. The second light-emitting control connection line EML2b is connected to the first light-emitting control connection line EML2a to transmit the second light-emitting control signal EM2 to the gate of the first multiplexing transistor Tm1 via the first light-emitting control connection line EML2a and the second light-emitting control connection line EML2b.

[0067] Please continue reading Figure 1B , Fig. 4I and Fig.5I The second source-drain layer 402 is located on the first source-drain layer 401, and the second source-drain layer 402 includes a first power line VDL, and the first power line VDL is electrically connected between the first power connection part VDa and the first voltage terminal VDD to achieve electrical connection between the first power connection part VDa and the first voltage terminal VDD.

[0068] Optionally, the first active layer 201 includes a silicon semiconductor material, and the first metal layer 301 , the second metal layer 302 , the first source and drain layer 401 , and the second source and drain layer 402 may include at least one of silver, copper, molybdenum, and titanium.

[0069] Since the data transistor Tda, the compensation transistor Tc and the initial transistor Ti may be oxide transistors, the display panel may further include a second active layer 202. Figure 1B , Figure 4A to Figure 4B , Figure 4F , Figure 5A to Figure 5B and Fig. 5F The display panel includes a second active layer 202, the second active layer 202 is located on the second metal layer 302, and the second active layer 202 includes a sixth active pattern I1 of the data transistor Tda, a seventh active pattern I2 of the compensation transistor Tc, and an eighth active pattern I3 of the initial transistor Ti.

[0070] In order to enhance the driving capability of the data transistor Tda, the compensation transistor Tc and the initial transistor Ti, gates may be provided on both sides of the channel portions of the sixth active pattern I1, the seventh active pattern I2 and the eighth active pattern I3. Figure 1B , Figure 4A to Figure 4B , Figure 4E to Figure 4G , Figure 5A to Figure 5B and Figure 5E to Figure 5G, the second metal layer 302 may include a first scan line Nscan1a and a first scan connection line Nscan2a. The display panel includes a third metal layer 303, the third metal layer 303 is located between the second active layer 202 and the first source and drain layer 401, and the third metal layer 303 includes a second scan line Nscan1b and a second scan connection line Nscan2b. Part of the first scan line Nscan1a and part of the second scan line Nscan1b overlap with the channel portion of the sixth active pattern I1 to form two gates of the data transistor Tda, respectively. Part of the first scan connection line Nscan2a and part of the second scan connection line Nscan2b overlap with the channel portion of the seventh active pattern I2 and the channel portion of the eighth active pattern I3 to form two gates of the compensation transistor Tc and the initial transistor Ti, respectively. The first scan wiring Nscan1a and the second scan wiring Nscan1b are configured to transmit a first scan signal Nscan1, and the first scan connection line Nscan2a and the second scan connection line Nscan2b are configured to transmit a second scan signal Nscan2.

[0071] Please continue reading Figure 1B , Figure 4A to Figure 4L and Figure 5A to Figure 5L The display panel includes a first gate insulating layer 501 , a second gate insulating layer 502 , a third gate insulating layer 503 , a first interlayer dielectric layer 601 , a second interlayer dielectric layer 602 , a first planarizing layer 701 , and a second planarizing layer 702 .

[0072] The first gate insulating layer 501 is located between the first active layer 201 and the first metal layer 301, the second gate insulating layer 502 is located between the first metal layer 301 and the second metal layer 302, the first interlayer dielectric layer 601 is located between the second metal layer 302 and the second active layer 202, the third gate insulating layer 503 is located between the second active layer 202 and the third metal layer 303, the second interlayer dielectric layer 602 is located between the third metal layer 303 and the first source and drain layer 401, the first planarizing layer 701 is located between the first source and drain layer 401 and the second source and drain layer 402, and the second planarizing layer 702 is located on the second source and drain layer 402.

[0073] Please continue reading Figure 4A to Figure 4L and Figure 5A to Figure 5L, to form the second capacitor C2, the first metal layer 301 includes a third electrode C2a, the third electrode C2a is located between the two first electrodes C1a, and the third electrode C2a partially overlaps with the two second electrodes C12b. The first source-drain layer 401 includes a second power connection portion VDb, the second power connection portion VDb partially overlaps with the third electrode C2a, and the second power connection portion VDb is electrically connected between the first power line VDL and the third electrode C2a, so as to realize the power connection between the third electrode C2a and the first voltage terminal VDD through the second power connection portion VDb and the first power line VDL. In addition, the same third electrode C2a forms the second capacitor C2 of the two sub-pixels Spi with the two second electrodes C12b respectively. Since the relative distance between the third electrode C2a and the second electrode C12b is relatively close, the use of the third electrode C2a and the second electrode C12b to form the second capacitor C2 is also conducive to increasing the capacitance value of the second capacitor C2. The second power connection portion VDb may be connected to the third electrode C2a through a first connection hole HoA penetrating the first planar layer 701, the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, and the second gate insulating layer 502. Figure 4J and Figure 5J shown.

[0074] Please continue reading Figure 4A to Figure 4H and Figure 5A to Figure 5H In order to realize the electrical connection between the second source-drain terminal of the compensation transistor Tc and the control terminal of the driving transistor Tdr, the first source-drain layer 401 includes a first electrode connecting portion Ce1 connected between the seventh active pattern I2 and the first electrode C1a. The first electrode connecting portion Ce1 is connected to the first electrode C1a through a first via hole Ho1 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, and the second gate insulating layer 502. Figure 4J and Figure 5J The first electrode connection portion Ce1 is connected to the seventh active pattern I2 through a second via hole Ho2 penetrating the second interlayer dielectric layer 602 and the third gate insulating layer 503, as shown in FIG. Figure 4K and Figure 5K shown.

[0075] In order to realize the connection between the second source-drain terminal of the data transistor Tda and the first capacitor C1 and the second capacitor C2, the first source-drain layer 401 further includes a second electrode connection portion Ce2, and the second electrode connection portion Ce2 is connected between the sixth active pattern I1 and the second electrode C12b. Since the second electrode C12b corresponds to an electrode of the first capacitor C1 and the second capacitor C2, the sixth active pattern I1 and the second electrode C12b are connected through the second electrode connection portion Ce2, so that the second source-drain terminal of the data transistor Tda and the first capacitor C1 and the second capacitor C2 can be connected. Among them, the second electrode connection portion Ce2 is connected to the second electrode C12b through the third via hole Ho3 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503 and the first interlayer dielectric layer 601, as shown in FIG. Figure 4J and Figure 5J The second electrode connection portion Ce2 is connected to the sixth active pattern I1 through a fourth via hole Ho4 penetrating the second interlayer dielectric layer 602 and the third gate insulating layer 503, as shown in FIG. Figure 4K and Figure 5K shown.

[0076] To achieve the connection between the first source and drain terminal of the data transistor Tda and the data line DL, the first source and drain layer 401 includes a third electrode connection portion Ce3 connected between the sixth active pattern I1 and the data line DL. The second source and drain layer 402 includes the data line DL. The third electrode connection portion Ce3 is connected to the sixth active pattern I1 through a fifth via hole Ho5 penetrating the second interlayer dielectric layer 602 and the third gate insulating layer 503, as shown in FIG. Figure 4K and Figure 5K The third electrode connection portion Ce3 is connected to the data line DL through the sixth via hole Ho6 penetrating the first planar layer 701, as shown in FIG. Figure 4L and Figure 5L shown.

[0077] In order to realize the electrical connection between the first source-drain terminal of the compensation transistor Tc and the first source-drain terminal of the switch transistor Ts and the second source-drain terminal of the driving transistor Tdr, the first source-drain layer 401 includes a fourth electrode connection portion Ce4 connected between the seventh active pattern I2 and the first active pattern P1 and the second active pattern P2. The fourth electrode connection portion Ce4 is connected to the first active pattern P1 and the second active pattern P2 through the seventh via hole Ho7 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, the second gate insulating layer 502 and the first gate insulating layer 501, as shown in FIG. Figure 4J and Figure 5J The fourth electrode connection portion Ce4 is connected to the seventh active pattern I2 through an eighth via hole Ho8 penetrating the second interlayer dielectric layer 602 and the third gate insulating layer 503, as shown in FIG. Figure 4K and Figure 5K shown.

[0078] Please continue reading Figure 4A to Figure 4L and Figure 5A to Figure 5L In order to provide the first initial signal to the initial transistor Ti, the first metal layer 301 further includes a first initial line VIL. In order to realize the electrical connection between the first initial line VIL and the initial transistor Ti, the first source-drain layer 401 includes a fifth electrode connection portion Ce5, and the fifth electrode connection portion Ce5 is connected between the eighth active pattern I3 and the first initial line VIL. The fifth electrode connection portion Ce5 is connected to the first initial line VIL through a ninth via hole Ho9 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, and the second gate insulating layer 502, as shown in FIG. Figure 4J and Figure 5J The fifth electrode connection portion Ce5 is connected to the eighth active pattern I3 through the tenth via hole Ho10 penetrating the second interlayer dielectric layer 602 and the third gate insulating layer 503, as shown in FIG. Figure 4K and Figure 5K shown.

[0079] Please continue reading Figure 4A to Figure 4L and Figure 5A to Figure 5L , the first active layer 201 includes a fifth active pattern P5 of the reset transistor Tr, and the fifth active pattern P5 is connected to an end of the second active pattern P2 away from the first active pattern P1. Optionally, the first source-drain layer 401 also includes a sixth electrode connection portion Ce6 connected to the anode of the light-emitting device LD and between the second active pattern P2 and the fifth active pattern P5. The sixth electrode connection portion Ce6 is connected to the second active pattern P2 and the fifth active pattern P5 through a second connection hole HoB penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, the second gate insulating layer 502, and the first gate insulating layer 501, as shown in FIG. Figure 4J and Figure 5J shown.

[0080] The following describes the differences in the wiring structures of the two-sub-pixel Spi multiplexing transistor Tm and the four-sub-pixel Spi multiplexing transistor Tm.

[0081] Please continue reading Figure 1B and Figure 4A to Figure 4L , the first connection portion Ca extends along a first direction, and the second active pattern P2, the third active pattern P3 and the fourth active pattern P4 extend along a second direction intersecting the first direction. The third active pattern P3 and the fourth active pattern P4 are located between the first connection portion Ca and the first light emission control trace EML1a, so that the two sub-pixels Spi can share the multiplexing transistor Tm. The first direction may correspond to one of the horizontal direction and the vertical direction, and the second direction may correspond to the other of the horizontal direction and the vertical direction.

[0082] Please continue reading Figure 1B and Figure 4H The second light-emitting control connection line EML2b includes a first sub-connection line EML2b1 and a second sub-connection line EML2b2. The first sub-connection line EML2b1 is connected to the first light-emitting control connection line EML2a and the second sub-connection line EML2b2, and the second sub-connection line EML2b2 is located on a side of the first light-emitting control wiring EML1a away from the third active pattern P3 and the fourth active pattern P4. The second sub-connection line EML2b2 is connected between the two first sub-connection lines EML2b1. The first sub-connection line EML2b1 is connected to the first light-emitting control connection line EML2a through an eleventh via hole Ho11 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, and the second gate insulating layer 502, as shown in FIG. Figure 4J shown.

[0083] Please continue reading Figure 1B and Figure 4G to Figure 4H , the third metal layer 303 includes a second gate control trace Pscan1b, the first source-drain layer 401 includes a third gate control trace Pscan1c, and the third gate control trace Pscan1c is connected between the first gate control trace Pscan1a and the second gate control trace Pscan1b to transmit the first gate control signal Pscan1 through the first gate control trace Pscan1a to the third gate control trace Pscan1c. The third gate control trace Pscan1c is connected to the first gate control trace Pscan1a through the twelfth via hole Ho12 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, and the second gate insulating layer 502, as shown in FIG. Figure 4J The third gate control wiring Pscan1c is connected to the second gate control wiring Pscan1b through the thirteenth via hole Ho13 penetrating the second interlayer dielectric layer 602, as shown in FIG. Figure 4K shown.

[0084] Please continue reading Figure 1B and Figure 4A to Figure 4L The first metal layer 301 includes a second gate control line PL for transmitting a second gate control signal Pscan2, and a portion of the second gate control line PL overlaps with a channel portion of the fifth active pattern P5 to form a gate of the reset transistor Tr. The second gate control line PL is located on a side of the first light emitting control trace EML1a away from the third active pattern P3 and the fourth active pattern P4.

[0085] Please continue reading Figure 1B and Figure 4A to Figure 4LThe second metal layer 302 includes a first reset line VL1a and a first reset connection line VL2a. The first source-drain layer 401 includes a second reset line VL1b and a second reset connection line VL2b. The second reset line VL1b is connected between the first reset line VL1a and the fourth active pattern P4, and the second reset connection line VL2b is connected between the first reset connection line VL2a and the fifth active pattern P5. The first reset line VL1 includes a first reset line VL1a and a second reset line VL1b, and the second reset line VL2 includes a first reset connection line VL2a and a second reset connection line VL2b.

[0086] The second reset line VL1b is connected to the fourth active pattern P4 through a fourteenth via hole Ho14 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, the second gate insulating layer 502 and the first gate insulating layer 501. Figure 4J The second reset line VL1b is connected to the first reset line VL1a through the fifteenth via hole Ho15 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, and the first interlayer dielectric layer 601, as shown. Figure 4J The second reset connection line VL2b is connected to the fifth active pattern P5 through the sixteenth via hole Ho16 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, the second gate insulating layer 502 and the first gate insulating layer 501, as shown in FIG. Figure 4J The second reset connection line VL2b is connected to the first reset connection line VL2a through the seventeenth via hole Ho17 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, and the first interlayer dielectric layer 601, as shown. Figure 4J shown.

[0087] The sixth electrode connection portion Ce6 may be electrically connected to the anode of the light emitting device LD through a third connection hole HoC penetrating the second planar layer 702. Figure 4L shown.

[0088] Please continue reading Figure 1B and Figure 5A to Figure 5LThe first connection portion Ca includes a first connection sub-portion Ca1 and a second connection sub-portion Ca2. The first connection sub-portion Ca1 extends along the first direction, and the second connection sub-portion Ca2 extends along the second direction intersecting the first direction. The first connection sub-portion Ca1 is connected between the first doped portions of two first active patterns P1 adjacent to each other along the first direction, and the second connection sub-portion Ca2 is connected between two first connection sub-portions Ca1 adjacent to each other along the second direction. The second active pattern P2 extends along the second direction, and the second active pattern P2 is electrically connected to an end of the first active pattern P1 away from the first connection sub-portion Ca1. The third active pattern P3 and the fourth active pattern P4 extend along the first direction, and the third active pattern P3 and the fourth active pattern P4 are located on opposite sides of the second connection sub-portion so that the four sub-pixels Spi can share the multiplexing transistor Tm.

[0089] The first light emitting control line EML1a is located between the first active pattern P1 and the third and fourth active patterns P3 and P4, so that the first light emitting control line EML1a and the corresponding second active pattern P2 are partially overlapped.

[0090] Please continue reading Figure 1B , Figure 5A to Figure 5B and Figure 5G to Figure 5H The third metal layer 303 includes a first reset line VL1a, the first source-drain layer 401 includes a second reset line VL1b, and the second reset line VL1b is connected between the first reset line VL1a and the fourth active pattern P4. The first reset line VL1 includes a second reset line VL1b and a first reset line VL1a.

[0091] The second reset line VL1b is connected to the fourth active pattern P4 through the eighteenth via hole Ho18 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, the second gate insulating layer 502 and the first gate insulating layer 501, and the second reset line VL1b is connected to the first reset line VL1a through the nineteenth via hole Ho19 penetrating the second interlayer dielectric layer 602. Figure 5J shown.

[0092] Please continue reading Figure 1B , Figure 5A to Figure 5B and Figure 5D The first metal layer 301 includes a first gate control connection line Pscan2a for transmitting a second gate control signal Pscan2, and a portion of the first gate control connection line Pscan2a overlaps with a channel portion of the fifth active pattern P5 to form a gate of the reset transistor Tr. The first gate control connection line Pscan2a is located between the first light emission control trace EML1a and the third active pattern P3 and the fourth active pattern P4.

[0093] Please continue reading Figure 1B, Figure 5A to Figure 5B and Figure 5G to Figure 5H , the third metal layer 303 includes a first reset connection line VL2a. The first source-drain layer 401 includes a second light-emitting control line EML1b, a second light-emitting control connection line EML2b, a second gate control line Pscan1b, a second gate control connection line Pscan2b and a second reset connection line VL2b, the second light-emitting control line EML1b is electrically connected to the first light-emitting control line EML1a, the second light-emitting control connection line EML2b is electrically connected to the first light-emitting control connection line EML2a, the second gate control line Pscan1b is connected to the first gate control line Pscan1a, the second gate control connection line Pscan2b is connected between the two first gate control connection lines Pscan2a, and the second reset connection line VL2b is connected between the first reset connection line VL2a and the fifth active pattern P5. The second light-emitting control wiring EML1b and the first light-emitting control wiring EML1a are configured to transmit the first light-emitting control signal EM1, and the second light-emitting control connection wire EML2b and the first light-emitting control connection wire EML2a are configured to transmit the second light-emitting control signal EM2. The second gate control wiring Pscan1b and the first gate control wiring Pscan1a are configured to transmit the first gate control signal Pscan1. The second gate control connection wire Pscan2b and the first gate control connection wire Pscan2a are configured to transmit the second gate control signal Pscan2. The second reset line VL2 includes a second reset connection wire VL2b and a first reset connection wire VL2a.

[0094] The second light-emitting control wiring EML1b is connected to the first light-emitting control wiring EML1a through the twentieth via hole Ho20 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, and the second gate insulating layer 502. The second light-emitting control connection line EML2b is connected to the first light-emitting control connection line EML2a through the twenty-first via hole Ho21 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, and the second gate insulating layer 502. The second gate control wiring Pscan1b is connected to the first gate control wiring Pscan1a through the twenty-second via hole Ho22 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, and the second gate insulating layer 502. The second gate control connection line Pscan2b is connected to the first gate control connection line Pscan2a through the twenty-third via hole Ho23 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, and the second gate insulating layer 502, the second reset connection line VL2b is connected to the fifth active pattern P5 through the twenty-fourth via hole Ho24 penetrating the second interlayer dielectric layer 602, the third gate insulating layer 503, the first interlayer dielectric layer 601, the second gate insulating layer 502, and the first gate insulating layer 501, and the second reset connection line VL2b is connected to the first reset connection line VL2a through the twenty-fifth via hole Ho25 penetrating the second interlayer dielectric layer 602, as shown in FIG. Figure 5J shown.

[0095] The first power connection portion VDa may be connected to the first power line VDL through the twenty-sixth via hole Ho26 penetrating the first planar layer 701. Figure 5L shown.

[0096] Optionally, the first source-drain layer 401 further includes a second power line VSa electrically connected to the second voltage terminal VSS, and the second source-drain layer 402 includes a third power connection portion VSb connected to the second power line VSa. The third power connection portion VSb is connected to the second power line VSa through a fourth connection hole HoD penetrating the second flat layer 702. The first power line VDL is connected to the second power connection portion through a fifth connection hole HoE penetrating the second flat layer 702. Figure 4L and Figure 5L shown.

[0097] In addition, a connecting line LA is also provided in the first metal layer 301 , and the connecting line can be configured to transmit one of a data signal, a power signal, etc., so as to improve the line resistance in the display panel, thereby improving the display quality.

[0098] Depend on Figure 4AIt can be seen from the sub-pixel Spi wiring structure shown that the first sub-pixel Spi1 includes a first multiplexing transistor Tm1, the second sub-pixel Spi2 includes a second multiplexing transistor Tm2, ​​and the first sub-pixel Spi1 and the second sub-pixel Spi2 are mirror-symmetrical. In addition, the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2 are arranged between the two second active patterns P2, which is conducive to realizing the design of multiplexing the transistor Tm of the first sub-pixel Spi1 and the second sub-pixel Spi2, so as to reduce the number of transistors included in the display panel.

[0099] Depend on Figure 5A It can be seen from the wiring structure of the sub-pixel Spi that the first sub-pixel Spi1 includes a first multiplexing transistor Tm1, the second sub-pixel Spi2 includes a second multiplexing transistor Tm2, ​​the first sub-pixel Spi1 and the second sub-pixel Spi2 are mirror-symmetrical, the first sub-pixel Spi1 and the third sub-pixel Spi3 are mirror-symmetrical about the first multiplexing transistor Tm1, and the second sub-pixel Spi2 and the fourth sub-pixel Spi4 are mirror-symmetrical about the second multiplexing transistor Tm2. And the first multiplexing transistor Tm1 and the second multiplexing transistor Tm2 are arranged between the fifth active pattern P5 and the first active pattern P1 of the four sub-pixels Spi, which is conducive to the realization of the first sub-pixel Spi1 to the fourth sub-pixel Spi4 multiplexing transistor Tm, so as to reduce the number of transistors included in the display panel.

[0100] It can be understood that the present application only uses the example that the repeating unit RU includes two sub-pixels Spi or four sub-pixels Spi. However, in actual applications, the repeating unit RU may include a design form that is greater than 4 sub-pixels Spi.

[0101] Please continue reading Figure 1B The display panel may further include a third source-drain layer 403, a third planar layer 703, and a pixel definition layer 800. The third source-drain layer 403 is located between the second planar layer 702 and the third planar layer 703, and the anode 901 of the light emitting device LD is located between the pixel definition layer 800 and the third planar layer 703. It can be understood that the display panel also includes the light emitting layer, cathode, and other unillustrated parts of the light emitting device LD.

[0102] Figure 6 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention. An embodiment of the present invention further provides a display device, comprising any of the above-mentioned display panels.

[0103] It can be understood that the display device includes a television, a computer, a virtual display device, etc.

[0104] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A display panel, characterized in that: comprising a plurality of repeating units, each of which comprises at least two sub-pixels, each of which comprises a light-emitting device, a driving transistor configured to drive the light-emitting device to emit light, and a switch transistor configured to control signal transmission between the light-emitting device and the driving transistor according to a first light-emitting control signal; Among them, at least one sub-pixel includes a multiplexing transistor, which is configured to control the signal transmission between multiple driving transistors and the multiplexing signal line according to a multiplexing control signal; in the same repeating unit, the number of the multiplexing transistors electrically connected to the same multiplexing signal line is less than the number of sub-pixels.

2. The display panel according to claim 1, characterized in that: In the same repeating unit, the multiplexing signal lines to which the multiplexing transistors included in different sub-pixels are electrically connected transmit different signals, and the multiplexing control signals corresponding to the multiplexing transistors included in different sub-pixels are different.

3. The display panel according to claim 2, characterized in that: The repeating unit includes a first sub-pixel and a second sub-pixel that are arranged in a mirror image, the first sub-pixel includes a first multiplexing transistor, and the second sub-pixel includes a second multiplexing transistor; The multiplexing control signal received by the control terminal of the first multiplexing transistor is a second light-emitting control signal, the multiplexing signal line electrically connected to the first source-drain terminal of the first multiplexing transistor is a first power line electrically connected to the first voltage terminal, and the second source-drain terminal of the first multiplexing transistor is electrically connected to the first source-drain terminal of the driving transistor of the first sub-pixel and the second sub-pixel; The multiplexing control signal received by the control end of the second multiplexing transistor is a first gate control signal, the multiplexing signal line to which the first source and drain ends of the second multiplexing transistor are electrically connected is a first reset line, and the second source and drain ends of the second multiplexing transistor are electrically connected to the first source and drain ends of the driving transistors of the first sub-pixel and the second sub-pixel.

4. The display panel according to claim 3, characterized in that: The repeating unit comprises a third sub-pixel and a fourth sub-pixel which are arranged in a mirror image, the third sub-pixel is symmetrical with the first sub-pixel about the first multiplexing transistor, and the fourth sub-pixel is symmetrical with the second sub-pixel about the second multiplexing transistor; The second source-drain terminals of the first multiplexing transistor and the second multiplexing transistor are electrically connected to the first source-drain terminals of the driving transistors of the third sub-pixel and the fourth sub-pixel.

5. The display panel according to claim 3 or 4, characterized in that: The display panel includes a gate driving circuit, the gate driving circuit includes a plurality of gate driving sub-circuits; the sub-pixel includes: a data transistor, comprising a control terminal configured to receive a first scan signal, a first source-drain terminal electrically connected to the data line, and a second source-drain terminal; a compensation transistor, comprising a control terminal for receiving a second scanning signal, a first source-drain terminal electrically connected to the first source-drain terminal of the switch transistor and the second source-drain terminal of the drive transistor, and a second source-drain terminal electrically connected to the control terminal of the drive transistor; an initial transistor, comprising a control terminal for receiving the second scanning signal, a first source-drain terminal electrically connected to the first initial line, and a second source-drain terminal electrically connected to the second source-drain terminal of the data transistor; a reset transistor, comprising a control terminal for receiving a second gate control signal, a first source-drain terminal electrically connected to a second reset line, and a second source-drain terminal electrically connected to an anode of the light-emitting device and a second source-drain terminal of the switch transistor; A first capacitor is connected in series between the second source-drain terminal of the data transistor and the control terminal of the driving transistor; and A second capacitor is connected in series between the first voltage terminal and the second source-drain terminal of the data transistor; Among them, the control ends of the second multiplexing transistor and the reset transistor are electrically connected to the gate driving sub-circuits of different levels; when the reset transistor is electrically connected to the second reset line and the anode of the light-emitting device according to the second gate control signal, the switching transistor is configured to be turned on according to the first light-emitting control signal, and the first multiplexing transistor is configured to be turned off according to the second light-emitting control signal.

6. The display panel according to claim 5, characterized in that: include: The first active layer comprises a first connection portion, a first active pattern of the driving transistor, a second active pattern of the switching transistor, a third active pattern of the first multiplexing transistor, and a fourth active pattern of the second multiplexing transistor; wherein, in the same repeating unit, the first connection portion is connected between the first doped portions of the plurality of first active patterns, the second active pattern is connected to an end of the corresponding first active pattern away from the first connection portion, and the third active pattern and the fourth active pattern are connected to the first connection portion; a first metal layer, located on the first active layer, comprising a first electrode, a first light-emitting control wiring, a first light-emitting control connecting wiring, and a first gate control wiring; the first electrode corresponds to the channel portion of the first active pattern, a portion of the first light-emitting control wiring overlaps with the channel portion of the second active pattern, a portion of the first light-emitting control connecting wiring overlaps with the channel portion of the third active pattern, and a portion of the first gate control wiring overlaps with the channel portion of the fourth active pattern; a second metal layer, located on the first metal layer, comprising a second electrode, a portion of the second electrode overlapping the first electrode; a first source-drain layer, located on the second metal layer, comprising a first power connection portion and a second light-emitting control connection line; the first power connection portion is connected between the third active pattern and the first voltage terminal, and the second light-emitting control connection line is connected to the first light-emitting control connection line; and The second source-drain layer is located on the first source-drain layer, and includes a first power line, and the first power line is electrically connected between the first power connection portion and the first voltage end.

7. The display panel according to claim 6, characterized in that: The first connection portion extends along a first direction, and the second active pattern, the third active pattern, and the fourth active pattern extend along a second direction intersecting the first direction; The third active pattern and the fourth active pattern are located between the first connecting portion and the first light-emitting control wiring, the second light-emitting control connecting wire includes a first sub-connecting wire and a second sub-connecting wire, the first sub-connecting wire is connected to the first light-emitting control connecting wire and the second sub-connecting wire, and the second sub-connecting wire is located on a side of the first light-emitting control wiring away from the third active pattern and the fourth active pattern.

8. The display panel according to claim 7, characterized in that: include: A third metal layer, located between the second metal layer and the first source-drain layer, including a second gate control wiring; The first source-drain layer includes a third gate control wiring, and the third gate control wiring is connected between the first gate control wiring and the second gate control wiring.

9. The display panel according to claim 7, characterized in that: The first active layer includes a fifth active pattern of the reset transistor, and the fifth active pattern is connected to an end of the second active pattern away from the first active pattern; The first metal layer includes a second gate control line for transmitting the second gate control signal, a portion of the second gate control line overlaps with a channel portion of the fifth active pattern, and the second gate control line is located on a side of the first light emitting control line away from the third active pattern and the fourth active pattern; The second metal layer includes a first reset trace and a first reset connection line; The first source-drain layer includes a second reset wiring and a second reset connection line, the second reset wiring is connected between the first reset wiring and the fourth active pattern, and the second reset connection line is connected between the first reset connection line and the fifth active pattern.

10. The display panel according to claim 6, characterized in that: The first connection portion includes a first connection sub-portion and a second connection sub-portion, the first connection sub-portion extends along a first direction, the second connection sub-portion extends along a second direction intersecting the first direction, the first connection sub-portion is connected between the first doped portions of two adjacent first active patterns along the first direction, and the second connection sub-portion is connected between two adjacent first connection sub-portions along the second direction; The second active pattern extends along the second direction, and the second active pattern is electrically connected to an end of the first active pattern away from the first connecting sub-portion; The third active pattern and the fourth active pattern extend along the first direction, and the third active pattern and the fourth active pattern are located at two opposite sides of the second connecting sub-portion; The first light emitting control wiring is located between the first active pattern, the third active pattern and the fourth active pattern.

11. The display panel according to claim 10, characterized in that: include: A third metal layer, located between the second metal layer and the first source-drain layer, comprising a first reset trace; The first source-drain layer includes a second reset line, and the second reset line is connected between the first reset line and the fourth active pattern.

12. The display panel according to claim 11, characterized in that: The first active layer includes a fifth active pattern of the reset transistor, and the fifth active pattern is connected to an end of the second active pattern away from the first active pattern; The first metal layer includes a first gate control connection line for transmitting the second gate control signal, a portion of the first gate control connection line overlaps with a channel portion of the fifth active pattern, and the first gate control connection line is located between the first light emitting control trace and the third active pattern and the fourth active pattern; The third metal layer includes a first reset connection line; The first source and drain layer includes a second light-emitting control routing, a second light-emitting control connecting line, a second gate control routing, a second gate control connecting line and a second reset connecting line, the second light-emitting control routing is electrically connected to the first light-emitting control routing, the second light-emitting control connecting line is electrically connected to the first light-emitting control connecting line, the second gate control routing is connected to the first gate control routing, the second gate control routing is connected between the two first gate control connecting lines, and the second reset connecting line is connected between the first reset connecting line and the fifth active pattern.

13. The display panel according to claim 6, characterized in that: The second metal layer includes a first scan line and a first scan connection line; the display panel includes: a second active layer, the second active layer being located on the second metal layer and comprising a sixth active pattern of the data transistor, a seventh active pattern of the compensation transistor, and an eighth active pattern of the initial transistor; A third metal layer, located between the second active layer and the first source / drain layer, comprising a second scan wiring and a second scan connection line; Part of the first scan routing line and part of the second scan routing line overlap with the channel portion of the sixth active pattern, and part of the first scan connecting line and part of the second scan connecting line overlap with the channel portion of the seventh active pattern and the channel portion of the eighth active pattern.

14. The display panel according to claim 13, characterized in that: The first metal layer includes the first initial line, the second source-drain layer includes the data line; the first source-drain layer includes: a first electrode connecting portion connected between the seventh active pattern and the first electrode; a second electrode connecting portion connected between the sixth active pattern and the second electrode; a third electrode connecting portion connected between the sixth active pattern and the data line; a fourth electrode connecting portion connected between the seventh active pattern and the first active pattern and the second active pattern; The fifth electrode connecting portion is connected between the eighth active pattern and the first initial line.

15. The display panel according to claim 6, characterized in that: The first metal layer includes a third electrode, the third electrode is located between the two first electrodes, and the third electrode partially overlaps with the two second electrodes; The first source-drain layer includes a second power connection portion, the second power connection portion partially overlaps with the third electrode, and the second power connection portion is electrically connected between the first power line and the third electrode.

16. The display panel according to claim 3, characterized in that: The first sub-pixel and the second sub-pixel emit different colors of light.

17. A display device, characterized in that: It comprises the display panel as claimed in any one of claims 1 to 16.

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