Gate driving circuit, driving method, goa circuit, and display device

Abstract

The application provides a gate driving circuit, a driving method, a GOA circuit and a display device, and relates to the display field.The gate driving circuit comprises: an output circuit comprising a first switch tube connected to a first power signal end and a second switch tube connected to a second power signal end; a first control circuit connected to the gate of the first switch tube, used for receiving a first clock signal and an input signal to control the switching of the first switch tube; a second control circuit connected to the gate of the second switch tube, used for receiving the first clock signal, a second clock signal and the input signal to control the switching of the second switch tube; and a potential holding circuit connected to the gate of the second switch tube, used for receiving the second clock signal and a control signal; under the action of multiple signals, the output circuit is used for outputting a reset control signal or a data control signal of a pixel circuit.The gate driving circuit provided by the scheme has better performance.

Description

Technical Field

[0001] This application relates to the field of display, and more specifically, to gate drive circuits, drive methods, GOA circuits, and display devices. Background Technology

[0002] In the display field, the driving mechanism of a display screen typically includes row driving circuits and column driving circuits. The row driving circuit, also known as the scan driving circuit or gate driving circuit, is used to select each row of pixels in the display screen. The column driving circuit, also known as the data driving circuit or source driving circuit, is used to provide data to the selected row pixels in the display screen. In some technologies, both the row driving circuit and the column driving circuit are implemented using separate driving chips.

[0003] With the innovation and development of display technology, Gate On Array (GOA) has emerged. Currently, GOA is being used more and more widely in displays, especially for large-size, narrow-bezel displays. Therefore, how to improve the overall performance of GOA to further optimize displays is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit, driving method, GOA circuit, and display device, which have better overall performance.

[0005] In a first aspect, a gate driving circuit is provided, comprising: a first control circuit, a second control circuit, a potential holding circuit, and an output circuit; the output circuit includes a first switching transistor connected to a first power supply signal terminal and a second switching transistor connected to a second power supply signal terminal, and the output circuit is used to output a first level signal or a second level signal; the first control circuit is connected to the gate of the first switching transistor and is used to receive a first clock signal and an input signal to control the turning on and off of the first switching transistor, wherein the input signal is a frame start signal or an output signal of a previous stage gate driving circuit; the second control circuit is connected to the gate of the second switching transistor and is used to receive the first clock signal... The system receives a first clock signal, a second clock signal, and an input signal to control the turn-on and turn-off of the second switch. The first clock signal and the second clock signal have a phase difference of at least one unit time. A potential holding circuit is connected to the gate of the second switch to receive the second clock signal and the control signal. Under the action of the input signal, the first clock signal, the second clock signal, and the control signal, the output circuit outputs a reset control signal or a data control signal for the pixel circuit. The effective levels of the reset control signal and the data control signal are opposite, and the duration of the effective level in the data control signal is twice the duration of the effective level in the reset control signal.

[0006] The technical solution of this application provides a gate driving circuit that can output both a reset control signal Reset_P and a data control signal Gate_N for the pixel circuit. In practical applications, the same gate driving circuit can receive the same input signal STV to generate two control signals for the pixel circuit, thereby reducing the circuit complexity and space required for the gate driving part of the display screen, which is beneficial to the development and application of low power consumption and narrow bezels in the display screen. Simultaneously, this gate driving circuit also includes a potential holding circuit, which can effectively stabilize the gate voltage of the second switching transistor, improve the quality of the control signal output by the gate driving circuit, and thus improve the driving effect and display performance of the display screen.

[0007] In some possible implementations, the gate driving circuit is an odd-numbered driving circuit in the GOA circuit, the control signals received by the potential holding circuit include a first power supply signal and a second power supply signal, and the output circuit is used to output a reset control signal for the pixel circuit; or, the gate driving circuit is an even-numbered driving circuit in the GOA circuit, the control signals received by the potential holding circuit include a frame start signal and the output signal of the previous stage gate driving circuit, and the output circuit is used to output a data control signal for the pixel circuit.

[0008] The technical solution of this application embodiment uses two power supply signals as control signals for odd-numbered stage drive circuits, ensuring that the output reset control signal Reset_P is VGH for an extended period. The control signals for even-numbered stages are the frame start signal and the output signal from the preceding stage gate drive circuit, ensuring that the output data control signal Gate_N is VGL for an extended period. This solution not only effectively guarantees the signal quality of the output Reset_P and Gate_N signals, but also allows for the reuse of existing signal lines for the control signals, without incurring additional space loss.

[0009] In some possible implementations, the GOA circuit containing the gate driving circuit has three corresponding clock signal terminals, each of which is at least one unit time apart in phase. The gate driving circuit is the i-th driving circuit in the GOA circuit, and the i-th driving circuit is connected to the first and second clock signal terminals among the three clock signal terminals. Alternatively, the gate driving circuit is the (i+1)-th driving circuit in the GOA circuit, and the i-th driving circuit is connected to the second and third clock signal terminals among the three clock signal terminals, where i is a positive integer.

[0010] The GOA circuit formed by the cascaded gate drive circuits, according to the technical solution of this application, requires only three clock signal input terminals. Each gate drive circuit receives two of these three clock signal input terminals, and the clock signals of two adjacent gate drive circuits have a phase difference of at least one unit of time. Compared to related technologies where the GOA circuit requires four or more clock signal input terminals, the reduced number of clock signal input terminals in this application's embodiment helps to further compress the space occupied by the GOA circuit, thereby reducing the bezel space of the display screen.

[0011] In some possible implementations, the first control circuit includes: a third switching transistor and a first capacitor; the first capacitor is connected to the first power supply signal terminal and the drain of the third switching transistor; the gate of the third switching transistor is used to receive a first clock signal, and the source of the third switching transistor is used to receive an input signal.

[0012] Through the technical solution of this embodiment, the circuit structure of the first control circuit is relatively simple, consisting of only one switching transistor and one capacitor. While ensuring the switching state of the first switching transistor, it helps to reduce the circuit complexity of the gate drive circuit, improve the signal quality of the output signal, and further compress the space required by the gate drive circuit.

[0013] In some possible implementations, the capacitance value of the first capacitor is greater than 0 and less than or equal to 200F.

[0014] In this embodiment, the capacitance value of the first capacitor is smaller than that of the gate drive circuit provided by related technologies, which can further save the space required by the gate drive circuit.

[0015] In some possible implementations, the second control circuit includes: a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, and a second capacitor; the gate of the fourth switch is used to receive a first clock signal, the source of the fourth switch is connected to a second power supply signal terminal, and the drain of the fourth switch is connected to the gate of the fifth switch; the source of the fifth switch is used to receive a second clock signal, and the drain of the fifth switch is connected to the source of the sixth switch; the second capacitor is connected between the gate and drain of the fifth switch; the gate of the sixth switch is used to receive the second clock signal, and the drain of the sixth switch is connected to the gate of the second switch; the gate of the seventh switch is used to receive an input signal, the source of the seventh switch is used to receive the first clock signal, and the drain of the seventh switch is connected to the gate of the fifth switch; the gate of the eighth switch is used to receive an input signal, the source of the eighth switch is connected to the first power supply signal terminal, and the drain of the eighth switch is connected to the gate of the second switch.

[0016] The technical solution of this embodiment has a relatively simple circuit structure for the second control circuit, consisting of five switching transistors and one capacitor. While ensuring the switching state of the second switching transistor, it helps to reduce the circuit complexity of the gate drive circuit, improve the signal quality of the output signal, and further reduce the space required by the gate drive circuit.

[0017] In some possible implementations, the capacitance value of the second capacitor is greater than 0 and less than or equal to 100f.

[0018] In this embodiment, the capacitance value of the second capacitor is smaller than that of the gate drive circuit provided by related technologies, which can further save the space required by the gate drive circuit.

[0019] In some possible implementations, the potential holding circuit includes: a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, and a third capacitor; the gate of the ninth switch is used to input a first control signal, the source of the ninth switch is connected to a first power supply signal terminal, and the drain of the ninth switch is connected to the drain of the tenth switch; the gate of the tenth switch is used to input a second control signal, and the source of the tenth switch is connected to a second power supply signal terminal; the gate of the eleventh switch is connected to the drains of the ninth and tenth switches, the source of the eleventh switch is used to input a second clock signal, and the drain of the eleventh switch is connected to the source of the twelfth switch; the gate of the twelfth switch is connected to the gate of the second switch, and the third capacitor is connected between the gate of the twelfth switch and the drain of the twelfth switch.

[0020] In this embodiment, a potential holding circuit is provided in the gate driving circuit. The control signal input to the potential holding circuit can be adjusted according to the number of stages of the gate driving circuit in the GOA circuit, so that the potential holding circuit can flexibly control the voltage of the second switching transistor according to the output control signal requirements, so as to ensure that the reset control signal Reset_P output by the odd-numbered stage gate driving circuit is VGH for a long time, and the data control signal Gate_N output by the even-numbered stage gate driving circuit is VGL for a long time.

[0021] In some possible implementations, the capacitance value of the third capacitor is greater than 0 and less than or equal to 50f.

[0022] In this embodiment, the capacitance value of the third capacitor is smaller than that of the gate drive circuit provided by related technologies, which can further save the space required by the gate drive circuit.

[0023] In some possible implementations, the rise time of the reset control signal is less than or equal to 408.1 ns and the fall time of the reset control signal is less than or equal to 1.142 μs; and / or, the rise time of the data control signal is less than or equal to 558.1 ns and the fall time of the data control signal is less than or equal to 1.167 μs.

[0024] In this embodiment, the rise time and fall time of the reset control signal Reset_P or data control signal Gate_N output by the gate drive circuit are both small, and less than the 2us to 3us level in related technologies. Therefore, the signal quality output by the gate drive circuit is better, with no output step, which is beneficial to improving the driving effect on the display screen and thus improving the display effect of the display screen.

[0025] In a second aspect, a driving method for a gate driving circuit is provided, used to drive the gate driving circuit in the first aspect or any possible embodiment of the first aspect. The driving method includes: inputting a first clock signal and an input signal to a first control circuit in the gate driving circuit to control the state of a first switch in the output circuit through the first control circuit, so that the gate driving circuit outputs a first level signal; inputting a first clock signal, a second clock signal, and an input signal to a second control circuit in the gate driving circuit to control the state of a second switch in the output circuit through the second control circuit, so that the gate driving circuit outputs a second level signal; and inputting a second clock signal and a control signal to a potential holding circuit in the gate driving circuit to hold the gate voltage of the second switch through the potential holding circuit, so that the gate driving circuit holds the output voltage.

[0026] In some possible implementations, the gate driving circuit is an odd-numbered stage driving circuit in the GOA circuit; in the first stage, the first clock signal and the input signal are at a second level, the second clock signal is at a first level, and the gate driving circuit outputs a first-level signal; in the second stage, the second clock signal and the input signal are at a second level, the first clock signal is at a first level, and the gate driving circuit outputs a first-level signal; in the third stage, the input signal is at a second level, the first clock signal and the second clock signal are at a first level, and the gate driving circuit outputs a first-level signal; in the fourth stage, the first clock signal is at a second level, the input signal and the second clock signal are at a first level, and the gate driving circuit outputs a first-level signal; in the fifth stage, the second clock signal is at a second level, the first clock signal and the input signal are at a first level, and the gate driving circuit outputs a second-level signal; in the sixth stage, the first clock signal, the second clock signal, and the input signal are at a first level, and the gate driving circuit outputs a second-level signal.

[0027] In some possible implementations, the gate driving circuit is an even-numbered stage driving circuit in the GOA circuit; in the first stage, the first clock signal and the input signal are at a second level, the second clock signal is at a first level, and the gate driving circuit outputs a first-level signal; in the second stage, the second clock signal and the input signal are at a second level, the first clock signal is at a first level, and the gate driving circuit outputs a first-level signal; in the third stage, the input signal, the first clock signal, and the second clock signal are at a first level, and the gate driving circuit outputs a first-level signal; in the fourth stage, the first clock signal is at a second level, the input signal and the second clock signal are at a first level, and the gate driving circuit outputs a first-level signal; in the fifth stage, the second clock signal is at a second level, the input signal and the first clock signal are at a first level, and the gate driving circuit outputs a second-level signal; in the sixth stage, the input signal, the first clock signal, and the second clock signal are at a first level, and the gate driving circuit outputs a second-level signal.

[0028] Thirdly, a GOA circuit is provided, comprising: at least two cascaded gate drive circuits provided in the first aspect or any possible implementation of the first aspect.

[0029] In some possible implementations, the reset control signal and data control signal generated by two cascaded adjacent gate drive circuits in the GOA circuit are used as inputs to two adjacent rows of pixel units in the display device; and / or, the GOA circuit includes two GOA sub-circuits, each GOA sub-circuit including at least two cascaded gate drive circuits, and each GOA sub-circuit is used to drive half of the pixel units in the display device.

[0030] Fourthly, a display device is provided, comprising: a GOA circuit provided in the third aspect or any possible embodiment of the third aspect.

[0031] Through the technical solutions of the embodiments of this application, the GOA circuit set in the display device has lower circuit complexity, requires less space, and has better output control signal quality, which is conducive to the development and application of low power consumption and narrow bezels in display devices, and also helps to improve the driving effect and display performance of display devices. Attached Figure Description

[0032] Figure 1 This is a schematic circuit diagram of a display screen to which this application applies.

[0033] Figure 2 This is a schematic architecture diagram of a scanning drive circuit provided in an embodiment of this application.

[0034] Figure 3 This is a schematic circuit diagram of a pixel circuit provided in an embodiment of this application.

[0035] Figure 4 yes Figure 3 The diagram shows a schematic timing diagram of multiple control signals in the pixel circuit shown.

[0036] Figure 5 This is a schematic block diagram of a gate driving circuit provided in an embodiment of this application.

[0037] Figure 6 This is a schematic block diagram of a GOA circuit composed of multiple cascaded gate drive circuits provided in the embodiments of this application.

[0038] Figure 7 This is a schematic waveform diagram of the three clock signal terminals CLKA, CLKB and CLKC provided in the embodiments of this application.

[0039] Figure 8 This is a schematic circuit diagram of a gate driving circuit provided in an embodiment of this application.

[0040] Figure 9 This is a schematic flowchart of a driving method for a gate driving circuit provided in an embodiment of this application.

[0041] Figure 10 This is a signal timing diagram of the odd-numbered gate drive circuit in the GOA circuit provided in the embodiments of this application.

[0042] Figures 11 to 16 This is a schematic diagram of the switching states of the odd-numbered gate drive circuit in the GOA circuit provided in this application, from the first stage to the sixth stage.

[0043] Figure 17 This is a signal timing diagram of the even-numbered gate drive circuit in the GOA circuit provided in the embodiments of this application.

[0044] Figures 18 to 23 This is a schematic diagram of the switching state of the even-numbered gate drive circuit in the GOA circuit provided in this application, from the first stage to the sixth stage.

[0045] Figure 24 A schematic waveform diagram of a GOA circuit formed by cascading multiple gate drive circuits is shown.

[0046] Figure 25 This is a schematic structural block diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0047] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0048] This application relates to a display screen, or display device. The display screen can be applied to various fields and scenarios. For example, it can be applied to 3C electronic products in the fields of computers, communications, and consumer electronics, including but not limited to televisions, mobile phones, computers, laptops, tablets, personal digital assistants (PDAs), in-vehicle computers, wearable devices, gaming devices, and photographic equipment. This application does not limit the specific type of electronic device in which the display screen is located.

[0049] In addition, the display screen involved in this application may be a liquid crystal display (LCD), an organic light-emitting diode (OLED) display screen, a quantum dot light-emitting diode (QLED) display screen, etc. This application does not limit the specific type of display screen.

[0050] Figure 1 A schematic circuit diagram of a display screen 100 to which this application applies is shown.

[0051] like Figure 1 As shown, the display screen 100 includes a pixel array 110, a scanning driving circuit 120, and a data driving circuit 130. The pixel array 110 includes multiple pixel units 111, which can be arranged in N rows and M columns according to actual needs to form the display area of ​​the display screen 100 and present different display effects.

[0052] For OLED displays, each pixel unit 111 may include an independent light-emitting unit and a pixel circuit for controlling the light-emitting unit. The light-emitting unit may include organic light-emitting materials of red, green, and blue colors. The light-emitting material emits light through current-driven illumination, forming a colored pixel. The pixel circuit may include electrical components such as switching transistors and capacitors. Controlling the state of the switching transistors through control signals can effectively drive the light-emitting unit.

[0053] While other types of displays each have their own light-emitting principles, each pixel unit 111, regardless of its type, contains a pixel circuit to control the light emission of each pixel unit 111. The scan drive circuit 120 and the data drive circuit 130 can be connected to each pixel unit 111 in the pixel array 110, thereby providing control signals to the pixel circuit of each pixel unit. Specifically, for N rows and M columns of pixel units 111, the scan drive circuit 120 can be connected to the N rows of pixel units 111 to control the turning on and off of the N rows of pixel units 111. The data drive circuit 130 can be connected to the M columns of pixel units 111 to provide display data to the M columns of pixel units.

[0054] Optionally, such as Figure 1 As shown, the display screen 100 may further include a timing control circuit 140, which may also be referred to as a timing controller (TCON), and can be connected to the scan drive circuit 120 and / or the data drive circuit 130. The timing control circuit 140 can receive display control signals and control the operating timing of the scan drive circuit 120 and / or the data drive circuit 130 according to the display control signals, and can control the display data of the data drive circuit 130. The display control signals include, but are not limited to, power signals, image signals, mode control signals, etc.

[0055] In some embodiments of this application, the data driving circuit 130 can be a source driver or a source driver IC, and the data driving circuit 130 can be separately disposed from the display panel 101 where the pixel array 110 is located. The display panel 101 may have different structures depending on the type of display screen 100, but generally speaking, the substrate of the display panel is a transparent substrate such as glass or plastic. The pixel circuit of the pixel array 110 can be formed on the substrate by semiconductor technology, and then combined with other components to form the light-emitting unit of the pixel array 110, thus forming the main part of the display panel 101 of the display screen 100. The specific structure of the display panel 101 can be found in the detailed description of related technologies, and will not be elaborated here.

[0056] In some embodiments of this application, the scan driving circuit 120 can be a gate driver or a gate driver IC independent of the display panel 101. Alternatively, as... Figure 1 As shown, the scanning drive circuit 120 can also be integrated into the display panel 101. The scanning drive circuit 120 can be called the GOA circuit. The GOA circuit can be fabricated on the transparent substrate synchronously with the pixel circuit of the pixel array 110, thus simplifying the manufacturing process of the display screen 100.

[0057] As an example, Figure 2 A schematic diagram of a scan drive circuit 120 is shown.

[0058] like Figure 2 As shown, the scan driving circuit 120 includes multiple cascaded gate driving circuits 121. The input signal of the first-stage gate driving circuit 121 includes a Start of Video Frame (STV) signal. The output signal SCAN[1] of the first-stage gate driving circuit 121 can drive the first row of pixel units of the display device and can also be used as the input signal of the second-stage gate driving circuit 121. Similarly, the scan driving circuit 120 may include at least N cascaded gate driving circuits 121. The output signal SCAN[N] of the Nth-stage gate driving circuit 121 can drive the Nth row of pixel units of the display device.

[0059] Understandable, Figure 2 Only a portion of the signals in the scan drive circuit 120 are illustrated. In addition to the STV, the scan drive circuit 120 also requires clock signals, power signals, and other signals. For details on the technical solution of the scan drive circuit formed by cascading multiple gate drive circuits 121, please refer to the specific descriptions in related technologies; further elaboration is not provided here.

[0060] As an example, Figure 3 A schematic circuit diagram of a pixel circuit 200 provided in an embodiment of this application is shown.

[0061] like Figure 3 As shown, the pixel circuit 200 includes eight switching transistors T1 to T8 and one capacitor Cst, so the pixel circuit 200 can be called an 8T1C circuit.

[0062] The pixel circuit 200 has multiple input power signals, control signals, and data signals. The power signals include: a high-level power signal VDD, a low-level power signal VSS, a first reset power signal Vinit1, a second reset power signal Vinit2, and a third reset power signal Vinit3. The data signal Date can be obtained from the above... Figure 1 The data driving circuit 130 shown in the illustrated embodiment generates the data. The control signals include: an emission control signal EM, a first reset control signal Reset_P, a second reset control signal ResetH_P, a first gate control signal Gate_N, and a second gate control signal Gate_P. These multiple control signals can be generated by the above-described... Figure 1 and Figure 2 The scanning drive circuit 120 shown in the embodiment generates the multiple control signals, which can control the state of different switching transistors in the pixel circuit 200 to control the light emission process of the pixel circuit 200.

[0063] Figure 4 It shows Figure 3 This is a schematic timing diagram of multiple control signals in the pixel circuit 200 shown. Figure 4 The control timing of each control signal shown can enable the pixel circuit 200 to enter the initialization stage t1, compensation stage t2, data writing stage t3, and light emission stage t4 respectively, thus completing the periodic pixel light emission.

[0064] See Figure 4 As shown, among the multiple control signals, the first reset control signal Reset_P mainly controls the switching state of the switching transistor T1, thereby controlling whether the first reset power supply signal Vinit1 resets the anode of the light-emitting unit. The first gate control signal Gate_N mainly controls the switching state of the switching transistor T2, thereby controlling whether the data signal Data can be written to the anode of the light-emitting unit so that the light-emitting unit emits light.

[0065] The effective level of the first reset control signal Reset_P is low, and the effective level of the first gate control signal Gate_N is high. Furthermore, the duration of the effective level of the first gate control signal Gate_N is twice the duration of the effective level of the first reset control signal Reset_P. For example, the first reset control signal Reset_P is a pulse signal with a low width of 4H, and the first gate control signal Gate_N is a pulse signal with a high width of 8H. Here, H represents a unit of time, which is the on-time of each row of pixel units. In this application, 1H is one unit of time, 4H is two units of time, and 8H is eight units of time.

[0066] As an example, Figure 3 and Figure 4 Only one 8T1C pixel circuit and its corresponding control timing diagram are shown. It is understood that the pixel circuit can be of various other structures besides the 8T1C structure, such as 7T1C, 7T3C, etc. This application does not limit the specific structure of the pixel circuit in its embodiments. In addition to the above... Figure 3 Besides the 8T1C pixel circuit shown, other conventional pixel circuits typically require the aforementioned first reset control signal Reset_P and first gate control signal Gate_N to control the state of the pixel circuit. For ease of description, the first reset control signal Reset_P will be simply referred to as the reset control signal Reset_P, and the first gate control signal Gate_N will be referred to as the data control signal Gate_N.

[0067] In some related technologies, the reset control signal Reset_P and the data control signal Gate_N need to be generated separately by two sets of gate driving circuits, and require a large number of input signals. The complex gate driving circuit will result in high power consumption and occupy a large space of the display panel, which is not conducive to the optimization of the overall performance of the display. In view of this, this application provides a novel gate driving circuit with a superior circuit structure, which can provide both the reset control signal Reset_P and the data control signal Gate_N to the pixel circuit, thereby reducing the design complexity of the gate driving circuit and the space required.

[0068] Figure 5 A schematic structural block diagram of a gate driving circuit 300 provided in an embodiment of this application is shown.

[0069] like Figure 5 As shown, the gate drive circuit 300 includes: a first control circuit 310, a second control circuit 320, a potential holding circuit 330, and an output circuit 340.

[0070] The output circuit 340 includes a first switching transistor 341 connected to the first power signal terminal and a second switching transistor 342 connected to the second power signal terminal. The output circuit 340 is used to output a first level signal or a second level signal.

[0071] The first control circuit 310 is connected to the gate of the first switching transistor 341 and is used to receive the first clock signal CLK1 and the input signal to control the first switching transistor 341 to turn on and off. The input signal is the frame start signal STV or the output signal of the previous stage gate driving circuit (e.g., the output signal Out[n-1] of the previous stage gate driving circuit).

[0072] The second control circuit 320 is connected to the gate of the second switch 342 and is used to receive the first clock signal CLK1, the second clock signal CLK2 and the input signal to control the turn-on and turn-off of the second switch 342. The first clock signal CLK1 and the second clock signal CLK2 have a phase difference of at least one unit time.

[0073] The potential holding circuit 330 is connected to the gate of the second switching transistor 342 and is used to receive the second clock signal CLK2 and the control signal Control. The potential holding circuit 330 can work with the second control circuit 320 to maintain the gate voltage of the second switching transistor 342.

[0074] Under the action of the aforementioned input signal, the first clock signal CLK1, the second clock signal CLK2, and the control signal Control, the output circuit 340 outputs the reset control signal Reset_P or the data control signal Gate_N of the pixel circuit. The effective levels of the reset control signal Reset_P and the data control signal Gate_N are opposite, and the duration of the effective level in the data control signal Gate_N is twice the duration of the effective level in the reset control signal Reset_P.

[0075] In this embodiment, the output circuit 340 consists of two series-connected switching transistors, which are respectively connected to a first power signal terminal and a second power signal terminal. The first power signal terminal and the second power signal terminal provide different power levels. Optionally, in some embodiments, the first power signal terminal and the second power signal terminal can be a high-level power signal terminal and a low-level power signal terminal, respectively, wherein the high-level power signal terminal can provide a constant positive voltage signal, and the low-level power signal terminal can provide a constant negative voltage signal.

[0076] The switching transistors in this application can be, for example, thin-film transistors (TFTs), field-effect transistors (FETs), or other switching devices with different characteristics. The field-effect transistors include, but are not limited to, metal-oxide-semiconductor FETs (MOSFETs). The specific type of switching transistor in this application can be adjusted according to actual needs.

[0077] In some implementations, the switching transistor can be a low-temperature polycrystalline silicon (LTPS) TFT, an oxide thin-film transistor (TFT), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the TFT is made of oxide semiconductors, such as indium gallium zinc oxide (IGaZN) or indium gallium tin oxide (IGaT). LTPS TFTs offer advantages such as high mobility and fast charging, while TFTs offer advantages such as low leakage current. Integrating LTPS and TFTs onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both to achieve low-frequency driving, reduce power consumption, and improve display quality.

[0078] In the gate drive circuit provided in the embodiments of this application, each of the switching transistors can be a P-type transistor. Alternatively, each of the switching transistors can be an N-type transistor. Alternatively, a portion of each switching transistor can be a P-type transistor and the other portion can be an N-type transistor.

[0079] In the output circuit 340, the gate of the first switching transistor 341 can be connected to the first control circuit 310, which can be used to control the switching on and off of the first switching transistor 341. The gate of the second switching transistor 342 can be connected to the second control circuit 320 and the potential holding circuit 330, which together control the switching on and off of the second switching transistor 342.

[0080] The source of the first switching transistor 341 can be connected to the first power signal terminal, and the source of the second switching transistor 342 can be connected to the second power signal terminal. The drains of the first switching transistor 341 and the drains of the second switching transistor 342 are connected to each other and are used as the output terminal of the output circuit 340.

[0081] The first control circuit 310 can be used to receive the first clock signal CLK1 and the input signal to generate a drive signal to control the first switching transistor 341. In the case where the gate drive circuit 300 is the first-stage drive circuit of the display screen, its input signal is STV. In the case where the gate drive circuit 300 is not the first-stage drive circuit of the display screen, its input signal is the output signal Out[n-1] of the previous stage drive circuit.

[0082] The second control circuit 320 can be used to receive the first clock signal CLK1, the second clock signal CLK2, and the above-mentioned input signal to generate a drive signal to control the second switch 342. The first clock signal CLK1 and the second clock signal CLK2 have a phase difference of at least one unit time, that is, a phase difference of 1H.

[0083] Optionally, in this embodiment of the application, the pulse period and pulse width of the first clock signal CLK1 and the second clock signal CLK2 are the same, and the second clock signal CLK2 may lag behind the first clock signal CLK1 by 1 pulse width, which may be 1H or 2H.

[0084] In addition to the first control circuit 310 and the second control circuit 320, the gate drive circuit 300 provided in this application embodiment may also include a potential holding circuit 330. The potential holding circuit 330 can be used to receive the second clock signal CLK2 and the control signal to generate a potential holding signal for the second switch 342, so as to cooperate with the second control circuit 320 to hold the gate electrode of the second switch 342, thereby stabilizing the output signal of the output circuit 340.

[0085] The technical solution of this application provides a gate driving circuit 300 that can output both a reset control signal Reset_P and a data control signal Gate_N for the pixel circuit. In practical applications, the same gate driving circuit 300 can receive the same input signal STV to generate two control signals for the pixel circuit, thereby reducing the circuit complexity and space required for the gate driving part of the display screen, which is beneficial to the development and application of low power consumption and narrow bezels in the display screen. Simultaneously, the gate driving circuit 300 also includes a potential holding circuit 330, which can effectively stabilize the gate voltage of the second switching transistor 342, improve the quality of the control signal output by the gate driving circuit 300, and thus improve the driving effect and display performance of the display screen.

[0086] Figure 6 A schematic structural block diagram of a GOA circuit 400 composed of multiple cascaded gate drive circuits 300 provided in an embodiment of this application is shown.

[0087] like Figure 6 As shown, in the GOA circuit 400, the output signal of the previous stage gate drive circuit is used as the input signal of the next stage gate drive circuit to form a cascaded structure. The input signal of the first stage gate drive circuit is the STV signal. In this GOA circuit 400, the odd-numbered drive circuit (or the odd-numbered drive circuit) can be used to output the reset control signal Reset_P of the pixel circuit, and the even-numbered drive circuit (or the even-numbered drive circuit) can be used to output the data control signal Gate_N of the pixel circuit.

[0088] In addition, from Figure 6 It can also be seen that the clock signals input to adjacent odd-numbered and even-numbered driving circuits are different, and the control signals input to odd-numbered and even-numbered driving circuits are different. The odd-numbered driving circuit is connected to the control signal terminal ControlA, which includes a first power signal terminal and a second power signal terminal. In the odd-numbered driving circuit, the control signals received by its potential-holding circuit include a first power signal and a second power signal. For example, the first power signal and the second power signal can be a high-level power signal VGH and a low-level power signal VGL, respectively. The even-numbered driving circuit is connected to the control signal terminal ControlB, which includes a frame start signal terminal and an output signal terminal of the previous stage gate driving circuit. In the even-numbered driving circuit, the control signals received by its potential-holding circuit include a frame start signal STV and the output signal of the previous stage gate driving circuit (e.g., the output signal Out[n-1] of the previous stage gate driving circuit).

[0089] The technical solution of this application embodiment uses a first power supply signal and a second power supply signal as control signals for odd-numbered driving circuits, ensuring that the output reset control signal Reset_P is VGH for an extended period. The control signals for even-numbered stages are the frame start signal and the output signal of the preceding gate driving circuit, ensuring that the output data control signal Gate_N is VGL for an extended period. This solution not only effectively guarantees the signal quality of the output Reset_P and Gate_N signals, but also allows for the reuse of existing signal lines for the control signals, without incurring additional space loss.

[0090] See also Figure 6 As shown, the GOA circuit 400 has three corresponding clock signal terminals CLKA, CLKB and CLKC, and the three clock signal terminals are phased by at least one unit of time between each pair.

[0091] As an example, Figure 7 A schematic waveform diagram of the three clock signal terminals CLKA, CLKB, and CLKC is shown.

[0092] like Figure 7 As shown, the three clock signal terminals CLKA, CLKB, and CLKC provide three clock signals with the same pulse period, and the duration of the effective level of a single pulse in each of the three clock signals is the same. For example, if the effective level duration of a single clock pulse is 2H, then the pulse period of the clock signal is 6H, and there is a 2H phase difference between each pair of the three clock signals.

[0093] In the GOA circuit 400, the i-th driving circuit is connected to the first clock signal terminal CLKA and the second clock signal terminal CLKB among the three clock signal terminals CLKA, CLKB, and CLKC. The (i+1)-th driving circuit is connected to the second clock signal terminal CLKB and the third clock signal terminal CLKC among the three clock signal terminals CLKA, CLKB, and CLKC. The (i+2)-th driving circuit is connected to the third clock signal terminal CLKC and the first clock signal terminal CLKA among the three clock signal terminals CLKA, CLKB, and CLKC. Similarly, other driving circuits in the GOA circuit 400 can also be connected to two of the three clock signal terminals CLKA, CLKB, and CLKC in the above manner to receive the first clock signal CLK1 and the second clock signal CLK2.

[0094] The GOA circuit formed by the cascaded gate drive circuits, according to the technical solution of this application, requires only three clock signal input terminals. Each gate drive circuit receives two of these three clock signal input terminals, and the clock signals of two adjacent gate drive circuits have a phase difference of at least one unit of time. Compared to related technologies where the GOA circuit requires four or more clock signal input terminals, the reduced number of clock signal input terminals in this application's embodiment helps to further compress the space occupied by the GOA circuit, thereby reducing the bezel space of the display screen.

[0095] Figure 8 A schematic circuit diagram of a gate drive circuit 300 provided in an embodiment of this application is shown. As an example, this embodiment uses P-type transistors as examples where all switching transistors in the gate drive circuit are P-type transistors. When the switching transistors are N-type transistors, their gate drive waveforms can be reversed compared to the drive waveforms of the P-type transistors, thus achieving the same switching effect.

[0096] like Figure 8 As shown, the gate drive circuit 300 may include a first switch T1 and a second switch T2. The source of the first switch T1 is used to input a first power supply signal. As an example, the first power supply signal shown in the figure is a high-level power supply signal VGH, and its drain is connected to the drain of the second switch T2. Its gate node is shown as N1 in the figure. The source of the second switch T2 is used to input a second power supply signal. As an example, the second power supply signal shown in the figure is a low-level power supply signal VGL, and its gate node is shown as N4 in the figure.

[0097] It is understood that these two switching transistors can constitute the output circuit 340 in the above embodiment. For the specific types of switching transistors involved in the embodiments of this application, please refer to the relevant descriptions in the above embodiments.

[0098] In addition, the first power signal can also provide... Figure 8 In addition to the high-level power supply signal VGH shown, the second power supply signal can also be a low-level power supply signal VGL; correspondingly, the second power supply signal can be... Figure 8 In addition to the low-level power supply signal VGL shown, it can also be a high-level power supply signal VGH.

[0099] In addition to the first switch T1 and the second switch T2, the gate drive circuit 300 provided in this application embodiment may also include a third switch T3 and a first capacitor C1, wherein the first capacitor C1 is connected to the first power supply signal terminal and the drain of the third switch T3, the gate of the third switch T3 is used to receive the first clock signal CLK1, and the source of the third switch T2 is used to receive the input signal STV or Out[n-1].

[0100] The third switch T3 and the first capacitor C1 can form the first control circuit 310 in the above embodiment, which is used to control the voltage of the gate node N1 of the first switch T1, thereby controlling the turn-on and turn-off of the first switch T1.

[0101] Through the technical solution of this embodiment, the circuit structure of the first control circuit 310 is relatively simple, consisting of only one switching transistor and one capacitor. While ensuring the switching state of the first switching transistor T1, it helps to reduce the circuit complexity of the gate drive circuit, improve the signal quality of the output signal, and further compress the space required by the gate drive circuit.

[0102] In some embodiments, the capacitance value of the first capacitor C1 may be greater than 0 and less than or equal to 200f. For example, the capacitance value of the first capacitor C1 may be 90f. This capacitance value is smaller than the capacitance value in the gate drive circuit provided by related technologies, which can further save the space required by the gate drive circuit.

[0103] See also Figure 8 The gate drive circuit 300 may also include a fourth switch T4, a fifth switch T5, a sixth switch T6, a seventh switch T7, an eighth switch T8, and a second capacitor C2.

[0104] The gate of the fourth switch T4 is used to receive the first clock signal CLK1, the source of the fourth switch T4 is connected to the second power supply signal terminal, and the drain of the fourth switch T4 is connected to the gate of the fifth switch T5.

[0105] The source of the fifth switch transistor T5 is used to receive the second clock signal CLK2. The drain of the fifth switch transistor T5 is connected to the source of the sixth switch transistor T6. The second capacitor C2 is connected between the gate and drain of the fifth switch transistor T5.

[0106] The gate of the sixth switch T6 is used to receive the second clock signal CLK2, and the drain of the sixth switch T6 is connected to the gate of the second switch T2.

[0107] The gate of the seventh switch T7 is used to receive the input signal STV or Out[n-1], the source of the seventh switch T7 is used to receive the first clock signal CLK1, and the drain of the seventh switch T7 is connected to the gate of the fifth switch T5.

[0108] The gate of the eighth switch T8 is used to receive the input signal STV or Out[n-1]. The source of the eighth switch T8 is connected to the first power supply signal terminal, and the drain of the eighth switch T8 is connected to the gate of the second switch T2.

[0109] The fourth switch T4 to the eighth switch T8, and the second capacitor C2 can form the second control circuit 320 in the above embodiment, which is used to control the voltage of the gate node N4 of the second switch T2, thereby controlling the turn-on and turn-off of the second switch T2.

[0110] Through the technical solution of this embodiment, the circuit structure of the second control circuit 320 is relatively simple, consisting of five switching transistors and one capacitor. While ensuring the switching state of the second switching transistor T2, it helps to reduce the circuit complexity of the gate drive circuit, improve the signal quality of the output signal, and further compress the space required by the gate drive circuit.

[0111] In some embodiments, the capacitance value of the second capacitor C2 may be greater than 0 and less than or equal to 100f. For example, the capacitance value of the second capacitor C2 may be 50f. This capacitance value is smaller than the capacitance value in the gate drive circuit provided by related technologies, which can further save the space required by the gate drive circuit.

[0112] See also Figure 8 The gate drive circuit 300 may also include a ninth switch T9, a tenth switch T10, an eleventh switch T11, a twelfth switch T12, and a third capacitor C3.

[0113] In this circuit, the gate of the ninth switch T9 is used to input the first control signal Control1, the source of the ninth switch T9 is connected to the first power supply signal terminal, and the drain of the ninth switch T9 is connected to the drain of the tenth switch T10.

[0114] The gate of the tenth switch transistor T10 is used to input the second control signal Control2, and the source of the tenth switch transistor T10 is connected to the second power supply signal terminal.

[0115] The gate of the eleventh switch T11 is connected to the drain of the ninth switch T9 and the drain of the tenth switch T10. The source of the eleventh switch T11 is used to input the second clock signal CLK2. The drain of the eleventh switch T11 is connected to the source of the twelfth switch T12.

[0116] The gate of the twelfth switch T12 is connected to the gate of the second switch T2, and the third capacitor C3 is connected between the gate of the twelfth switch T12 and the drain of the twelfth switch T12.

[0117] It should be noted that when the gate drive circuit 300 is an odd-numbered stage circuit in the GOA circuit, the first control signal Control1 input to the gate of the ninth switch T9 is VGL, and the second control signal Control2 input to the gate of the tenth switch T10 is VGH. By setting these two control signals, it can be ensured that the ninth switch T9 is on, the tenth switch T10 is off, the potential of node N5 is always VGH, the eleventh switch T11 is always off, the potential of node N6 is not affected by the transition of the second clock signal CLK2, and the potential of node N4 can be controlled by the second control circuit 320 to ensure that the reset control signal Reset_P output by the odd-numbered stage gate drive circuit is VGH for a long time.

[0118] In the case that the gate drive circuit 300 is an even-numbered stage circuit in the GOA circuit, the first control signal Control1 input to the gate of the ninth switch T9 is Out[n-1], and the second control signal Control2 input to the gate of the tenth switch T10 is STV. This ensures that when the output data control signal Gate_N is low, the ninth switch T9 is off, the tenth switch T10 is on, the N5 node potential is always VGL, the eleventh switch T11 is on, and the N6 node can be written with the potential of the second clock signal CLK2. By switching, the N4 node is kept at a negative potential or a more negative potential, thereby turning on the second switch T2 and outputting VGL.

[0119] The ninth switch T9 to the twelfth switch T12 and the third capacitor C3 can form the potential holding circuit 330 in the above embodiment, which is used to maintain the voltage of the gate node N4 of the second switch T2, thereby controlling the second switch T2 to remain in the on state.

[0120] In this embodiment, a potential holding circuit 330 is provided in the gate driving circuit 300. The control signal input to the potential holding circuit 330 can be adjusted according to the number of stages of the gate driving circuit 300 in the GOA circuit, so that the potential holding circuit 330 can flexibly control the voltage of the second switching transistor T2 according to the output control signal requirements, so as to ensure that the reset control signal Reset_P output by the odd-numbered stage gate driving circuit is VGH for a long time, and the data control signal Gate_N output by the even-numbered stage gate driving circuit is VGL for a long time.

[0121] In some embodiments, the capacitance value of the third capacitor C3 may be greater than 0 and less than or equal to 50f. For example, the capacitance value of the third capacitor C3 may be 10f. This capacitance value is smaller than the capacitance value in the gate drive circuit provided by related technologies, which can further save the space required by the gate drive circuit.

[0122] Based on the gate drive circuit 300 provided in the above embodiment, the rise time Tr of the output reset control signal Reset_P is less than or equal to 408.1 ns, and the fall time Tf of the reset control signal Reset_P is less than or equal to 1.142 μs. The rise time Tr of the output data control signal Gate_N is less than or equal to 558.1 ns, and the fall time Tf of the data control signal Gate_N is less than or equal to 1.167 μs.

[0123] The rise time and fall time of the reset control signal Reset_P or data control signal Gate_N output by the gate drive circuit 300 are both small, and less than the 2us to 3us level in related technologies. Therefore, the signal quality output by the gate drive circuit 300 is better, with no output step, which is beneficial to improving the driving effect on the display screen and thus improving the display effect.

[0124] In conjunction with the above text Figures 5 to 8 The gate drive circuit 300 shown is... Figure 9 A schematic flowchart of a driving method 500 for driving the gate driving circuit 300 is shown.

[0125] like Figure 9 As shown, the driving method 500 includes the following steps.

[0126] S510: Input a first clock signal and an input signal to the first control circuit in the gate drive circuit, so as to control the state of the first switch in the output circuit through the first control circuit, so that the gate drive circuit outputs a first level signal.

[0127] S520: Input a first clock signal, a second clock signal, and an input signal to the second control circuit in the gate drive circuit, so as to control the state of the second switch in the output circuit through the second control circuit, so that the gate drive circuit outputs a second level signal.

[0128] S530: Input a second clock signal and a control signal to the potential holding circuit in the gate drive circuit to maintain the gate voltage of the second switch through the potential holding circuit, so that the gate drive circuit maintains the output voltage.

[0129] In this embodiment of the application, the gate driving circuit 300 may have a corresponding input signal terminal, for example, Figure 6The diagram shows three clock signal terminals CLKA, CLKB, and CLKC, and control signal terminals ControlA and ControlB. ControlA includes a first power supply signal terminal and a second power supply signal terminal (e.g., a high-level power supply signal terminal and a low-level power supply signal terminal), used to provide power to the odd-numbered gate drive circuit. ControlB includes a frame start signal terminal and an output signal terminal of the preceding gate drive circuit, used to provide power to the even-numbered gate drive circuit. The first clock signal CLK1 and the second clock signal CLK2 input to the odd-numbered gate drive circuit can be clock signals provided by two of the three clock signal terminals CLKA, CLKB, and CLKC. The first clock signal CLK1 and the second clock signal CLK2 input to the even-numbered gate drive circuit can be clock signals provided by the other two of the three clock signal terminals CLKA, CLKB, and CLKC.

[0130] In this driving method 500, the input signal terminal of the gate driving circuit 300 can provide a corresponding input signal with a specific waveform to control the switching state of each switching transistor in the gate driving circuit 300, thereby enabling the gate driving circuit 300 to output a reset control signal Reset_P or a data control signal Gate_N that meets the requirements.

[0131] Below, in conjunction with Figures 10 to 16 This describes the signal timing and switching state of the odd-numbered gate drive circuit in the GOA circuit. Figure 10 The signal timing diagram of the odd-numbered gate drive circuit is shown. Figures 11 to 16 The diagram shows the switching states of the odd-numbered gate drive circuit from the first stage t1 to the sixth stage t6.

[0132] Optionally, in Figure 10 In the signal timing diagram shown, the duration of each stage from t1 to t6 can be the pulse duration in the clock signal. For example, the duration of a pulse in the clock signal can be 1H or 2H, so the duration of each stage from t1 to t6 can also be 1H or 2H.

[0133] Additionally, as an example, Figure 10 The signal waveforms described are designed for gate drive circuits composed of P-type transistors. When the gate drive circuit is composed of N-type transistors... Figure 10 The signal waveform in the signal can be inverted to drive an N-type transistor.

[0134] For the odd-numbered gate drive circuit, the first control signal Control1 received by the gate of the ninth switch T9 is constant at VGL, and the second control signal Control2 received by the gate of the tenth switch T10 is constant at VGH.

[0135] See Figure 10 and Figure 11 In the first stage t1, the first clock signal CLK1 and the input signal STV are at low level, while the second clock signal CLK2 is at high level. The first switch T1, the third switch T3, the fourth switch T4, the fifth switch T5, the seventh switch T7, the eighth switch T8, and the ninth switch T9 are turned on, while the remaining switches are turned off. Because the first switch T1 is on and the second switch T2 is off, the gate drive circuit outputs a high-level signal in the first stage t1.

[0136] As an example, in the first stage t1, the voltage values ​​of each node in the gate drive circuit are as follows: N1: ~-9.35V; N2: ~5.24V; N3: ~9.4V; N4: ~9.4V; N5: ~9.4V; N6: ~-8.24V; N7: ~-8.3V; where the symbol "~" means "approximately equal to".

[0137] See Figure 10 and Figure 12 In the second stage t2, the second clock signal CLK2 and the input signal STV are at low levels, while the first clock signal CLK1 is at a high level. The first switch T1, the sixth switch T6, the seventh switch T7, the eighth switch T8, and the ninth switch T9 are turned on, while the remaining switches are turned off. Because the first switch T1 is on and the second switch T2 is off, the gate drive circuit continuously outputs a high-level signal in the second stage t2.

[0138] During this phase, the third switch T3 is off. Due to the voltage regulation effect of the first capacitor C1, the N1 node remains almost unchanged, and the first switch T1 remains on, with the gate drive circuit outputting VGH. Meanwhile, the seventh switch T7 is on, the first clock signal CLK1 is written high, and the fifth switch T5 is off. The third switch T8 is on, VGH is written to N4, causing the second switch T2 to be off, and VGL cannot be output. The sixth switch T6 is on, and the potentials of N3 and N4 are equal.

[0139] As an example, in the second stage t2, the voltage values ​​of each node in the gate drive circuit are as follows: N1: ~-9.31V; N2: ~9.4V; N3: ~9.78V; N4: ~9.4V; N5: ~9.4V; N6: ~-8.28V; N7: ~-8.31V.

[0140] See Figure 10 and Figure 13In the third stage t3, the input signal STV is low, while the first clock signal CLK1 and the second clock signal CLK2 are high. The first switch T1, the seventh switch T7, the eighth switch T8, and the ninth switch T9 are turned on, while the remaining switches are turned off. Because the first switch T1 is on and the second switch T2 is off, the gate drive circuit continuously outputs a high-level signal in the third stage t3.

[0141] During this stage, the third switch T3 is off. Due to the voltage regulation effect of the first capacitor C1, the N1 node remains almost unchanged, and the first switch T1 remains on, outputting VGH. Additionally, the fifth switch T5 and the sixth switch T6 are off, writing the VGH signal to the N3 and N4 nodes. The second switch T2 is off, and VGL cannot be output.

[0142] As an example, in the third stage t3, the voltage values ​​of each node in the gate drive circuit are as follows: N1: ~-9.30V; N2: ~9.4V; N3: ~9.78V; N4: ~9.4V; N5: ~9.4V; N6: ~-8.28V; N7: ~-8.31V.

[0143] See Figure 10 and Figure 14 In the fourth stage t4, the first clock signal CLK1 is low, while the input signal STV and the second clock signal CLK2 are high. The third switch T3, the fourth switch T4, the fifth switch T5, and the ninth switch T9 are turned on, while the remaining switches are turned off. Since the first switch T1 and the second switch T2 are both off, in the fourth stage t4, the gate drive circuit continues the signal level from the previous stage, continuously outputting a high-level signal.

[0144] During this stage, the input signal STV is high, the third switch T3 is turned on, and the high level is written to node N1, causing the first switch T1 to turn off. Due to the voltage regulation effect of the third capacitor C3, the potential of node N4 remains basically unchanged, and the second switch T2 remains off.

[0145] As an example, in the fourth stage t4, the voltage values ​​of each node in the gate drive circuit are as follows: N1: ~9.4V; N2: ~-6.53V; N3: ~9.4V; N4: ~10.26V; N5: ~9.4V; N6: ~-7.6V; N7: ~-7.47V.

[0146] See Figure 10 and Figure 15In the fifth stage t5, the second clock signal CLK2 is low, while the input signal STV and the first clock signal CLK1 are high. The second switch T2, the fifth switch T5, the sixth switch T6, the ninth switch T9, and the twelfth switch T12 are turned on, while the remaining switches are turned off. Because the first switch T1 is off and the second switch T2 is on, the gate drive circuit outputs a low-level signal in the fifth stage t5.

[0147] During this phase, the fifth switch T5 is turned on, and the negative potential of the second clock signal CLK2 is written to N3. Due to the coupling effect of the second capacitor C2, N2 is further pulled low. The sixth switch T6 is turned on, and the negative potential of N3 is written to N4, causing the twelfth switch T12 to turn on. Due to the coupling of the third capacitor C3, the potential of the junction between N4 and N6 is pulled low, causing the second switch T2 to turn on, and VGL is output at a low level.

[0148] As an example, in the fifth stage t5, the voltage values ​​of each node in the gate drive circuit are as follows: N1: 7.89V; N2: -22.34V; N3: -9.4V; N4: -16.14V; N5: 9.4V; N6: -13.84V; N7: -33.65V.

[0149] See Figure 10 and Figure 16 In the sixth stage t6, the input signal STV, the first clock signal CLK1, and the second clock signal CLK2 are all high. The second switch T2, the fifth switch T5, the ninth switch T9, and the twelfth switch T12 are turned on, while the remaining switches are turned off. Because the first switch T1 is off and the second switch T2 is on, the gate drive circuit continuously outputs a low-level signal in the sixth stage t6.

[0150] During this stage, the twelfth switch T12 is turned on. Due to the coupling of the third capacitor C3, the N4 node maintains its original voltage. The second switch T2 is turned on, and VGL is output at a low level.

[0151] As an example, in stage t6, the voltage values ​​of each node in the gate drive circuit are as follows: N1: 7.88V; N2: -2.92V; N3: 9.4V; N4: -16.07V; N5: 9.4V; N6: -14.5V; N7: -33V.

[0152] It is understandable that in the subsequent stages after the sixth stage t6, the state of each switch in the gate drive circuit can be referred to the analysis of the first stage t1 to the third stage t3 above. The output signal out[n] of the gate drive circuit can remain at a high level.

[0153] Additionally, it should be noted that, Figures 10 to 16The explanation uses an STV signal as an example. When the input signal is Out[n-1], Out[n-1] is the signal output by the even-numbered gate drive circuit, which is similar to the STV signal and is also a high-level active pulse wave signal. Using Out[n-1] as the input signal can also generate the required reset control signal Reset_P.

[0154] It should also be noted that in the above embodiments, the high level of each signal can be understood as the first level, and the low level can be understood as the second level. Besides being the high and low levels described in the above embodiments, the first and second levels can also be low and high levels, respectively.

[0155] The above text combined Figures 10 to 16 This document describes the timing diagram and switching transistor state diagram of the odd-level gate drive circuit provided in the embodiments of this application. Below, in conjunction with... Figures 17 to 23 This application provides timing diagrams and switching transistor state diagrams for even-level gate drive circuits in its embodiments.

[0156] Figure 17 The signal timing diagram of the even-numbered gate drive circuit is shown. Figures 18 to 23 The diagram shows the switching states of the even-numbered gate drive circuit from the first stage t1 to the sixth stage t6.

[0157] Optionally, in Figure 17 In the signal timing diagram shown, the duration of each stage from t1 to t6 can be the pulse duration in the clock signal. For example, the duration of a pulse in the clock signal can be 1H or 2H, so the duration of each stage from t1 to t6 can also be 1H or 2H.

[0158] Additionally, as an example, Figure 17 The signal waveforms described are designed for gate drive circuits composed of P-type transistors. When the gate drive circuit is composed of N-type transistors... Figure 17 The signal waveform in the signal can be inverted to drive an N-type transistor.

[0159] For the even-numbered gate drive circuit, the first control signal Control1 received by the gate of the ninth switch T9 is Out[n-1], and the second control signal Control2 received by the gate of the tenth switch T10 is STV.

[0160] See Figure 17 and Figure 18In the first stage t1, the first clock signal CLK1 is low, the second clock signal CLK2 is high, the input signal and the first control signal out1 are low, and the second control signal STV is high. The first switch T1, the third switch T3, the fourth switch T4, the fifth switch T5, the seventh switch T7, the eighth switch T8, and the ninth switch T9 are turned on, while the remaining switches are turned off. Because the first switch T1 is on and the second switch T2 is off, the gate drive circuit outputs a high-level signal in the first stage t1.

[0161] During this phase, node N1 is low, the first switch T1 is on, and VGH is output at a high level. The eighth switch T8 is on, VGH is written to node N4, the second switch T2 is off, and VGL cannot be output.

[0162] As an example, in the first stage t1, the voltage values ​​of each node in the gate drive circuit are as follows: N1: -5.9V; N2: 5.23V; N3: 9.4V; N4: 9.4V; N5: 9.4V; N6: 11.50V; N7: 12.08V.

[0163] See Figure 17 and Figure 19 In the second stage t2, the first clock signal CLK1 is high, the second clock signal CLK2 is low, the input signal and the first control signal out1 are low, and the second control signal STV is high. The first switch T1, the sixth switch T6, the seventh switch T7, the eighth switch T8, and the ninth switch T9 are turned on, while the remaining switches are turned off. Because the first switch T1 is on and the second switch T2 is off, the gate drive circuit continuously outputs a high-level signal in the second stage t2.

[0164] During this stage, the third switch T3 is off. Due to the voltage regulation effect of the first capacitor C1, the N1 node remains almost unchanged, and the first switch T1 remains on. The eighth switch T8 is on, VGH is written to the N4 node, the second switch T2 is off, and VGL cannot be output.

[0165] As an example, in the second stage t2, the voltage values ​​of each node in the gate drive circuit are as follows: N1: -6.13V; N2: 9.4V; N3: 9.4V; N4: 9.4V; N5: 9.4V; N6: 10.31V; N7: 11.67V.

[0166] See Figure 17 and Figure 20In the third stage t3, the first clock signal CLK1 and the second clock signal CLK2 are at high levels, the input signal and the first control signal out1 are at high levels, and the second control signal STV is at low level. The first switch T1, the tenth switch T10, and the eleventh switch T11 are turned on, and the remaining switches are turned off. Since the first switch T1 is turned on and the second switch T2 is turned off, the gate drive circuit continuously outputs a high-level signal in the third stage t3.

[0167] During this stage, the third switch T3 is off. Due to the voltage regulation effect of the first capacitor C1, the N1 node remains almost unchanged, and the first switch T1 remains on. The STV signal is low, the tenth switch T10 is on, N5 writes a low level VGL, the eleventh switch T11 is on, N6 writes a high level VGH to CLK2, and the potentials of N4 and N7 rise due to the coupling effect of the twelfth switch T12 and the third capacitor C3. The second switch T2 is off, and VGL cannot be output.

[0168] As an example, in the third stage t3, the voltage values ​​of each node in the gate drive circuit are as follows: N1: -6.13V; N2: 10.17V; N3: 10.54V; N4: 9.84V; N5: -6.96V; N6: 9.4V; N7: 11.94V.

[0169] See Figure 17 and Figure 21 In the fourth stage t4, the first clock signal CLK1 is low, the second clock signal CLK2 is high, the input signal and the first control signal out1 are high, and the second control signal STV is low. The third switch T3, the tenth switch T10, and the eleventh switch T11 are turned on, while the remaining switches are turned off. The first switch T1 and the second switch T2 are both turned off. Therefore, in the fourth stage t4, the gate drive circuit continues the output level signal from the previous stage, outputting a high-level signal.

[0170] During this stage, the potential of node N4 remains basically unchanged through the coupling effect of the twelve-switch transistor T12 and the third capacitor C3, while the second switch transistor T2 is turned off.

[0171] As an example, in the fourth stage t4, the voltage values ​​of each node in the gate drive circuit are as follows: N1: 9.4V; N2: -6.61V; N3: 9.4V; N4: 9.81V; N5: -7.40V; N6: 9.4V; N7: 11.7V.

[0172] See Figure 17 and Figure 22In the fifth stage t5, the first clock signal CLK1 is high, the second clock signal CLK2 is low, the input signal and the first control signal out1 are high, and the second control signal STV is low. The second switch T2, the fifth switch T5, the sixth switch T6, the tenth switch T10, the eleventh switch T11, and the twelfth switch T12 are turned on, while the remaining switches are turned off. Because the first switch T1 is off and the second switch T2 is on, the gate drive circuit outputs a low-level signal in the fifth stage t5.

[0173] During this phase, the STV signal is low, the tenth switch T10 is turned on, the eleventh switch T11 is turned on, and CLK2 is written low to N6. The fifth switch T5 is turned on, and CLK2 is written low to N3. Due to the coupling effect of the second capacitor C2, the potential of N2 further decreases. The sixth switch T6 is turned on, and a low level is written to N4. Combined with the coupling effect of the twelfth switch T12 and the third capacitor C3, the potential of node N4 decreases, the second switch T2 is turned on, and VGL is output.

[0174] As an example, in the fifth stage t5, the voltage values ​​of each node in the gate drive circuit are as follows: N1: 7.89V; N2: -22.42V; N3: -9.4V; N4: -15.73V; N5: -22.37V; N6: -9.4V; N7: -9.4V.

[0175] See Figure 17 and Figure 23 In the sixth stage t6, both the first clock signal CLK1 and the second clock signal CLK2 are high, the input signal and the first control signal out1 are high, and the second control signal STV is low. The second switch T2, the fifth switch T5, the sixth switch T6, the tenth switch T10, the eleventh switch T11, and the twelfth switch T12 are turned on, while the remaining switches are turned off. Because the first switch T1 is off and the second switch T2 is on, the gate drive circuit outputs a low-level signal in the fifth stage t5.

[0176] During this stage, due to the maintenance of the first capacitor C1, the potential of node N1 remains basically unchanged, the first switch T1 is turned off, and VGH does not output. STV is low, the tenth switch T10 is turned on, the eleventh switch T11 is turned on, CLK2 is written low to N6, the potential of node N4 remains basically unchanged through the coupling effect of the twelfth switch T12 and the third capacitor C3, the second switch T2 is turned on, and VGL is output.

[0177] As an example, in stage t6, the voltage values ​​of each node in the gate drive circuit are as follows: N1: 7.88V; N2: -2.92V; N3: 9.4V; N4: -13.89V; N5: -7.18V; N6: 9.4V; N7: 9.4V.

[0178] It is understandable that in the subsequent stages after the sixth stage t6, the voltage at point N4 can be maintained by the tenth switch T10, the eleventh switch T11, the twelfth switch T12 and the third capacitor C3, so that the second switch T2 remains in the open state and the output signal out[n] of the gate drive circuit can remain at a low level.

[0179] Additionally, it should be noted that in the above embodiments, the high level of each signal can be understood as the first level, and the low level can be understood as the second level. Besides being the high and low levels described in the above embodiments, the first and second levels can also be low and high levels, respectively.

[0180] The driving method provided in this application embodiment can effectively drive each stage of the gate driving circuit in the GOA circuit, so that the odd-numbered stage gate driving circuit outputs the reset control signal Reset_P of the pixel circuit, and the even-numbered stage gate driving circuit can output the data control signal Gate_N.

[0181] Combining the gate driving circuit and related driving method provided in the above embodiments, Figure 24 A schematic waveform diagram of a GOA circuit formed by cascading multiple gate drive circuits is shown.

[0182] In addition to showing the STV signal input to the GOA circuit, the three clock signal terminals CLKA, CLKB and CLKC, and the output signals Out[1] to Out[4] of the first-stage gate drive circuit to the fourth-stage gate drive circuit in the GOA circuit, the waveforms of the N1 to N7 nodes in the odd-stage gate drive circuit of the GOA circuit, the waveforms of the first control signal Control1 and the second control signal Control2 input to the odd-stage gate drive circuit, and the waveforms of the N1 to N7 nodes in the even-stage gate drive circuit of the GOA circuit, the waveforms of the first control signal Control1 and the second control signal Control2 input to the even-stage gate drive circuit.

[0183] Figure 25 A schematic structural block diagram of a display device 600 provided in an embodiment of this application is shown.

[0184] like Figure 25As shown, in the display device 600, the GOA circuit 602 may include at least two cascaded gate drive circuits, which may be the gate drive circuit 300 provided in any of the embodiments described above.

[0185] Optionally, in some implementations, the GOA circuit 602 may include two GOA sub-circuits, for example, Figure 25 The first GOA sub-circuit 6021 and the second GOA sub-circuit 6022 are shown in the diagram. Each GOA sub-circuit includes at least two cascaded gate drive circuits, and each GOA sub-circuit is used to drive half of the pixel units 601 in the display device.

[0186] exist Figure 25 In the illustrated embodiment, the first GOA sub-circuit 6021 can be used to drive the pixel units 601 in rows (4n+1) and (4n+2) of the display device, where n is an integer greater than or equal to 0. That is, the first GOA sub-circuit 6021 can be used to drive the pixel units 601 in rows 1, 2, 5, 6, 9, 10, 13, 14, etc. in the display device. The second GOA sub-circuit 6021 can be used to drive the pixel units 601 in rows (4n+3) and (4n+4) of the display device, where n is an integer greater than or equal to 0. That is, the first GOA sub-circuit 6021 can be used to drive the pixel units 601 in rows 3, 4, 7, 8, 11, 12, 15, 16, etc. in the display device.

[0187] When the GOA circuit 602 includes two GOA sub-circuits, the STV signals input to these two GOA sub-circuits must have a certain phase difference. This phase difference is related to the pulse width of the clock signal. For example, when the pulse width of the clock signal is 2H, the STV signals input to the two GOA sub-circuits also have a phase difference of 2H.

[0188] Optionally, in some embodiments, the reset control signal Reset_P and the data control signal Gate_N generated by two adjacent gate drive circuits in the GOA circuit 602 are used to input to two adjacent rows of pixel units 601 in the display device.

[0189] exist Figure 25In the illustrated embodiment, the reset control signal Reset_P generated by the first-stage gate driving circuit in the first GOA sub-circuit 6021 is input to the first and second row pixel units 601 in the display device, and the data control signal Gate_N generated by the second-stage gate driving circuit in the first GOA sub-circuit 6021 is also input to the first and second row pixel units 601 in the display device. Similarly, the reset control signal Reset_P generated by the third-stage gate driving circuit in the first GOA sub-circuit 6021 is input to the fifth and sixth row pixel units 601 in the display device, and the data control signal Gate_N generated by the fourth-stage gate driving circuit in the first GOA sub-circuit 6021 is also input to the fifth and sixth row pixel units 601 in the display device.

[0190] Similar to the first GOA sub-circuit 6021 described above, the reset control signal Reset_P and the data control signal Gate_N generated by the first-stage gate driving circuit and the second-stage gate driving circuit in the second GOA sub-circuit 6022 are both used to input the pixel units 601 in the third and fourth rows of the display device. The reset control signal Reset_P and the data control signal Gate_N generated by the third-stage gate driving circuit and the fourth-stage gate driving circuit in the second GOA sub-circuit 6022 are both used to input the pixel units 601 in the seventh and eighth rows of the display device.

[0191] Through the technical solution of this application embodiment, the GOA circuit 602 may include two sub-circuits, which facilitates their distribution on both sides of the display device 600, thus helping to compress the width space of a single side bezel. Furthermore, in the GOA circuit 602, the reset control signal Reset_P and data control signal Gate_N generated by two cascaded adjacent gate drive circuits can be used as inputs to two adjacent rows of pixel units in the display device, thereby reducing the number of cascaded gate drive circuits in the GOA circuit 602, which further helps to compress the width space of the display screen bezel.

[0192] In some alternative embodiments, the GOA circuit 602 may not be divided into two sub-circuits, but may be disposed on the same side bezel of the display device 600 to drive all rows of pixel units 601 in the display device 600. Alternatively, the reset control signal Reset_P and data control signal Gate_N generated by two cascaded adjacent gate driving circuits in the GOA circuit 602 may be input only to the same row of pixel units 601 in the display device 600. Or, the reset control signal Reset_P and data control signal Gate_N generated by two cascaded adjacent gate driving circuits in the GOA circuit 602 may be input to two or more rows of pixel units 601, for example, simultaneously input to four rows of pixel units 601.

[0193] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0194] In the method embodiments provided in this application, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0195] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0196] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0197] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0198] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0199] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A gate driving circuit, characterized in that, include: The circuit consists of a first control circuit, a second control circuit, a potential holding circuit, and an output circuit. The output circuit includes a first switching transistor connected to a first power signal terminal and a second switching transistor connected to a second power signal terminal. The output circuit is used to output a first level signal or a second level signal. The first control circuit is connected to the gate of the first switching transistor and is used to receive a first clock signal and an input signal to control the turning on and off of the first switching transistor. The input signal is a frame start signal or the output signal of the previous stage gate drive circuit. The second control circuit is connected to the gate of the second switching transistor and is used to receive the first clock signal, the second clock signal and the input signal to control the turning on and off of the second switching transistor, wherein the first clock signal and the second clock signal have a phase difference of at least one unit time. The potential holding circuit is connected to the gate of the second switching transistor and is used to receive the second clock signal and control signal; Under the influence of the input signal, the first clock signal, the second clock signal, and the control signal, the output circuit outputs a reset control signal or a data control signal for the pixel circuit. The effective level of the reset control signal is opposite to that of the data control signal, and the duration of the effective level in the data control signal is twice the duration of the effective level in the reset control signal.

2. The gate driving circuit according to claim 1, characterized in that, The gate driving circuit is an odd-numbered stage driving circuit in the substrate gate driving GOA circuit; the control signal received by the potential holding circuit includes a first power supply signal and a second power supply signal; and the output circuit is used to output the reset control signal of the pixel circuit; or... The gate driving circuit is the even-numbered stage driving circuit in the GOA circuit. The control signal received by the potential holding circuit includes a frame start signal and the output signal of the previous stage gate driving circuit. The output circuit is used to output the data control signal of the pixel circuit.

3. The gate driving circuit according to claim 1, characterized in that, The GOA circuit where the gate drive circuit is located has three corresponding clock signal terminals, and the clock signals of the three clock signal terminals are at least one unit time apart in phase. The gate driving circuit is the i-th driving circuit in the GOA circuit, and the i-th driving circuit is connected to the first clock signal terminal and the second clock signal terminal among the three clock signal terminals. or, The gate driving circuit is the (i+1)th driving circuit in the GOA circuit. The i-th driving circuit is connected to the second clock signal terminal and the third clock signal terminal among the three clock signal terminals, where i is a positive integer.

4. The gate driving circuit according to any one of claims 1 to 3, characterized in that, The first control circuit includes: a third switching transistor and a first capacitor; The first capacitor is connected to the first power signal terminal and the drain of the third switching transistor; The gate of the third switch is used to receive the first clock signal, and the source of the third switch is used to receive the input signal.

5. The gate driving circuit according to claim 4, characterized in that, The capacitance value of the first capacitor is greater than 0 and less than or equal to 200F.

6. The gate driving circuit according to any one of claims 1 to 3, characterized in that, The second control circuit includes: a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, and a second capacitor; The gate of the fourth switch is used to receive the first clock signal, the source of the fourth switch is connected to the second power signal terminal, and the drain of the fourth switch is connected to the gate of the fifth switch. The source of the fifth switch is used to receive the second clock signal, the drain of the fifth switch is connected to the source of the sixth switch, and the second capacitor is connected between the gate and the drain of the fifth switch. The gate of the sixth switch is used to receive the second clock signal, and the drain of the sixth switch is connected to the gate of the second switch. The gate of the seventh switch is used to receive the input signal, the source of the seventh switch is used to receive the first clock signal, and the drain of the seventh switch is connected to the gate of the fifth switch. The gate of the eighth switch is used to receive the input signal, the source of the eighth switch is connected to the first power signal terminal, and the drain of the eighth switch is connected to the gate of the second switch.

7. The gate driving circuit according to claim 6, characterized in that, The capacitance value of the second capacitor is greater than 0 and less than or equal to 100F.

8. The gate driving circuit according to any one of claims 1 to 3, characterized in that, The potential holding circuit includes: a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, and a third capacitor; The gate of the ninth switch is used to input the first control signal, the source of the ninth switch is connected to the first power signal terminal, and the drain of the ninth switch is connected to the drain of the tenth switch. The gate of the tenth switch is used to input the second control signal, and the source of the tenth switch is connected to the second power signal terminal. The gate of the eleventh switch is connected to the drain of the ninth switch and the drain of the tenth switch. The source of the eleventh switch is used to input the second clock signal. The drain of the eleventh switch is connected to the source of the twelfth switch. The gate of the twelfth switch is connected to the gate of the second switch, and the third capacitor is connected between the gate of the twelfth switch and the drain of the twelfth switch.

9. The gate driving circuit according to claim 8, characterized in that, The capacitance value of the third capacitor is greater than 0 and less than or equal to 50f.

10. The gate driving circuit according to any one of claims 1 to 3, characterized in that, The rise time of the reset control signal is less than or equal to 408.1 ns, and the fall time of the reset control signal is less than or equal to 1.142 μs; and / or, The rise time of the data control signal is less than or equal to 558.1 ns, and the fall time of the data control signal is less than or equal to 1.167 μs.

11. A driving method for a gate driving circuit, characterized in that, The driving method for driving a gate driving circuit as described in any one of claims 1 to 10 includes: A first clock signal and an input signal are input to the first control circuit in the gate drive circuit so that the state of the first switch in the output circuit is controlled by the first control circuit, so that the gate drive circuit outputs a first level signal. The first clock signal, the second clock signal, and the input signal are input to the second control circuit in the gate drive circuit, so that the second control circuit controls the state of the second switch in the output circuit, causing the gate drive circuit to output a second level signal. The second clock signal and control signal are input to the potential holding circuit in the gate drive circuit to maintain the gate voltage of the second switch through the potential holding circuit, so that the gate drive circuit maintains the output voltage.

12. The driving method according to claim 11, characterized in that, The gate drive circuit is the odd-numbered stage drive circuit in the GOA circuit; In the first stage, the first clock signal and the input signal are at a second level, the second clock signal is at a first level, and the gate drive circuit outputs a first level signal; In the second stage, the second clock signal and the input signal are at a second level, the first clock signal is at a first level, and the gate drive circuit outputs a first level signal; In the third stage, the input signal is at the second level, the first clock signal and the second clock signal are at the first level, and the gate drive circuit outputs the first level signal; In the fourth stage, the first clock signal is at the second level, the input signal and the second clock signal are at the first level, and the gate drive circuit outputs the first level signal. In the fifth stage, the second clock signal is at the second level, the first clock signal and the input signal are at the first level, and the gate drive circuit outputs the second level signal; In the sixth stage, the first clock signal, the second clock signal, and the input signal are at a first level, and the gate drive circuit outputs a second level signal.

13. The driving method according to claim 11, characterized in that, The gate drive circuit is the even-numbered stage drive circuit in the GOA circuit. In the first stage, the first clock signal and the input signal are at a second level, the second clock signal is at a first level, and the gate drive circuit outputs a first level signal; In the second stage, the second clock signal and the input signal are at a second level, the first clock signal is at a first level, and the gate drive circuit outputs a first level signal. In the third stage, the input signal, the first clock signal, and the second clock signal are at a first level, and the gate drive circuit outputs a first level signal; In the fourth stage, the first clock signal is at the second level, the input signal and the second clock signal are at the first level, and the gate drive circuit outputs the first level signal. In the fifth stage, the second clock signal is at the second level, the input signal and the first clock signal are at the first level, and the gate drive circuit outputs the second level signal; In the sixth stage, the input signal, the first clock signal, and the second clock signal are at a first level, and the gate drive circuit outputs a second level signal.

14. A GOA circuit, characterized in that, include: At least two cascaded gate drive circuits as described in any one of claims 1 to 10.

15. The GOA circuit according to claim 14, characterized in that, The reset control signal and data control signal generated by the two cascaded adjacent gate drive circuits in the GOA circuit are used as inputs to two adjacent rows of pixel units in the display device; and / or, The GOA circuit includes two GOA sub-circuits, each GOA sub-circuit includes at least two cascaded gate drive circuits, and each GOA sub-circuit is used to drive half of the pixel units in the display device.

16. A display device, characterized in that, include: The GOA circuit as described in claim 14 or 15.

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