Silicon-based liquid crystal chip control system and method

Abstract

The application provides a silicon-based liquid crystal chip control system and method, the system comprises: a data buffering module, which is used for converting an external video signal into a digital image signal and storing; a data adjusting module connected with the data buffering module, which is used for rearranging data of the digital image signal to obtain a rearranged digital signal; and a data driving module connected with the data adjusting module, which is used for generating a control signal and a clock signal of a silicon-based liquid crystal chip based on the rearranged digital signal, and outputting the digital image signal, the clock signal and the control signal to the silicon-based liquid crystal chip. The silicon-based liquid crystal chip control system and method of the application decodes a video signal based on an FPGA, realizes a video stream to LCoS signal bridging function, and meets the resolution and high refresh rate requirements of the silicon-based liquid crystal chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of silicon-based liquid crystal (Liquid Crystal on Silicon, LCoS) driving control, and particularly relates to a silicon-based liquid crystal chip control system and method. BACKGROUND

[0002] LCoS micro display technology has numerous applications in the display field, and has the advantages of high frame rate, high resolution and small volume. LCoS is developed from liquid crystal display screen technology LCD, and is favored due to its mature production line and low cost. In early applications, LCoS is mainly used for laser projection, display and holographic projection, etc. Based on LCoS technology, a wavelength display switch can be made to switch any wavelength channel received at the input port to any output port. Today, the development of LCoS technology has changed the optical communication and display industry, and provides flexible and reliable solutions for various applications.

[0003] LCoS devices are mainly used as amplitude modulation devices and phase modulation devices. Amplitude modulation type LCOS devices are mainly used for video and image display, and phase modulation type LCOS devices are suitable for holographic projection and optical fields. The existing general resolution display control system cannot meet the requirements of special resolution and high refresh rate of LCoS chips. Therefore, it is an important task to design a processing system for high-definition images or video streams. A reliable processing system can provide stable data stream for the display chip, and can also implement some real-time algorithms for image processing. Especially for more complex algorithms, the flexibility and efficiency of the system platform are very important. Generally, it is difficult to use CPU to efficiently process high-speed video streams. Compared with GPU and ASIC, FPGA can customize the data stream algorithm and function according to the requirements. FPGA not only can use parallelization and pipeline for data processing, but also has advantages in energy efficiency. Compared with GPU, the ability to work without additional host makes FPGA suitable for embedded systems to meet the needs of image processing. In most applications using LCoS, the resolution of the chip is not high, and the requirements for the control system are relatively simple. However, in the face of growing data and special high-resolution specifications, traditional processing devices are powerless.

[0004] In summary, in the LCoS chip control system, a general-purpose processor is often needed to control the driving of the chip. Traditional CPU and GPU can complete the control function, but also have some disadvantages. For example, the processing capability of CPU for image data is weak, the power consumption of GPU is too large, and it is not suitable for edge application scenarios. For the control system designed using FPGA, high resolution and high refresh rate are the bottleneck of driving LCoS. SUMMARY

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a silicon-based liquid crystal chip control system and method, which decodes a video signal based on an FPGA, realizes a video stream to LCoS signal bridging function, and meets the resolution and high refresh rate requirements of a silicon-based liquid crystal chip.

[0006] In a first aspect, the present application provides a silicon-based liquid crystal chip control system applied to an FPGA, comprising: a data buffering module configured to convert an external video signal into a digital image signal and store the digital image signal; a data adjusting module connected to the data buffering module and configured to rearrange the digital image signal to obtain a rearranged digital signal; and a data driving module connected to the data adjusting module and configured to generate a control signal and a clock signal of a silicon-based liquid crystal chip based on the rearranged digital signal, and output the digital image signal, the clock signal and the control signal to the silicon-based liquid crystal chip.

[0007] In an implementation form of the first aspect, the data buffering module comprises a frame data parsing module, a frame data storage module and a storage control module.

[0008] The frame data parsing module is configured to convert the external video signal into the digital image signal.

[0009] The frame data storage module is connected to the frame data parsing module and configured to store the digital image signal.

[0010] The storage control module is connected to the frame data parsing module and the frame data storage module, and is configured to control a read frame number, a write frame number, a frame data storage location and a storage bit width of the frame data storage module.

[0011] In an implementation form of the first aspect, the frame data storage module comprises a storage space of three frame image sizes on the FPGA to realize three-level frame buffering, and the write frame number is always prior to the read frame number.

[0012] In an implementation form of the first aspect, the data buffering module obtains the external video signal through an HDMI interface.

[0013] In an implementation form of the first aspect, the data adjusting module comprises a row data buffering module, a data rearranging module, a rearranged data buffering module and a data adjusting control module.

[0014] The row data buffering module is configured to access the data buffering module, obtain and store the digital image signal.

[0015] The data rearrangement module is connected with the row data buffer module, and is configured to pack and rearrange the digital image signal to obtain a rearranged digital signal so that the rearranged digital signal meets an input sequence of the silicon-based liquid crystal chip.

[0016] The rearranged data buffer module is connected with the data rearrangement module, and is configured to store the rearranged digital signal.

[0017] The data adjustment control module is connected with the row data buffer module, the data rearrangement module and the rearranged data buffer module, and is configured to control data access of the row data buffer module, data rearrangement of the data rearrangement module and data storage of the rearranged data buffer module.

[0018] In an implementation form of the first aspect, the data rearrangement module is configured to rearrange the packed digital image signal into a plurality of groups of parallel structure rearranged digital signals by using a pipeline operation.

[0019] In an implementation form of the first aspect, the data driving module comprises a driving control module, a data parsing module, a driving signal generation module and a data alignment module.

[0020] The driving control module is connected with the data parsing module, the driving signal generation module and the data alignment module, and is configured to control the data parsing module, the driving signal generation module and the data alignment module.

[0021] The data parsing module is configured to access the data adjustment module to obtain the rearranged digital signal.

[0022] The driving signal generation module is connected with the data parsing module, and is configured to generate a control signal and a clock signal of the silicon-based liquid crystal chip based on the rearranged digital signal.

[0023] The data alignment module is connected with the driving signal generation module, and is configured to output the digital image signal, the clock signal and the control signal to the silicon-based liquid crystal chip after aligning the digital image signal, the clock signal and the control signal with the clock.

[0024] In an implementation form of the first aspect, the data alignment module outputs the signals through a high-speed external interface.

[0025] In an implementation form of the first aspect, the control signal comprises a row driving signal and a field driving signal.

[0026] Secondly, the application provides a silicon-based liquid crystal chip control method applied to an FPGA, and the method comprises the following steps:

[0027] An external video signal is converted into a digital image signal based on a data buffer module, and the digital image signal is stored.

[0028] The data adjustment module rearranges the digital image signal to obtain a rearranged digital signal;

[0029] The data driving module generates a control signal and a clock signal of the silicon-based liquid crystal chip according to the rearranged digital signal, and outputs the digital image signal, the clock signal and the control signal to the silicon-based liquid crystal chip.

[0030] As described above, the silicon-based liquid crystal chip control system and method has the following beneficial effects:

[0031] (1) The video signal is decoded by using the FPGA to realize the bridging function of the video stream to the LCoS signal, and the problem that the existing resolution display control system cannot meet the special resolution and high refresh rate of the LCoS chip is solved;

[0032] (2) The image structure is complete under the full resolution and high refresh rate of the LCoS driving, and the needs of the edge application scenarios are met;

[0033] (3) The configurable parameter design can independently control the data rate and clock frequency output to the silicon-based liquid crystal chip, and meet the data and control needs of the silicon-based liquid crystal chip under different functions;

[0034] (4) Low power consumption, high real-time performance and fast processing speed. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 Fig. 1 shows the structure of the silicon-based liquid crystal chip control system in an embodiment of the present application;

[0036] Figure 2 Fig. 2 shows the running flowchart of the silicon-based liquid crystal chip control system in an embodiment of the present application;

[0037] Figure 3 Fig. 3 shows the read-write sequence number diagram of the data buffer module in an embodiment of the present application;

[0038] Figure 4 Fig. 4 shows the schematic diagram of the data rearrangement mechanism in an embodiment of the present application;

[0039] Figure 5 Fig. 5 shows the flowchart of the silicon-based liquid crystal chip control system in an embodiment of the present application. DETAILED DESCRIPTION

[0040] Following make the specific concrete example explain the implementation of the present application, the person skilled in the art can be easily understood from the present application disclosed in the content of the other advantages and efficacy of the present application can also be implemented or applied by different specific implementation, the details in the specification can be based on different views and applications, without departing from the spirit of the present application, various modifications or changes are made.The need to explain that, in the following examples and the features in the examples can be combined with each other without conflict.

[0041] Need to explain, the drawings provided in the following examples only in a schematic way to illustrate the basic concept of the present application, and the drawings only show the relevant components in the present application is not drawn according to the actual implementation of the number of components, shape and size, the actual implementation of each component type, quantity and proportion can be a random change, and its component layout type can be more complex.

[0042] In addition, in the present application as described in the "first", "second" and so on for the purpose of description, and can not be understood as indicating or implying its relative importance or implied indicate the number of technical features indicated. Thus, the "first", "second" limited features can be explicitly or implicitly include at least one the feature.In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the ordinary skill of the person skilled in the art can be realized, when the technical solution of the combination of each other contradictory or can not be realized when the technical solution of the combination of should be considered that this does not exist, also not within the scope of protection claimed in the present application.

[0043] The silicon-based liquid crystal chip control system and method of the present application decodes the video signal based on FPGA, realizes the video stream to LCoS signal bridging function through data buffering and data rearrangement, can convert the video data into control signal and data signal for silicon-based liquid crystal chip in real time, so as to meet the resolution and high refresh rate requirements of silicon-based liquid crystal chip.

[0044] The silicon-based liquid crystal chip control system of the present application is applied to FPGA.As shown in Figure 1 and Figure 2 In an embodiment, the silicon-based liquid crystal chip control system of the present application includes a data buffering module 1, a data adjustment module 2 and a data driving module 3.

[0045] The data buffering module 1 is used to convert the external video signal into a digital image signal and store it. Wherein, the data buffering module 1 obtains the external video signal through the HDMI interface, and the external video signal is HDMI signal.

[0046] In an embodiment, the data buffering module comprises a frame data parsing module 11, a frame data storage module 12 and a storage control module 13. The frame data parsing module 11 is configured to convert the external video signal into the digital image signal. In an embodiment, the frame data parsing module 11 converts the external video HDMI signal into a multi-bit digital image signal in a specific format and video image control signals such as field synchronization VS, line synchronization HS, data enable DataEn, etc., with an input frame rate of 60 Hz and an image resolution of the color digital image signal being 1920x1080. The frame data storage module 12 is connected to the frame data parsing module 11 and configured to store the digital image signal. The frame data storage module 12 comprises an on-chip memory. The storage control module 13 is connected to the frame data parsing module 11 and the frame data storage module 12 and configured to control the read frame number, the write frame number, the frame data storage location and the storage bit width of the frame data storage module. The storage control module 13 controls the current read frame number R_Num and the current write frame number W_Num to sample and buffer the digital image signal. The frame data storage module 12 opens a space of three frame image sizes on the FPGA to realize three-level frame buffering, and controls the three-level frame buffering and R_Num and W_Num so that the write frame number W_Num is always prior to the read frame number R_Num, thereby satisfying that the write data rate is less than the read data rate. As shown in FIG. 1, under the control of the read frame number R_Num and the write frame number W_Num, W_Num is always the upper level of R_Num. Figure 3

[0047] The data adjustment module 2 is connected to the data buffering module 1 and configured to rearrange the digital image signal to obtain a rearranged digital signal.

[0048] ​In an embodiment, the data adjustment module 2 comprises a row data buffer module 21, a data rearrangement module 22, a rearranged data buffer module 23, and a data adjustment control module 24. The row data buffer module 21 is configured to access the data buffer module, acquire and store the digital image signal. Specifically, the row data buffer module 21 accesses the digital image signal in the frame data storage module 12 through the on-chip memory and the on-chip high-speed bus according to the control signal generated by the data adjustment control module 24, and carries the digital image signal to the row data buffer module 21. The data rearrangement module 22 is connected to the row data buffer module 21, and is configured to package and rearrange the digital image signal to obtain a rearranged digital signal so that the rearranged digital signal meets the input order of the liquid crystal on silicon chip. Specifically, the data rearrangement module 22 uses pipeline operation to rearrange the packaged digital image signal into a plurality of groups of parallel structure. It should be noted that the rearranged digital signal is in a plurality of groups in parallel, and each group can be configured separately to meet the application requirements of different scenarios. The rearranged data buffer module 23 is connected to the data rearrangement module 22, and is configured to store the rearranged digital signal according to the signal scheduling of the data adjustment control module 24. Specifically, in the row data buffer module 21, the frame data storage module 12 is accessed through the control signal and the AXI on-chip high-speed bus, and the digital image signal corresponding to the read frame number R_Num is obtained. The storage control module 13 encodes four pixels into a group, i.e., 40 bits as a burst packet for transmission. The data rearrangement module 22 makes the data meet the order of output to the liquid crystal on silicon chip, i.e., one row of data is divided into four equal parts and rearranged. As shown in FIG. 8, the packaged data is divided into four groups by data rearrangement and stored in four on-chip Block Rans. Figure 4

[0049] The data driving module 3 is connected to the data adjustment module 2, and is configured to generate a control signal and a clock signal of the liquid crystal on silicon chip based on the rearranged digital signal, and output the digital image signal, the clock signal, and the control signal to the liquid crystal on silicon chip.

[0050] ​In an embodiment, the data driving module 3 comprises a driving control module 31, a data analysis module 32, a driving signal generation module 33 and a data alignment module 34. The driving control module 31 is connected with the data analysis module 32, the driving signal generation module 33 and the data alignment module 34, and is used for controlling the data analysis module 32, the driving signal generation module 33 and the data alignment module 34. The data analysis module 32 is used for accessing the data adjustment module 2 to obtain the rearranged digital signal. The data analysis module 32 accesses the rearranged data buffer module 23 through a high-speed bus according to a signal generated by the driving control module 31, and carries the rearranged digital signal to the driving signal generation module 33. The driving signal generation module 33 is connected with the data analysis module 32, and is used for generating a control signal and a clock signal of a silicon-based liquid crystal chip based on the rearranged digital signal. The control signal comprises a row driving signal and a field driving signal. The data alignment module 34 is connected with the driving signal generation module 33, and is used for outputting the digital image signal, the clock signal and the control signal to the silicon-based liquid crystal chip after alignment with a clock. Preferably, the data alignment module 34 converts the digital image signal and the clock signal into corresponding differential signals, and outputs the differential signals and the control signal to the silicon-based liquid crystal chip through a high-speed external interface such as an LVDS interface. The frequency of the clock signal output to the silicon-based liquid crystal chip is 250 MHz at most, the maximum single-pixel precision is 10 bits, the number of output channels is 13, and the total transmission rate is 5.75 Gbps.

[0051] For a conventional 1080p@60Hz resolution video stream control system, the system processing speed is 356 MB / s. The video stream output specification processed by the application is 1620p@120Hz, and the system processing speed is 593 MB / s. It can be seen that the silicon-based liquid crystal chip control system of the application can process high-speed video streams more efficiently, and can design different control kernels according to different input resolutions to meet the real-time processing function.

[0052] The silicon-based liquid crystal chip control method of the application is applied to an FPGA. As shown in Figure 5 In an embodiment, the silicon-based liquid crystal chip control method of the application comprises steps S1-S3.

[0053] In step S1, the external video signal is converted into a digital image signal based on a data buffer module, and is stored.

[0054] Specifically, in an embodiment, the data buffer module comprises a frame data parsing module, a frame data storage module and a storage control module. The frame data parsing module converts the external video signal into the digital image signal. The frame data storage module stores the digital image signal. The storage control module controls the read frame number, the write frame number, the frame data storage location and the storage bit width of the frame data storage module.

[0055] Step S2, data rearrangement is performed on the digital image signal based on a data adjustment module to obtain a rearranged digital signal.

[0056] Specifically, the data adjustment module comprises a line data buffer module, a data rearrangement module, a rearranged data buffer module and a data adjustment control module. The line data buffer module accesses the data buffer module to obtain and store the digital image signal. The data rearrangement module packs and rearranges the digital image signal to obtain a rearranged digital signal so that the rearranged digital signal meets the input sequence of the liquid crystal on silicon chip. The rearranged data buffer module stores the rearranged digital signal according to the signal scheduling of the data adjustment control module.

[0057] Step S3, a control signal and a clock signal of the liquid crystal on silicon chip are generated based on a data driving module according to the rearranged digital signal, and the digital image signal, the clock signal and the control signal are output to the liquid crystal on silicon chip.

[0058] Specifically, the data driving module comprises a driving control module, a data parsing module, a driving signal generation module and a data alignment module. The driving control module controls the data parsing module, the driving signal generation module and the data alignment module. The data parsing module obtains the rearranged digital signal. The driving signal generation module generates the control signal and the clock signal of the liquid crystal on silicon chip based on the rearranged digital signal. The data alignment module aligns the digital image signal, the clock signal and the control signal with the clock and then outputs them to the liquid crystal on silicon chip.

[0059] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A silicon-based liquid crystal chip control system applied to an FPGA, characterized in that, The system comprises: a data buffering module for converting an external video signal into a digital image signal and storing the same; the data buffering module comprises a frame data parsing module, a frame data storage module and a storage control module; the frame data parsing module is used for converting the external video signal into the digital image signal; the frame data storage module is connected with the frame data parsing module and is used for storing the digital image signal; the storage control module is connected with the frame data parsing module and the frame data storage module and is used for controlling the read frame number, the write frame number, the frame data storage position and the storage bit width of the frame data storage module; the frame data storage module comprises a storage space of three frame image sizes on the FPGA to realize three-level frame buffering, and the write frame number is always prior to the read frame number; a data adjusting module connected with the data buffering module and used for data rearrangement of the digital image signal to obtain a rearranged digital signal; the data adjusting module comprises a row data buffering module, a data rearrangement module, a rearranged data buffering module and a data adjusting control module; the row data buffering module is used for accessing the data buffering module to obtain and store the digital image signal; the data rearrangement module is connected with the row data buffering module and is used for packing and data rearrangement of the digital image signal to obtain a rearranged digital signal so that the rearranged digital signal meets the input sequence of the liquid crystal on silicon chip; the rearranged data buffering module is connected with the data rearrangement module and is used for storing the rearranged digital signal; the data adjusting control module is connected with the row data buffering module, the data rearrangement module and the rearranged data buffering module and is used for controlling the data access of the row data buffering module, the data rearrangement of the data rearrangement module and the data storage of the rearranged data buffering module; a data driving module connected with the data adjusting module and used for generating a control signal and a clock signal of the liquid crystal on silicon chip based on the rearranged digital signal and outputting the digital image signal, the clock signal and the control signal to the liquid crystal on silicon chip; the data driving module comprises a driving control module, a data parsing module, a driving signal generation module and a data alignment module; the driving control module is connected with the data parsing module, the driving signal generation module and the data alignment module and is used for controlling the data parsing module, the driving signal generation module and the data alignment module; the data parsing module is used for accessing the data adjusting module to obtain the rearranged digital signal; the driving signal generation module is connected with the data parsing module and is used for generating a control signal and a clock signal of the liquid crystal on silicon chip based on the rearranged digital signal; the data alignment module is connected with the driving signal generation module and is used for outputting the digital image signal, the clock signal and the control signal to the liquid crystal on silicon chip after clock alignment.

2. The silicon-based liquid crystal chip control system of claim 1, wherein: The data buffering module obtains the external video signal through an HDMI interface.

3. The silicon-based liquid crystal chip control system of claim 1, wherein: The data rearrangement module rearranges the packaged digital image signal into a plurality of groups of parallel structure rearranged digital signals through pipeline operation.

4. The silicon-based liquid crystal chip control system of claim 1, wherein: The data alignment module outputs signals through a high-speed external interface.

5. The silicon-based liquid crystal chip control system of claim 1, wherein: The control signals include row driving signals and field driving signals.

6. A silicon-based liquid crystal chip control method applied to an FPGA, characterized in that, The method comprises the following steps: The external video signal is converted into a digital image signal based on a data buffering module, and is stored; the data buffering module comprises a frame data analysis module, a frame data storage module and a storage control module; the frame data analysis module is used to convert the external video signal into the digital image signal; the frame data storage module is connected with the frame data analysis module, and is used to store the digital image signal; the storage control module is connected with the frame data analysis module and the frame data storage module, and is used to control the read frame number, the write frame number, the frame data storage position and the storage bit width of the frame data storage module; the frame data storage module comprises a storage space of three frame image sizes on the FPGA to realize three-level frame buffering, and the write frame number is always prior to the read frame number; The data adjustment module is used to rearrange the digital image signal to obtain a rearranged digital signal; the data adjustment module comprises a row data buffering module, a data rearrangement module, a rearranged data buffering module and a data adjustment control module; the row data buffering module is used to access the data buffering module to obtain and store the digital image signal; the data rearrangement module is connected with the row data buffering module, and is used to package and rearrange the digital image signal to obtain a rearranged digital signal so that the rearranged digital signal meets the input sequence of the liquid crystal on silicon chip; the rearranged data buffering module is connected with the data rearrangement module, and is used to store the rearranged digital signal; the data adjustment control module is connected with the row data buffering module, the data rearrangement module and the rearranged data buffering module, and is used to control the data access of the row data buffering module, the data rearrangement of the data rearrangement module and the data storage of the rearranged data buffering module; The data driving module generates a control signal and a clock signal of the silicon-based liquid crystal chip based on the rearranged digital signal, and outputs the digital image signal, the clock signal and the control signal to the silicon-based liquid crystal chip; the data driving module comprises a driving control module, a data analysis module, a driving signal generation module and a data alignment module; the driving control module is connected with the data analysis module, the driving signal generation module and the data alignment module, and is used for controlling the data analysis module, the driving signal generation module and the data alignment module; the data analysis module is used for accessing the data adjustment module and obtaining the rearranged digital signal; the driving signal generation module is connected with the data analysis module, and is used for generating a control signal and a clock signal of the silicon-based liquid crystal chip based on the rearranged digital signal; the data alignment module is connected with the driving signal generation module, and is used for outputting the digital image signal, the clock signal and the control signal to the silicon-based liquid crystal chip after aligning the digital image signal, the clock signal and the control signal with the clock.

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