Method for preparing split gate structure

Abstract

The present invention provides a method for preparing a split gate structure. On the premise of ensuring the total thickness of the silicon nitride layer, the preparation of the silicon nitride layer is divided into two growths and two etchings, and between the two etchings, the silicon oxide layer is dry-etched once, so that the silicon oxide layer at the bottom of the isolation sidewall is not undercut based on the anisotropic characteristics of the dry etching, the window of the silicon oxide layer is reduced, and the probability of the gate oxide layer of the first gate structure being oxidized again is reduced. Furthermore, after the second growth of the silicon nitride layer, an oxygen plasma oxidation step is added to reduce the loss of the silicon nitride layer of the isolation sidewall and protect the surface of the isolation sidewall.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuits and relates to a method for preparing a split gate structure. Background Art

[0002] Split-gate technology is widely used in the field of semiconductor integrated circuit manufacturing, especially in non-volatile memory such as Flash memory. The split-gate structure usually includes a select gate, a control gate, and a storage gate. This structure is designed to improve the isolation of the memory cell and reduce bit cell interference, thereby improving the performance and reliability of the memory.

[0003] The existing split gate preparation mainly includes the following steps:

[0004] See also Figure 1 , forming a first gate structure 20 on the silicon substrate 10, wherein the first gate structure 20 includes a first gate oxide layer 21 and a first polysilicon gate layer 22;

[0005] See also Figure 2 , forming a stacked silicon oxide layer 30 and a silicon nitride layer 40 around the first gate structure 20;

[0006] See also Figure 3 , removing a portion of the silicon nitride layer 40 by dry etching to expose the silicon oxide layer 30 , and retaining the silicon nitride layer 40 located on the sidewall of the first gate structure 20 ;

[0007] See also Figure 4 , removing a portion of the silicon oxide layer 30 by wet etching to expose the silicon substrate 10 , and retaining the silicon oxide layer 30 located on the sidewall of the first gate structure 20 ;

[0008] See also Figure 5 A second gate structure 50 is formed on the exposed silicon substrate 10, and the second gate structure 50 includes a second gate oxide layer 51 and a second polysilicon gate layer 52, and the first gate structure 10 and the second gate structure 50 are separated by a reserved silicon oxide layer 30 and a silicon nitride layer 40 as isolation sidewalls.

[0009] In order to ensure the anti-leakage capability between the first gate structure 20 and the second gate structure 50 , a thicker silicon oxide layer 30 and a silicon nitride layer 40 are used as isolation sidewalls to ensure the voltage resistance of the dielectric layer between the gates.

[0010] However, due to the feature of using relatively thick silicon oxide layer 30 and silicon nitride layer 40, before growing the second gate oxide layer 51 of the second gate structure 50, the silicon oxide layer 30 is removed due to the isotropy of the wet process and the large window of the silicon oxide layer at the bottom of the isolation sidewall, such as Figure 4In the embodiment, the silicon oxide layer 30 with a thickness of H will inevitably produce a side-digging phenomenon at the bottom of the isolation spacer of the first gate structure 20, such as Figure 4 In the middle A region, there is a risk of process short circuit, and because thicker silicon oxide layer 30 and silicon nitride layer 40 are used, and the larger window of the silicon oxide layer at the bottom of the isolation sidewall is not covered by the silicon nitride layer 40, that is, there is a larger silicon oxide layer 30 with a thickness of H under the silicon nitride layer 40 with a thickness of D, so when the second gate oxide layer 51 is grown, there is a risk of re-oxidizing the first gate oxide layer 21 of the first gate structure 20, such as Figure 5 In the process, the first gate oxide layer 21 is oxidized again, resulting in a thickness difference of the first gate oxide layer 21 being thin in the middle and thick on both sides, which affects the device performance.

[0011] Therefore, it is necessary to provide a method for preparing a split-gate structure. Summary of the invention

[0012] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for preparing a split gate structure, which is used to solve the problems such as the above-mentioned undercut and re-oxidation of the gate oxide layer generated when preparing the isolation spacer of the split gate structure in the prior art.

[0013] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a split gate structure, comprising the following steps:

[0014] providing a silicon substrate;

[0015] forming a first gate structure on the silicon substrate;

[0016] forming a silicon oxide layer and a first silicon nitride layer on the silicon substrate, wherein the silicon oxide layer covers the first gate structure, and the first silicon nitride layer covers the silicon oxide layer;

[0017] Performing dry etching on the first silicon nitride layer to remove a portion of the first silicon nitride layer to expose the silicon oxide layer, and retaining the first silicon nitride layer located at the sidewall of the first gate structure;

[0018] performing dry etching on the silicon oxide layer to thin the silicon oxide layer;

[0019] forming a second silicon nitride layer on the silicon substrate, wherein the second silicon nitride layer covers the silicon oxide layer and the first silicon nitride layer;

[0020] performing dry etching on the second silicon nitride layer to remove a portion of the second silicon nitride layer to expose the silicon oxide layer, and retaining the second silicon nitride layer located at the sidewall of the first gate structure;

[0021] Wet-etching the silicon oxide layer to expose the silicon substrate;

[0022] A second gate structure is formed on the silicon substrate, and a sidewall of the second gate structure is in contact with the second silicon nitride layer.

[0023] Optionally, a thickness of the first silicon nitride layer is smaller than a thickness of the second silicon nitride layer.

[0024] Optionally, a ratio of a thickness of the first silicon nitride layer to a thickness of the second silicon nitride layer is 1:2.

[0025] Optionally, the thickness of the thinned silicon oxide layer is in the range of 2 to 3 nm.

[0026] Optionally, between the steps of forming the second silicon nitride layer and dry-etching the second silicon nitride layer, a step of performing surface oxidation treatment on the second silicon nitride layer using oxygen plasma is also included.

[0027] Optionally, when the first silicon nitride layer is dry-etched, an endpoint detection method is adopted; when the second silicon nitride layer is dry-etched, an endpoint detection method is adopted.

[0028] Optionally, when the silicon oxide layer is wet-etched, the etching solution includes hydrofluoric acid.

[0029] Optionally, the total thickness of the first silicon nitride layer and the second silicon nitride layer is 10-15 nm; the thickness of the silicon oxide layer before thinning is 6-12 nm.

[0030] Optionally, the first gate structure includes a first gate oxide layer and a first polysilicon gate layer, and the second gate structure includes a second gate oxide layer and a second polysilicon gate layer.

[0031] Optionally, the first gate structure includes a storage gate structure, and the second gate structure includes a selection gate structure.

[0032] As described above, the preparation method of the split gate structure of the present invention divides the preparation of the silicon nitride layer into two growths and two etchings under the premise of ensuring the total thickness of the silicon nitride layer, and between the two etchings, the silicon oxide layer is dry-etched once, so as to ensure that the silicon oxide layer at the bottom of the isolation sidewall is not undercut based on the anisotropic characteristics of the dry etching, reduce the window of the silicon oxide layer, and reduce the probability of the first gate oxide layer of the first gate structure being oxidized again. Furthermore, adding the step of oxygen plasma oxidation after the second growth of the silicon nitride layer can reduce the loss of the silicon nitride layer of the isolation sidewall and protect the surface of the isolation sidewall. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of the structure after the first gate structure is formed in the prior art.

[0034] Figure 2 It is a schematic diagram of the structure after forming a stacked silicon oxide layer and a silicon nitride layer in the prior art.

[0035] Figure 3 It is a schematic diagram of the structure after a portion of the silicon nitride layer is removed by dry etching in the prior art.

[0036] Figure 4 It is a schematic diagram of the structure after a portion of the silicon oxide layer is removed by wet etching in the prior art.

[0037] Figure 5 It is a schematic diagram of the structure after the second gate structure is formed in the prior art.

[0038] Figure 6 Shown is a process flow chart of preparing a split gate structure according to the present invention.

[0039] Figure 7 It is a schematic diagram of the structure after forming the first gate structure in an embodiment of the present invention.

[0040] Figure 8 It is a schematic diagram of the structure after a stacked silicon oxide layer and a first silicon nitride layer are formed in an embodiment of the present invention.

[0041] Fig. 9 It is a schematic diagram of the structure after a portion of the first silicon nitride layer is removed by dry etching in an embodiment of the present invention.

[0042] Fig.10 It is a schematic diagram of the structure after a portion of the silicon oxide layer is removed by dry etching in an embodiment of the present invention.

[0043] Fig.11 It is a schematic diagram of the structure after forming the second silicon nitride layer in an embodiment of the present invention.

[0044] Fig.12 It is a schematic diagram of the structure after a portion of the second silicon nitride layer is removed by dry etching in an embodiment of the present invention.

[0045] Fig.13 It is a schematic diagram of the structure after a portion of the silicon oxide layer is removed by wet etching in an embodiment of the present invention.

[0046] Fig.14 It is a schematic diagram of the structure after the second gate structure is formed in the embodiment of the present invention.

[0047] Description of Reference Numerals

[0048] 10, 100 - silicon substrate; 20, 200 - first gate structure; 21, 201 - first gate oxide layer; 22, 202 - first polysilicon gate layer; 30, 300 - silicon oxide layer; 40 - silicon nitride layer; 401 - first silicon nitride layer; 402 - second silicon nitride layer; 50, 500 - second gate structure; 51, 501 - second gate oxide layer; 52, 502 - second polysilicon gate layer. DETAILED DESCRIPTION

[0049] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0051] For ease of description, spatial relational terms such as “under”, “below”, “below”, “below”, “over”, etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.

[0052] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0053] See also Figure 6 , this embodiment provides a method for preparing a split-gate structure, comprising the following steps:

[0054] S1: Provide silicon substrate;

[0055] S2: forming a first gate structure on the silicon substrate;

[0056] S3: forming a silicon oxide layer and a first silicon nitride layer on the silicon substrate, wherein the silicon oxide layer covers the first gate structure, and the first silicon nitride layer covers the silicon oxide layer;

[0057] S4: performing dry etching on the first silicon nitride layer to remove a portion of the first silicon nitride layer to expose the silicon oxide layer, and retaining the first silicon nitride layer located on the sidewall of the first gate structure;

[0058] S5: performing dry etching on the silicon oxide layer to thin the silicon oxide layer;

[0059] S6: forming a second silicon nitride layer on the silicon substrate, wherein the second silicon nitride layer covers the silicon oxide layer and the first silicon nitride layer;

[0060] S7: performing dry etching on the second silicon nitride layer to remove a portion of the second silicon nitride layer to expose the silicon oxide layer, and retaining the second silicon nitride layer located on the sidewall of the first gate structure;

[0061] S8: wet-etching the silicon oxide layer to expose the silicon substrate;

[0062] S9: forming a second gate structure on the silicon substrate, wherein a sidewall of the second gate structure contacts the second silicon nitride layer.

[0063] In this embodiment, the first gate structure is a storage gate structure having a first gate oxide layer and a first polysilicon gate layer, and the second gate structure is a selection gate structure having a second gate oxide layer and a second polysilicon gate layer, but the specific types of the first gate structure and the second gate structure are not limited thereto.

[0064] In this embodiment, under the premise of ensuring the total thickness of the silicon nitride layer at the isolation sidewall, the preparation of the silicon nitride layer is divided into two growths and two etchings, and between the two etchings, the silicon oxide layer is dry-etched once, so as to ensure that the silicon oxide layer at the bottom of the isolation sidewall is not undercut based on the anisotropic characteristics of the dry etching, reduce the window of the silicon oxide layer, and reduce the probability of the first gate oxide layer of the first gate structure being oxidized again.

[0065] The following combination Figure 7 to Figure 14 , further introduction is given to the preparation of the split gate structure.

[0066] First, see Figure 6 and Figure 7 , perform step S1, provide a silicon substrate 100, the size of the silicon substrate 100 is not excessively limited here, and can be a wafer-level size, such as 6 inches, 8 inches, 12 inches, etc.

[0067] Next, see Figure 6 and Figure 7 , executing step S2 to form a first gate structure 200 on the silicon substrate 100 .

[0068] Specifically, the first gate structure 200 includes a first gate oxide layer 201 formed by a thermal oxidation process, and a first polysilicon gate layer 202 located on the first gate oxide layer 201, wherein the preparation and size of the first gate oxide layer 201 and the first polysilicon gate layer 202 can be selected as needed and are not excessively restricted herein.

[0069] Next, see Figure 6 and Figure 8 , performing step S3 to form a silicon oxide layer 300 and a first silicon nitride layer 401 on the silicon substrate 100 , wherein the silicon oxide layer 300 covers the first gate structure 200 , and the first silicon nitride layer 401 covers the silicon oxide layer 300 .

[0070] Specifically, the method for forming the silicon oxide layer 300 and the first silicon nitride layer 401 may adopt a low pressure chemical vapor deposition (LPCVD) method with good coverage performance, but the method for preparing the silicon oxide layer 300 and the first silicon nitride layer 401 is not limited thereto.

[0071] Among them, see Fig.14 In order to achieve the isolation performance between the first gate structure 200 and the second gate structure 500, that is, the anti-leakage ability between the first gate structure 200 and the second gate structure 500, the thickness H of the silicon oxide layer 300 constituting the isolation sidewall is preferably 6-12nm, and the thickness D of the silicon nitride, that is, the thickness D of the silicon nitride composed of the sum of the thickness D1 of the first silicon nitride layer 401 and the thickness D2 of the second silicon nitride layer 402, is preferably 10-15nm. For example, the thickness H of the silicon oxide layer 300 can be any value within the range of 6nm, 9nm, 10nm, 12nm, etc., and the thickness D of the silicon nitride can be any value within the range of 10nm, 12nm, 13nm, 15nm, etc.

[0072] As an example, preferably, the thickness D1 of the first silicon nitride layer 401 is smaller than the thickness D2 of the second silicon nitride layer 402 .

[0073] Specifically, when the thickness D1 of the first silicon nitride layer 401 is less than the thickness D2 of the second silicon nitride layer 402, when the subsequent step S9 is performed, that is, when the second gate oxide layer 501 of the second gate structure 500 is prepared by a thermal oxidation process, the second silicon nitride layer 402 with a larger thickness can better prevent the penetration of oxygen, reduce the probability of the first gate oxide layer 201 being oxidized again, and reduce the phenomenon of thickness difference in the first gate oxide layer 201, so as to improve device performance.

[0074] Among them, it is preferred that the ratio of the thickness D1 of the first silicon nitride layer 401 to the thickness D2 of the second silicon nitride layer 402 is 1:2, so that under the premise of ensuring the total thickness D of the silicon nitride layer, that is, ensuring the isolation effect of the silicon nitride layer, the first silicon nitride layer 401 with a thickness of D1 can protect the silicon oxide layer 300 located on the side wall of the first gate structure 200, and the probability of the first gate oxide layer 201 being oxidized again can be reduced by the second silicon nitride layer 402 with a thickness of D2.

[0075] Next, see Figure 6 and Fig. 9 , perform step S4, dry-etch the first silicon nitride layer 401, remove a portion of the first silicon nitride layer 401 to expose the silicon oxide layer 300, and retain the first silicon nitride layer 401 located on the side wall of the first gate structure 200.

[0076] Specifically, when the first silicon nitride layer 401 is dry-etched, an endpoint detection method is used to stop etching in time when the first silicon nitride layer 401 is removed to expose the silicon oxide layer 300, thereby reducing over-etching of the silicon oxide layer 300. For the method of dry-etching the first silicon nitride layer 401, reference may be made to the prior art, which is not limited here.

[0077] Next, see Figure 6 and Fig.10 , executing step S5, dry etching the silicon oxide layer 300 to thin the silicon oxide layer 300.

[0078] For details, see Figure 9~Figure 10 After the silicon oxide layer 300 is dry-etched, the thickness H of the silicon oxide layer 300 can be reduced to a thickness of H1, and the reserved silicon oxide layer 300 with a thickness of H1 can protect the silicon substrate 100 and the first polysilicon gate layer 202 to avoid damage to the silicon substrate 100 and the first polysilicon gate layer 202.

[0079] Among them, based on the anisotropic characteristics of dry etching, it can be ensured that the silicon oxide layer 300 at the bottom of the isolation sidewall is not side-excavated, so as to reduce the thickness of the silicon oxide layer 300. The thickness H1 of the reserved silicon oxide layer 300, that is, the thickness of the silicon oxide layer 300 remaining in the polysilicon gate layer spacing region, is preferably 2-3 nm, such as a value within any range of 2 nm, 3 nm, etc., and the reserved thinner silicon oxide layer 300 can reduce the window of the silicon oxide layer 300, that is, the window of the silicon oxide layer 300 is reduced from the thickness H to the thickness H1. It can effectively avoid the phenomenon that the silicon oxide layer 300 is side-hollowed out during the subsequent step S8, that is, when the reserved silicon oxide layer 300 is wet-etched, thereby effectively reducing the risk of process short circuit in the isolation side wall. The smaller window of the silicon oxide layer 300 can also reduce the probability of the first gate oxide layer 201 being re-oxidized during the subsequent preparation of the second gate oxide layer 501 of the second gate structure 500, thereby avoiding the phenomenon that the first gate oxide layer 201 has a thickness difference of being thin in the middle and thick on both sides due to re-oxidation, thereby improving device performance.

[0080] Next, see Figure 6 and Fig.11 , perform step S6 to form a second silicon nitride layer 402 on the silicon substrate 100 , wherein the second silicon nitride layer 402 covers the silicon oxide layer 300 and the first silicon nitride layer 401 .

[0081] Specifically, the method for preparing the second silicon nitride layer 402 may adopt LPCVD with good coverage performance, but the method for preparing the second silicon nitride layer 402 is not limited thereto.

[0082] Among them, it is preferred that the ratio of the thickness D1 of the first silicon nitride layer 401 to the thickness D2 of the second silicon nitride layer 402 is 1:2, and the sum D of the thickness D1 of the first silicon nitride layer 401 and the thickness D2 of the second silicon nitride layer 402 is 10~15nm, wherein, for the values ​​and beneficial effects of the thickness D1 of the first silicon nitride layer 401 and the thickness D2 of the second silicon nitride layer 402, please refer to the above content and will not be repeated here.

[0083] As an example, after forming the second silicon nitride layer 402, a step of performing surface oxidation treatment on the second silicon nitride layer 402 using oxygen plasma is also included to reduce the loss of the second silicon nitride layer 402 on the surface of the side wall of the first gate structure 200 in the subsequent etching process to protect the isolation side wall surface.

[0084] Next, see Figure 6 and Fig.12, perform step S7, dry-etch the second silicon nitride layer 402, remove a portion of the second silicon nitride layer 402 to expose the silicon oxide layer 300, and retain the second silicon nitride layer 402 located on the side wall of the first gate structure 200.

[0085] Specifically, when the second silicon nitride layer 402 is dry-etched, an endpoint detection method is used to stop etching in time when the second silicon nitride layer 402 is removed to expose the silicon oxide layer 300, thereby reducing over-etching of the silicon oxide layer 300. For the method of dry-etching the second silicon nitride layer 402, reference may be made to the prior art, which is not limited here.

[0086] Next, see Figure 6 and Fig.13 , perform step S8 to wet-etch the silicon oxide layer 300 to expose the silicon substrate 100 .

[0087] As an example, when the silicon oxide layer 300 is wet-etched, the etching solution is preferably hydrofluoric acid to utilize the selective etching ratio of silicon oxide to silicon material to prevent damage to the silicon substrate 100 and the first polysilicon gate layer 202 when etching the silicon oxide layer 300 .

[0088] Among them, since the silicon oxide layer 300 has a relatively thin thickness H1, the window of the silicon oxide layer 300 is relatively small, so that the probability of side cutting of the silicon oxide layer 300 during wet etching can be effectively reduced.

[0089] Next, see Figure 6 and Fig.14 , performing step S9 to form a second gate structure 500 on the silicon substrate 100 , and the sidewall of the second gate structure 500 is in contact with the second silicon nitride layer 402 .

[0090] For details, see Fig.13 and Fig.14 The second gate structure 500 includes the second gate oxide layer 501 formed by a thermal oxidation process, and the second polysilicon gate layer 502 located on the second gate oxide layer 501, wherein the preparation and size of the second gate oxide layer 501 and the second polysilicon gate layer 502 can be selected as needed and are not excessively restricted herein.

[0091] Among them, since the silicon oxide layer 300 has a relatively thin thickness H1, the window of the silicon oxide layer 300 is relatively small, which can effectively reduce the probability of the first gate oxide layer 201 being oxidized again.

[0092] In summary, the preparation method of the split gate structure of the present invention divides the preparation of the silicon nitride layer into two growths and two etchings under the premise of ensuring the total thickness of the silicon nitride layer, and between the two etchings, the silicon oxide layer is dry-etched once, so as to ensure that the silicon oxide layer at the bottom of the isolation sidewall is not undercut based on the anisotropic characteristics of the dry etching, reduce the window of the silicon oxide layer, and reduce the probability of the first gate oxide layer of the first gate structure being oxidized again. Furthermore, adding the step of oxygen plasma oxidation after the second growth of the silicon nitride layer can reduce the loss of the silicon nitride layer of the isolation sidewall and protect the surface of the isolation sidewall.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a split-gate structure, characterized in that: The following steps are involved: providing a silicon substrate; forming a first gate structure on the silicon substrate; forming a silicon oxide layer and a first silicon nitride layer on the silicon substrate, wherein the silicon oxide layer covers the first gate structure, and the first silicon nitride layer covers the silicon oxide layer; Performing dry etching on the first silicon nitride layer to remove a portion of the first silicon nitride layer to expose the silicon oxide layer, and retaining the first silicon nitride layer located at the sidewall of the first gate structure; performing dry etching on the silicon oxide layer to thin the silicon oxide layer; forming a second silicon nitride layer on the silicon substrate, wherein the second silicon nitride layer covers the silicon oxide layer and the first silicon nitride layer; performing dry etching on the second silicon nitride layer to remove a portion of the second silicon nitride layer to expose the silicon oxide layer, and retaining the second silicon nitride layer located at the sidewall of the first gate structure; Wet-etching the silicon oxide layer to expose the silicon substrate; A second gate structure is formed on the silicon substrate, and a sidewall of the second gate structure is in contact with the second silicon nitride layer.

2. The method for preparing a split-gate structure according to claim 1, characterized in that: The thickness of the first silicon nitride layer is smaller than the thickness of the second silicon nitride layer.

3. The method for preparing a split-gate structure according to claim 1, characterized in that: The ratio of the thickness of the first silicon nitride layer to the thickness of the second silicon nitride layer is 1:

2.

4. The method for preparing a split-gate structure according to claim 1, characterized in that: The thickness of the thinned silicon oxide layer is in the range of 2-3 nm.

5. The method for preparing a split-gate structure according to claim 1, characterized in that: The step of performing surface oxidation treatment on the second silicon nitride layer by using oxygen plasma is included between the step of forming the second silicon nitride layer and the step of dry-etching the second silicon nitride layer.

6. The method for preparing a split-gate structure according to claim 1, characterized in that: When the first silicon nitride layer is dry-etched, an endpoint detection method is used; when the second silicon nitride layer is dry-etched, an endpoint detection method is used.

7. The method for preparing a split-gate structure according to claim 1, characterized in that: When the silicon oxide layer is wet-etched, the etching solution includes hydrofluoric acid.

8. The method for preparing a split-gate structure according to claim 1, characterized in that: The total thickness of the first silicon nitride layer and the second silicon nitride layer is 10-15 nm; the thickness of the silicon oxide layer before thinning is 6-12 nm.

9. The method for preparing a split-gate structure according to claim 1, characterized in that: The first gate structure includes a first gate oxide layer and a first polysilicon gate layer, and the second gate structure includes a second gate oxide layer and a second polysilicon gate layer.

10. The method for preparing a split-gate structure according to claim 1, characterized in that: The first gate structure includes a storage gate structure, and the second gate structure includes a selection gate structure.

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