Semiconductor structure and method of forming

Abstract

The application provides a semiconductor structure and a forming method thereof, and the forming method comprises the following steps: providing a substrate; forming a first shallow trench isolation structure in the substrate; forming a drift region in the substrate, the first shallow trench isolation structure is located in the drift region, the drift region comprises a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region is greater than that in the second drift region, and one side and part of the bottom of the first shallow trench isolation structure are located in the second drift region; forming a gate structure on the surface of the substrate, the gate structure covers the surface of the second drift region and extends to the surface of the part of the first shallow trench isolation structure in the first drift region; the width of the depletion region is increased, the electric field is evenly distributed as much as possible, the difficulty of avalanche breakdown is improved, the breakdown voltage is greatly improved, the quality of the semiconductor structure is improved, and the application range is wide.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method. BACKGROUND

[0002] LDMOS (Laterally Diffused Metal Oxide Semiconductor) is a high-voltage semiconductor device widely used in radio frequency base stations, plasma display panel (PDP) display driving, power management, and automotive electronics, etc. Compared with traditional IGBT (Insulated Gate Bipolar Transistor), it has higher response speed and lower leakage current, and as a planar device, it has greater advantages in process integration. Adding a shallow trench isolation (STI) region in the drift region of the traditional LDMOS device can effectively improve the breakdown voltage of the high-voltage device, and also improve the on-resistance of the device, so the STI type LDMOS device has been widely applied. Because in most applications, the drain end often needs to be connected to a high voltage, the influence of the hot carrier effect is very prominent. In the field of device reliability, the density and position information of the interface trap have an important effect on the reliability of the device.

[0003] The BVDS (Breakdown Voltage) is an important parameter of the LDMOS, and also an important aspect of the reliability of the LDMOS device. Although the LDMOS has a low-doped drift region, which makes it have a higher breakdown voltage compared with other MOS devices, but with the development needs of high-voltage and high-power in society, it is necessary to improve the breakdown voltage of the LDMOS device.

[0004] Adding an STI in the drift region of the traditional LDMOS device can effectively improve the breakdown voltage of the LDMOS device, so the STI type LDMOS device has been widely applied. However, the power LDMOS device has a "silicon limit" constraint relationship. While improving the LDMOS device, the on-resistance will also increase. While using the STI type LDMOS device to improve the breakdown voltage, the on-resistance of the LDMOS device will greatly increase.

[0005] The performance of the LDMOS device needs to be improved. SUMMARY

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a forming method thereof, so as to improve the performance of the semiconductor structure.

[0007] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first shallow trench isolation structure in the substrate; forming a drift region in the substrate, wherein the first shallow trench isolation structure is located in the drift region, the drift region includes a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region is greater than the ion concentration in the second drift region, and one side and part of the bottom of the first shallow trench isolation structure are located in the second drift region; forming a gate structure on the surface of the substrate, wherein the gate structure covers the surface of the second drift region and extends to the surface of the portion of the first shallow trench isolation structure in the first drift region.

[0008] Optionally, the ion type in the first drift region is the same as the ion type in the second drift region, the width of the first drift region in the first direction is greater than the width of the second drift region in the first direction, and the first direction is parallel to the channel direction.

[0009] Optionally, a width of the first shallow trench isolation structure in the second drift region is smaller than a width of the first shallow trench isolation structure in the first drift region, and a direction of the width is parallel to a channel direction.

[0010] Optionally, a ratio of a width of the first shallow trench isolation structure in the second drift region to a width of the first shallow trench isolation structure in the first drift region is in a range of 0.2:1-0.4:1, and a direction of the width is parallel to a channel direction.

[0011] Optionally, the method of forming the drift region comprises: forming a first mask layer on the surface of the substrate, the first mask layer having a first mask layer opening therein, the bottom of the first mask layer opening exposing a portion of the top surface of the first shallow trench isolation structure and a portion of the surface of the substrate on one side of the first shallow trench isolation structure; performing a first ion implantation on the exposed surface of the substrate and the exposed portion of the substrate at the bottom of the first shallow trench isolation structure to form the first drift region; removing the first mask layer; forming a second mask layer on the surface of the substrate, the second mask layer having a second mask layer opening therein, the bottom of the second mask layer opening exposing the top surface of the first shallow trench isolation structure outside the first drift region and a portion of the surface of the substrate on one side of the first shallow trench isolation structure and adjacent to the first drift region; performing a second ion implantation on the exposed surface of the substrate and the exposed portion of the substrate at the bottom of the first shallow trench isolation structure to form the second drift region, the first drift region and the second drift region forming the drift region, the first drift region and the second drift region being adjacent to each other, and the first shallow trench isolation structure being located in the drift region.

[0012] Optionally, the process parameters of the first ion implantation include that the implanted element is phosphorus, the implanted dopant amount is about 4E12 atom / cm 2 -5E12 atom / cm 2 , and the implanted energy is about 100 Kev-200 Kev.

[0013] Optionally, the process parameters of the second ion implantation include that the implanted element is phosphorus, the implanted dopant amount is about 2E12 atom / cm 2 -3E12 atom / cm 2 , and the implanted energy is about 100 Kev-200 Kev.

[0014] Optionally, after the gate structure is formed, the method further comprises: forming a body doping region in the substrate on one side of the gate structure, the body doping region and the first drift region being located on two sides of the second drift region.

[0015] Optionally, the ion type in the drift region is opposite to the ion type of the body doping region.

[0016] Optionally, the method further comprises: forming a first source / drain doping region in the drift region and the body doping region on two sides of the gate structure; and forming a second source / drain doping region in the body doping region between the adjacent first source / drain doping regions.

[0017] Correspondingly, the application also provides a semiconductor structure, comprising: a substrate; a first shallow trench isolation structure in the substrate; a drift region in the substrate, the first shallow trench isolation structure being in the drift region, the drift region comprising a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region being greater than that in the second drift region, one side and part of the bottom of the first shallow trench isolation structure being in the second drift region; and a gate structure on the surface of the substrate, the gate structure covering the surface of the second drift region and extending to the surface of part of the first shallow trench isolation structure in the first drift region.

[0018] Optionally, the width of the first drift region in a first direction is greater than that of the second drift region in the first direction, the first direction being parallel to the channel direction.

[0019] Optionally, the width of the first shallow trench isolation structure in the second drift region is less than that in the first drift region, the ratio of the width of the first shallow trench isolation structure in the second drift region to that in the first drift region being in the range of 0.2:1-0.4:1, the width being parallel to the channel direction.

[0020] Compared with the prior art, the technical scheme of the application has the following advantages:

[0021] In the forming method of the semiconductor structure, the substrate is provided, the first shallow trench isolation structure is formed in the substrate, the drift region is formed in the substrate, the first shallow trench isolation structure is in the drift region, the drift region comprises the first drift region and the second drift region, the ion concentration in the first drift region is greater than that in the second drift region, the sidewall and part of the bottom of the first shallow trench isolation structure are in the second drift region, the gate structure is formed on the surface of part of the drift region, the gate structure covers the second drift region and extends to the surface of part of the first shallow trench isolation structure in the first drift region; the ion concentration in the second drift region is reduced by means of reducing the ion concentration in the second drift region, the contact area between the bottom of the gate structure and the second drift region is reduced, the width of the depletion region is increased, the electric field is as evenly distributed as possible, the difficulty of avalanche breakdown is increased, the breakdown voltage is greatly improved, the quality of the semiconductor structure is improved, and the application range is wide. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 It is a sectional view of the semiconductor structure in an embodiment;

[0023] Figure 2 It is an electric field distribution of the semiconductor structure in an embodiment;

[0024] Figures 3 to 9 is a schematic diagram of the structure of each step of the method for forming a semiconductor structure in an embodiment of the present application;

[0025] Figure 10 is an electric field distribution diagram of a semiconductor structure in an embodiment of the present application. DETAILED DESCRIPTION

[0026] As the background art, the performance of the existing semiconductor structure is poor, combined with Figure 1 and Figure 2 are described in detail.

[0027] Please refer to Figure 1 , the semiconductor structure includes a substrate 100; a shallow trench isolation structure 101 located in the substrate 100; a drift region 102 located in the substrate 100, at least one shallow trench isolation structure 101 is located in the drift region 102 and the drift region 102 also extends to the bottom of the adjacent one shallow trench isolation structure; a body doped region 104 is formed in the substrate 100; a gate structure 103 is formed on the substrate 100, the gate structure 103 is located on the top surface of the shallow trench isolation structure of part of the drift region and the gate structure 103 is also located on the surface of the substrate 100 between the body doped region 104 and the drift region 102; the substrate 100 on both sides of the gate structure 103 is doped to form a source-drain doped region 105.

[0028] The inventor found that the contact area between the shallow trench isolation structure at the bottom of the gate structure and the drift region in such a semiconductor structure is the area where the electric field is concentrated (the dotted line ring in the figure), which is easy to cause impact ionization, thereby causing avalanche breakdown, reducing the quality of the semiconductor structure, according to Figure 2 the breakdown voltage BV is 55V and Rsp is 37.

[0029] The inventor found through research that a substrate is provided, a first shallow trench isolation structure is formed in the substrate, a drift region is formed in the substrate, the first shallow trench isolation structure is located in the drift region, the drift region includes a first drift region and a second drift region, the ion concentration in the first drift region is greater than the ion concentration in the second drift region, one side wall and part of the bottom of the first shallow trench isolation structure are located in the second drift region, a gate structure is formed on the surface of the substrate in part of the drift region, the gate structure covers the second drift region and extends to the surface of the part of the first shallow isolation trench structure in the first drift region; by means of reducing the concentration of injected ions in the second drift region, the withstand voltage of the contact area between the first shallow trench isolation structure at the bottom of the gate structure and the second drift region is reduced, the widening of the depletion region is increased, the electric field is as evenly distributed as possible, the difficulty of avalanche breakdown is increased, thereby greatly improving the breakdown voltage and improving the quality of the semiconductor structure, which has a wide range of applications.

[0030] In order to make the above object, features and advantages of the present application more obvious and comprehensible, specific embodiments of the present application will be described in detail below with reference to the drawings.

[0031] Figures 3 to 9 is a schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present application.

[0032] Referring to Figure 3 , a substrate 200 is provided.

[0033] In this embodiment, the material of the substrate 200 is silicon.

[0034] In other embodiments, the material of the substrate 200 also includes single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon germanium, gallium arsenide and other semiconductor materials.

[0035] In this embodiment, the substrate 200 is a P-type substrate 200.

[0036] Referring to Figure 3 , the substrate 200 is etched to form a first shallow trench 201 in the substrate 200.

[0037] In this embodiment, in the process of etching the substrate 200, in addition to forming the first shallow trench 201, a plurality of shallow trenches are also formed, for example, a second shallow trench 202 is also formed in the substrate 200. Figure 3

[0038] In this embodiment, two shallow trenches are shown.

[0039] Referring to Figure 4 , an isolation layer is filled in the first shallow trench 201 to form a first shallow trench isolation structure 203.

[0040] In this embodiment, the second shallow trench 202 is also filled at the same time when the first shallow trench 201 is filled, and a second shallow trench isolation structure 204 is formed in the second shallow trench 202.

[0041] In this embodiment, the method for forming the first shallow trench isolation structure 203 and the second shallow trench isolation structure 204 includes forming an isolation structure film (not shown) on the substrate 200; etching back the isolation structure film to form the first shallow trench isolation structure 203 and the second shallow trench isolation structure 204.

[0042] The process for forming the isolation structure film is a deposition process, such as a fluid chemical vapor deposition process. The fluid chemical vapor deposition process is used to form the isolation structure film, so that the filling performance of the isolation structure film is better.

[0043] In this embodiment, the material of the isolation layer includes silicon oxide.​

[0044] In this embodiment, after the shallow trench is fully filled with the isolation layer, the isolation layer is planarized until its surface is flush with the surface of the substrate 200 .

[0045] For the process of forming the drift region in the substrate 200, please refer to Figures 5 to 6 .

[0046] Please refer to Figure 5 A first mask layer (not shown in the figure) is formed on the surface of the substrate 200, and a first mask layer opening (not shown in the figure) is provided in the first mask layer. The bottom of the first mask layer opening exposes a portion of the top surface of the first shallow trench isolation structure 203 and a portion of the surface of the substrate 200 on one side of the first shallow trench isolation structure 203.

[0047] Specifically, the first mask layer opening exposes a portion of the top surface of the first shallow trench isolation structure 203, a portion of the top surface of the second shallow trench isolation structure 204, and the surface of the substrate 200 between the first shallow trench isolation structure 203 and the second shallow trench isolation structure 204. The size of the first shallow trench isolation structure 203 exposed by the first mask layer opening is larger than the size of the second shallow trench isolation structure 204 exposed by the first mask layer opening.

[0048] In this embodiment, a first ion implantation is performed on the exposed surface of the substrate 200 and the exposed bottom of the first shallow trench isolation structure 203 of the substrate 200 to form the first drift region 205 .

[0049] In this embodiment, after the first drift region 205 is formed, the first mask layer is removed.

[0050] In this embodiment, the material of the first mask layer is photoresist.

[0051] In other embodiments, the material of the first mask layer may also be a hard mask layer such as silicon oxide, silicon nitride, etc.

[0052] In this embodiment, the ion type of the first ion implantation is N-type ions.

[0053] In other embodiments, the ion type of the first ion implantation may also be P-type ions.

[0054] In this embodiment, the process parameters of the first ion implantation include that the implanted element is phosphorus, the doping dose of the ion implantation is about 4E12atom / cm2-5E12atom / cm2, and the energy of the ion implantation is about 100Kev-200Kev.

[0055] In the embodiment, the process of removing the first mask layer is a gray etching process.

[0056] In other embodiments, the process of removing the first mask layer can be a wet etching process.

[0057] Please refer to Figure 6 A second mask layer (not shown in the figure) is formed on the surface of the substrate 200, and the second mask layer has a second mask layer opening (not shown in the figure) therein. The bottom of the second mask layer opening exposes the top surface of the first shallow trench isolation structure 203 outside the first drift region 205 and the surface of the substrate 200 located on one side of the first shallow trench isolation structure 203 and adjacent to the first drift region 205.

[0058] In the embodiment, the material of the second mask layer is photoresist.

[0059] In the embodiment, the exposed surface of the substrate 200 and the substrate 200 at the bottom of the first shallow trench isolation structure 203 are subjected to a second ion implantation to form the second drift region 206. The first drift region 205 and the second drift region 206 constitute the drift region, the first drift region 205 and the second drift region 206 are adjacent, and the first shallow trench isolation structure 203 is located in the drift region.

[0060] In the embodiment, the ion type of the second ion implantation is N-type.

[0061] In other embodiments, the ion type of the second ion implantation can also be P-type.

[0062] In the embodiment, the ion type of the first ion implantation is the same as the ion type of the second ion implantation.

[0063] In the embodiment, the width (a2) of the first shallow trench isolation structure 203 in the first direction located in the second drift region 206 is less than the width (a1) of the first shallow trench isolation structure 203 in the first direction located in the first drift region 205. The purpose of this design is to alleviate the density of the potential lines at the right side of the first shallow trench isolation structure 203 and the junction with the gate and at the lower right corner of the first shallow trench isolation structure 203, thereby alleviating the peak electric field strength at these positions to increase the breakdown voltage of the device.

[0064] In the embodiment, the ratio of the width (a2) of the first shallow trench isolation structure 203 in the first direction within the second drift region 206 to the width (a1) of the first shallow trench isolation structure 203 in the first direction within the first drift region 205 is in the range of 0.2:1-0.4:1, and the first direction is parallel to the channel direction.

[0065] In the embodiment, the process parameters of the second ion implantation include that the ion-implanted element is phosphorus, the ion-implanted dopant amount is about 2E12 atom / cm 2 -3E12 atom / cm 2 , and the ion-implanted energy is about 100Kev-200Kev.

[0066] In the embodiment, the ion concentration of the first drift region 205 is greater than the ion concentration within the second drift region 206.

[0067] Please refer to Figure 7 , a gate structure 207 is formed on the substrate 200, the gate structure 207 covers the surface of the second drift region 206 and extends to the surface of part of the first shallow trench isolation structure 203 within the first drift region 205.

[0068] In the embodiment, by using the ion concentration within the second drift region 206 being less than the ion concentration within the first drift region 205, the contact area between the gate structure 207 bottom shallow trench isolation structure and the second drift region 206 bears voltage, the expansion of the depletion region is increased, the electric field is as evenly distributed as possible, the difficulty of avalanche breakdown is increased, thereby greatly improving the breakdown voltage, improving the quality of the semiconductor structure, and having a wide range of applications.

[0069] In the embodiment, the gate structure 207 includes a gate oxide layer 207b formed on the surface of the substrate 200 and a gate layer 207a formed on the surface of the gate oxide layer 207b, and the material of the gate layer 207a is polysilicon.

[0070] In the embodiment, a side wall 207c is further formed on the sidewall of the gate structure 207.

[0071] Please refer to Figure 8 , a body-doped region 208 is formed in the substrate 200 on one side of the gate structure 207, and the body-doped region 208 and the first drift region 205 are located on both sides of the second drift region 206.

[0072] In the embodiment, the ion type doped in the body-doped region 208 is opposite to the ion type doped in the drift region.

[0073] In the embodiment, the ion type in the drift region is N type, and the ion type in the body doped region 208 is P type.

[0074] In the embodiment, the doping depth of the drift region and the body doped region 208 is the same.

[0075] Please refer to Figure 9 Further comprising: forming a first source-drain doped region 209 in the drift region and the body doped region 208 on both sides of the gate structure 207; and forming a second source-drain doped region 210 in the body doped region 208 between adjacent first source-drain doped regions 209.

[0076] In the embodiment, the ion type in the first source-drain doped region 209 is the same as the ion type in the first drift region 205.

[0077] In the embodiment, the ion type in the second source-drain doped region 210 is opposite to the ion type in the first source-drain doped region 209.

[0078] In the embodiment, please refer to Figure 10 After the semiconductor structure formed by the above method is applied with an electric field, the breakdown voltage BV thereof is 69V, and Rsp is 39, which greatly improves the difficulty of avalanche breakdown of the semiconductor structure, greatly improves BVDS of the LDMOS in the case that Rsp changes very little; the optimized IMP injection makes the depletion region of the LDMOS expand greatly, and the electric field distribution is more uniform; the optimized electric field is more conducive to the device reliability of the LDMOS, and does not introduce a new process step, but only divides the original forming mask of the drift region into two masks for injection, the cost change is not large, and has a wide range of application.

[0079] The meaning of Rsp is specific on-resistance, which is a normalized quantity used to eliminate the influence of different areas of resistance on performance, and represents the relationship between resistance and area in the on state, and the unit is mohm*mm. 2 .

[0080] Please refer to Figure 9The application further provides a semiconductor structure, comprising: a substrate 200; a first shallow trench isolation structure 203 in the substrate 200; a drift region in the substrate 200, the first shallow trench isolation structure 203 being in the drift region, the drift region comprising a first drift region 205 and a second drift region 206 adjacent to the first drift region 205, the ion concentration in the first drift region 205 being greater than the ion concentration in the second drift region 206, one side and part of the bottom of the first shallow trench isolation structure 203 being in the second drift region 206; a gate structure 207 on the surface of the substrate 200, the gate structure 207 covering the surface of the second drift region 206 and extending to the surface of the part of the first shallow trench isolation structure 203 in the first drift region 205.

[0081] In the embodiment, the width of the first drift region 205 in a first direction is greater than the width of the second drift region 206 in the first direction, the first direction being parallel to the channel direction.

[0082] In the embodiment, the width of the first shallow trench isolation structure 203 in the first direction in the second drift region 206 is less than the width of the first shallow trench isolation structure 203 in the first direction in the first drift region 205.

[0083] In the embodiment, the ratio of the width of the first shallow trench isolation structure 203 in the first direction in the second drift region 206 to the width of the first shallow trench isolation structure 203 in the first direction in the first drift region 205 ranges from 0.2:1 to 0.4:1, the first direction being parallel to the channel direction.

[0084] In the embodiment, further comprising: a side wall on the sidewall of the gate structure 207.

[0085] In the embodiment, further comprising: a body doped region 208 in the substrate 200 on one side of the gate structure 207, the body doped region 208 and the first drift region 205 being on both sides of the second drift region 206.

[0086] In the embodiment, the type of ions doped in the body doped region 208 is opposite to the type of ions doped in the drift region.

[0087] In the embodiment, the type of ions in the drift region is N type, and the type of ions in the body doped region 208 is P type.

[0088] In the embodiment, the doping depth of the drift region and the body doped region 208 is the same.

[0089] In the embodiment, the first source / drain doped region 209 is located in the drift region on both sides of the gate structure 207 and in the body doped region 208; and the second source / drain doped region 210 is located between the first source / drain doped regions 209 and in the body doped region 208.

[0090] In the embodiment, the type of ion doping in the first source / drain doped region 209 is opposite to that in the second source / drain doped region 210.

[0091] Although the present application has been disclosed with reference to the above embodiments, the present application is not limited to the above embodiments. Any modifications and changes can be made without departing from the spirit and scope of the present application, and the scope of protection of the present application should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a first shallow trench isolation structure in the substrate; forming a drift region in the substrate, wherein the first shallow trench isolation structure is located in the drift region, the drift region including a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region being greater than the ion concentration in the second drift region, and one side and a portion of the bottom of the first shallow trench isolation structure being located in the second drift region; A gate structure is formed on the surface of the substrate, where the gate structure covers the surface of the second drift region and extends to a surface of a portion of the first shallow trench isolation structure in the first drift region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The ion type in the first drift region is the same as the ion type in the second drift region. The width of the first drift region in a first direction is greater than the width of the second drift region in the first direction. The first direction is parallel to the channel direction.

3. The method for forming a semiconductor structure according to claim 1, wherein: The width of the first shallow trench isolation structure in the second drift region is smaller than the width of the first shallow trench isolation structure in the first drift region, and a direction of the width is parallel to a channel direction.

4. The method for forming a semiconductor structure according to claim 1, wherein: A ratio of a width of the first shallow trench isolation structure in the second drift region to a width of the first shallow trench isolation structure in the first drift region is in a range of 0.2:1-0.4:1, and a direction of the width is parallel to a channel direction.

5. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming the drift region includes: forming a first mask layer on the surface of the substrate, wherein the first mask layer has a first mask layer opening, and the bottom of the first mask layer opening exposes a portion of the top surface of the first shallow trench isolation structure and a portion of the surface of the substrate on one side of the first shallow trench isolation structure; Performing a first ion implantation on the exposed surface of the substrate and the exposed bottom of the first shallow trench isolation structure to form the first drift region; removing the first mask layer; forming a second mask layer on the surface of the substrate, wherein the second mask layer has a second mask layer opening, and the bottom of the second mask layer opening exposes the top surface of the first shallow trench isolation structure outside the first drift region and a portion of the substrate surface located on one side of the first shallow trench isolation structure and adjacent to the first drift region; A second ion implantation is performed on the exposed surface of the substrate and the substrate at the bottom of the first shallow trench isolation structure to form the second drift region. The first drift region and the second drift region constitute the drift region. The first drift region and the second drift region are adjacent to each other, and the first shallow trench isolation structure is located in the drift region.

6. The method for forming a semiconductor structure according to claim 5, wherein: The process parameters of the first ion implantation include that the element implanted is phosphorus and the doping dose of the ion implantation is about 4E12atom / cm 2 -5E12atom / cm 2 The energy of ion implantation is about 100Kev-200Kev.

7. The method for forming a semiconductor structure according to claim 5, wherein: The process parameters of the second ion implantation include that the element implanted is phosphorus and the doping dose of the ion implantation is about 2E12atom / cm 2 -3E12atom / cm 2 The energy of ion implantation is about 100Kev-200Kev.

8. The method for forming a semiconductor structure according to claim 1, wherein: After forming the gate structure, the method further includes: A body doping region is formed in the substrate at one side of the gate structure, and the body doping region and the first drift region are located on both sides of the second drift region.

9. The method for forming a semiconductor structure according to claim 8, wherein: The ion type in the drift region is opposite to the ion type in the body doping region.

10. The method for forming a semiconductor structure according to claim 8, wherein: Also includes: forming a first source-drain doped region in the drift region and the body doped region on both sides of the gate structure; A second source-drain doping region is formed in the body doping region between adjacent first source-drain doping regions.

11. A semiconductor structure, characterized in that include: substrate; a first shallow trench isolation structure located in the substrate; a drift region located in the substrate, wherein the first shallow trench isolation structure is located in the drift region, the drift region including a first drift region and a second drift region adjacent to the first drift region, the ion concentration in the first drift region being greater than the ion concentration in the second drift region, and one side and a portion of the bottom of the first shallow trench isolation structure being located in the second drift region; A gate structure is located on the surface of the substrate, and the gate structure covers the surface of the second drift region and extends to the surface of a portion of the first shallow trench isolation structure in the first drift region.

12. The semiconductor structure according to claim 11, wherein A width of the first drift region in a first direction is greater than a width of the second drift region in the first direction, and the first direction is parallel to a channel direction.

13. The semiconductor structure according to claim 11, wherein: The width of the first shallow trench isolation structure in the second drift region is smaller than the width of the first shallow trench isolation structure in the first drift region. The ratio of the width of the first shallow trench isolation structure in the second drift region to the width of the first shallow trench isolation structure in the first drift region is in the range of 0.2:1-0.4:1, and the direction of the width is parallel to the channel direction.

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