Methods for forming semiconductor structures

Abstract

A method for forming a semiconductor structure includes: providing a substrate; forming a dielectric structure on the substrate; forming a first groove within the dielectric structure, the width of the first groove being greater than its depth; forming a barrier layer on the sidewall surface of the first groove, the material of the barrier layer being different from the material of the dielectric structure; etching the dielectric structure at the bottom of the first groove using the barrier layer as a mask; and forming a second groove within the dielectric structure, the width of the second groove being smaller than the width of the first groove. The method improves the positional and dimensional accuracy of the second groove.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing processes, the contact hole process involves etching many tiny vertical vias on the ILD dielectric layer, and then forming metal within the vertical vias to interconnect the front and rear structures.

[0003] However, the process for forming small vertical through holes still needs improvement. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the process of forming fine vertical vias.

[0005] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a dielectric structure on the substrate; forming a first groove within the dielectric structure, wherein the width of the first groove is greater than the depth of the first groove; forming a barrier layer on the sidewall surface of the first groove, wherein the material of the barrier layer is different from the material of the dielectric structure; etching the dielectric structure at the bottom of the first groove using the barrier layer as a mask; and forming a second groove within the dielectric structure, wherein the width of the second groove is less than the width of the first groove.

[0006] Optionally, the dielectric structure has a first height in a direction perpendicular to the substrate surface, and the barrier layer has a second height in a direction perpendicular to the substrate surface, wherein the first height is greater than the second height.

[0007] Optionally, the ratio of the first height to the second height is in the range of 11:(1 to 1.7).

[0008] Optionally, forming a first groove within the dielectric structure includes: forming a first mask structure on the dielectric structure; etching the dielectric structure using the first mask structure as a mask to form the first groove within the dielectric structure.

[0009] Optionally, forming a barrier layer on the sidewall surface of the first groove includes: forming an initial barrier layer in the first groove, wherein the material of the initial barrier layer is different from the material of the dielectric structure; forming a second mask structure on the dielectric structure and the initial barrier layer; etching the initial barrier layer using the second mask structure as a mask until the bottom of the first groove is exposed, thereby forming a barrier layer on the sidewall surface of the first groove.

[0010] Optionally, etching the dielectric structure at the bottom of the first groove using the barrier layer as a mask to form a second groove within the dielectric structure includes: etching the dielectric structure at the bottom of the first groove using the second mask structure and the barrier layer as masks to form a second groove within the dielectric structure, wherein the width of the second groove is smaller than the width of the first groove.

[0011] Optionally, the depth of the first groove ranges from 300 angstroms to 500 angstroms.

[0012] Optionally, the projection range of the second groove on the substrate is located within the projection range of the first groove on the substrate.

[0013] Optionally, the thickness of the barrier layer located on the sidewall of the first groove ranges from 50 angstroms to 100 angstroms.

[0014] Optionally, the etching rate of the barrier layer is lower than the etching rate of the dielectric structure at the bottom of the first groove in the process of etching the dielectric structure using the barrier layer as a mask.

[0015] Optionally, the process of etching the dielectric structure at the bottom of the first groove using the barrier layer as a mask includes a dry etching process.

[0016] Optionally, the material of the barrier layer includes silicon nitride or silicon oxynitride.

[0017] Optionally, it further includes: forming a device layer on the substrate, the device layer including an isolation structure and a device structure located within the isolation structure, the device structure including a transistor, diode, triode, capacitor, inductor, or conductive structure; the dielectric structure including an isolation structure and a dielectric layer located on the isolation structure.

[0018] Optionally, the transistor includes: a gate structure located on a substrate and source / drain doped regions located in the substrate on both sides of the gate structure; the second groove exposes a portion of the top surface of the gate structure, or the second groove exposes a portion of the surface of the source / drain doped regions, or a plurality of the second grooves respectively expose a portion of the top surface of the gate structure and a portion of the surface of the source / drain doped regions.

[0019] Optionally, the isolation structure and the dielectric layer are made of the same material; the isolation structure and the dielectric layer are formed using different processes.

[0020] Optionally, the first mask structure includes: a first anti-reflective layer and a first photoresist layer located on the first anti-reflective layer, wherein the first photoresist layer exposes a portion of the surface of the first anti-reflective layer.

[0021] Optionally, the second mask structure includes: a hard mask layer, a second anti-reflective layer on the hard mask layer, and a second photoresist layer on the second anti-reflective layer, wherein the second photoresist layer exposes a portion of the surface of the second anti-reflective layer on the initial blocking layer.

[0022] Optionally, the material of the hard mask layer is different from the material of the second anti-reflective layer.

[0023] Optionally, the material of the hard mask layer includes silicon oxide or silicon nitride.

[0024] Optionally, the material of the second anti-reflective layer includes a dielectric anti-reflective layer.

[0025] Optionally, it also includes forming a conductive layer within the second groove.

[0026] Optionally, the method for forming the conductive layer includes: forming a conductive material layer in the first groove, the second groove, and on the dielectric structure; planarizing the conductive material layer and the dielectric structure until the blocking layer is removed, and forming a conductive layer in the second groove.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] The method of this invention involves forming a first groove within a dielectric structure, the width of which is greater than its depth, and then forming a barrier layer on the sidewall surface of the first groove. The dielectric structure at the bottom of the first groove is then etched using the barrier layer as a mask to form a second groove within the dielectric structure. The barrier layer is made of a different material than the dielectric structure, resulting in less wear on the barrier layer during etching to form the second groove. This allows for precise control of the width of the second groove by using the width of the first groove and the thickness of the barrier layer, improving the dimensional and positional accuracy of the second groove. This prevents the conductive layer from short-circuiting with adjacent devices due to positional drift during the subsequent formation of the conductive layer within the second groove. Attached Figure Description

[0029] Figures 1 to 7 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation

[0030] As described in the background section, the process for forming small vertical through-holes still needs improvement.

[0031] Specifically, due to the relatively thick ILD dielectric layer, the etching amount during vertical vias is large, which can easily cause the top opening of the via in contact with the photoresist to be etched. Subsequently, after metal filling, the via opening may be too large, causing short circuits between adjacent vias, resulting in a decrease in product yield.

[0032] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure. This involves forming a first groove within a dielectric structure, wherein the width of the first groove is greater than its depth, and then forming a barrier layer on the sidewall surface of the first groove. The dielectric structure at the bottom of the first groove is then etched using the barrier layer as a mask to form a second groove within the dielectric structure. The barrier layer is made of a different material than the dielectric structure, resulting in less loss of the barrier layer during etching to form the second groove. This allows for precise control of the width of the second groove by using the width of the first groove and the thickness of the barrier layer, improving the dimensional and positional accuracy of the second groove. This prevents the conductive layer from short-circuiting with adjacent devices due to positional drift during the subsequent formation of the conductive layer within the second groove.

[0033] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Figures 1 to 7 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0035] Please refer to Figure 1 Provide a substrate 100; form a dielectric structure on the substrate 100.

[0036] In this embodiment, the method further includes: forming a device layer on the substrate 100, the device layer including an isolation structure 104 and a device structure located within the isolation structure 104, the device structure including a transistor, diode, triode, capacitor, inductor or conductive structure; and forming a dielectric layer 105 on the device layer.

[0037] The dielectric structure includes an isolation structure 104 and a dielectric layer 105 located on the isolation structure 104.

[0038] The material of the isolation structure 104 includes a dielectric material, and the material of the dielectric layer 105 includes a dielectric material, wherein the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0039] In this embodiment, the isolation structure 104 and the dielectric layer 105 are made of the same material.

[0040] In this embodiment, the materials of the isolation structure 104 and the dielectric layer 105 include silicon oxide.

[0041] In this embodiment, the isolation structure 104 and the dielectric layer 105 are formed using different processes. The process for forming the isolation structure 104 includes a first chemical vapor deposition process, wherein the reaction gas in the first chemical vapor deposition process includes silane; the process for forming the dielectric layer 105 includes a second chemical vapor deposition process, wherein the reaction gas in the second chemical vapor deposition process includes tetraethyl orthosilicate (TEOS).

[0042] In other embodiments, the isolation structure and the dielectric layer are formed using the same process.

[0043] In other embodiments, the materials of the isolation structure and the dielectric layer are different.

[0044] In this embodiment, the device structure includes a transistor, which includes a gate structure 101 located on a substrate 100 and source / drain doped regions 103 located in the substrate 100 on both sides of the gate structure 101.

[0045] The transistor also includes a sidewall 102 located on the sidewall of the gate structure 101.

[0046] The gate structure 101 includes: a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0047] In one embodiment, the material of the gate dielectric layer includes silicon oxide or a low-k (K less than 3.9) material; the material of the gate layer includes polysilicon.

[0048] In one embodiment, the gate dielectric layer is made of a high dielectric constant material with a dielectric constant greater than 3.9. The gate dielectric layer material includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide; LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3(BST), Al2O3, Si3N4, oxynitrides, or other suitable materials; the gate layer material includes a metal, specifically tungsten.

[0049] The sidewall 102 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, and silicon oxynitride nitride. In this embodiment, the sidewall 102 is made of silicon nitride.

[0050] In other embodiments, the device structure also includes other structures that require external electrical connection.

[0051] Please continue to refer to this. Figure 1 The first mask structure is formed on the dielectric structure.

[0052] The first mask structure includes a first anti-reflection layer 106 and a first photoresist layer 107 located on the first anti-reflection layer 106, wherein the first photoresist layer 107 exposes a portion of the surface of the first anti-reflection layer 106.

[0053] In this embodiment, the first photoresist layer 107 has a first opening 108, which exposes a portion of the surface of the first antireflective layer 106. The first opening 108 has a first width in a direction X parallel to the surface of the substrate 100.

[0054] The first antireflective layer 106 includes a thin silicon antireflective layer (Si-ARC), an organic material bottom antireflective layer (organic BARC), a dielectric antireflective layer (DARC), or a combination of an organic bottom antireflective layer and a dielectric antireflective layer.

[0055] In this embodiment, the first anti-reflective layer 106 includes an organic material bottom anti-reflective layer (organicBARC).

[0056] Please refer to Figure 2 The medium structure is etched using the first mask structure as a mask to form a first groove 109 within the medium structure. The width of the first groove 109 is greater than the depth of the first groove 109.

[0057] The width of the first groove 109 is the dimension in the direction X parallel to the surface of the substrate 100, and the depth of the first groove 109 is the dimension in the direction perpendicular to the surface of the substrate 100.

[0058] In this embodiment, the depth of the first groove 109 ranges from 300 angstroms to 500 angstroms.

[0059] The width of the first groove 109 is greater than the depth of the first groove 109, so the first mask structure only requires two layers, the first anti-reflection layer 106 and the first photoresist layer 107, to ensure the morphology of the first groove 109. The film structure of the first mask structure can be simplified.

[0060] In this embodiment, the first groove 109 is located within the dielectric layer 105.

[0061] In other embodiments, the first groove is also located within the isolation structure.

[0062] Please refer to Figure 3 An initial barrier layer 110 is formed in the first groove 109, and the material of the initial barrier layer 110 is different from the material of the medium structure.

[0063] In this embodiment, the material of the initial barrier layer 110 is different from the material of the dielectric layer 105.

[0064] In this embodiment, the material of the initial barrier layer 110 includes silicon nitride or silicon oxynitride.

[0065] The method of forming the initial barrier layer 110 includes: forming a barrier material layer (not shown) on the medium structure and within the first groove 109; planarizing the barrier material layer until the surface of the medium structure is exposed, and forming the initial barrier layer 110 within the first groove 109.

[0066] In this embodiment, the dielectric structure has a first height in a direction perpendicular to the surface of the substrate 100, and the initial barrier layer 110 has a second height in a direction perpendicular to the surface of the substrate 100, wherein the first height is greater than the second height.

[0067] In this embodiment, the ratio of the first height to the second height is in the range of 11:(1~1.7).

[0068] Please refer to Figure 4 A second mask structure is formed on the medium structure and the initial barrier layer 110.

[0069] The second mask structure includes: a hard mask layer 111, a second anti-reflection layer 112 located on the hard mask layer 111, and a second photoresist layer 113 located on the second anti-reflection layer 112, wherein the second photoresist layer 113 exposes a portion of the surface of the second anti-reflection layer 112 on the initial barrier layer 110.

[0070] The material of the hard mask layer 111 is different from the material of the second anti-reflective layer 112.

[0071] In this embodiment, the hard mask layer 111 is made of silicon oxide or silicon nitride. The second antireflective layer 112 is made of a dielectric antireflective layer.

[0072] In this embodiment, the second photoresist layer 113 has a second opening 114, which exposes a portion of the surface of the second antireflective layer 112. The second opening 114 has a second width in a direction X parallel to the surface of the substrate 100, and the second width is smaller than the first width.

[0073] Next, the initial barrier layer 110 is etched using the second mask structure as a mask until the bottom of the first groove 109 is exposed, forming a barrier layer on the sidewall surface of the first groove 109. The dielectric structure at the bottom of the first groove 109 is then etched using the second mask structure and the barrier layer as masks, forming a second groove within the dielectric structure. The width of the second groove is smaller than the width of the first groove. Please refer to [link / reference] for details. Figure 5 and Figure 6 .

[0074] Please refer to Figure 5 Using the second photoresist layer 113 as a mask, the second anti-reflection layer 112 and the hard mask layer 111 are etched until the surface of the initial barrier layer 110 is exposed; the initial barrier layer 110 is etched again using the second mask structure as a mask until the bottom of the first groove 109 is exposed, and a barrier layer 115 is formed on the sidewall surface of the first groove 109.

[0075] In this embodiment, the thickness of the barrier layer 115 located on the sidewall of the first groove 109 ranges from 50 angstroms to 100 angstroms.

[0076] In this embodiment, the process of etching the initial barrier layer 110 using the second mask structure as a mask includes a dry etching process.

[0077] Please refer to Figure 6 Using the second mask structure and the barrier layer 115 as a mask, the dielectric structure at the bottom of the first groove 109 is etched, and a second groove 116 is formed in the dielectric structure. The width of the second groove 116 is smaller than the width of the first groove 109.

[0078] In this embodiment, the projection range of the second groove 116 on the substrate 100 is located within the projection range of the first groove 109 on the substrate 100.

[0079] In this embodiment, the dielectric structure has a first height in a direction perpendicular to the substrate surface, and the barrier layer 115 has a second height in a direction perpendicular to the substrate 100 surface, wherein the first height is greater than the second height.

[0080] Preferably, the ratio of the first height to the second height is in the range of 11:(1~1.7). During the subsequent etching process of the etching medium structure, the barrier layer 115 within the second height range can ensure that the barrier layer 115 is not easily consumed, thereby ensuring that the width of the first groove 109 and the thickness of the barrier layer 115 are precisely controlled to control the width of the second groove 116.

[0081] The second groove 116 exposes a portion of the top surface of the gate structure 101, or the second groove 116 exposes a portion of the surface of the source / drain doped region 103, or multiple second grooves 116 respectively expose a portion of the top surface of the gate structure 101 and a portion of the surface of the source / drain doped region 103.

[0082] In this embodiment, the second groove 116 exposes a portion of the surface of the source / drain doped region 103.

[0083] The material of the barrier layer 115 is different from that of the dielectric structure, so the loss of the barrier layer 115 is small when the dielectric structure is etched to form the second groove 116. Thus, the width of the second groove 116 can be precisely controlled by the width of the first groove 109 and the thickness of the barrier layer 115, which improves the dimensional accuracy and positional accuracy of the second groove 116. This avoids the situation where the conductive layer is easily short-circuited with adjacent devices due to the positional drift of the second groove 116 when a conductive layer is subsequently formed in the second groove 116.

[0084] In this embodiment, the process of etching the dielectric structure at the bottom of the first groove 109 using the second mask structure and the barrier layer 115 as a mask includes a dry etching process.

[0085] The etching process of the dielectric structure at the bottom of the first groove 109 using the second mask structure and the barrier layer 115 as a mask results in a lower etching rate for the barrier layer 115 than for the dielectric structure. This ensures that the consumption of the barrier layer 115 is minimized, and the width of the second groove 116 can be precisely controlled by the width of the first groove 109 and the thickness of the barrier layer 115.

[0086] Please continue to refer to this. Figure 6 After forming the second groove 116, the second mask structure is removed.

[0087] Please refer to Figure 7 A conductive layer 117 is formed in the second groove 116.

[0088] The method for forming the conductive layer 117 includes: forming a conductive material layer (not shown) in the first groove 109, the second groove 116 and the dielectric structure; planarizing the conductive material layer and the dielectric structure until the barrier layer 115 is removed, and forming the conductive layer 117 in the first groove 109 and the second groove 116.

[0089] In this embodiment, the barrier layer 115 is removed during the planarization of the conductive material layer and the dielectric structure, thereby removing the first groove 109 as well, and the conductive layer 117 is located in the second groove 116.

[0090] The process for planarizing the conductive material layer and the dielectric structure includes chemical mechanical polishing.

[0091] The conductive layer 117 is made of a metal or a metal nitride; the metal includes one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more of tantalum nitride and titanium nitride.

[0092] The formation method precisely controls the width of the second groove 116 by using the width of the first groove 109 and the thickness of the barrier layer 115, thereby improving the dimensional and positional accuracy of the second groove 116. This prevents the conductive layer 117 from being short-circuited with the gate structure 101 due to positional drift of the second groove 116 when the conductive layer 117 is formed in the second groove 116.

[0093] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A dielectric structure is formed on a substrate, the dielectric structure including an isolation structure and a dielectric layer located on the isolation structure; A first groove is formed within the dielectric structure, the width of the first groove being greater than its depth, and the first groove being located within the dielectric layer and the isolation structure; A barrier layer is formed on the sidewall surface of the first groove, and the material of the barrier layer is different from the material of the medium structure. Using the barrier layer as a mask, the dielectric structure at the bottom of the first groove is etched to form a second groove within the dielectric structure, the width of the second groove being smaller than the width of the first groove.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The dielectric structure has a first height in a direction perpendicular to the substrate surface, and the barrier layer has a second height in a direction perpendicular to the substrate surface, wherein the first height is greater than the second height.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The ratio of the first height to the second height is in the range of 11: (1~1.7).

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, Forming a first groove within the dielectric structure includes: forming a first mask structure on the dielectric structure; etching the dielectric structure using the first mask structure as a mask to form the first groove within the dielectric structure.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, Forming a barrier layer on the sidewall surface of the first groove includes: forming an initial barrier layer in the first groove, wherein the material of the initial barrier layer is different from the material of the dielectric structure; forming a second mask structure on the dielectric structure and the initial barrier layer; etching the initial barrier layer using the second mask structure as a mask until the bottom of the first groove is exposed, thereby forming a barrier layer on the sidewall surface of the first groove.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The process of etching the dielectric structure at the bottom of the first groove using the barrier layer as a mask to form a second groove within the dielectric structure includes: etching the dielectric structure at the bottom of the first groove using the second mask structure and the barrier layer as masks to form a second groove within the dielectric structure, wherein the width of the second groove is smaller than the width of the first groove.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The depth of the first groove ranges from 300 angstroms to 500 angstroms.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The projection range of the second groove on the substrate is within the projection range of the first groove on the substrate.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the barrier layer located on the sidewall of the first groove ranges from 50 angstroms to 100 angstroms.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The etching rate of the barrier layer is lower than the etching rate of the dielectric structure at the bottom of the first groove in the process of etching the barrier layer using the barrier layer as a mask.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of etching the dielectric structure at the bottom of the first groove using the barrier layer as a mask includes a dry etching process.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the barrier layer includes silicon nitride or silicon oxynitride.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: A device layer is formed on a substrate, the device layer including an isolation structure and a device structure located within the isolation structure, the device structure including a transistor, diode, triode, capacitor, inductor or conductive structure.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The transistor includes: a gate structure located on a substrate and source / drain doped regions located in the substrate on both sides of the gate structure; the second groove exposes a portion of the top surface of the gate structure, or the second groove exposes a portion of the surface of the source / drain doped regions, or a plurality of the second grooves respectively expose a portion of the top surface of the gate structure and a portion of the surface of the source / drain doped regions.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, The isolation structure and the dielectric layer are made of the same material; the isolation structure and the dielectric layer are formed using different processes.

16. The method for forming a semiconductor structure as described in claim 4, characterized in that, The first mask structure includes a first anti-reflective layer and a first photoresist layer located on the first anti-reflective layer, wherein the first photoresist layer exposes a portion of the surface of the first anti-reflective layer.

17. The method for forming a semiconductor structure as described in claim 5, characterized in that, The second mask structure includes: a hard mask layer, a second anti-reflective layer on the hard mask layer, and a second photoresist layer on the second anti-reflective layer, wherein the second photoresist layer exposes a portion of the surface of the second anti-reflective layer on the initial blocking layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The material of the hard mask layer is different from the material of the second anti-reflective layer.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The material of the hard mask layer includes silicon oxide or silicon nitride.

20. The method for forming a semiconductor structure as described in claim 18, characterized in that, The material of the second anti-reflective layer includes a dielectric anti-reflective layer.

21. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: A conductive layer is formed within the second groove.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, The method for forming the conductive layer includes: forming a conductive material layer in the first groove, the second groove, and on the dielectric structure; planarizing the conductive material layer and the dielectric structure until the blocking layer is removed; and forming a conductive layer in the second groove.

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