Contact hole etching optimization method, device and semiconductor device

Abstract

The present application relates to the field of semiconductor technology, and discloses a contact hole etching optimization method, device and semiconductor device, including performing a first etching process, etching a dielectric layer with a first etching gas, forming a first contact hole above a first part, and forming a second contact hole above a protruding part; performing an etch-back sputtering process, sputtering a barrier layer with an inert gas, forming a protective layer in the first contact hole, and stopping the etch-back sputtering process when the angle between the protective layer and the dielectric layer meets a preset angle threshold; performing a second etching process, continuing to etch the dielectric layer with the first etching gas, and stopping the second etching process when the bottom of the second contact hole exposes the barrier layer located above the protruding part; performing a third etching process, etching the barrier layer and the capacitor dielectric layer with a second etching gas. Its beneficial effect is to keep the contact hole in a vertical state.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a contact hole etching optimization method, device and semiconductor device. Background Art

[0002] In the BEOL (Back End of Line) semiconductor capacitor manufacturing process, the metal layer-insulator layer-metal layer (MIM) structure is widely used, especially in the context of the gradual reduction of interconnection structures. The metal hole of the MIM top plate is an important component of the connection between the semiconductor device and the external circuit, and its structural accuracy and reliability directly affect the device performance.

[0003] However, the traditional manufacturing process of the metal hole connecting the upper plate has some challenges, especially the sidewalls are prone to lateral etching, which causes the bottom size to increase, thereby destroying the accuracy of the structure. This change in size increases the risk of device short circuit. As integrated circuit technology continues to develop towards miniaturization, the etching aperture of the MIM structure has gradually decreased, but the etching depth has remained unchanged, resulting in an increase in the etching depth-to-width ratio, further exacerbating the difference in the etching depth-to-width ratio between the upper and lower plates. In addition, the related technology has limited control over the etching morphology of the upper plate holes in the MIM structure. The occurrence of lateral etching makes subsequent metal filling difficult and easily forms holes, which directly affects the reliability of the device.

[0004] Therefore, there is an urgent need to improve the manufacturing process of the MIM structure to enhance the overall performance and reliability of semiconductor devices. Summary of the invention

[0005] The present application provides a contact hole etching optimization method, device and semiconductor device, which solves the technical problem that the sidewalls of the contact holes are prone to lateral etching, and achieves the technical effect of reducing lateral etching and maintaining the vertical state of the contact holes.

[0006] In order to achieve the above objectives, the main technical solutions adopted in this application include:

[0007] In a first aspect, an embodiment of the present application provides a contact hole etching optimization method, the method comprising:

[0008] A substrate is provided, on which a capacitor and a dielectric layer on the outer surface of the capacitor are formed; wherein the capacitor comprises a first portion and a second portion arranged below the first portion, the second portion extending beyond the first portion in the length direction to form a protruding portion; the first portion comprises an upper plate and an upper plate metal barrier layer, the upper plate metal barrier layer being formed on the upper plate; the second portion comprises a lower plate and a capacitor dielectric layer, the capacitor dielectric layer being formed between the upper plate and the lower plate; the upper surface of the first portion and the upper surface of the protruding portion are both covered with a barrier layer;

[0009] Performing a first etching process, etching the dielectric layer using a first etching gas, forming a first contact hole above the first portion, and forming a second contact hole above the protruding portion, and stopping the first etching process when the bottom of the first contact hole exposes the barrier layer above the first portion;

[0010] Performing an etch-back sputtering process, sputtering the barrier layer using an inert gas to form a protective layer in the first contact hole, and stopping the etch-back sputtering process when an angle between the protective layer and the dielectric layer meets a preset angle threshold;

[0011] Performing a second etching process, continuing to etch the dielectric layer using the first etching gas, and stopping the second etching process when the bottom of the second contact hole exposes the barrier layer located above the protruding portion;

[0012] A third etching process is performed to etch the barrier layer and the capacitor dielectric layer using a second etching gas, so that the bottom of the first contact hole exposes the upper electrode metal barrier layer and the bottom of the second contact hole exposes the lower electrode.

[0013] The present embodiment provides a contact hole etching optimization method, which first forms a capacitor structure of a first part and a second part on a substrate at the same time, especially the design of the protruding part, so as to effectively utilize space, improve the integration of the capacitor, and reduce the occupied area of ​​the circuit board. Through the first etching process and the second etching process, the contact hole formed can accurately expose the key layer in the capacitor, ensure good electrical contact performance, and improve the signal transmission efficiency and reliability of the overall circuit. The back etching and sputtering process provides an additional layer of protection for the contact hole, reduces the potential impact of subsequent processes on the performance of the capacitor, and enhances the stability and durability of the entire structure during production and use. By adopting different gases and process steps, etching and coating can be effectively layered, so that the interaction between different materials is minimized, thereby improving the compatibility of the multi-layer structure and ensuring good connection between the layers.

[0014] Optionally, the preset angle threshold range is 10° to 30°.

[0015] Optionally, the barrier layer has a thickness ranging from 30 nm to 100 nm.

[0016] Optionally, in the second etching process, an etching selectivity ratio between the dielectric layer and the barrier layer ranges from 7:1 to 10:1.

[0017] Optionally, the first etching gas includes at least one of C4F8 and CF4; and the second etching gas is CH2F2.

[0018] Optionally, process conditions of the first etching process and the second etching process include:

[0019] The etching flow rate range is 5sccm to 20sccm;

[0020] The etching pressure range is 30mT to 200mT;

[0021] The etching power ranges from 200W to 1000W.

[0022] Optionally, the process conditions of the etch-back sputtering process include:

[0023] The inert gas flow rate ranges from 100 sccm to 300 sccm;

[0024] The etch-back pressure ranges from 30mT to 100mT;

[0025] High frequency power range is 1000W to 2000W;

[0026] The low frequency power range is 100W to 200W.

[0027] Optionally, the process conditions of the third etching process include:

[0028] The etching flow rate range is 10sccm to 50sccm;

[0029] The etching pressure ranges from 30mT to 100mT;

[0030] The etching power ranges from 300W to 700W.

[0031] Optionally, the material of the upper electrode plate and the lower electrode plate includes aluminum; the material of the metal barrier layer of the upper electrode plate includes titanium nitride; and the material of the capacitor dielectric layer includes silicon nitride.

[0032] Optionally, the material of the barrier layer includes silicon oxynitride; and the material of the dielectric layer includes silicon dioxide.

[0033] In a second aspect, an embodiment of the present application provides an etching optimization device for a contact hole, the device comprising:

[0034] A capacitor acquisition unit, used for providing a substrate, on which a capacitor and a dielectric layer on the outer surface of the capacitor are formed; wherein the capacitor comprises a first part and a second part arranged below the first part, the second part extending beyond the first part in the length direction to form a protruding part; the first part comprises an upper plate and an upper plate metal barrier layer, the upper plate metal barrier layer being formed on the upper plate; the second part comprises a lower plate and a capacitor dielectric layer, the capacitor dielectric layer being formed between the upper plate and the lower plate; the upper surface of the first part and the upper surface of the protruding part are both covered with a barrier layer;

[0035] a first etching unit, configured to perform a first etching process, etching the dielectric layer using a first etching gas, forming a first contact hole above the first portion, and forming a second contact hole above the protruding portion, and stopping the first etching process when the bottom of the first contact hole exposes the barrier layer above the first portion;

[0036] an etch-back sputtering unit, configured to perform an etch-back sputtering process, sputter the barrier layer using an inert gas to form a protective layer in the first contact hole, and stop the etch-back sputtering process when an angle between the protective layer and the dielectric layer meets a preset angle threshold;

[0037] a second etching unit, configured to perform a second etching process, continue etching the dielectric layer using the first etching gas, and stop the second etching process when the bottom of the second contact hole exposes the barrier layer above the protruding portion;

[0038] The third etching unit is used to perform a third etching process, using a second etching gas to etch the barrier layer and the capacitor dielectric layer so that the bottom of the first contact hole exposes the upper electrode metal barrier layer and the bottom of the second contact hole exposes the lower electrode.

[0039] In a third aspect, an embodiment of the present application provides a semiconductor device, which is manufactured based on the above-mentioned contact hole etching optimization method. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0041] Figure 1 A schematic diagram of the structure of a capacitor provided by the prior art;

[0042] Figure 2 A flow chart of a contact hole etching optimization method provided in an embodiment of the present application;

[0043] Figure 3-Figure 7 A schematic diagram of the structure of each step of a contact hole etching optimization method provided in an embodiment of the present application;

[0044] Figure 8 A block diagram of a contact hole etching optimization device provided in an embodiment of the present application.

[0045] Description of Reference Numerals

[0046] 1-substrate, 2-capacitor, 3-dielectric layer, 4-barrier layer, 5-first contact hole, 6-second contact hole, 7-protective layer, 21-first part, 22-second part, 23-protruding part, 211-upper plate, 212-upper plate metal barrier layer, 221-lower plate, 222-capacitor dielectric layer. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0048] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0049] Figure 1 A schematic diagram of the structure of a capacitor provided by the prior art. The current method of forming the capacitor MIM is referenced Figure 1 A substrate 1 is provided, on which a capacitor 2 and a dielectric layer 3 on the outer surface of the capacitor 2 are formed; wherein the capacitor 2 includes a first portion 21 and a second portion 22 arranged below the first portion 21, the second portion 22 extends beyond the first portion 21 in the length direction to form a protruding portion 23; the first portion 21 includes an upper electrode plate 211 and an upper electrode plate metal barrier layer 212, the upper electrode plate metal barrier layer 212 is formed on the upper electrode plate 211; the second portion 22 includes a lower electrode plate 221 and a capacitor dielectric layer 222, the capacitor dielectric layer 222 is formed between the upper electrode plate 211 and the lower electrode plate 221; the upper surface of the first portion 21 and the upper surface of the protruding portion 23 are both covered with a barrier layer 4.

[0050] In the manufacturing process of the contact holes, there are problems caused by the contact holes of different depths during the etching process. The first contact hole 5 is etched to the upper plate metal barrier layer 212, and the second contact hole 6 is etched to the lower plate 221. Due to the inconsistent depth, when the first contact hole 5 has been etched to the upper plate metal barrier layer 212, the second contact hole 6 continues to etch downwards. During this period of time, the etched gas in the first contact hole 5 cannot etch downwards, so it will etch laterally, and then may etch the barrier layer 4 on the side, causing the bottom size of the first contact hole 5 to become larger, destroying the structural accuracy, and the local size becomes larger, increasing the risk of device short circuit.

[0051] In order to solve the above technical problems, according to an embodiment of the present application, an embodiment of a contact hole etching optimization method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0052] In this embodiment, a contact hole etching optimization method is provided. Figure 2 A flow chart of a contact hole etching optimization method provided in an embodiment of the present application, Figure 3-Figure 7 A schematic diagram of an etching optimization process for forming a contact hole provided in an embodiment of the present application. The process includes the following steps:

[0053] Step S1, please refer to Figure 3 A substrate 1 is provided, on which a capacitor 2 and a dielectric layer 3 on the outer surface of the capacitor 2 are formed; wherein the capacitor 2 includes a first portion 21 and a second portion 22 arranged below the first portion 21, the second portion 22 extends beyond the first portion 21 in the length direction to form a protruding portion 23; the first portion 21 includes an upper electrode plate 211 and an upper electrode plate metal barrier layer 212, the upper electrode plate metal barrier layer 212 is formed on the upper electrode plate 211; the second portion 22 includes a lower electrode plate 221 and a capacitor dielectric layer 222, the capacitor dielectric layer 222 is formed between the upper electrode plate 211 and the lower electrode plate 221; the upper surface of the first portion 21 and the upper surface of the protruding portion 23 are both covered with a barrier layer 4.

[0054] Specifically, the material of the upper plate 211 and the lower plate 221 includes aluminum; the material of the upper plate metal barrier layer 212 includes titanium nitride; the material of the capacitor dielectric layer 222 includes silicon nitride; the material of the barrier layer 4 includes silicon oxynitride; and the material of the dielectric layer 3 includes silicon dioxide.

[0055] Step S3, please refer to Figure 4, perform a first etching process, use a first etching gas to etch the dielectric layer 3, form a first contact hole 5 above the first portion 21, and form a second contact hole 6 above the protruding portion 23, and stop the first etching process when the bottom of the first contact hole 5 exposes the barrier layer 4 located above the first portion 21.

[0056] Specifically, the dielectric layer 3 is etched using a first etching gas. The dielectric layer 3 is usually made of silicon dioxide (SiO2) or other insulating materials, and is located above the first portion 21 and the protruding portion 23 of the capacitor 2. By etching the dielectric layer 3, a first contact hole 5 is formed above the first portion 21, and this contact hole will be used to connect to the upper plate metal barrier layer 212 later. At the same time, a second contact hole 6 is formed above the protruding portion 23, and this contact hole will be used to connect to the lower plate 221 later. When the bottom of the first contact hole 5 is etched to the barrier layer 4, it is considered that the first etching process is completed. The barrier layer 4 is usually made of silicon nitride (Si3N4) or other etching-resistant materials. Once the barrier layer 4 is exposed at the bottom of the first contact hole 5, that is, when the barrier layer 4 is etched, the first etching process needs to be stopped immediately. This is usually determined by controlling the time to determine whether to stop the first etching process immediately. Based on past production experience and data, a rough time range can be established, which is determined based on the thickness of the dielectric layer 3 to the barrier layer 4. Alternatively, experimental methods such as slicing (cross-sectional analysis) can be used to determine how much time is required to etch the actual thickness of the dielectric layer 3. Endpoint detection technology can also be used to monitor the etching process in real time, and the exact moment when the dielectric layer 3 is etched and the bottom of the first contact hole 5 exposes the barrier layer 4 is detected, thereby accurately stopping the etching process. Endpoint detection can be achieved based on changes in optical, spectral or other physical properties.

[0057] In some preferred embodiments, the first etching gas includes at least one of C4F8 or CF4.

[0058] In some preferred embodiments, the process conditions of the first etching process include: an etching flow rate range of 5 sccm to 20 sccm; an etching pressure range of 30 mT to 200 mT; and an etching power range of 200 W to 1000 W.

[0059] Specifically, the first etching gas C4F8 or CF4 is mainly used to remove materials by releasing fluorine free radicals, which is plasma etching. These fluorine free radicals can react chemically with the dielectric layer 3 to generate gaseous volatile products, such as water vapor and carbon dioxide, thereby removing materials. The etching flow rate determines the amount of gas for etching, thereby affecting the etching rate and uniformity. A higher flow rate can provide more reactive gas, but it may also affect the uniformity of etching. The etching pressure affects the density of the plasma and the energy of the ions. A lower etching pressure is generally conducive to improving anisotropy, while a higher etching pressure may lead to isotropic etching. The etching power controls the energy of the plasma, thereby affecting the energy of ion bombardment. A higher etching power can increase the etching rate, but it may also increase the risk of damage to the dielectric layer 3. Therefore, the embodiment of the present application can accurately control the etching process by limiting these process condition parameters, ensuring that the size and shape of the contact hole meet the design requirements, while avoiding damage to the barrier layer 4 to achieve the best etching effect.

[0060] Step S5, please refer to Figure 5 , perform an etch-back sputtering process, use an inert gas to sputter the barrier layer 4, form a protective layer 7 in the first contact hole 5, and stop the etch-back sputtering process when the angle between the protective layer 7 and the dielectric layer 3 meets a preset angle threshold.

[0061] The etch-back sputtering process is a technique for forming the protection layer 7 , and its purpose is to form a layer of protection layer 7 in the contact hole to prevent accidental etching of the dielectric layer 3 on the bottom sidewall of the first contact hole 5 in subsequent process steps.

[0062] Specifically, the purpose of the back-etching sputtering process is to use an inert gas to sputter the barrier layer 4 and form a protective layer 7 on the bottom side wall of the first contact hole 5. The function of this protective layer 7 is to protect the dielectric layer 3 on the bottom side wall of the first contact hole 5 from being over-etched in the subsequent etching process, thereby maintaining the size and structural accuracy of the contact hole. Inert gas, such as argon, nitrogen or helium, is introduced and excited to form plasma. The ions in the plasma are used to bombard the surface of the barrier layer 4, so that the barrier layer 4 is sputtered out in the form of particles and deposited on the bottom side wall of the first contact hole 5 to form a protective layer 7. It should be noted that the material of the protective layer 7 and the barrier layer 4 is the same. For example, if the material of the barrier layer 4 is silicon oxynitride, the material of the protective layer 7 is also silicon oxynitride. When the angle between the protective layer 7 and the dielectric layer 3 reaches a preset angle threshold, the back-etching sputtering process is stopped. This angle threshold is pre-set to ensure that the protective layer 7 can protect the bottom side wall of the first contact hole 5 in the subsequent etching process, while avoiding excessive deposition affecting the subsequent process. Through this etch-back sputtering process, the bottom sidewall of the first contact hole 5 can be effectively protected to avoid the enlargement of the size and the damage of the structural precision caused by lateral etching, thereby reducing the risk of device short circuit and improving the reliability and performance of the semiconductor device.

[0063] It should be noted that, as can be seen from the figure, the protective layer 7 is inclined and closely attached to the dielectric layer 3 on the bottom side wall of the first contact hole 5. Here, the angle between the protective layer 7 and the dielectric layer 3 is the angle between the downward oblique direction of the top of the protective layer 7 and the vertical direction of the side wall of the first contact hole 5.

[0064] In some preferred embodiments, the preset angle threshold ranges from 10° to 30°, and the thickness of the barrier layer ranges from 30 nm to 100 nm.

[0065] Specifically, by controlling this angle, it can be ensured that the protective layer 7 is completely etched away in the subsequent etching process, while the dielectric layer 3 at the bottom side wall of the first contact hole 5 is not damaged, so that the first contact hole 5 remains vertical and does not deform. If the angle is too small (less than 10°), the protective layer 7 may be too thin to provide sufficient protection, resulting in damage to the bottom side wall of the first contact hole 5 in the subsequent etching. If the angle is too large (greater than 30°), the protective layer 7 may be too thick, resulting in the inability to completely remove the protective layer 7 in the subsequent etching process, affecting the electrical performance of the device.

[0066] In some preferred embodiments, the process conditions of the etch-back sputtering process include: an inert gas flow range of 100 sccm to 300 sccm; an etch-back pressure range of 30 mT to 100 mT; a high-frequency power range of 1000 W to 2000 W; and a low-frequency power range of 100 W to 200 W.

[0067] Specifically, the inert gas flow rate determines the density of the plasma and the rate of ion generation. A higher flow rate can increase the density of the plasma, allowing the inert gas to quickly enter the bottom of the first contact hole 5, effectively sputtering the barrier layer 4, thereby increasing the sputtering rate. Pressure affects the characteristics of the plasma and the energy of the ions. Lower pressures are generally conducive to improving the anisotropy of sputtering, while higher pressures may lead to isotropic sputtering. High-frequency power controls the energy of the plasma, affecting the bombardment energy and sputtering rate of the ions. Higher high-frequency power can increase the energy of the ions, increase the forward etching capability, and quickly sputter the barrier layer 4 to the bottom sidewall of the first contact hole 5 to form a protective layer 7. Low-frequency power can reduce physical etching and prevent etching back losses on the bottom sidewall of the first contact hole 5. By precisely controlling these process conditions, the quality of the formation of the protective layer 7 can be ensured, thereby effectively protecting the bottom sidewall of the first contact hole 5 in subsequent etching processes and improving the reliability and performance of semiconductor devices.

[0068] Step S7, please refer to Figure 6 , perform a second etching process, continue to etch the dielectric layer 3 using the first etching gas, and stop the second etching process when the bottom of the second contact hole 6 exposes the barrier layer 4 located above the protruding portion 23.

[0069] Specifically, the dielectric layer 3 is continuously etched with the first etching gas. Since the first contact hole 5 has reached the barrier layer 4, the etching gas cannot continue to etch downward, so lateral etching occurs. This lateral etching may cause the dielectric layer 3 on the bottom sidewall of the first contact hole 5 to be etched, thereby changing the size and shape of the first contact hole 5. At this time, the protective layer 7 can protect the dielectric layer 3 on the bottom sidewall of the first contact hole 5 from being affected by the lateral etching. The second contact hole 6 continues to be etched downward until its bottom exposes the barrier layer 4 located above the protruding portion 23, and the second etching process is stopped.

[0070] In some preferred embodiments, the etching selectivity ratio of the dielectric layer to the barrier layer in the second etching process ranges from 7:1 to 10:1.

[0071] Specifically, the etching selectivity etches the dielectric layer 3 more effectively than would otherwise be helpful in minimizing the etching of the barrier layer 4.

[0072] In some preferred embodiments, the process conditions of the second etching process include: an etching flow rate range of 5 sccm to 20 sccm; an etching pressure range of 30 mT to 200 mT; and an etching power range of 200 W to 1000 W.

[0073] Specifically, the etching flow rate determines the amount of gas for etching, thereby affecting the etching rate and uniformity. A higher flow rate can provide more reactive gas, but it may also affect the uniformity of etching. The etching pressure affects the density of the plasma and the energy of the ions. A lower etching pressure is generally beneficial to improving anisotropy, while a higher etching pressure may lead to isotropic etching. The etching power controls the energy of the plasma, thereby affecting the energy of ion bombardment. A higher etching power can increase the etching rate, but it may also increase the risk of damage to the dielectric layer 3. Therefore, the embodiments of the present application can accurately control the etching process by limiting these process condition parameters to ensure that the size and shape of the contact hole meet the design requirements to achieve the best etching effect.

[0074] Step S9, please refer to Figure 7 , perform a third etching process, and use the second etching gas to etch the barrier layer 4 and the capacitor dielectric layer 222, so that the bottom of the first contact hole 5 exposes the upper electrode metal barrier layer 212 and the bottom of the second contact hole 6 exposes the lower electrode 221.

[0075] Specifically, the second etching gas is used to remove the barrier layer 4 and the capacitor dielectric layer 222 , so that the upper electrode metal barrier layer 212 is exposed at the bottom of the first contact hole 5 , and the lower electrode 221 is exposed at the bottom of the second contact hole 6 .

[0076] It should be noted that in the third etching, a second etching gas is used, which should have a high etching rate for the barrier layer 4 and the capacitor dielectric layer 222, while having a low etching rate for the upper plate metal barrier layer 212 and the lower plate 221 to ensure that these layers are not over-etched. The first contact hole 5 is etched from the protective layer 7, gradually passing through the barrier layer 4, and finally exposing the upper plate metal barrier layer 212. Due to the design and position of the protective layer 7, the first contact hole 5 can be prevented from being lateral etched during the etching process. At the same time, the second contact hole 6 is etched downward, starting from the barrier layer 4, until the capacitor dielectric layer 222 is completely etched, exposing the lower plate 221. In other words, the presence of the protective layer 7 allows the etching time of the first contact hole 5 to be extended to match the etching time of the second contact hole 6, ensuring that the etching of the two contact holes is completed at the same time, and helps to maintain the vertical shape of the first contact hole 5, avoiding lateral etching due to waiting for the second contact hole 6 to be etched. Likewise, endpoint detection technology may be used to monitor the etching process to ensure that the etching process is stopped in time when the upper plate metal barrier layer 212 and the lower plate 221 are exposed.

[0077] In some preferred embodiments, the second etching gas is CH2F2.

[0078] Specifically, CH2F2 is used as the second etching gas, which generally has a high etching rate for the barrier layer 4 and the capacitor dielectric layer 222, maintaining the steepness of the side walls during the etching process, while having a lower etching rate for the upper plate metal barrier layer 212 and the lower plate 221 to ensure that these layers are not over-etched.

[0079] In some preferred embodiments, process conditions of the third etching process include: an etching flow rate range of 10 sccm to 50 sccm; an etching pressure range of 30 mT to 100 mT; and an etching power range of 300 W to 700 W.

[0080] Specifically, the process conditions of the third etching process are helpful to achieve effective etching of the barrier layer 4 and the capacitor dielectric layer 222, while ensuring the safety of the upper plate metal barrier layer 212 and the lower plate 221. By precisely controlling these parameters, the etching process can be optimized to ensure that the first contact hole 5 and the second contact hole 6 remain vertical, avoiding dimensional deformation due to lateral etching, thereby improving the quality and reliability of the capacitor 2.

[0081] The present embodiment provides a contact hole etching optimization method, which first forms a capacitor 2 structure of a first part 21 and a second part 22 on a substrate 1 at the same time, especially the design of the protruding part 23, so as to effectively utilize space, improve the integration of the capacitor 2, and reduce the occupied area of ​​the circuit board. Through the first etching process and the second etching process, the contact hole formed can accurately expose the key layer in the capacitor 2, ensure good electrical contact performance, and improve the signal transmission efficiency and reliability of the overall circuit. The back etching and sputtering process provides an additional layer of protection for the contact hole, reduces the potential impact of subsequent processes on the performance of the capacitor, and enhances the stability and durability of the entire structure during production and use. By adopting different gases and process steps, effective layered etching and coating can be achieved, so that the interaction between different materials is minimized, thereby improving the compatibility of the multilayer structure and ensuring good connection between the layers.

[0082] Accordingly, please refer to Figure 8 A block diagram of a contact hole etching optimization device provided in an embodiment of the present application, the device comprising:

[0083] The capacitor acquisition unit S101 is used to provide a substrate, on which a capacitor and a dielectric layer on the outer surface of the capacitor are formed; wherein the capacitor includes a first part and a second part arranged below the first part, the second part extends beyond the first part in the length direction to form a protruding part; the first part includes an upper plate and an upper plate metal barrier layer, the upper plate metal barrier layer is formed on the upper plate; the second part includes a lower plate and a capacitor dielectric layer, the capacitor dielectric layer is formed between the upper plate and the lower plate; the upper surface of the first part and the upper surface of the protruding part are both covered with a barrier layer;

[0084] A first etching unit S103 is used to perform a first etching process, etching the dielectric layer using a first etching gas to form a first contact hole above the first portion, and a second contact hole above the protruding portion, and stop the first etching process when the bottom of the first contact hole exposes the barrier layer above the first portion;

[0085] The etch-back sputtering unit S105 is used to perform an etch-back sputtering process, sputter the barrier layer with an inert gas to form a protective layer in the first contact hole, and stop the etch-back sputtering process when the angle between the protective layer and the dielectric layer meets a preset angle threshold;

[0086] A second etching unit S107, configured to perform a second etching process, continue etching the dielectric layer using the first etching gas, and stop the second etching process when the bottom of the second contact hole exposes the barrier layer above the protruding portion;

[0087] The third etching unit S109 is used to perform a third etching process, using a second etching gas to etch the barrier layer and the capacitor dielectric layer so that the bottom of the first contact hole exposes the upper electrode metal barrier layer and the bottom of the second contact hole exposes the lower electrode.

[0088] In some optional embodiments, the preset angle threshold range is 10° to 30°.

[0089] In some optional embodiments, the barrier layer has a thickness ranging from 30 nm to 100 nm.

[0090] In some optional embodiments, an etching selectivity ratio of the dielectric layer to the barrier layer in the second etching process ranges from 7:1 to 10:1.

[0091] In some optional embodiments, the first etching gas includes at least one of C4F8 or CF4; and the second etching gas is CH2F2.

[0092] In some optional implementations, the process conditions of the first etching process and the second etching process include:

[0093] The etching flow rate range is 5sccm to 20sccm;

[0094] The etching pressure range is 30mT to 200mT;

[0095] The etching power ranges from 200W to 1000W.

[0096] In some optional embodiments, the process conditions of the etch-back sputtering process include:

[0097] The inert gas flow rate ranges from 100 sccm to 300 sccm;

[0098] The etch-back pressure ranges from 30mT to 100mT;

[0099] High frequency power range is 1000W to 2000W;

[0100] The low frequency power range is 100W to 200W.

[0101] In some optional implementations, the process conditions of the third etching process include:

[0102] The etching flow rate range is 10sccm to 50sccm;

[0103] The etching pressure ranges from 30mT to 100mT;

[0104] The etching power ranges from 300W to 700W.

[0105] In some optional embodiments, the material of the upper electrode plate and the lower electrode plate includes aluminum; the material of the metal barrier layer of the upper electrode plate includes titanium nitride; and the material of the capacitor dielectric layer includes silicon nitride.

[0106] In some optional embodiments, the material of the barrier layer includes silicon oxynitride; and the material of the dielectric layer includes silicon dioxide.

[0107] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0108] An embodiment of the present application further provides a semiconductor device, which is manufactured based on the above-mentioned contact hole etching optimization method.

[0109] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

[0110] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0111] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0112] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0113] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A contact hole etching optimization method, characterized in that: The method comprises: A substrate is provided, on which a capacitor and a dielectric layer on the outer surface of the capacitor are formed; wherein the capacitor comprises a first portion and a second portion arranged below the first portion, the second portion extending beyond the first portion in the length direction to form a protruding portion; the first portion comprises an upper plate and an upper plate metal barrier layer, the upper plate metal barrier layer being formed on the upper plate; the second portion comprises a lower plate and a capacitor dielectric layer, the capacitor dielectric layer being formed between the upper plate and the lower plate; the upper surface of the first portion and the upper surface of the protruding portion are both covered with a barrier layer; Performing a first etching process, etching the dielectric layer using a first etching gas, forming a first contact hole above the first portion, and forming a second contact hole above the protruding portion, and stopping the first etching process when the bottom of the first contact hole exposes the barrier layer above the first portion; Performing an etch-back sputtering process, sputtering the barrier layer with an inert gas, forming a protective layer on the bottom sidewall of the first contact hole, and stopping the etch-back sputtering process when the angle between the protective layer and the dielectric layer meets a preset angle threshold; wherein the protective layer and the barrier layer are made of the same material; Performing a second etching process, continuing to etch the dielectric layer using the first etching gas, and stopping the second etching process when the bottom of the second contact hole exposes the barrier layer located above the protruding portion; A third etching process is performed to etch the barrier layer and the capacitor dielectric layer using a second etching gas, so that the bottom of the first contact hole exposes the upper electrode metal barrier layer and the bottom of the second contact hole exposes the lower electrode.

2. The method according to claim 1, characterized in that The preset angle threshold range is 10° to 30°.

3. The method according to claim 1, characterized in that The thickness of the barrier layer is in the range of 30 nm to 100 nm.

4. The method according to claim 1, characterized in that The etching selectivity ratio of the dielectric layer and the barrier layer in the second etching process ranges from 7:1 to 10:

1.

5. The method according to claim 1, characterized in that The first etching gas includes at least one of C4F8 and CF4; the second etching gas is CH2F2.

6. The method according to claim 1, characterized in that The process conditions of the first etching process and the second etching process include: The etching flow rate range is 5sccm to 20sccm; The etching pressure range is 30mT to 200mT; The etching power ranges from 200W to 1000W.

7. The method according to claim 1, characterized in that The process conditions of the etch-back sputtering process include: The inert gas flow rate ranges from 100 sccm to 300 sccm; The etch-back pressure ranges from 30mT to 100mT; High frequency power range is 1000W to 2000W; The low frequency power range is 100W to 200W.

8. The method according to claim 1, characterized in that The process conditions of the third etching process include: The etching flow rate range is 10sccm to 50sccm; The etching pressure ranges from 30mT to 100mT; The etching power ranges from 300W to 700W.

9. The method according to claim 1, characterized in that: The materials of the upper plate and the lower plate include aluminum; the material of the metal barrier layer of the upper plate includes titanium nitride; and the material of the capacitor dielectric layer includes silicon nitride.

10. The method according to claim 1, characterized in that The material of the barrier layer includes silicon oxynitride; the material of the dielectric layer includes silicon dioxide.

11. A contact hole etching optimization device, characterized in that: The device comprises: A capacitor acquisition unit, used for providing a substrate, on which a capacitor and a dielectric layer on the outer surface of the capacitor are formed; wherein the capacitor comprises a first part and a second part arranged below the first part, the second part extending beyond the first part in the length direction to form a protruding part; the first part comprises an upper plate and an upper plate metal barrier layer, the upper plate metal barrier layer being formed on the upper plate; the second part comprises a lower plate and a capacitor dielectric layer, the capacitor dielectric layer being formed between the upper plate and the lower plate; the upper surface of the first part and the upper surface of the protruding part are both covered with a barrier layer; a first etching unit, configured to perform a first etching process, etching the dielectric layer using a first etching gas, forming a first contact hole above the first portion, and forming a second contact hole above the protruding portion, and stopping the first etching process when the bottom of the first contact hole exposes the barrier layer above the first portion; an etch-back sputtering unit, configured to perform an etch-back sputtering process, sputter the barrier layer using an inert gas to form a protective layer on the bottom sidewall of the first contact hole, and stop the etch-back sputtering process when the angle between the protective layer and the dielectric layer meets a preset angle threshold; wherein the protective layer and the barrier layer are made of the same material; a second etching unit, configured to perform a second etching process, continue etching the dielectric layer using the first etching gas, and stop the second etching process when the bottom of the second contact hole exposes the barrier layer above the protruding portion; The third etching unit is used to perform a third etching process, using a second etching gas to etch the barrier layer and the capacitor dielectric layer so that the bottom of the first contact hole exposes the upper electrode metal barrier layer and the bottom of the second contact hole exposes the lower electrode.

12. A semiconductor device, characterized in that: The semiconductor device is manufactured based on the contact hole etching optimization method described in any one of claims 1 to 10.

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