Semiconductor structure and method of forming

Abstract

The application provides a semiconductor structure forming method, comprising: providing a substrate; forming a first gate structure and a second gate structure on the surface of the substrate, the width of the first gate structure in a channel direction is greater than the width of the second gate structure in the channel direction; forming a first offset side wall layer on the sidewall of the first gate structure, the first offset side wall layer comprising a first oxide layer; forming a second offset side wall layer on the sidewall of the second gate structure, the second offset side wall layer comprising a second oxide layer, the thickness of the first oxide layer is different from the thickness of the second oxide layer; due to the fact that the segregation effect in the oxide layer mainly affects the channel surface below the offset side wall layer, the degree of oxidation enhancement diffusion at the bottom of the first gate structure and the second gate structure is differentiated by the different thicknesses of the first oxide layer and the second oxide layer, so that the threshold voltage of the corresponding channel is improved, and the application range is wide.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming it. Background Technology

[0002] In lightly doped drain structures, ring-halo ion implantation (pocket) improves source-drain punch-through and drain-induced barrier reduction (DIBL) effects. By implanting ions of the same type as the substrate, ring-halo ion implantation suppresses lateral widening of the source-drain depletion region, prevents source-drain punch-through, suppresses short-channel effects, and increases the threshold voltage of the MOSFET. Ring-halo ion implantation is highly effective for short-channel devices, while its impact on long-channel devices is negligible.

[0003] However, in current I / O processes, NIO devices only have lightly doped drain structures and lack a halo ion implantation process. When adjusting the threshold voltage of long-channel devices by changing the well implantation, there is a lack of a method similar to halo ion implantation that can effectively adjust the threshold voltage of short-channel devices. Therefore, the performance of current NIO devices still needs to be improved. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming it, so as to improve the performance of the semiconductor structure.

[0005] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first gate structure and a second gate structure on the surface of the substrate, wherein the width of the first gate structure in the channel direction is greater than the width of the second gate structure in the channel direction; forming a first offset sidewall layer on the sidewall of the first gate structure, the first offset sidewall layer including a first oxide layer; forming a second offset sidewall layer on the sidewall of the second gate structure, the second offset sidewall layer including a second oxide layer, wherein the thickness of the first oxide layer is different from the thickness of the second oxide layer.

[0006] Optionally, the thickness of the first oxide layer is less than the thickness of the second oxide layer.

[0007] Optionally, the ratio of the thickness of the first oxide layer to the thickness of the second oxide layer is in the range of 0.1:1 to 1:1.

[0008] Optionally, the first offset sidewall layer further includes a first dielectric layer formed on the surface of the first oxide layer; the second offset sidewall layer further includes a second dielectric layer formed on the surface of the second oxide layer.

[0009] Optionally, the method for forming the first offset sidewall layer and the second offset sidewall layer includes: forming an initial first oxide layer covering the first gate structure and the second gate structure on the substrate; forming an initial intermediate dielectric layer on the surface of the initial first oxide layer; etching away the initial first oxide layer and the initial intermediate dielectric layer on the surface of the second gate structure, and forming the first oxide layer and the intermediate dielectric layer on the sidewall of the first gate structure; forming an initial second oxide layer on the sidewall and top surface of the second gate structure; forming an initial second dielectric layer on the surface of the initial second oxide layer and the surface of the intermediate dielectric layer; etching away a portion of the initial second dielectric layer, the initial second oxide layer, the intermediate dielectric layer, and the first oxide layer, and forming the second oxide layer and the second dielectric layer on the sidewall of the second gate structure, and forming the first oxide layer and the first dielectric layer on the sidewall of the first gate structure, wherein the intermediate dielectric layer and the second dielectric layer constitute the first dielectric layer.

[0010] Optionally, the material of the first dielectric layer includes silicon nitride, and the material of the second dielectric layer includes silicon nitride.

[0011] Optionally, the ratio of the thickness of the first dielectric layer to the thickness of the second dielectric layer is in the range of 1.25:1 to 2:1.

[0012] Optionally, the thickness of the first offset sidewall layer is the same as the thickness of the second offset sidewall layer.

[0013] Optionally, before forming the first gate structure and the second gate structure, a well region is further formed in the substrate, wherein the first gate structure and the second gate structure are formed on the surface of the substrate of the well region.

[0014] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate; a first gate structure located on the substrate; a second gate structure located on the substrate, wherein the width of the first gate structure in the channel direction is greater than the width of the second gate structure in the channel direction; a first offset sidewall layer located on the sidewalls and top surface of the first gate structure, the first offset sidewall layer comprising a first oxide layer; and a second offset sidewall layer located on the sidewalls and top surface of the second gate structure, the second offset sidewall layer comprising a second oxide layer, wherein the thickness of the first oxide layer is different from the thickness of the second oxide layer.

[0015] Optionally, the thickness of the first oxide layer is less than the thickness of the second oxide layer.

[0016] Optionally, the ratio of the thickness of the first oxide layer to the thickness of the second oxide layer is in the range of 0.1:1 to 1:1.

[0017] Optionally, the first offset sidewall layer further includes a first dielectric layer located on the surface of the first oxide layer sidewall; the second offset sidewall layer further includes a second dielectric layer located on the surface of the second oxide layer sidewall, wherein the thickness of the first offset sidewall layer is the same as the thickness of the second offset sidewall layer.

[0018] Optionally, it may also include a well region located within the substrate, wherein the first gate structure and the second gate structure are formed on the surface of the substrate in the well region.

[0019] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0020] In the semiconductor structure formation method of the present invention, a first gate structure and a second gate structure are formed on the surface of a substrate. The width of the first gate structure in the channel direction is greater than the width of the second gate structure in the channel. A first offset sidewall layer is formed on the sidewall and top surface of the first gate structure, wherein the first offset sidewall layer includes a first oxide layer. A second offset sidewall layer is formed on the sidewall and top surface of the second gate structure, wherein the second offset sidewall layer includes a second oxide layer. The thicknesses of the first oxide layer and the second oxide layer are different. Since the segregation effect in the oxide layer mainly affects the channel surface below the offset sidewall layer, the degree of oxide enhancement diffusion at the bottom of the first gate structure and the second gate structure can be differentiated by the different thicknesses of the first oxide layer and the second oxide layer. Lightly doped drain implantation (LDD) is not required, thereby increasing the threshold voltage of the corresponding channel and having a wide range of applications.

[0021] Furthermore, the thickness of the first oxide layer is less than the thickness of the second oxide layer. Subsequently, source and drain doped layers are formed on the substrates on both sides of the gate structure. The solid solubility of dopant ions in the source and drain doped layers is greater than that in the silicon substrate, so they will accumulate and diffuse towards one side of the oxide layer. Taking advantage of the fact that the thickness of the first oxide layer is less than the thickness of the second oxide layer, the doping concentration on the bottom channel surface of the second gate structure is greater than that on the bottom channel surface of the first gate structure. The threshold voltage corresponding to the bottom channel of the second gate structure is greater than that corresponding to the bottom channel of the first gate structure, thereby effectively adjusting the threshold voltage of the short channel (the channel at the bottom of the second gate structure between the source and drain doped regions). Attached Figure Description

[0022] Figures 1 to 6 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0023] As mentioned in the background section, in current IO processes, NIO devices only have lightly doped drain structures and lack a ring halo ion implantation process, making it difficult to adjust the threshold voltage of NIO devices under short-channel conditions.

[0024] Through research, the inventors discovered that by forming a first gate structure and a second gate structure on the surface of a substrate, with the width of the first gate structure in the channel direction being greater than the width of the second gate structure in the channel, and forming a first offset sidewall layer on the sidewall and top surface of the first gate structure, wherein the first offset sidewall layer includes a first oxide layer, and forming a second offset sidewall layer on the sidewall and top surface of the second gate structure, wherein the thickness of the first oxide layer and the second oxide layer are different; since the segregation effect in the oxide layer mainly affects the channel surface below the offset sidewall layer, by differentiating the thickness of the first oxide layer and the second oxide layer, the degree of oxide enhancement diffusion at the bottom of the first gate structure and the second gate structure can be differentiated, thereby increasing the threshold voltage of the corresponding channel, which has a wide range of applications.

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Figures 1 to 6 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0027] Please refer to Figure 1 Substrate 100 is provided.

[0028] In this embodiment, the substrate 100 is made of silicon.

[0029] In other embodiments, the substrate 100 may also be made of semiconductor materials such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium, silicon germanide, and gallium arsenide.

[0030] Please continue to refer to this. Figure 1 Ion implantation is performed on the substrate 100 to form a well region 100'.

[0031] In this embodiment, the ions doped in the well region 100' include B ions.

[0032] Please refer to Figure 2 The first gate structure 101 and the second gate structure 102 are formed on the surface of the substrate 100, wherein the width of the first gate structure 101 in the channel direction is greater than the width of the second gate structure 102 in the channel direction.

[0033] In this embodiment, the direction of the channel refers to a thin semiconductor layer between the source and drain doped regions, wherein the source and drain doped regions are formed in the substrate on both sides of the gate structure, so the channel is a thin substrate at the bottom of the gate structure between the source and drain doped regions.

[0034] In this embodiment, the width of the first gate structure 101 in the channel direction is greater than the width of the second gate structure 102 in the channel direction. After the source and drain doped regions are formed in the substrates 100 on both sides of the gate structure, the thin substrate 100 at the bottom of the first gate structure 101 is defined as a long channel, and the thin substrate 100 at the bottom of the second gate structure 102 is defined as a short channel.

[0035] In this embodiment, the first gate structure 101 includes a first gate dielectric layer 101b formed on the surface of the substrate 100 and a first gate layer 101a formed on the surface of the first gate dielectric layer 101b. The material of the first gate dielectric layer 101b is silicon oxide, and the material of the first gate layer 101a is polysilicon.

[0036] In this embodiment, the second gate structure 102 includes a second gate dielectric layer 102b formed on the surface of the substrate 100 and a second gate layer 102a formed on the surface of the second gate dielectric layer 102b. The material of the second gate dielectric layer 102b is silicon oxide, and the material of the second gate layer 102a is polysilicon.

[0037] For the process of forming the first offset sidewall layer on the sidewall of the first gate structure 101 and the second offset sidewall layer on the sidewall of the second gate structure 102, please refer to [reference needed]. Figures 3 to 6 .

[0038] Please refer to Figure 3 An initial first oxide layer 103 covering the first gate structure 101 and the second gate structure 102 is formed on the substrate 100; an initial intermediate dielectric layer 104 is formed on the surface of the initial first oxide layer 103.

[0039] In this embodiment, the material of the initial first oxide layer 103 is silicon oxide.

[0040] In this embodiment, the material of the initial intermediate dielectric layer 104 is silicon nitride.

[0041] Please refer to Figure 4 The initial first oxide layer 103 and the initial intermediate dielectric layer 104 are etched to form the first oxide layer 105 and the intermediate dielectric layer 106 on the sidewall of the first gate structure 101.

[0042] In this embodiment, the first oxide layer 105 and the intermediate dielectric layer 106 are also formed on the top surface of the first gate structure 101.

[0043] In this embodiment, after the intermediate dielectric layer 106 is formed on the sidewall of the first oxide layer 105, the second oxide layer will not be formed on the surface of the intermediate dielectric layer 106 during the subsequent formation of the second oxide layer on the sidewall of the second gate structure 102, thereby reducing the number of process steps and reducing damage to the first gate structure 101.

[0044] Please refer to Figure 5 An initial second oxide layer 107 is formed on the sidewall and top surface of the second gate structure 102; an initial second dielectric layer 108 is formed on the surface of the initial second oxide layer 107 and the surface of the intermediate dielectric layer 106.

[0045] In this embodiment, the material of the initial second oxide layer 107 is silicon oxide.

[0046] In this embodiment, the material of the initial second dielectric layer 108 is silicon nitride.

[0047] Please refer to Figure 6 The initial second dielectric layer 108, the initial second oxide layer 107, the intermediate dielectric layer 106, and the first oxide layer 105 are partially etched away. The second oxide layer 109 and the second dielectric layer 110 are formed on the sidewall of the second gate structure 102, and the first oxide layer 105 and the first dielectric layer 111 are formed on the sidewall of the first gate structure 101. The intermediate dielectric layer 106 and the second dielectric layer 109 constitute the first dielectric layer 111.

[0048] In this embodiment, the second oxide layer 109 and the second dielectric layer 110 constitute the second offset sidewall layer 113, and the first oxide layer 105 and the first dielectric layer 111 constitute the first offset sidewall layer 112.

[0049] In this embodiment, the thickness of the first oxide layer 105 and the thickness of the second oxide layer 109 are different. The dopant ions in the well region 100' will undergo a segregation effect under the high-temperature oxidation environment generated by the oxide layer. Since the solid solubility of the dopant ions in the well region 100' in the oxide layer is greater than that in the substrate, the dopant ions in the well region 100' will accumulate and diffuse towards one side of the oxide layer, thereby increasing the doping concentration on the channel surface and thus increasing the threshold voltage. Since the segregation effect in the oxide layer mainly affects the channel surface below the offset sidewall layer, the degree of oxidation enhancement diffusion at the bottom of the first gate structure 101 and the second gate structure 102 can be adjusted by differentiating the thickness of the first oxide layer 105 and the second oxide layer 109, thereby improving the threshold voltage of the corresponding channel, which has a wide range of applications.

[0050] In this embodiment, the thickness of the first oxide layer 105 is less than the thickness of the second oxide layer 109. The thicker second oxide layer 109 increases the threshold voltage of the short channel, narrowing the difference between the threshold voltage of the short channel and the threshold voltage of the long channel. This makes the increased threshold voltage of the short channel near the threshold voltage of the long channel, thereby effectively adjusting the threshold voltage of the short channel.

[0051] In this embodiment, the ratio of the thickness of the first oxide layer 105 to the thickness of the second oxide layer 109 is in the range of 0.1:1 to 1:1. Due to the short-channel effect, the threshold voltage of the short-channel device decreases, leading to an increase in leakage current. By adjusting the thickness of the first oxide layer, the diffusion of boron can be adjusted, increasing the surface boron content, thereby improving the threshold voltage of the device and reducing the leakage current of the short-channel device.

[0052] In this embodiment, the thickness of the first offset sidewall layer 112 is the same as the thickness of the second offset sidewall layer 113.

[0053] In other embodiments, the thickness of the first offset sidewall layer 112 and the thickness of the second offset sidewall layer 113 may be different.

[0054] In this embodiment, the ratio of the thickness of the first dielectric layer 111 to the thickness of the second dielectric layer 110 is in the range of 1.25:1 to 1:1. Since the back end of the long and short trench devices has consistency, by changing the thickness of the second dielectric layer 110, so that the thickness of the second dielectric layer 110 plus the second oxide layer 109 is equal to the thickness of the first dielectric layer 111 plus the first oxide layer 105, it is beneficial to maintain the consistency of the back end design of the device and maintain the breakdown voltage of the device.

[0055] Accordingly, the present invention also provides a semiconductor structure including a substrate 100; a first gate structure 101 located on the substrate 100; a second gate structure located on the substrate 100, wherein the width of the first gate structure 101 in the channel direction is greater than the width of the second gate structure 102 in the channel direction; a first offset sidewall layer 112 located on the sidewalls and top surface of the first gate structure 101, the first offset sidewall layer 112 including a first oxide layer; and a second offset sidewall layer 113 located on the sidewalls and top surface of the second gate structure 102, the second offset sidewall layer 113 including a second oxide layer 109, wherein the thickness of the first oxide layer 105 is different from the thickness of the second oxide layer 109.

[0056] In this embodiment, ion implantation is also performed on the substrate 100 to form a well region 100'.

[0057] In this embodiment, the ions doped in the well region 100' include B ions.

[0058] In this embodiment, the dopant ions in the well region 100' will undergo a segregation effect under the high-temperature oxidation environment generated by the oxide layer. Since the solid solubility of the dopant ions in the well region 100' in the oxide layer is greater than that in the substrate, the dopant ions in the well region 100' will accumulate and diffuse towards the oxide layer side, thereby increasing the doping concentration on the channel surface and thus increasing the threshold voltage. Since the segregation effect in the oxide layer mainly affects the channel surface below the offset sidewall layer, the degree of oxidation enhancement diffusion at the bottom of the first gate structure 101 and the second gate structure 102 can be adjusted differently by using the different thicknesses of the first oxide layer 105 and the second oxide layer 109, thereby improving the threshold voltage of the corresponding channel and having a wide range of applications.

[0059] In this embodiment, the thickness of the first oxide layer 105 is less than the thickness of the second oxide layer 109, and the threshold voltage corresponding to the short channel at the bottom of the second gate structure 102 is greater than the threshold voltage corresponding to the long channel at the bottom of the first gate structure 101, thereby effectively adjusting the threshold voltage of the short channel.

[0060] In this embodiment, the ratio of the thickness of the first oxide layer 105 to the thickness of the second oxide layer 109 is in the range of 0.1:1 to 1:1.

[0061] In this embodiment, the first offset sidewall layer 112 further includes a first dielectric layer located on the sidewall surface of the first oxide layer 105; the second offset sidewall layer 113 further includes a second dielectric layer located on the sidewall surface of the second oxide layer 109, and the thickness of the first offset sidewall layer 112 is the same as the thickness of the second offset sidewall layer 113.

[0062] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A first gate structure and a second gate structure are formed on the surface of the substrate, wherein the width of the first gate structure in the channel direction is greater than the width of the second gate structure in the channel direction; A first offset sidewall layer is formed on the sidewall of the first gate structure, the first offset sidewall layer including a first oxide layer, and the first oxide layer is formed on the sidewall of the first gate structure; A second offset sidewall layer is formed on the sidewall of the second gate structure. The second offset sidewall layer includes a second oxide layer. The thickness of the first oxide layer is different from the thickness of the second oxide layer. The thickness of the first oxide layer is less than the thickness of the second oxide layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The ratio of the thickness of the first oxide layer to the thickness of the second oxide layer is in the range of 0.1:1 to 1:

1.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first offset sidewall layer further includes a first dielectric layer formed on the surface of the first oxide layer; the second offset sidewall layer further includes a second dielectric layer formed on the surface of the second oxide layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The method for forming the first offset sidewall layer and the second offset sidewall layer includes: forming an initial first oxide layer covering the first gate structure and the second gate structure on the substrate; forming an initial intermediate dielectric layer on the surface of the initial first oxide layer; etching away the initial first oxide layer and the initial intermediate dielectric layer on the surface of the second gate structure, forming the first oxide layer and the intermediate dielectric layer on the sidewall of the first gate structure; forming an initial second oxide layer on the sidewall and top surface of the second gate structure; forming an initial second dielectric layer on the surface of the initial second oxide layer and the surface of the intermediate dielectric layer; etching away portions of the initial second dielectric layer, the initial second oxide layer, the intermediate dielectric layer, and the first oxide layer, forming the second oxide layer and the second dielectric layer on the sidewall of the second gate structure, and forming the first oxide layer and the first dielectric layer on the sidewall of the first gate structure, wherein the intermediate dielectric layer and the second dielectric layer constitute the first dielectric layer.

5. The method for forming a semiconductor structure as described in claim 3, characterized in that, The ratio of the thickness of the first dielectric layer to the thickness of the second dielectric layer ranges from 1.25:1 to 2:

1.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the first gate structure and the second gate structure, a well region is formed within the substrate, wherein the first gate structure and the second gate structure are formed on the surface of the substrate of the well region.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the first offset sidewall layer is the same as the thickness of the second offset sidewall layer.

8. A semiconductor structure, characterized in that, include: Substrate; The first gate structure is located on the substrate; A second gate structure located on the substrate, wherein the width of the first gate structure in the channel direction is greater than the width of the second gate structure in the channel direction; A first offset sidewall layer is located on the sidewall and top surface of the first gate structure, the first offset sidewall layer includes a first oxide layer, the first oxide layer is located on the sidewall of the first gate structure; A second offset sidewall layer is located on the sidewall and top surface of the second gate structure. The second offset sidewall layer includes a second oxide layer. The second oxide layer is located on the sidewall of the second gate structure. The thickness of the first oxide layer is different from the thickness of the second oxide layer. The thickness of the first oxide layer is less than the thickness of the second oxide layer.

9. The semiconductor structure as described in claim 8, characterized in that, The ratio of the thickness of the first oxide layer to the thickness of the second oxide layer is in the range of 0.1:1 to 1:

1.

10. The semiconductor structure as described in claim 8, characterized in that, The first offset sidewall layer further includes a first dielectric layer located on the sidewall surface of the first oxide layer; the second offset sidewall layer further includes a second dielectric layer located on the sidewall surface of the second oxide layer, and the thickness of the first offset sidewall layer is the same as the thickness of the second offset sidewall layer.

11. The semiconductor structure as described in claim 8, characterized in that, It also includes a well region located within the substrate, wherein the first gate structure and the second gate structure are formed on the surface of the substrate in the well region.

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