Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, the structure comprising: a substrate, the substrate comprising a drift region; an isolation structure within the drift region, the isolation structure comprising at least one first portion and at least one second portion, the second portion having a dimension along a first direction that is less than a dimension of the first portion along the first direction, the first portion and the second portion being arranged alternately along a second direction, the first portion and the second portion being adjacent to each other, the second direction being parallel to a surface of the substrate, and the first direction being a direction from a top surface of the substrate to a bottom surface of the substrate. When electrons flow from a source, a portion of the electrons do not need to move along a sidewall surface of the first portion to a bottom of the first portion and then to a drain, but instead move along a sidewall surface of the second portion to a bottom of the second portion and then to the drain. The flow path of the electrons along the second portion is shorter than the flow path of the electrons along the first portion, resulting in a reduction in the on-resistance of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] A lateral type metal oxide semiconductor field effect transistor (MOSFET) is a metal oxide semiconductor field effect transistor whose current flow direction is parallel to the cross-sectional direction of the wafer substrate. A conventional lateral double-diffused MOSFET (LDMOS) adopts a double diffusion technology, and in order to further improve the breakdown voltage of the lateral metal oxide semiconductor field effect transistor device, the surface charge effect of the device needs to be overcome. In a power lateral metal oxide semiconductor field effect transistor device, the two most important performance parameters are the breakdown voltage and the specific on-resistance.

[0003] A deep trench isolation structure (DTI) effectively reduces the relative occupation area of the device and increases the effective length of the drift region by replacing the width in the lateral direction with the depth in the longitudinal direction, thereby providing a higher breakdown voltage for high-voltage devices.

[0004] However, the improvement of the breakdown voltage of the device tends to increase the specific on-resistance of the device, and the isolation structure of the current device needs to be optimized. SUMMARY

[0005] The problem solved by the present application is how to etch a deep trench structure with a height difference to optimize the isolation structure, utilize an additional low-resistance current path, and make the specific on-resistance of the isolation structure smaller while providing a higher breakdown voltage for high-voltage devices.

[0006] To solve the above problems, the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a drift region; an isolation structure located in the drift region, the isolation structure comprising at least one first part and at least one second part, the size of the second part in the first direction being smaller than the size of the first part in the first direction, the first part and the second part being arranged alternately in the second direction, the first part and the second part being adjacent to each other, the second direction being parallel to the surface of the substrate, and the first direction being a direction from the top surface of the substrate to the bottom surface of the substrate.

[0007] Optionally, the isolation structure further comprises: a third part, the third part being adjacent to the first part and the second part, and the projection of the third part on the substrate surface being located within the projection range of the second part on the substrate surface.

[0008] Optionally, the third subpart has a dimension in the third direction smaller than a dimension of the first subpart in the third direction, the third direction being perpendicular to the second direction, the third direction being parallel to a surface of the substrate.

[0009] Optionally, a sum of the dimension of the third subpart in the first direction and the dimension of the second subpart in the first direction is not greater than the dimension of the first subpart in the first direction.

[0010] Optionally, a ratio of the dimension of the first subpart in the first direction to the dimension of the first subpart in the third direction ranges from 1.5 to 8.

[0011] Optionally, the semiconductor structure further comprises a source electrode and a drain electrode, the source electrode and the drain electrode being located on two sides of the isolation structure along the third direction.

[0012] Optionally, the semiconductor structure further comprises a gate electrode, the gate electrode being located on a side of the source electrode away from the isolation structure along the third direction.

[0013] Optionally, the substrate comprises a substrate, an insulating layer on a surface of the substrate, and a semiconductor layer on a surface of the insulating layer, the semiconductor layer comprising the drift region.

[0014] Correspondingly, the embodiment of the present application further provides a forming method of a semiconductor structure, comprising: providing a substrate, the substrate having a drift region; etching the substrate of the drift region to form a first opening; after forming the first opening, forming a first mask layer on the substrate, the first mask layer exposing the substrate of the drift region; taking the first mask layer as a mask, etching the substrate of the drift region to form an isolation groove; and filling the isolation groove to form an isolation structure, the isolation structure comprising at least one first subpart and at least one second subpart, the second subpart having a dimension in a first direction smaller than a dimension of the first subpart in the first direction, the first subpart and the second subpart being arranged alternately along a second direction, the first subpart and the second subpart being adjacent to each other, the second direction being parallel to a surface of the substrate, and the first direction being a direction in which a top surface of the substrate points to a bottom surface of the substrate.

[0015] Optionally, in the step of forming the isolation groove, the isolation groove comprises a first region and a second region, the first region and the second region being arranged alternately along the second direction, the isolation groove of the first region corresponding to the first opening, and the isolation groove of the second region being in communication with the isolation groove of the first region; and in the step of filling the isolation groove to form the isolation structure, the isolation groove of the first region and the isolation groove of the second region are filled to form the first subpart and the second subpart respectively.

[0016] Optionally, a depth of the first opening is greater than a difference between a size of the first portion along the first direction and a size of the second portion along the first direction.

[0017] Optionally, after forming the first opening, before forming the first mask layer, the method further comprises: forming a second opening in the drift region, the second opening is arranged along a second direction with the first opening, a size of the second opening along a third direction is not greater than a size of the first opening along the third direction, the third direction is perpendicular to the second direction, and the third direction is parallel to the surface of the substrate.

[0018] Optionally, a depth of the second opening is not greater than a depth of the first opening.

[0019] Optionally, the first mask layer is a hard mask.

[0020] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0021] In the semiconductor structure of the technical scheme of the present application, the isolation structure comprises at least one first portion and at least one second portion, a size of the second portion along a first direction is smaller than a size of the first portion along the first direction, and the first direction is a direction in which a top surface of a substrate points to a bottom surface of the substrate. When electrons flow out from a source electrode, a part of the electrons do not need to move along a sidewall surface of the first portion to a bottom of the first portion and then flow to a drain electrode, but move along a sidewall surface of the second portion to a bottom of the second portion and then flow to the drain electrode. The flow path of the electrons flowing along the second portion is shorter than the flow path of the electrons flowing along the first portion, so that the feature on-resistance of the device is reduced.

[0022] In the optional scheme of the present application, the isolation structure further comprises a third portion, the third portion is adjacent to the first portion and the second portion, and a projection of the third portion on a surface of the substrate is located in a projection range of the second portion on the surface of the substrate. A size of the third portion along a third direction is smaller than a size of the first portion along the third direction, the third direction is perpendicular to the second direction, and the third direction is parallel to the surface of the substrate. A sum of a size of the third portion along the first direction and a size of the second portion along the first direction is not greater than a size of the first portion along the first direction. When the electrons flow out from the source electrode, a part of the electrons do not need to move along a sidewall surface of the first portion to a bottom of the first portion and then flow to the drain electrode, but move along a sidewall surface of the second portion to a bottom of the second portion, then move along a sidewall of the third portion to a bottom of the third portion, and then flow to the drain electrode. The flow path of the electrons flowing along the second portion and the third portion is shorter than the flow path of the electrons flowing along the first portion, so that the feature on-resistance of the device is reduced.

[0023] In an optional embodiment of the present invention, the ratio of the dimension of the first portion along the first direction to the dimension of the first portion in the third direction ranges from 1.5 to 8. The isolation structure has a large depth-to-width ratio, reducing the relative occupied area of ​​the semiconductor device and increasing the effective length of the drift region, thereby improving the breakdown voltage of the semiconductor device.

[0024] In the semiconductor structure formation method of the present invention, after forming the first opening, the substrate of the drift region is etched to form an isolation trench. In the isolation trench, the depth of the region corresponding to the first opening is greater than the depth of the region not corresponding to the first opening, such that the dimension of the first portion of the isolation structure forming the isolation trench along the first direction is greater than the dimension of the second portion along the first direction. When electrons flow out from the source, some electrons do not need to move down along the sidewall surface of the first portion to the bottom of the first portion and then flow to the drain. Instead, they move along the sidewall surface of the second portion to the bottom of the second portion and then flow to the drain. The flow path of electrons flowing out along the second portion is shorter than the flow path of electrons flowing out along the first portion, thus reducing the characteristic on-resistance of the device. Attached Figure Description

[0025] Figures 1 to 3 This is a schematic diagram of a semiconductor structure according to one embodiment;

[0026] Figures 4 to 15 This is a schematic diagram of the steps in the formation process of a semiconductor structure according to an embodiment of the present invention;

[0027] Figures 16 to 33 This is a schematic diagram of the steps in the formation process of a semiconductor structure according to another embodiment of the present invention;

[0028] Figure 34 This is a perspective view of a semiconductor structure according to an embodiment of the present invention;

[0029] Figure 35 This is a perspective view of a semiconductor structure according to another embodiment of the present invention;

[0030] Figure 36 This is a perspective view of a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0031] As the background technology shows, the characteristic on-resistance of lateral metal-oxide-semiconductor field-effect transistors with deep trench isolation structures in the prior art is relatively large. The reasons for this problem are analyzed below using a specific semiconductor structure as an example:

[0032] Please refer to Figures 1 to 3 , Figure 2 and Figure 3 They are Figure 1In the cross-sectional views at positions AA1 and BB1, the semiconductor structure includes:

[0033] Substrate 100, the substrate 100 including drift region I;

[0034] An isolation structure 101 located within the drift region I has a first dimension h along the direction from the top surface of the substrate 100 to the bottom surface of the substrate 100.

[0035] The semiconductor structure further includes a source (not shown) and a drain (not shown), with the source and the drain located on opposite sides of the isolation structure 101 along the first direction Y.

[0036] The ratio of the first dimension h of the isolation structure 101 along the direction from the top surface of the substrate 100 to the bottom surface of the substrate 100 to the dimension of the isolation structure 101 along the first direction Y is greater than a first threshold. The first threshold is 5:1, and the first dimension h is greater than 1 μm.

[0037] By replacing the width with the depth in the vertical direction, the high aspect ratio isolation structure 101 effectively reduces the relative area occupied by the device and increases the effective length of the drift region, providing a higher breakdown voltage for high-voltage devices. However, the increase in the breakdown voltage of the device often increases the characteristic on-resistance of the device, resulting in an increase in the characteristic conduction resistance of the device.

[0038] To address the aforementioned technical problem, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate having a drift region; etching the substrate of the drift region to form a first opening; after forming the first opening, forming a first mask layer on the substrate, the first mask layer exposing the substrate of the drift region; using the first mask layer as a mask, etching the substrate of the drift region to form an isolation trench; filling the isolation trench to form an isolation structure, the isolation structure comprising at least one first portion and at least one second portion, the second portion having a dimension along a first direction smaller than the first portion along the first direction, the first portion and the second portion being alternately arranged along a second direction, the first portion and the second portion being adjacent to each other, the second direction being parallel to the surface of the substrate, and the first direction being the direction from the top surface of the substrate to the bottom surface of the substrate.

[0039] In the semiconductor structure formation method of the present invention, after forming the first opening, the substrate of the drift region is etched to form an isolation trench. In the isolation trench, the depth of the region corresponding to the first opening is greater than the depth of the region not corresponding to the first opening, such that the dimension of the first portion of the isolation structure forming the isolation trench along the first direction is greater than the dimension of the second portion along the first direction. When electrons flow out from the source, some electrons do not need to move down along the sidewall surface of the first portion to the bottom of the first portion and then flow to the drain. Instead, they move along the sidewall surface of the second portion to the bottom of the second portion and then flow to the drain. The flow path of electrons flowing out along the second portion is shorter than the flow path of electrons flowing out along the first portion, thus reducing the characteristic on-resistance of the device.

[0040] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Figures 4 to 15 This is a schematic diagram of the steps in the formation process of a semiconductor structure according to an embodiment of the present invention.

[0042] Please refer to Figure 4 and Figure 5 , Figure 5 yes Figure 4 A cross-sectional view at position CC1 provides a substrate 200 having a drift region I.

[0043] Specifically, in some embodiments of the present invention, the substrate 200 includes a substrate, an insulating layer located on the surface of the substrate, and a semiconductor layer located on the surface of the insulating layer, the semiconductor layer including the drift region I.

[0044] The substrate is made of silicon. The insulating layer is made of silicon oxide. The semiconductor layer is made of silicon.

[0045] The semiconductor layer of the drift region I provides the structural basis for the subsequent formation of the isolation structure 205.

[0046] In other embodiments, the substrate includes a substrate and an epitaxial layer located on the substrate, the epitaxial layer including the drift region. The substrate is made of silicon, and the epitaxial layer is made of silicon.

[0047] Please refer to Figures 6 to 9 The substrate 200 of the drift region I is etched to form a first opening 202.

[0048] The steps for forming the first opening 202 include: as follows Figure 6 and Figure 7 As shown, Figure 7 yesFigure 6 In the cross-sectional view at position CC1, a second mask layer 201 is formed on the substrate 200; as shown... Figure 8 and Figure 9 As shown, Figure 9 yes Figure 8 In the cross-sectional view at position CC1, the substrate 200 of the drift region I is etched using the second mask layer 201 as a mask to form the first opening 202.

[0049] The first opening 202 defines the location of the first region II of the subsequently formed isolation trench 204. The first opening 202 provides the structural basis for the first region II of the subsequently formed isolation trench 204.

[0050] Specifically, in some embodiments of the present invention, the number of the first openings 202 is greater than one, and the first openings 202 are arranged along the second direction X. In other embodiments, the number of the first openings may be one.

[0051] The first opening 202 has a depth in the first direction Z and the first opening 202 precedes the isolation trench 204 (e.g.) Figure 13 As shown), this forms an isolation trench 204 (as shown) subsequently formed on the basis of the first opening 202. Figure 13 As shown, the depth of the region corresponding to the first opening 202 is greater than the depth of the region not corresponding to the first opening 202, so that different regions of the isolation trench 204 have different depths. The first direction Z is the direction from the top surface of the substrate 200 to the bottom surface of the substrate 200.

[0052] Specifically, in some embodiments of the present invention, the second mask layer 201 is a hard mask, which is suitable for etching a material of a large thickness to form a first opening 202 with a large depth.

[0053] In the step of forming a second mask layer 201 on the substrate 200, the second mask layer 201 exposes the substrate 200. The step of forming the second mask layer 201 includes: forming an initial hard mask on the substrate 200; forming a photoresist layer on the initial hard mask; exposing and developing the photoresist layer; and after exposing and developing the photoresist layer, etching the initial hard mask to form the second mask layer 201.

[0054] After forming the first opening 202, the method further includes: removing the second mask layer 201.

[0055] Please refer to Figure 10 and Figure 11 , Figure 11 yes Figure 10In the cross-sectional view at position CC1, after the first opening 202 is formed, a first mask layer 203 is formed on the substrate 200, the first mask layer 203 exposing the substrate 200 of the drift region I.

[0056] The first mask layer 203 is used to define the location of the isolation trench 204.

[0057] In the step of forming a first mask layer 203 on the substrate 200 after forming the first opening 202, the step of forming the first mask layer 203 includes: forming an initial hard mask on the substrate 200; forming a photoresist layer on the initial hard mask; exposing and developing the photoresist layer; and etching the initial hard mask after exposing and developing the photoresist layer to form the first mask layer 203.

[0058] Specifically, in some embodiments of the present invention, the first mask layer 203 and the second mask layer 201 are made of the same material. The first mask layer 203 is a hard mask. The hard mask is suitable for etching materials of considerable thickness to form isolation trenches 204 of considerable depth.

[0059] Please refer to Figure 12 and Figure 13 , Figure 13 yes Figure 12 In the cross-sectional view at position CC1, the substrate 200 of the drift region I is etched using the first mask layer 203 as a mask to form an isolation trench 204.

[0060] First, the first opening 202 is formed in the drift region I, so that the drift region I has two regions with different depths: the region corresponding to the first opening 202 and the region not corresponding to the first opening 202. Then, the substrate 200 of the drift region I with the depth difference is etched to form an isolation trench 204, so that the isolation trench 204 has two regions with different depths: the region corresponding to the first opening 202 and the region not corresponding to the first opening 202. In the isolation trench 204, the depth of the region corresponding to the first opening 202 is greater than the depth of the region not corresponding to the first opening 202.

[0061] In the step of forming the isolation trench 204, the isolation trench 204 includes a first region II and a second region III, the first region II and the second region III are arranged alternately along the second direction X, the isolation trench 204 of the first region II corresponds to the first opening 202, and the isolation trench 204 of the second region III is connected to the isolation trench 204 of the first region II.

[0062] The first zone II and the second zone III are arranged alternately along the second direction X, that is: along the second direction X, the zone adjacent to the first zone II must be the second zone III, and the zone adjacent to the second zone III must be the first zone II.

[0063] The isolation trench 204 provides a structural foundation for the subsequent formation of the isolation structure 205.

[0064] Specifically, in some embodiments of the present invention, the depth of the first opening 202 is greater than the difference between the depth H1 of the first zone II and the depth H2 of the second zone III of the isolation trench 204.

[0065] Please refer to Figure 14 and Figure 15 , Figure 15 yes Figure 14 In the cross-sectional view at position CC1, the isolation trench 204 is filled to form an isolation structure 205. The isolation structure 205 includes at least one first portion A and at least one second portion B. The dimension H2 of the second portion B along the first direction Z is smaller than the dimension H1 of the first portion A along the first direction Z. The first portion A and the second portion B are arranged alternately along the second direction X. The first portion A and the second portion B are adjacent to each other. The second direction X is parallel to the surface of the substrate 200. The first direction Z is the direction from the top surface of the substrate 200 to the bottom surface of the substrate 200.

[0066] The isolation structure 205 has a first section A and a second section B with different depths. When electrons flow out from the source, some electrons do not need to move down the sidewall surface of the first section A to the bottom of the first section A before flowing to the drain. Instead, they move down the sidewall surface of the second section B to the bottom of the second section B before flowing to the drain. The flow path of electrons flowing out along the second section B is shorter than that of electrons flowing out along the first section A, thus reducing the characteristic on-resistance of the device. In the step of filling the isolation trench 204 to form the isolation structure 205, the isolation trench 204 of the first region II and the isolation trench 204 of the second region III are filled to form the first section A and the second section B, respectively. The depth of the first opening 202 is greater than the difference between the dimension H1 of the first section A along the first direction Z and the dimension H2 of the second section B along the first direction Z.

[0067] The ratio of the dimension of the first portion A along the first direction Z to the dimension of the first portion A along the third direction Y ranges from 1.5 to 8. The dimension of the first portion A along the first direction Z is greater than 1 μm.

[0068] Specifically, in some embodiments of the present invention, the size range of the first portion A along the first direction Z is 10μm to 25μm; the size range of the first portion A along the second direction X is 1μm to 5μm; and the size range of the first portion A along the third direction Y is 3μm to 15μm. The size range of the second portion B along the first direction Z is 3μm to 15μm; the size range of the second portion B along the second direction X is 1μm to 3μm; and the size range of the second portion B along the third direction Y is 3μm to 15μm.

[0069] The material of the isolation structure 205 is an insulating material, which includes silicon oxide.

[0070] Figures 16 to 33 This is a schematic diagram of the steps in the formation process of a semiconductor structure according to another embodiment of the present invention.

[0071] Please Figures 4 to 9 Based on reference Figures 16 to 33 After forming the first opening 202, the method further includes: forming a second opening 302 in the drift region I, the second opening 302 being arranged with the first opening 202 along the second direction X, the size of the second opening 302 in the third direction Y being no greater than the size of the first opening 202 in the third direction Y, the third direction Y being perpendicular to the second direction X, and the third direction Y being parallel to the surface of the substrate 200.

[0072] The steps for forming the second opening 302 include:

[0073] like Figures 16 to 18 As shown, Figure 17 yes Figure 16 A sectional view at position CC1. Figure 18 yes Figure 16 A cross-sectional view at position DD1 shows a third mask layer 301 formed on the substrate 200;

[0074] like Figures 19 to 21 As shown, Figure 20 yes Figure 19 A sectional view at position CC1. Figure 21 yes Figure 19 In the cross-sectional view at position DD1, the substrate 200 of the drift region I is etched using the third mask layer 301 as a mask to form the second opening 302;

[0075] like Figures 22 to 24 As shown, Figure 23 yes Figure 22 A sectional view at position CC1. Figure 24 yes Figure 22 A cross-sectional view at position DD1, with the third mask layer 301 removed.

[0076] The second opening 302 provides a structural basis for forming the trench structure 304. The third mask layer 301 defines the subsequently formed isolation structure 305 (e.g., Figure 33 The third part C (as shown) is located on the surface of the parallel substrate 200.

[0077] The second opening 302 and the first opening 202 are arranged along the second direction X, and the area corresponding to the second opening 302 in the second direction X does not overlap with the area corresponding to the first opening 202 in the second direction X.

[0078] The depth of the second opening 302 is not greater than the depth of the first opening 202. That is, the dimension of the second opening 302 in the first direction Z is smaller than the dimension of the first opening 202 in the first direction Z. Specifically, in some embodiments of the present invention, the depth of the second opening 302 is less than the depth of the first opening 202. In other embodiments, the depth of the second opening may also be equal to the depth of the first opening.

[0079] Please refer to Figures 25 to 27 , Figure 26 yes Figure 25 A sectional view at position CC1. Figure 27 yes Figure 25 In the cross-sectional view at position DD1, after the second opening 302 is formed, a first mask layer 303 is formed on the substrate 200, the first mask layer 303 exposing the substrate 200 of the drift region I.

[0080] The first mask layer 303 is used to define the isolation trench 304 (e.g. Figure 29 (as shown in the image)

[0081] In the step of forming a first mask layer 303 on the substrate 200 after forming the second opening 302, the step of forming the first mask layer 303 includes: forming an initial hard mask on the substrate 200; forming a photoresist layer on the initial hard mask; exposing and developing the photoresist layer; and etching the initial hard mask after exposing and developing the photoresist layer to form the first mask layer 303.

[0082] Specifically, in some embodiments of the present invention, the first mask layer 303 and the second mask layer 201 are made of the same material. The first mask layer 303 is a hard mask. The hard mask is suitable for etching materials of considerable thickness to form isolation trenches 304 of considerable depth.

[0083] Please refer to Figures 28 to 30 , Figure 29 yes Figure 28 A sectional view at position CC1.Figure 30 yes Figure 28 In the cross-sectional view at position DD1, the substrate 200 of the drift region I is etched using the first mask layer 303 as a mask to form an isolation trench 304.

[0084] First, the first opening 202 and the second opening 302 are formed in the drift region I, so that the drift region I has three regions with different depths: the region corresponding to the first opening 202, the region corresponding to the second opening 302, and the region that does not correspond to the first opening 202 or the second opening 302. Then, the substrate 200 of the drift region I with depth differences is etched to form an isolation trench 304, so that the isolation trench 304 has three regions with different depths: the region corresponding to the first opening 202, the region corresponding to the second opening 302, and the region that does not correspond to the first opening 202 or the second opening 302. In the isolation trench 304, the depth of the region corresponding to the first opening 202 is greater than the depth of the region corresponding to the second opening 302, and the depth of the region corresponding to the second opening 302 is greater than the depth of the regions that do not correspond to the first opening 202 or the second opening 302.

[0085] In the isolation trench 304, the area corresponding to the second opening 302 is located within the second region III of the substrate 200.

[0086] In the step of forming the isolation trench 304, the isolation trench 304 includes a first region II and a second region III, the first region II and the second region III are arranged alternately along the second direction X, the isolation trench 304 of the first region II corresponds to the first opening 202, and the isolation trench 304 of the second region III is connected to the isolation trench 304 of the first region II.

[0087] The first zone II and the second zone III are arranged alternately along the second direction X, that is: along the second direction X, the zone adjacent to the first zone II must be the second zone III, and the zone adjacent to the second zone III must be the first zone II.

[0088] The isolation trench 304 provides a structural foundation for the subsequent formation of the isolation structure 305.

[0089] Please refer to Figures 31 to 33 , Figure 32 yes Figure 31 A sectional view at position CC1. Figure 33 yes Figure 31In the cross-sectional view at position DD1, the isolation trench 204 is filled to form an isolation structure 305. The isolation structure 305 includes at least one first portion A and at least one second portion B. The dimension H2 of the second portion B along the first direction Z is smaller than the dimension H1 of the first portion A along the first direction Z. The first portion A and the second portion B are alternately arranged along the second direction X. The first portion A and the second portion B are adjacent to each other. The second direction X is parallel to the surface of the substrate 200. The first direction Z is the direction from the top surface of the substrate 200 to the bottom surface of the substrate 200.

[0090] The isolation structure 305 further includes a third portion C, which is adjacent to the first portion A and the second portion B, and the projection of the third portion C onto the surface of the substrate 200 is located within the projection range of the second portion B onto the surface of the substrate 200. The third portion C (e.g. Figure 33 The projection of the image on the surface of the substrate 200 (as shown) corresponds to the second opening 302 (e.g.) Figure 27 (as shown) Projection onto the surface of substrate 200.

[0091] The dimension of the third portion C in the third direction Y is smaller than the dimension of the second portion B in the third direction Y. The dimension of the second portion B in the third direction Y is the same as the dimension of the first portion A in the third direction Y. Therefore, the dimension of the third portion C in the third direction Y is smaller than the dimension of the first portion A in the third direction Y. The third direction Y is perpendicular to the second direction X and parallel to the surface of the substrate 200.

[0092] The sum of the dimensions of the third portion C along the first direction Z and the second portion B along the first direction Z is not greater than the dimension of the first portion A along the first direction Z. When electrons flow out of the source, some electrons do not need to move down the sidewall surface of the first portion A to the bottom of the first portion A and then flow to the drain. Instead, they move down the sidewall surface of the second portion B to the bottom of the second portion B, and then down the sidewall surface of the third portion C to the bottom of the third portion C and then flow to the drain. The flow path of electrons flowing out along the second portion B and the third portion C is shorter than the flow path of electrons flowing out along the first portion A, which reduces the characteristic on-resistance of the device.

[0093] The ratio of the dimension of the first portion A along the first direction Z to the dimension of the first portion A along the third direction Y ranges from 1.5 to 8. The dimension of the first portion A along the first direction Z is greater than 1 μm. Specifically, in some embodiments of the present invention, the dimension of the first portion A along the first direction Z ranges from 10 μm to 25 μm; the dimension of the first portion A along the second direction X ranges from 1 μm to 5 μm; and the dimension of the first portion A along the third direction Y ranges from 3 μm to 15 μm. The dimension of the second portion B along the first direction Z ranges from 3 μm to 15 μm; the dimension of the second portion B along the second direction X ranges from 1 μm to 3 μm; and the dimension of the second portion B along the third direction Y ranges from 3 μm to 15 μm. The size range of the third portion C along the first direction Z is: ; the size range of the third portion C along the second direction X is: 1μm~3μm; the size range of the third portion C along the third direction Y is: 5μm~10μm.

[0094] The material of the isolation structure 305 is an insulating material, which includes silicon oxide.

[0095] Accordingly, this invention also provides a semiconductor structure, please refer to [the relevant documentation]. Figure 14 and Figure 15 and in conjunction with references Figure 34 , Figure 15 yes Figure 14 A sectional view at position CC1. Figure 34 This is a perspective view of an embodiment of the present invention, including: a substrate 200, the substrate 200 including a drift region I; an isolation structure 205 located within the drift region I, the isolation structure 205 including at least one first portion A and at least one second portion B, the second portion B having a dimension H2 along a first direction Z that is smaller than the first portion A having a dimension H1 along the first direction Z, the first portion A and the second portion B being alternately arranged along a second direction X, the first portion A and the second portion B being adjacent to each other, the second direction X being parallel to the surface of the substrate 200, and the first direction Z being the direction from the top surface of the substrate 200 to the bottom surface of the substrate 200.

[0096] In the semiconductor structure of the present invention, the isolation structure includes at least one first portion A and at least one second portion B. The dimension of the second portion B along the first direction Z is smaller than the dimension of the first portion A along the first direction Z. The first direction Z is the direction from the top surface of the substrate 200 to the bottom surface of the substrate 200. When electrons flow out from the source, some electrons do not need to move down along the sidewall surface of the first portion A to the bottom of the first portion A and then flow to the drain. Instead, they move along the sidewall surface of the second portion B to the bottom of the second portion B and then flow to the drain. The flow path of electrons flowing out along the second portion B is shorter than the flow path of electrons flowing out along the first portion A, thereby reducing the characteristic on-resistance of the device.

[0097] The semiconductor structure includes a substrate 200, which includes a drift region I.

[0098] The substrate 200 includes a substrate, an insulating layer on the surface of the substrate, and a semiconductor layer on the surface of the insulating layer, the semiconductor layer including the drift region I.

[0099] The semiconductor structure includes an isolation structure 205 located within the drift region I. The isolation structure 205 includes at least one first portion A and at least one second portion B. The dimension H1 of the second portion B along the first direction Z is smaller than the dimension H2 of the first portion A along the first direction Z. The first portion A and the second portion B are alternately arranged along the second direction X. The first portion A and the second portion B are adjacent to each other. The second direction X is parallel to the surface of the substrate 200. The first direction Z is the direction from the top surface of the substrate 200 to the bottom surface of the substrate 200.

[0100] The ratio of the dimension of the first portion A along the first direction Z to the dimension of the first portion A along the third direction Y ranges from 1.5 to 8. The third direction Y is perpendicular to the second direction X and parallel to the surface of the substrate 200. The dimension of the first portion A along the first direction Z ranges from 15 μm to 25 μm; the dimension of the first portion A along the second direction X ranges from 1 μm to 5 μm; the dimension of the first portion A along the third direction Y ranges from 8 μm to 15 μm. The dimension of the second portion B along the first direction Z ranges from 3 μm to 8 μm; the dimension of the second portion B along the second direction X ranges from 1 μm to 3 μm; the dimension of the second portion B along the third direction Y ranges from 8 μm to 15 μm.

[0101] The semiconductor structure further includes a source 206 and a drain 207, with the source 206 and the drain 207 located on opposite sides of the isolation structure 205 along the third direction Y.

[0102] The semiconductor structure further includes a gate 208, which is located on the side of the source 206 away from the isolation structure 205 along the third direction Y.

[0103] Accordingly, embodiments of the present invention also provide another semiconductor structure, please refer to [the relevant documentation]. Figures 31 to 33 and in conjunction with references Figure 35 , Figure 32 yes Figure 31 A sectional view at position CC1. Figure 33 yes Figure 31 Sectional view at position DD1, Figure 35 This is a perspective view of an embodiment of the present invention.

[0104] The similarities to the foregoing embodiments will not be repeated here. The difference from the foregoing embodiments is that the isolation structure 305 further includes: a third portion C, which is adjacent to the first portion A and the second portion B, and the projection of the third portion C on the surface of the substrate 200 is located within the projection range of the second portion B on the surface of the substrate 200.

[0105] The dimension of the third portion C in the third direction Y is smaller than the dimension of the first portion A in the third direction Y. The third direction Y is perpendicular to the second direction X and parallel to the surface of the substrate 200.

[0106] The sum of the dimensions of the third portion C along the first direction Z and the second portion B along the first direction Z is not greater than the dimension of the first portion A along the first direction Z. Specifically, in some embodiments of the present invention, the sum of the dimensions of the third portion C along the first direction Z and the second portion B along the first direction Z is less than the dimension of the first portion A along the first direction Z.

[0107] The dimensions of the first portion A along the first direction Z are 15μm to 25μm; the dimensions of the first portion A along the second direction X are 1μm to 5μm; and the dimensions of the first portion A along the third direction Y are 8μm to 15μm. The dimensions of the second portion B along the first direction Z are 3μm to 8μm; the dimensions of the second portion B along the second direction X are 1μm to 3μm; and the dimensions of the second portion B along the third direction Y are 8μm to 15μm. The dimensions of the third portion C along the first direction Z are 4μm to 7μm; the dimensions of the third portion C along the second direction X are 1μm to 3μm; and the dimensions of the third portion C along the third direction Y are 3μm to 8μm.

[0108] Accordingly, embodiments of the present invention also provide another semiconductor structure, please refer to [the relevant documentation]. Figures 31 to 33 and in conjunction with references Figure 36 , Figure 32 yes Figure 31 A sectional view at position CC1. Figure 33 yes Figure 31 Sectional view at position DD1, Figure 36 This is a perspective view of an embodiment of the present invention.

[0109] The similarities to the foregoing embodiments will not be repeated here. The difference from the foregoing embodiments is that the sum of the dimension of the third portion C along the first direction Z and the dimension of the second portion B along the first direction Z is equal to the dimension of the first portion A along the first direction Z.

[0110] The dimensions of the first portion A along the first direction Z are 15μm to 25μm; the dimensions of the first portion A along the second direction X are 1μm to 5μm; and the dimensions of the first portion A along the third direction Y are 8μm to 15μm. The dimensions of the second portion B along the first direction Z are 3μm to 9μm; the dimensions of the second portion B along the second direction X are 1μm to 3μm; and the dimensions of the second portion B along the third direction Y are 8μm to 15μm. The dimensions of the third portion C along the first direction Z are 7μm to 16μm; the dimensions of the third portion C along the second direction X are 1μm to 3μm; and the dimensions of the third portion C along the third direction Y are 3μm to 8μm.

[0111] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The application relates to a semiconductor device, comprising: a substrate, the substrate comprising a drift region; an isolation structure in the drift region, the isolation structure comprising at least two first sections and at least one second section along a second direction, the second section having a dimension along a first direction smaller than the first section, the first section and the second section being arranged alternately along the second direction, the first section and the second section being adjacent to each other, the second direction being parallel to a surface of the substrate, and the first direction being a direction from a top surface of the substrate to a bottom surface of the substrate.

2. The semiconductor structure of claim 1, wherein, The isolation structure further comprises a third section, the third section being adjacent to the first section and the second section, and a projection of the third section on the surface of the substrate being within a projection of the second section on the surface of the substrate.

3. The semiconductor structure of claim 2, wherein, The third section has a dimension along a third direction smaller than the first section, the third direction being perpendicular to the second direction, and the third direction being parallel to the surface of the substrate.

4. The semiconductor structure of claim 2, wherein, The sum of the dimension of the third section along the first direction and the dimension of the second section along the first direction is not greater than the dimension of the first section along the first direction.

5. The semiconductor structure of claim 3, wherein, The ratio of the dimension of the first section along the first direction to the dimension of the first section along the third direction is in a range of 1.5 to 8.

6. The semiconductor structure of claim 3, wherein, The application further relates to a semiconductor device, comprising: a source and a drain, the source and the drain being located on two sides of the isolation structure along the third direction.

7. The semiconductor structure of claim 6, wherein the first and second semiconductor layers are formed of a same material. The application further relates to a semiconductor device, comprising: a gate, the gate being located on a side of the source away from the isolation structure along the third direction.

8. The semiconductor structure of claim 1, wherein, The substrate comprises a substrate, an insulating layer on the substrate, and a semiconductor layer on the insulating layer, the semiconductor layer comprising the drift region.

9. A method of forming a semiconductor structure, comprising: The application relates to a method for manufacturing a semiconductor device, comprising: providing a substrate, the substrate having a drift region; etching the substrate of the drift region to form a first opening; after forming the first opening, forming a first mask layer on the substrate, the first mask layer exposing the substrate of the drift region; using the first mask layer as a mask, etching the substrate of the drift region to form an isolation trench; filling the isolation trench to form an isolation structure, the isolation structure comprising at least two first sections and at least one second section along a second direction, the second section having a dimension along a first direction smaller than the first section, the first section and the second section being arranged alternately along the second direction, the first section and the second section being adjacent to each other, the second direction being parallel to a surface of the substrate, and the first direction being a direction from a top surface of the substrate to a bottom surface of the substrate.

10. The method of forming a semiconductor structure of claim 9, wherein, In the step of forming the isolation trench, the isolation trench comprises first regions and second regions, the first regions and the second regions being arranged alternately along the second direction, the isolation trench of the first regions corresponding to the first opening, and the isolation trench of the second regions being connected to the isolation trench of the first regions; In the step of filling the isolation trench to form the isolation structure, the isolation trench of the first regions and the isolation trench of the second regions are filled to form the first section and the second section respectively.

11. The method of forming a semiconductor structure of claim 9, wherein, A depth of the first opening is greater than a difference between a size of the first sub-portion along the first direction and a size of the second sub-portion along the first direction.

12. The method of forming a semiconductor structure of claim 9, wherein, After the first opening is formed, before the first mask layer is formed, the method further includes forming a second opening in the drift region, the second opening being arranged along a second direction with the first opening, a size of the second opening along a third direction being not greater than a size of the first opening along the third direction, the third direction being perpendicular to the second direction, the third direction being parallel to the surface of the substrate.

13. The method of forming a semiconductor structure of claim 12, wherein, A depth of the second opening is not greater than a depth of the first opening.

14. The method of forming a semiconductor structure of claim 9, wherein, The first mask layer is a hard mask.

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