Electronic device with Schottky contact and preparation method thereof

Abstract

The invention relates to an electronic device with Schottky contact. The electronic device comprises an AOS layer; the first metal layer is positioned on one side of the AOS layer, and the material of the first metal layer is metal of which the work function is not less than 4.7 eV; the insertion layer is located between the AOS layer and the first metal layer and is in direct contact with the AOS layer and the first metal layer, and the insertion layer is made of oxide with the relative dielectric constant not smaller than 8 and the band gap not smaller than 3.5 eV; wherein the AOS layer, the insertion layer and the first metal layer form a Schottky contact structure; wherein the AOS layer is not in direct contact with the first metal layer; wherein the thickness of the insertion layer is not greater than 5nm. According to the electronic device with the Schottky contact, reverse bias current can be reduced, the Schottky barrier is improved, and the overall performance is greatly improved. The invention also relates to a preparation method of the electronic device with Schottky contact.

Description

Technical Field

[0001] The present application relates to a semiconductor electronic device, and in particular to an electronic device with Schottky contact and a preparation method thereof. Background Art

[0002] Schottky contacts are widely used in the structures of electronic devices such as Schottky diodes (SBDs), metal semiconductor field effect transistors (MESFETs), source-gate transistors (SGTs), and high electron mobility transistors (HEMTs). These electronic devices with Schottky contacts play an important role in photoelectric detection, power devices, sensing, and other fields.

[0003] At the same time, the emergence of amorphous oxide semiconductor (AOS) materials represented by amorphous indium gallium zinc oxide (a-IGZO) has injected new development space into the application of thin film transistors (TFT) and semiconductor electronic devices with Schottky contacts, such as Schottky diodes (SBDs) and source-gate transistors (SGTs), in cutting-edge fields such as flexible electronics and wearable devices.

[0004] However, compared to ohmic contacts, it is more difficult for AOS materials to form stable Schottky contacts with metals. This is mainly because the interface between metal and AOS is easily affected by oxygen, metal and hydrogen-related defects in AOS. These defects and dangling bonds at the metal-semiconductor interface will produce a large number of interface states. Another source of interface states is the metal wave function that decays into the semiconductor band gap, called metal induced gap state (MIGS). The interface state sources mainly composed of the above two will lead to Fermi level pinning at the metal-semiconductor interface, making it difficult to form a high-performance metal-AOS Schottky contact with a high Schottky barrier height.

[0005] In addition to the characteristics of the material itself, in the preparation process of electronic devices with metal-AOS Schottky contact, the plasma treatment process, the adsorption and desorption process of AOS on oxygen, hydrogen and water in the atmospheric environment brought by the non-vacuum environment, etc., will also have an adverse effect on the performance and long-term stability of electronic devices with metal-AOS Schottky contact.

[0006] Taking the common top anode AOS Schottky diode as an example, on the one hand, due to the large number of defect states and MIGS effect of the AOS material itself, and on the other hand, additional defects introduced in the preparation process such as reactive ion etching (RIE) of the passivation layer opening, both the characteristics of the material itself and the preparation process will make it difficult to form high-performance AOS Schottky diodes, such as resulting in high reverse bias current, low rectification ratio, and low breakdown voltage of the AOS Schottky diode. Summary of the invention

[0007] In response to the technical problems existing in the prior art, the present application proposes an electronic device with Schottky contact, comprising: an AOS layer; a first metal layer located on one side of the AOS layer, the material of the first metal layer is a metal with a work function of not less than 4.7 eV; and an insertion layer located between the AOS layer and the first metal layer and in direct contact with the AOS layer and the first metal layer, the material of the insertion layer is an oxide with a relative dielectric constant of not less than 8 and a band gap of not less than 3.5 eV; wherein the AOS layer, the insertion layer and the first metal layer form a Schottky contact structure; wherein the AOS layer is not in direct contact with the first metal layer; wherein the thickness of the insertion layer is not greater than 5 nm.

[0008] Particularly, the electronic device is a diode, and further comprises: a second metal layer located on the other side of the AOS layer, wherein the material of the second metal layer is a metal with a work function less than 4.7 eV.

[0009] In particular, the electronic device is a bottom-gate SGT transistor, the AOS layer is the active layer of the bottom-gate SGT transistor, and the first metal layer is the source electrode layer of the bottom-gate SGT transistor; the bottom-gate SGT transistor also includes: a substrate layer; a third metal layer serving as a gate electrode layer located above the substrate layer, the material of the third metal layer being a metal with a work function less than 4.7 eV; a gate dielectric layer located between the substrate layer and the AOS layer and covering the third metal layer; and a fourth metal layer serving as a drain electrode layer located on the surface of the AOS layer not covered by the insertion layer.

[0010] In particular, the electronic device is a top-gate SGT transistor, the AOS layer is the active layer of the top-gate SGT transistor, and the first metal layer is the source electrode layer of the top-gate SGT transistor; the top-gate SGT transistor also includes: a substrate layer; a fourth metal layer located between the substrate layer and the AOS layer and serving as a drain electrode layer; a gate oxide dielectric layer located above the AOS layer and in contact with the insertion layer and the fourth metal layer; a third metal layer located above the gate oxide dielectric layer and serving as a gate electrode layer, wherein the material of the third metal layer is a metal having a work function less than 4.7 eV; wherein the fourth metal layer is not in direct contact with the first metal layer and the insertion layer.

[0011] The present application proposes a method for preparing an electronic device with Schottky contact, comprising: forming an AOS layer; forming an insertion layer on the AOS layer through an atomic layer deposition process, wherein the material of the insertion layer is an oxide with a relative dielectric constant of not less than 8 and a band gap of not less than 3.5 eV; forming a first metal layer on the insertion layer, wherein the material of the first metal layer is a metal with a work function of not less than 4.7 eV; wherein the thickness of the insertion layer is not greater than 5 nm; wherein the AOS layer is not in direct contact with the first metal layer.

[0012] Particularly, the deposition temperature range of the atomic deposition process is 100° C. to 300° C.

[0013] In particular, the method further includes performing N treatment on the surface of the AOS layer in contact with the AOS layer before forming the insertion layer. 2 O plasma treatment and annealing in an oxygen atmosphere.

[0014] The present application also proposes a method for preparing an electronic device with a Schottky contact, comprising: forming a first metal layer, wherein the material of the first metal layer is a metal having a work function of not less than 4.7 eV; forming an insertion layer on the first metal layer through an atomic layer deposition process, wherein the material of the insertion layer is an oxide having a relative dielectric constant of not less than 8 and a band gap of not less than 3.5 eV; forming an AOS layer on the insertion layer; wherein the thickness of the insertion layer is not greater than 5 nm; wherein the AOS layer is not in direct contact with the first metal layer.

[0015] Particularly, the deposition temperature range of the atomic deposition process is 100° C. to 300° C. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0017] Figure 1 is a schematic diagram of a Schottky contact structure according to an embodiment of the present application;

[0018] Figure 2(a) to Figure 2(e) is a schematic diagram of the state of the top anode Schottky diode preparation process according to an embodiment of the present application;

[0019] Figure 3(a) to Figure 3(d) is a schematic diagram of the preparation process of a bottom anode Schottky diode according to an embodiment of the present application;

[0020] Figure 4(a) to Figure 4(f) This is a schematic diagram of the state of the bottom-gate AOS source-gate thin-film transistor preparation process according to an embodiment of the present application;

[0021] Figure 5(a) to Figure 5(f) is a schematic diagram of the state of the top-gate AOS source-gate thin-film transistor preparation process according to an embodiment of the present application; and

[0022] Figure 6 This is a comparison diagram of current density-anode voltage curves of a Schottky diode before and after the insertion layer is introduced according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0024] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0025] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0026] In order to suppress the interface state of the Schottky contact, the present application proposes a metal-amorphous oxide semiconductor (AOS) Schottky contact structure, and introduces an insertion layer into the existing Schottky contact structure. Compared with the existing Schottky contact structure, the metal-AOS Schottky contact structure proposed in the present application can reduce the reverse bias current and increase the Schottky barrier, thereby greatly improving the overall performance of the Schottky contact structure and the electronic device having the structure. In addition, the metal-AOS Schottky contact structure proposed in the present application can be prepared under low temperature conditions, greatly reducing the preparation cost of the Schottky contact structure and the electronic device having the structure.

[0027] Figure 1 Schematic diagram of a Schottky contact structure according to an embodiment of the present application.

[0028] According to one embodiment, Figure 1 The illustrated Schottky contact structure 100 may include an AOS layer 130 .

[0029] According to one embodiment, the material of the AOS layer 130 may be amorphous indium gallium zinc oxide (a-IGZO), amorphous indium gallium oxide (a-IGO), amorphous indium zinc oxide (a-IZO), amorphous indium tin zinc oxide (a-ITZO), amorphous zinc tin oxide (a-ZTO), amorphous indium oxide (a-In 2 O 3 ) and the like.

[0030] According to one embodiment, Figure 1 The illustrated Schottky contact structure 100 may include a metal layer 160 .

[0031] According to one embodiment, the material of the metal layer 160 may be a metal having a high work function (eg, not less than 4.7 eV), such as any one of platinum, gold, palladium, nickel, cobalt, and the like.

[0032] According to one embodiment, Figure 1 The Schottky contact structure 100 shown may include an insertion layer 150 located between the AOS layer 130 and the metal layer 160 , wherein the insertion layer 150 is in direct contact with both the AOS layer 130 and the metal layer 160 ; and the AOS layer 130 is not in direct contact with the metal layer 160 .

[0033] According to one embodiment, the material of the insertion layer 150 may be an oxide insulator with a high dielectric constant (eg, a relative dielectric constant not less than 8) and an ultra-high band gap (eg, not less than 5.5 eV), such as aluminum oxide (Al2O3). 2 O 3 ), hafnium dioxide (HfO 2 ), silicon dioxide (SiO 2 ), Tantalum pentoxide (Ta 2 O 5 )、ZrO 2 ), niobium pentoxide (Nb 2 O 5 ), Erbium Oxide (Er 2 O 3 ), samarium oxide (Sm 2 O 3 ), lanthanum oxide (La 2 O 3 ), SrTiO 3 ), Germanium dioxide (GeO 2 ) etc.

[0034] If the actual application requires a higher on-state current of the Schottky contact structure 100 and a lower tunneling resistance, according to one embodiment, the material of the insertion layer 150 can be an oxide insulator with a high dielectric constant (e.g., a relative dielectric constant not less than 8) and a relatively narrow band gap (e.g., between 3.5 eV and 4.5 eV), such as gallium oxide (GaO). 2 O 3 ), titanium dioxide (TiO 2 ), zinc oxide (ZnO), etc.

[0035] According to one embodiment, the thickness of the insertion layer 150 may be no greater than 5 nm.

[0036] The insertion layer 150 is introduced between the AOS layer 130 and the metal layer 160. On the one hand, it can reduce the dangling bond density originating from the AOS layer at the metal-AOS Schottky contact interface, passivate the defect states of the interface, and then reduce the interface state density, thereby achieving Fermi level depinning; on the other hand, the insertion layer 150 can make the metal induced gap state (MIGS) originating from the metal layer at the metal-AOS Schottky contact interface decay faster, thereby quickly releasing the pinning of the Fermi level.

[0037] At the same time, when the thickness of the insertion layer 150 is not greater than 5 nm, a metal-AOS Schottky contact with a high Schottky barrier can be obtained, thereby significantly reducing the reverse bias current density of the metal-AOS Schottky contact structure, and at a positive bias, electrons can pass through the insertion layer 150 by the tunneling effect without significant degradation, thereby effectively improving the Figure 1 The breakdown voltage and overall performance of the electronic device of the metal-AOS Schottky contact structure 100 are shown.

[0038] Figure 2(a) to Figure 2(e) It is a schematic diagram of the state of the top anode Schottky diode preparation process according to an embodiment of the present application; wherein, FIG2(e) shows the structure of the top anode Schottky diode 200 having the metal-AOS Schottky contact structure proposed in the present application prepared by the process.

[0039] According to one embodiment, the top anode Schottky diode 200 shown in FIG. 2( e ) may include a substrate layer 210 and a cathode metal layer 220 located on the substrate layer 210 .

[0040] According to one embodiment, the material of the substrate layer 210 may be any one of silicon, glass and the like.

[0041] According to one embodiment, the material of the substrate layer 210 may be any one of flexible materials such as polyimide (PI) and polyethylene terephthalate (PET).

[0042] According to one embodiment, the material of the cathode metal layer 220 may be a metal with a low work function (eg, less than 4.7 eV), such as any one of molybdenum (Mo), titanium (Ti), and the like.

[0043] According to one embodiment, the top anode Schottky diode 200 shown in FIG. 2( e ) may include a patterned AOS layer 231 located on the cathode metal layer 220 .

[0044] According to one embodiment, the material of the patterned AOS layer 231 may be amorphous indium gallium zinc oxide (a-IGZO), amorphous indium gallium oxide (a-IGO), amorphous indium zinc oxide (a-IZO), amorphous indium tin zinc oxide (a-ITZO), amorphous zinc tin oxide (a-ZTO), amorphous indium oxide (a-In 2 O 3 ) and the like.

[0045] According to one embodiment, the top anode Schottky diode 200 shown in FIG2(e) may include a patterned passivation layer 241. The patterned passivation layer 241 is located on the cathode metal layer 220 and surrounds the patterned AOS layer 231, and the lower surface of the patterned passivation layer 241 covers a portion of the upper surface of the patterned AOS layer 231.

[0046] According to one embodiment, the material of the patterned passivation layer 241 may include silicon dioxide (SiO 2 ) etc.

[0047] According to one embodiment, the top anode Schottky diode 200 shown in FIG. 2( e ) may include a patterned insertion layer 251 , wherein both ends of the lower surface of the patterned insertion layer 251 are in contact with the upper surface of the patterned passivation layer 241 , and the remaining portion of the lower surface of the patterned insertion layer 251 is located above the upper surface of the patterned AOS layer 231 not covered by the patterned passivation layer 241 .

[0048] According to one embodiment, the thickness of the patterned insertion layer 251 may be no greater than 5 nm.

[0049] According to one embodiment, the material of the patterned insertion layer 251 may be an oxide insulator with a high dielectric constant (eg, a relative dielectric constant not less than 8) and an ultra-high band gap (eg, not less than 5.5 eV), such as aluminum oxide (Al 2 O 3 ), hafnium dioxide (HfO 2 ), silicon dioxide (SiO 2 ), Tantalum pentoxide (Ta 2 O 5 )、ZrO 2 ), niobium pentoxide (Nb 2 O 5 ), Erbium Oxide (Er 2 O 3 ), samarium oxide (Sm 2 O 3 ), lanthanum oxide (La 2 O 3 ), SrTiO 3 ), Germanium dioxide (GeO 2) etc.

[0050] If the actual application requires a higher on-state current of the Schottky contact structure in the top anode Schottky diode 200 and a lower tunneling resistance, according to one embodiment, the material of the patterned insertion layer 251 can be an oxide insulator with a high dielectric constant (e.g., a relative dielectric constant not less than 8) and a relatively narrow band gap (e.g., between 3.5 eV and 4.5 eV), such as gallium oxide (GaO). 2 O 3 ), titanium dioxide (TiO 2 ), zinc oxide (ZnO), etc.

[0051] According to one embodiment, the top anode Schottky diode 200 shown in FIG. 2( e ) may include a patterned anode metal layer 261 located on the patterned insertion layer 251 .

[0052] According to one embodiment, the patterned anode metal layer 261 is not in direct contact with the patterned AOS layer 231 .

[0053] According to one embodiment, the material of the patterned anode metal layer 261 may be a metal with a high work function (eg, not less than 4.7 eV), such as any one of platinum, gold, palladium, nickel, cobalt, and the like.

[0054] According to one embodiment, a method for preparing the top anode Schottky diode 200 shown in FIG. 2( e ) includes:

[0055] 2000: Provide a substrate layer 210 as shown in FIG. 2( a ).

[0056] 2100: Form a cathode metal layer 220 on the substrate layer 210 by a process such as sputtering deposition, as shown in FIG. 2( a ).

[0057] 2200 : Forming an AOS layer 230 on the cathode metal layer 220 by a process such as sputtering deposition, as shown in FIG. 2( a ).

[0058] 2250 : Patterning the AOS layer 230 to form a patterned AOS layer 231 , as shown in FIG. 2( b ).

[0059] 2300 : Depositing a passivation layer (not shown) on the patterned AOS layer 231 and the cathode metal layer 220 by a process such as plasma enhanced chemical vapor deposition (PECVD).

[0060] 2350: The passivation layer is opened and patterned by a process such as reactive ion etching (RIE) to form a patterned passivation layer 241, as shown in FIG. 2(c).

[0061] 2400 : pre-treating the upper surface of the patterned AOS layer 231 that is not covered by the patterned passivation layer 241 .

[0062] According to an exemplary embodiment, the pretreatment may be performed by nitrous oxide plasma (N 2 O Plasma) treatment. The reaction gas pressure was 0.55 Torr, and the reaction gas was 400 sccm N 2 O, reaction power is 50W, processing time is 200 seconds, and processing temperature is 150°C. Then annealing is carried out in an oxygen atmosphere, the annealing time is 2 hours, and the annealing temperature is 350°C.

[0063] 2410 : Depositing an insertion layer (not shown) having a thickness not greater than 5 nm on the patterned AOS layer 231 and the patterned passivation layer 241 by a process such as magnetron sputtering deposition or atomic layer deposition (ALD).

[0064] According to one embodiment, a layer of Al is deposited by a plasma enhanced atomic layer deposition (PEALD) process. 2 O 3 Taking the insertion layer as an example: trimethylaluminum (TMA) and oxygen plasma are used as reaction sources; the deposition temperature is 200°C; each ALD cycle consists of a 0.5-second TMA pulse, a 15-second nitrogen pulse purge, a 0.3-second oxygen plasma pulse, and a 15-second nitrogen pulse purge.

[0065] According to one embodiment, the deposition temperature of the ALD process may range from 100° C. to 300° C.

[0066] According to other embodiments, the method in 2410 can be replaced by: depositing a metal layer (not shown) on the patterned AOS layer 231 and the patterned passivation layer 241 through processes such as magnetron sputtering deposition, atomic layer deposition (ALD), electron beam evaporation coating, thermal evaporation, etc., and then oxidizing the metal layer through processes such as high-temperature thermal oxidation to form an insertion layer (not shown) with a thickness not greater than 5 nm.

[0067] 2450: Patterning the insertion layer to form a patterned insertion layer 251, as shown in FIG. 2(d).

[0068] 2500 : Depositing an anode metal layer (not shown) on the patterned insertion layer 251 by a process such as sputtering deposition.

[0069] 2550: Patterning the anode metal layer to form a patterned anode metal layer 261, as shown in FIG. 2(e).

[0070] Figure 6This is a comparison diagram of current density-voltage curves of a Schottky diode before and after the insertion layer is introduced according to an embodiment of the present application.

[0071] According to one embodiment, taking a Schottky diode having an AOS layer whose material is amorphous indium zinc oxide (a-IZO) as an example, Figure 6 Curve 601 is a graph showing the current density versus anode voltage (JV) of an a-IZO Schottky diode without an insertion layer. A )curve, Figure 6 The curve 602 is a curve of a material having a thickness of 1 nm and Al 2 O 3 JV of the insertion layer of the a-IZO Schottky diode A curve.

[0072] Comparing curves 601 and 602, it can be seen that, compared with the current density of the Schottky diode without the insertion layer, the current density of the Schottky diode with the insertion layer is only reduced by less than one order of magnitude in the positive voltage range, but is reduced by more than four orders of magnitude in the negative voltage range. It can be seen that the Schottky diode with the insertion layer significantly reduces the reverse biased off-state current, improves the Schottky barrier, and improves the rectification ratio by about four orders of magnitude without significantly affecting the on-state current.

[0073] According to one embodiment, if the material of the insertion layer is an oxide insulator with a high dielectric constant (e.g., a relative dielectric constant not less than 8) and a relatively narrow band gap (e.g., between 3.5 eV and 4.5 eV), such as gallium oxide (Ga 2 O 3 ), titanium dioxide (TiO 2 ), zinc oxide (ZnO), etc., the Schottky diode with an insertion layer will have less impact on the on-state current.

[0074] Figure 3(a) to Figure 3(d) It is a schematic diagram of the bottom anode Schottky diode preparation process according to an embodiment of the present application; wherein, FIG3(d) shows the structure of the bottom anode Schottky diode 300 having the metal-AOS Schottky contact structure proposed in the present application prepared by the process.

[0075] According to one embodiment, the bottom anode Schottky diode 300 shown in FIG. 3( d ) may include a substrate layer 310 and an anode metal layer 360 located on the substrate layer 310 .

[0076] According to one embodiment, the material of the substrate layer 310 may be any one of silicon, glass, etc.

[0077] According to one embodiment, the material of the substrate layer 310 may be any one of flexible materials such as polyimide (PI) and polyethylene terephthalate (PET).

[0078] According to one embodiment, the material of the anode metal layer 360 may be a metal with a high work function (eg, not less than 4.7 eV), such as any one of platinum, gold, palladium, nickel, cobalt, and the like.

[0079] According to one embodiment, the bottom anode Schottky diode 300 shown in FIG. 3( d ) may include a patterned insertion layer 351 located on the anode metal layer 360 .

[0080] According to one embodiment, the thickness of the patterned insertion layer 351 may be no greater than 5 nm.

[0081] According to one embodiment, the material of the patterned insertion layer 351 may be an oxide insulator with a high dielectric constant (eg, a relative dielectric constant not less than 8) and an ultra-high band gap (eg, not less than 5.5 eV), such as aluminum oxide (Al 2 O 3 ), hafnium dioxide (HfO 2 ), silicon dioxide (SiO 2 ), Tantalum pentoxide (Ta 2 O 5 )、ZrO 2 ), niobium pentoxide (Nb 2 O 5 ), Erbium Oxide (Er 2 O 3 ), samarium oxide (Sm 2 O 3 ), lanthanum oxide (La 2 O 3 ), SrTiO 3 ), Germanium dioxide (GeO 2 ) etc.

[0082] If the actual application requires a higher on-state current of the Schottky contact structure in the bottom anode Schottky diode 300 and a lower tunneling resistance, according to a preferred embodiment, the material of the patterned insertion layer 351 can be an oxide insulator with a high dielectric constant (e.g., a relative dielectric constant of not less than 8) and a relatively narrow band gap (e.g., between 3.5 eV and 4.5 eV) in an oxygen-rich state, such as gallium oxide (Ga 2 O 3 ), titanium dioxide (TiO 2 ), zinc oxide (ZnO), etc.

[0083] According to one embodiment, the bottom anode Schottky diode 300 shown in FIG. 3( d ) may include a patterned AOS layer 331 on top of the patterned insertion layer 351 .

[0084] According to one embodiment, the patterned AOS layer 331 is not in direct contact with the anode metal layer 360 .

[0085] According to one embodiment, the material of the patterned AOS layer 331 may be amorphous indium gallium zinc oxide (a-IGZO), amorphous indium gallium oxide (a-IGO), amorphous indium zinc oxide (a-IZO), amorphous indium tin zinc oxide (a-ITZO), amorphous zinc tin oxide (a-ZTO), amorphous indium oxide (a-In 2 O 3 ) and the like.

[0086] According to one embodiment, the bottom anode Schottky diode 300 shown in FIG3(d) may include a patterned passivation layer 341. The patterned passivation layer 341 is located on the anode metal layer 360 and surrounds the patterned AOS layer 331 and the patterned insertion layer 351, and the lower surface of the patterned passivation layer 341 covers a portion of the upper surface of the patterned AOS layer 331.

[0087] According to one embodiment, the material of the patterned passivation layer 341 may include silicon dioxide (SiO 2 ) etc.

[0088] According to one embodiment, the bottom anode Schottky diode 300 shown in FIG. 3( d ) may include a patterned cathode metal layer 321 , wherein both ends of the lower surface of the patterned cathode metal layer 321 are in contact with the upper surface of the patterned passivation layer 341 , and the remaining portion of the lower surface of the patterned cathode metal layer 321 is located above the upper surface of the patterned AOS layer 331 not covered by the patterned passivation layer 341 .

[0089] According to one embodiment, the material of the patterned cathode metal layer 321 may be a metal with a low work function (eg, less than 4.7 eV), such as any one of molybdenum (Mo), titanium (Ti), and the like.

[0090] According to one embodiment, a method for preparing the bottom anode Schottky diode 300 shown in FIG. 3( d ) includes:

[0091] 3000: Provide a substrate layer 310 as shown in FIG. 3( a ).

[0092] 3100: An anode metal layer 360 is formed on the substrate layer 310 by a process such as sputtering deposition, as shown in FIG. 3(a).

[0093] 3200: Deposit an insertion layer 350 with a thickness not greater than 5 nm on the anode metal layer 360 by a process such as magnetron sputtering deposition, atomic layer deposition (ALD), etc., as shown in FIG. 3( a ).

[0094] According to one embodiment, a layer of Al is deposited by a plasma enhanced atomic layer deposition (PEALD) process. 2 O 3 Taking the insertion material layer as an example: trimethylaluminum (TMA) and oxygen plasma are used as reaction sources; the deposition temperature is 200°C; each ALD cycle consists of a 0.5-second TMA pulse, a 15-second nitrogen pulse purge, a 0.3-second oxygen plasma pulse, and a 15-second nitrogen pulse purge.

[0095] According to one embodiment, the deposition temperature of the ALD process may range from 100° C. to 300° C.

[0096] According to other embodiments, the method in 3200 can be replaced by: depositing a metal layer (not shown) on the anode metal layer 360 by processes such as magnetron sputtering deposition, atomic layer deposition (ALD), electron beam evaporation coating, thermal evaporation, etc., and then oxidizing the metal layer by processes such as high-temperature thermal oxidation to form an insertion layer 350 with a thickness not greater than 5 nm, as shown in Figure 3(a).

[0097] 3300 : An AOS layer 330 is formed on the insertion layer 350 by a process such as sputtering deposition, as shown in FIG. 3( a ).

[0098] 3400 : patterning the insertion layer 350 and the AOS layer 330 to form a patterned insertion layer 351 and a patterned AOS layer 331 , as shown in FIG. 3( b ).

[0099] 3500 : Depositing a passivation layer (not shown) on the patterned AOS layer 331 and the anode metal layer 360 by a process such as plasma enhanced chemical vapor deposition (PECVD).

[0100] 3550: The passivation layer is opened and patterned by a process such as reactive ion etching (RIE) to form a patterned passivation layer 341, as shown in FIG. 3(c).

[0101] 3600 : Depositing a cathode metal layer (not shown) on the patterned AOS layer 331 and the patterned passivation layer 341 by a process such as sputtering deposition.

[0102] 3650: Patterning the cathode metal layer to form a patterned cathode metal layer 321, as shown in FIG. 3(d).

[0103] Figure 4(a) to Figure 4(f)It is a schematic diagram of the bottom-gate AOS source-gate thin-film transistor preparation process according to an embodiment of the present application; wherein, FIG4(f) shows the structure of a bottom-gate AOS source-gate thin-film transistor 400 having a metal-AOS Schottky contact structure proposed in the present application, which is prepared by the process.

[0104] According to one embodiment, the bottom-gate AOS source-gate thin film transistor 400 shown in FIG. 4( f ) may include a substrate layer 410 and a patterned gate metal layer 471 located on the substrate layer 410 .

[0105] According to one embodiment, the material of the substrate layer 410 may be any one of silicon, glass, etc.

[0106] According to one embodiment, the material of the substrate layer 410 may be any one of flexible materials such as polyimide (PI) and polyethylene terephthalate (PET).

[0107] According to one embodiment, the material of the patterned gate metal layer 471 may be a metal with a low work function (eg, less than 4.7 eV), such as any one of molybdenum (Mo), titanium (Ti), and the like.

[0108] According to one embodiment, the bottom-gate AOS source-gate thin film transistor 400 shown in FIG. 4( f ) may include a gate oxide dielectric layer 475 covering the substrate layer 410 and the patterned gate metal layer 471 .

[0109] According to one embodiment, the material of the gate oxide dielectric layer 475 may be silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), hafnium dioxide (HfO 2 )) etc.

[0110] According to one embodiment, the bottom-gate AOS source-gate thin film transistor 400 shown in FIG. 4( f ) may include a patterned AOS layer 431 located on the gate oxide dielectric layer 471 .

[0111] According to one embodiment, the material of the patterned AOS layer 431 may be amorphous indium gallium zinc oxide (a-IGZO), amorphous indium gallium oxide (a-IGO), amorphous indium zinc oxide (a-IZO), amorphous indium tin zinc oxide (a-ITZO), amorphous zinc tin oxide (a-ZTO), amorphous indium oxide (a-In 2 O 3 ) and the like.

[0112] According to one embodiment, the bottom-gate AOS source-gate thin film transistor 400 shown in FIG4(f) may include a patterned insertion layer 451. A portion of the lower surface of the patterned insertion layer 451 contacts the upper surface of the gate oxide dielectric layer 475; another portion of the lower surface of the patterned insertion layer 451 covers a portion of the upper surface of the patterned AOS layer.

[0113] According to one embodiment, the thickness of the patterned insertion layer 451 may be no greater than 5 nm.

[0114] According to one embodiment, the material of the patterned insertion layer 451 may be an oxide insulator with a high dielectric constant (eg, a relative dielectric constant not less than 8) and an ultra-high band gap (eg, not less than 5.5 eV), such as aluminum oxide (Al2O3). 2 O 3 ), hafnium dioxide (HfO 2 ), silicon dioxide (SiO 2 ), Tantalum pentoxide (Ta 2 O 5 )、ZrO 2 ), niobium pentoxide (Nb 2 O 5 ), Erbium Oxide (Er 2 O 3 ), samarium oxide (Sm 2 O 3 ), lanthanum oxide (La 2 O 3 ), SrTiO 3 ), Germanium dioxide (GeO 2 ) etc.

[0115] If the actual application requires a higher on-state current of the Schottky contact structure in the AOS source-gate thin film transistor and a lower tunneling resistance, according to one embodiment, the material of the patterned insertion layer 451 can be an oxide insulator with a high dielectric constant (e.g., a relative dielectric constant of not less than 8) and a relatively narrow band gap (e.g., between 3.5 eV and 4.5 eV), such as gallium oxide (GaO). 2 O 3 ), titanium dioxide (TiO 2 ), zinc oxide (ZnO), etc.

[0116] According to one embodiment, the bottom-gate AOS source-gate thin film transistor 400 shown in FIG. 4( f ) may include a patterned source metal layer 481 located on the patterned insertion layer 451 .

[0117] According to one embodiment, the patterned source metal layer 481 is not in direct contact with the patterned AOS layer 431 .

[0118] According to one embodiment, the material of the patterned source metal layer 481 may be a metal with a high work function (eg, not less than 4.7 eV), such as any one of platinum, gold, palladium, nickel, cobalt, and the like.

[0119] According to one embodiment, the bottom-gate AOS source-gate thin film transistor 400 shown in FIG4(f) may include a patterned drain metal layer 491. A portion of the lower surface of the patterned drain metal layer 491 contacts the gate oxide dielectric layer 475; another portion of the lower surface of the patterned drain metal layer 491 covers the upper surface of the patterned AOS layer 431 that is not covered by the patterned insertion layer 451.

[0120] According to one embodiment, the material of the patterned drain metal layer 491 may be a metal with a low work function (eg, less than 4.7 eV), such as any one of molybdenum (Mo), titanium (Ti), and the like.

[0121] According to one embodiment, the material of the patterned drain metal layer 491 may be a metal with a high work function (eg, not less than 4.7 eV), such as any one of platinum, gold, palladium, nickel, cobalt, and the like.

[0122] According to one embodiment, a method for preparing the bottom-gate AOS source-gate transistor 400 shown in FIG. 4( f ) includes:

[0123] 4000: Provide a substrate layer 410 as shown in FIG. 4( a ).

[0124] 4100 : A gate metal layer (not shown) is formed on the substrate layer 410 by a process such as sputtering deposition.

[0125] 4150: Patterning the gate metal layer to form a patterned gate metal layer 471, as shown in FIG. 4(a).

[0126] 4200 : Forming a gate oxide dielectric layer 475 on the substrate layer 410 and the patterned gate metal layer 471 by a process such as sputtering deposition, as shown in FIG. 4( b ).

[0127] 4300 : Form an AOS layer (not shown) on the gate oxide dielectric layer 475 by a process such as sputtering deposition.

[0128] 4350: Patterning the AOS layer to form a patterned AOS layer 431, as shown in FIG. 4(c).

[0129] 4400 : Pre-treating the upper surface of the patterned AOS layer 431 .

[0130] According to an exemplary embodiment, the pretreatment may be performed by nitrous oxide plasma (N 2O Plasma) treatment. The reaction gas pressure was 0.55 Torr, and the reaction gas was 400 sccm N 2 O, reaction power is 50W, processing time is 200 seconds, and processing temperature is 150°C. Then annealing is carried out in an oxygen atmosphere, the annealing time is 2 hours, and the annealing temperature is 350°C.

[0131] 4410 : Deposit an insertion layer (not shown) having a thickness not greater than 5 nm on the patterned AOS layer 431 and the gate oxide dielectric layer 475 by processes such as magnetron sputtering deposition and atomic layer deposition (ALD).

[0132] According to one embodiment, a layer of Al is deposited by a plasma enhanced atomic layer deposition (PEALD) process. 2 O 3 Taking the insertion material layer as an example: trimethylaluminum (TMA) and oxygen plasma are used as reaction sources; the deposition temperature is 200°C; each ALD cycle consists of a 0.5-second TMA pulse, a 15-second nitrogen pulse purge, a 0.3-second oxygen plasma pulse, and a 15-second nitrogen pulse purge.

[0133] According to one embodiment, the deposition temperature of the ALD process may range from 100° C. to 300° C.

[0134] According to other embodiments, the method in 4410 can be replaced by: depositing a metal layer (not shown) on the patterned AOS layer 431 and the gate oxide dielectric layer 475 through processes such as magnetron sputtering deposition, atomic layer deposition (ALD), electron beam evaporation coating, thermal evaporation, etc., and then oxidizing the metal layer through processes such as high-temperature thermal oxidation to form an insertion layer (not shown) with a thickness not greater than 5 nm.

[0135] 4450: Patterning the insertion layer to form a patterned insertion layer 451, as shown in FIG. 4(d).

[0136] 4500 : Depositing a source metal layer (not shown) on the patterned insertion layer 451 by a process such as sputtering deposition.

[0137] 4550: Patterning the source metal layer to form a patterned source metal layer 481, as shown in FIG. 4(e).

[0138] 4600 : Depositing a drain metal layer (not shown) on the upper surface of the gate oxide dielectric layer 475 and the patterned AOS layer 431 that is not covered by the patterned insertion layer 451 by a process such as sputtering deposition.

[0139] 4650: Patterning the drain metal layer to form a patterned drain metal layer 491, as shown in FIG. 4(f).

[0140] Figure 5(a) to Figure 5(f) 5(f) shows the structure of a top-gate AOS source-gate thin film transistor 500 having a metal-AOS Schottky contact structure proposed in the present application, which is obtained by the process.

[0141] According to one embodiment, the top-gate AOS source-gate thin film transistor 500 shown in FIG. 5( f ) may include a substrate layer 510 and a patterned source metal layer 581 located on the substrate layer 510 .

[0142] According to one embodiment, the material of the substrate layer 510 may be any one of silicon, glass, etc.

[0143] According to one embodiment, the material of the substrate layer 510 may be any one of flexible materials such as polyimide (PI) and polyethylene terephthalate (PET).

[0144] According to one embodiment, the material of the patterned source metal layer 581 may be a metal with a high work function (eg, not less than 4.7 eV), such as any one of platinum, gold, palladium, nickel, cobalt, and the like.

[0145] According to one embodiment, the top-gate AOS source-gate thin film transistor 500 shown in FIG. 5( f ) may include a patterned insertion layer 551 , wherein the patterned insertion layer 551 is located on the substrate 510 and the patterned source metal layer 581 , and covers the patterned source metal layer 581 .

[0146] According to one embodiment, the thickness of the patterned insertion layer 551 may be no greater than 5 nm.

[0147] According to one embodiment, the material of the patterned insertion layer 551 may be an oxide insulator with a high dielectric constant (eg, a relative dielectric constant not less than 8) and an ultra-high band gap (eg, not less than 5.5 eV), such as aluminum oxide (Al2O3). 2 O 3 ), hafnium dioxide (HfO 2 ), silicon dioxide (SiO 2 ), Tantalum pentoxide (Ta 2 O 5 )、ZrO 2 ), niobium pentoxide (Nb 2 O 5 ), Erbium Oxide (Er 2 O 3 ), samarium oxide (Sm 2 O 3 ), lanthanum oxide (La 2 O3 ), SrTiO 3 ), Germanium dioxide (GeO 2 ) etc.

[0148] If the actual application requires a higher on-state current of the Schottky contact structure in the AOS source-gate thin film transistor and a lower tunneling resistance, according to one embodiment, the material of the patterned insertion layer 551 can be an oxide insulator with a high dielectric constant (e.g., a relative dielectric constant of not less than 8) and a relatively narrow band gap (e.g., between 3.5 eV and 4.5 eV), such as gallium oxide (GaO). 2 O 3 ), titanium dioxide (TiO 2 ), zinc oxide (ZnO), etc.

[0149] According to one embodiment, the top-gate AOS source-gate TFT 500 shown in FIG5(f) may include a patterned drain metal layer 591 located on a substrate 510. There is a gap between the patterned drain metal layer 591 and the patterned source metal layer 581 and the patterned insertion layer 551 covering the patterned drain metal layer 591.

[0150] According to one embodiment, the material of the patterned drain metal layer 591 may be a metal with a low work function (eg, less than 4.7 eV), such as any one of molybdenum (Mo), titanium (Ti), and the like.

[0151] According to one embodiment, the material of the patterned drain metal layer 591 may be a metal with a high work function (eg, not less than 4.7 eV), such as any one of platinum, gold, palladium, nickel, cobalt, and the like.

[0152] According to one embodiment, the top-gate AOS source-gate thin film transistor 500 shown in FIG5(f) may include a patterned AOS layer 531. One side of the lower surface of the patterned AOS layer 531 covers a portion of the upper surface of the patterned insertion layer 551, and the other side of the lower surface covers a portion of the upper surface of the patterned drain metal layer 591, and the remaining portion covers the upper surface of the substrate 510 in the interval area between the patterned source metal layer 581 / patterned insertion layer 551 and the patterned drain metal layer 591.

[0153] According to one embodiment, the patterned AOS layer 531 is not in direct contact with the patterned source metal layer 581 .

[0154] According to one embodiment, the material of the patterned AOS layer 531 may be amorphous indium gallium zinc oxide (a-IGZO), amorphous indium gallium oxide (a-IGO), amorphous indium zinc oxide (a-IZO), amorphous indium tin zinc oxide (a-ITZO), amorphous zinc tin oxide (a-ZTO), amorphous indium oxide (a-In2 O 3 ) and the like.

[0155] According to one embodiment, the top-gate AOS source-gate thin film transistor 500 shown in FIG5(f) may include a patterned gate oxide dielectric layer 576. The lower surface of the patterned gate oxide dielectric layer 576 covers the upper surface of the patterned AOS layer 531, and the upper surfaces of the patterned insertion layer 551 and the patterned drain metal layer 591 not covered by the patterned AOS layer 531.

[0156] According to one embodiment, the material of the patterned gate oxide dielectric layer 576 may be silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), hafnium dioxide (HfO 2 ) etc.

[0157] According to one embodiment, the top-gate AOS source-gate thin film transistor 500 shown in FIG. 5( f ) may include a patterned gate metal layer 571 located on the patterned gate oxide dielectric layer 576 .

[0158] According to one embodiment, the material of the patterned gate metal layer 571 may be a metal with a low work function (eg, less than 4.7 eV), such as any one of molybdenum (Mo), titanium (Ti), and the like.

[0159] According to one embodiment, a method for preparing the top-gate AOS source-gate transistor 500 shown in FIG. 5( f ) includes:

[0160] 5000: Provide a substrate layer 510 as shown in FIG. 5( a ).

[0161] 5100 : A source metal layer (not shown) is formed on the substrate layer 510 by a process such as sputtering deposition.

[0162] 5150: Patterning the source metal layer to form a patterned source metal layer 481, as shown in FIG. 5(a).

[0163] 5200 : Depositing an insertion layer (not shown) with a thickness not greater than 5 nm on the patterned source metal layer 581 and the substrate 510 by processes such as magnetron sputtering deposition and atomic layer deposition (ALD).

[0164] According to one embodiment, a layer of Al is deposited by a plasma enhanced atomic layer deposition (PEALD) process. 2 O 3Taking the insertion material layer as an example: trimethylaluminum (TMA) and oxygen plasma are used as reaction sources; the deposition temperature is 200°C; each ALD cycle consists of a 0.5-second TMA pulse, a 15-second nitrogen pulse purge, a 0.3-second oxygen plasma pulse, and a 15-second nitrogen pulse purge.

[0165] According to one embodiment, the deposition temperature of the ALD process may range from 100° C. to 300° C.

[0166] According to other embodiments, the method in 5200 can be replaced by: depositing a metal layer (not shown) on the patterned source metal layer 581 and the substrate 510 through processes such as magnetron sputtering deposition, atomic layer deposition (ALD), electron beam evaporation coating, thermal evaporation, etc., and then oxidizing the metal layer through processes such as high-temperature thermal oxidation to form an insertion layer (not shown) with a thickness not greater than 5 nm.

[0167] 5250: Patterning the insertion layer to form a patterned insertion layer 551, as shown in FIG. 5(b).

[0168] 5300 : Deposit a drain metal layer (not shown) on the substrate 510 by a process such as sputtering deposition.

[0169] 5350: Patterning the drain metal layer to form a patterned drain metal layer 591, as shown in FIG. 5(c).

[0170] 5400 : An AOS layer (not shown) is formed on the patterned insertion layer 551 , the substrate 510 , and the patterned drain metal layer 591 by a process such as sputtering deposition.

[0171] 5450: Patterning the AOS layer to form a patterned AOS layer 531, as shown in FIG. 5(d).

[0172] 5500 : forming a gate oxide dielectric layer (not shown) on the patterned insertion layer 551 , the patterned AOS layer 531 , and the patterned drain metal layer 591 by a process such as sputtering deposition.

[0173] 5550: Patterning the gate oxide dielectric layer to form a patterned gate oxide dielectric layer 576, as shown in FIG. 5(e).

[0174] 5600: Depositing a gate metal layer (not shown) on the patterned gate oxide dielectric layer 576 by a process such as sputtering deposition.

[0175] 5650: Patterning the gate metal layer to form a patterned gate metal layer 571, as shown in FIG5(f). In summary, the present application proposes a metal-AOS Schottky contact structure, and introduces an insertion layer into the existing Schottky contact structure. Compared with the existing Schottky contact structure, the metal-AOS Schottky contact structure proposed in the present application can reduce the reverse bias current and increase the Schottky barrier, thereby greatly improving the overall performance of the Schottky contact structure and the electronic devices having the structure. In addition, the metal-AOS Schottky contact structure proposed in the present application can be prepared under low temperature conditions, which greatly reduces the preparation cost of the Schottky contact structure and the electronic devices having the structure, and has broad application prospects in the fields of flexible electronics and three-dimensional integration.

[0176] It should be noted that the Schottky contact structure and preparation method thereof proposed in the present application can be used in any electronic device having a Schottky contact structure, and is not limited to the several embodiments listed in this specification.

[0177] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. An electronic device having a Schottky contact, comprising: AOS layer; A first metal layer located on one side of the AOS layer, wherein the material of the first metal layer is a metal having a work function of not less than 4.7 eV; as well as an insertion layer located between the AOS layer and the first metal layer and in direct contact with the AOS layer and the first metal layer, wherein the material of the insertion layer is an oxide having a relative dielectric constant of not less than 8 and a band gap of not less than 3.5 eV; Wherein, the AOS layer, the insertion layer and the first metal layer form a Schottky contact structure; Wherein, the AOS layer is not in direct contact with the first metal layer; Wherein, the thickness of the insertion layer is not greater than 5 nm.

2. The electronic device according to claim 1, wherein the electronic device is a diode, and further comprising: A second metal layer is located on the other side of the AOS layer, wherein the material of the second metal layer is a metal with a work function less than 4.7 eV.

3. The electronic device according to claim 1, wherein the electronic device is a bottom-gate SGT transistor, the AOS layer is an active layer of the bottom-gate SGT transistor, and the first metal layer is a source electrode layer of the bottom-gate SGT transistor; The bottom-gate SGT transistor further comprises: substrate layer; a third metal layer as a gate electrode layer located on the substrate layer, wherein the material of the third metal layer is a metal with a work function less than 4.7 eV; a gate dielectric layer located between the substrate layer and the AOS layer and covering the third metal layer; A fourth metal layer as a drain electrode layer is located on a surface of the AOS layer not covered by the insertion layer.

4. The electronic device according to claim 1, wherein the electronic device is a top-gate SGT transistor, the AOS layer is an active layer of the top-gate SGT transistor, the first metal layer is a source electrode layer of the top-gate SGT transistor; the top-gate SGT transistor further comprises: substrate layer; a fourth metal layer located between the substrate layer and the AOS layer and serving as a drain electrode layer; a gate oxide dielectric layer located on the AOS layer and in contact with the insertion layer and the fourth metal layer; A third metal layer as a gate electrode layer located on the gate oxide dielectric layer, wherein the material of the third metal layer is a metal with a work function less than 4.7 eV; The fourth metal layer is not in direct contact with the first metal layer and the insertion layer.

5. A method for preparing an electronic device having a Schottky contact, comprising: Forming an AOS layer; Forming an insertion layer on the AOS layer by an atomic layer deposition process, wherein the material of the insertion layer is an oxide having a relative dielectric constant of not less than 8 and a band gap of not less than 3.5 eV; forming a first metal layer on the insertion layer, wherein the material of the first metal layer is a metal having a work function of not less than 4.7 eV; Wherein, the thickness of the insertion layer is not greater than 5 nm; Wherein, the AOS layer is not in direct contact with the first metal layer.

6. The preparation method according to claim 5, wherein: The deposition temperature range of the atomic deposition process is 100° C. to 300° C. 7 . The preparation method according to claim 6 , further comprising, before forming the insertion layer, performing N 2 O plasma treatment on the surface of the AOS layer in contact with the insertion layer and annealing in an oxygen atmosphere.

8. A method for preparing an electronic device having a Schottky contact, comprising: forming a first metal layer, wherein the material of the first metal layer is a metal having a work function of not less than 4.7 eV; Forming an insertion layer on the first metal layer by an atomic layer deposition process, wherein the material of the insertion layer is an oxide having a relative dielectric constant of not less than 8 and a band gap of not less than 3.5 eV; forming an AOS layer on the insertion layer; Wherein, the thickness of the insertion layer is not greater than 5 nm; Wherein, the AOS layer is not in direct contact with the first metal layer.

9. The preparation method according to claim 8, wherein: The deposition temperature range of the atomic deposition process is 100° C. to 300° C.

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