Solar cell, manufacturing method thereof and photovoltaic module

Abstract

The invention relates to a solar cell, a manufacturing method thereof and a photovoltaic module. The solar cell comprises a substrate which comprises a first area and a second area which are alternately arranged on the first side of the substrate in the preset direction, and an isolation area is further arranged between the adjacent first area and second area; a first doped polycrystalline silicon layer and a second doped polycrystalline silicon layer, the first doped polycrystalline silicon layer is doped with a P-type element and is arranged on one side, deviating from the substrate, of the first region, and the second doped polycrystalline silicon layer is doped with an N-type element and a carbon element and is arranged on one side, deviating from the substrate, of the second region; an insulating isolation groove extending to the isolation area of the substrate is arranged between the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer. According to the solar cell and the manufacturing method thereof provided by the embodiment of the invention, the passivation effect of the photovoltaic module is relatively high, and the cost is relatively low.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a solar cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] IBC (Interdigitated Back Contact) cells have no metal grid lines on the front, and the emitter and back field and the corresponding positive and negative metal electrodes are integrated in a forked shape on the back of the cell. This structure minimizes optical losses and can achieve higher conversion efficiency under the same area. TBC cells introduce TOPCon cell structures based on the existing IBC cell structure, which can significantly reduce the carrier recombination losses in the silicon substrate and emitter, especially in the metal contact area. At present, there have been a large number of technical developments to improve the passivation performance of TBC cells. Since the polycrystalline silicon film structure on the back of TBC cells accounts for a large proportion, how to balance the passivation performance while reducing parasitic absorption is one of the key points of improving TBC cell efficiency and process development. However, in the preparation process of the existing TBC cell's back boron diffusion doping area and phosphorus diffusion doping area, multiple boron diffusion, phosphorus diffusion and crystallization steps are often required. Repeated high-temperature processes will make the diffusion depth of the doping elements in the first crystallized doped polysilicon uncontrollable, resulting in poor passivation effect of solar cells. In addition, multiple high-temperature treatment processes also increase the number of processes, making the production cost higher. Summary of the invention

[0003] Based on this, it is necessary to provide a solar cell and a manufacturing method thereof, and a photovoltaic module with high passivation effect and low cost.

[0004] A first aspect of an embodiment of the present application provides a solar cell, comprising:

[0005] A substrate, comprising first regions and second regions alternately arranged on a first side of the substrate along a preset direction, and an isolation region is provided between adjacent first regions and second regions; and

[0006] A first doped polysilicon layer and a second doped polysilicon layer, the first doped polysilicon layer is doped with a P-type element and is disposed on a side of the first region away from the substrate, and the second doped polysilicon layer is doped with an N-type element and a carbon element and is disposed on a side of the second region away from the substrate;

[0007] An insulating isolation trench extending to an isolation region of the substrate is provided between the first doped polysilicon layer and the second doped polysilicon layer.

[0008] In one embodiment, the solar cell further comprises:

[0009] The first tunneling oxide layer and the third doped polysilicon layer are located between the first region and the first doped polysilicon layer, and are sequentially stacked on the surface of the first region; the doping element of the third doped polysilicon layer is the same as that of the first doped polysilicon layer, and the doping element concentration of the third doped polysilicon layer is less than that of the first doped polysilicon layer; and / or

[0010] Solar cells also include:

[0011] The second tunneling oxide layer and the fourth doped polysilicon layer are located between the second region and the second doped polysilicon layer, and are sequentially stacked on the surface of the second region; the doping element of the fourth doped polysilicon layer is the same as that of the second doped polysilicon layer, and the doping element concentration of the fourth doped polysilicon layer is less than that of the second doped polysilicon layer.

[0012] In one embodiment, the solar cell further includes a first passivation layer and a second passivation layer, wherein the first passivation layer is disposed on surfaces of the first doped polysilicon layer and the second doped polysilicon layer facing away from the substrate, and the second passivation layer is disposed on a surface of the second side of the substrate.

[0013] A second aspect of an embodiment of the present application provides a method for manufacturing a solar cell, comprising:

[0014] A substrate is provided, the substrate comprising a substrate, a surface of a first side of the substrate comprising a first region and a processing region which are staggered and connected to each other along a preset direction, a first doped amorphous silicon material layer doped with a P-type element is formed on a first side of the first region, and a second doped amorphous silicon material layer doped with an N-type element is formed on a first side of the processing region;

[0015] Performing annealing treatment to form the first doped amorphous silicon material layer into a first doped polysilicon material layer, and to form the second doped amorphous silicon material layer into a second doped polysilicon material layer;

[0016] Wherein, the second doped amorphous silicon material layer is doped with carbon element.

[0017] In one embodiment, the second doped amorphous silicon material layer is formed by the following steps:

[0018] forming a second doped amorphous silicon material layer using a reaction gas including a carbon source and a silicon source;

[0019] The gas flow ratio of the carbon source to the silicon source is greater than 0 and less than or equal to 1.

[0020] In one embodiment, the annealing temperature of the annealing treatment is 910°C-930°C.

[0021] In one embodiment, a first tunneling oxide material layer and a first intrinsic amorphous silicon material layer are sequentially provided between the first region and the first doped amorphous silicon material layer; a second tunneling oxide material layer and a second intrinsic amorphous silicon material layer are sequentially provided between the processing region and the second doped amorphous silicon material layer;

[0022] The steps of annealing treatment specifically include:

[0023] Performing annealing to form the first doped amorphous silicon material layer into a first doped polysilicon material layer, and diffusing the doping elements in the first doped amorphous silicon material layer into the first intrinsic amorphous silicon material layer, so that the first intrinsic amorphous silicon material layer forms a third doped polysilicon material layer;

[0024] The second doped amorphous silicon material layer is formed into a second doped polysilicon material layer, and the doping elements in the second doped amorphous silicon material layer are diffused into the second intrinsic amorphous silicon material layer, so that the second intrinsic amorphous silicon material layer is formed into a fourth doped polysilicon material layer.

[0025] In one embodiment, the doping concentration of the third doped polysilicon material layer is less than the doping concentration of the first doped polysilicon material layer, and the doping concentration of the fourth doped polysilicon material layer is less than the doping concentration of the second doped polysilicon material layer.

[0026] In one embodiment, the step of providing a substrate comprises:

[0027] On the entire surface of the first side of the substrate, a first tunneling oxide material layer, a first intrinsic amorphous silicon material layer and a first doped amorphous silicon material layer are sequentially stacked;

[0028] removing the first tunneling oxide material layer, the first intrinsic amorphous silicon material layer and the first doped amorphous silicon material layer covering the surface of the processing area;

[0029] A second tunneling oxide material layer, a second intrinsic amorphous silicon material layer and a second doped amorphous silicon material layer are sequentially stacked in the processing area.

[0030] In one embodiment, each processing region includes a second region and an isolation region connected to each other, and an isolation region is provided between adjacent first regions and second regions; and after the annealing step, the following step is further included:

[0031] The structural layer covering the isolation area is removed so that the first doped polysilicon material layer forms a first doped polysilicon layer, the third doped polysilicon material layer forms a third doped polysilicon layer, the second doped polysilicon material layer forms a second doped polysilicon layer, and the fourth doped polysilicon material layer forms a fourth doped polysilicon layer.

[0032] In one embodiment, after the step of removing the structural layer covering the isolation area, the step further includes:

[0033] removing an oxide material layer generated during the annealing process on the side surface of the substrate and on the surface of a second side of the substrate, the second side being the opposite side to the first side;

[0034] forming a second passivation layer on the surface of the second side of the substrate, and forming a first passivation layer on the entire surface of the first side of the substrate;

[0035] A second anti-reflection layer and a first anti-reflection layer are respectively formed on the surfaces of the second passivation layer and the first passivation layer facing away from the substrate.

[0036] A third aspect of an embodiment of the present application provides a photovoltaic assembly, comprising at least one battery string, wherein the battery string comprises at least two of the above-mentioned solar cells.

[0037] The above-mentioned solar cell and its manufacturing method, photovoltaic module have the following beneficial effects:

[0038] Since the second doped polysilicon layer is doped with carbon, the reaction temperature required for crystallization of the second doped polysilicon layer is increased to the same as the reaction temperature of the first doped polysilicon layer. Therefore, the first doped polysilicon layer and the second doped polysilicon layer can be crystallized simultaneously in the same process. Under the same reaction conditions, the diffusion depth of the doped elements in the first doped polysilicon layer and the second doped polysilicon layer formed thereby is easy to be consistent, thereby improving the passivation performance of the solar cell. In addition, compared with the prior art that requires the first doped polysilicon layer and the second doped polysilicon layer to be crystallized separately, the number of processes can be saved and the cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG1 is a schematic diagram of the structure of a solar cell provided in an embodiment of the present application;

[0040] FIG2 is a schematic diagram of a process of manufacturing a solar cell provided in an embodiment of the present application;

[0041] 3 is a schematic diagram of forming a first tunneling oxide material layer, a first intrinsic amorphous silicon material layer and a first doped amorphous silicon material layer on a substrate in a method for manufacturing a solar cell provided in an embodiment of the present application;

[0042] FIG4 is a schematic structural diagram of removing a film layer on a processing area in a method for manufacturing a solar cell provided in an embodiment of the present application;

[0043] FIG5 is a schematic diagram of the structure of a substrate in a method for manufacturing a solar cell provided in an embodiment of the present application;

[0044] FIG6 is a schematic structural diagram of a substrate after annealing treatment in a method for manufacturing a solar cell provided in an embodiment of the present application;

[0045] FIG. 7 is a schematic diagram of forming an insulating isolation trench in a method for manufacturing a solar cell provided in an embodiment of the present application.

[0046] Description of Figure Numbers:

[0047] 100, solar cell; 101, substrate; 102, insulating isolation groove;

[0048] 10. substrate; 20. first doped polysilicon layer; 21. first doped amorphous silicon material layer; 22. first doped polysilicon material layer; 30. third doped polysilicon layer; 31. first intrinsic amorphous silicon material layer; 32. third doped polysilicon material layer; 41. first tunneling oxide layer; 411. first tunneling oxide layer; 42. second tunneling oxide layer; 421. second tunneling oxide layer; 50. second doped polysilicon layer; 51. second doped amorphous silicon material layer; 52. second doped polysilicon material layer; 60. fourth doped polysilicon layer; 61. second intrinsic amorphous silicon material layer; 62. fourth doped polysilicon material layer; 71. first passivation layer; 72. second passivation layer; 81. first anti-reflection layer; 82. second anti-reflection layer; 91. first electrode; 92. second electrode;

[0049] F, first side; S, second side; Y, first area; R, second area; T, processing area; G, isolation area. DETAILED DESCRIPTION

[0050] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0051] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0052] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0053] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0054] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0055] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.

[0056] The solar cell and its manufacturing method of the embodiment of the present application are described below with reference to the accompanying drawings. It should be noted that the solar cell is a TBC cell as an example for description in the present application, and the solar cell can also be set as other types of cells according to actual needs, such as a back contact solar cell of a traditional structure and a HBC type solar cell. The case where the solar cell is of other types is similar to this and will not be repeated here.

[0057] FIG. 1 is a schematic diagram of the structure of a solar cell provided in an embodiment of the present application.

[0058] 1 , a solar cell 100 provided in an embodiment of the present application includes a substrate 10, a first doped polysilicon layer 20, and a second doped polysilicon layer 50. The solar cell 100 can be manufactured using the solar cell manufacturing method described below.

[0059] The substrate 10 includes first regions Y and second regions R alternately arranged on a first side F of the substrate 10 along a preset direction, and an isolation region G is further provided between adjacent first regions Y and second regions R. It can be understood that there are multiple first regions Y, isolation regions G, and second regions R on the substrate 10, and FIG1 only shows the structure of one group of adjacent first regions Y, isolation regions G, and second regions R. The structures of the remaining groups of first regions Y, isolation regions G, and second regions R are similar to this, and are not described in detail here.

[0060] The first doped polysilicon layer 20 is doped with P-type elements and disposed on a side of the first region Y away from the substrate 10 . The second doped polysilicon layer 50 is doped with N-type elements and carbon elements and disposed on a side of the second region R away from the substrate 10 .

[0061] An insulating isolation trench extending to the isolation region G of the substrate 10 is provided between the first doped polysilicon layer 20 and the second doped polysilicon layer 50 .

[0062] Since the second doped polysilicon layer 50 is doped with carbon, the reaction temperature required for crystallization of the second doped polysilicon layer 50 is increased to the same as the reaction temperature of the first doped polysilicon layer 20. Therefore, the first doped polysilicon layer 20 and the second doped polysilicon layer 50 can be crystallized simultaneously in the same process. When the reaction is carried out under the same reaction conditions in the same process, the diffusion depth of the doped elements in the first doped polysilicon layer 20 and the second doped polysilicon layer 50 formed is easy to be consistent, thereby improving the passivation performance of the solar cell 100. In addition, compared with the prior art in which the first doped polysilicon layer 20 and the second doped polysilicon layer 50 need to be crystallized separately, the number of processes can be saved and the cost can be reduced.

[0063] In the embodiment of the present application, the solar cell 100 further includes a first tunneling oxide layer 41 and a third doped polysilicon layer 30, the first tunneling oxide layer 41 and the third doped polysilicon layer 30 are located between the first region Y and the first doped polysilicon layer 20, and are sequentially stacked on the surface of the first region Y. The doping element of the third doped polysilicon layer 30 is the same as that of the first doped polysilicon layer 20, and the doping element concentration of the third doped polysilicon layer 30 is less than that of the first doped polysilicon layer 20.

[0064] Further, the solar cell 100 further includes a second tunneling oxide layer 42 and a fourth doped polysilicon layer 60. The second tunneling oxide layer 42 and the fourth doped polysilicon layer 60 are located between the second region R and the second doped polysilicon layer 50, and are sequentially stacked on the surface of the second region R. The doping element of the fourth doped polysilicon layer 60 is the same as that of the second doped polysilicon layer 50, and the doping element concentration of the fourth doped polysilicon layer 60 is less than that of the second doped polysilicon layer 50.

[0065] In this configuration, a high-low junction is formed between the first doped polysilicon layer 20 and the third doped polysilicon layer 30, and a high-low junction is also formed between the second doped polysilicon layer 50 and the fourth doped polysilicon layer 60, which can improve the recombination of carriers and the passivation performance of the solar cell 100. In addition, it can also reduce the negative impact of parasitic current on battery efficiency.

[0066] In a specific implementation, the first doped polysilicon layer 20 and the third doped polysilicon layer 30 may be doped with boron, and the second doped polysilicon layer 50 and the fourth doped polysilicon layer 60 may be doped with phosphorus.

[0067] In the embodiment of the present application, referring to FIG. 1 , the solar cell 100 further includes a first passivation layer 71 and a second passivation layer 72. The first passivation layer 71 is disposed on the surface of the first doped polysilicon layer 20 and the second doped polysilicon layer 50 away from the substrate 10, and the second passivation layer 72 is disposed on the surface of the second side S of the substrate 10. In addition, a portion of the first passivation layer 71 also covers the bottom wall of the insulating isolation trench 102 and the side trench wall of the insulating isolation trench 102 (not shown in the figure).

[0068] Furthermore, the solar cell 100 further includes a first antireflection layer 81 and a second antireflection layer 82. The first antireflection layer 81 is disposed on the surface of the first passivation layer 71 away from the substrate 10, and the second antireflection layer 82 is disposed on the surface of the second passivation layer 72 away from the substrate 10.

[0069] The solar cell further includes a first electrode 91 and a second electrode 92, which are arranged alternately and spaced apart from each other. The first electrode 91 is disposed on the first anti-reflection layer 81 at a position corresponding to the first doped polysilicon layer 20, and is in ohmic contact with the first doped polysilicon layer 20, and the second electrode 92 is disposed on the first anti-reflection layer 81 at a position corresponding to the second doped polysilicon layer 50, and is in ohmic contact with the second doped polysilicon layer 50.

[0070] A second aspect of an embodiment of the present application provides a method for manufacturing a solar cell. The method can be used to manufacture the solar cell 100 as described above.

[0071] Figure 2 is a schematic diagram of the process of the method for manufacturing a solar cell provided in an embodiment of the present application; Figure 3 is a schematic diagram of forming a first tunneling oxide material layer, a first intrinsic amorphous silicon material layer and a first doped amorphous silicon material layer on a substrate in the method for manufacturing a solar cell provided in an embodiment of the present application; Figure 4 is a schematic diagram of the structure of removing the film layer on the processing area in the method for manufacturing a solar cell provided in an embodiment of the present application; Figure 5 is a schematic diagram of the structure of a substrate in the method for manufacturing a solar cell provided in an embodiment of the present application; Figure 6 is a schematic diagram of the structure of the substrate after annealing treatment in the method for manufacturing a solar cell provided in an embodiment of the present application; Figure 7 is a schematic diagram of forming an insulating isolation groove in the method for manufacturing a solar cell provided in an embodiment of the present application.

[0072] 2, 5 and 6, the method for manufacturing a solar cell provided in an embodiment of the present application includes:

[0073] S10. Provide a substrate, the substrate comprising a substrate, a surface of a first side of the substrate comprising a first region and a processing region which are staggered and connected to each other along a preset direction, a first doped amorphous silicon material layer doped with a P-type element is formed on the first side of the first region, and a second doped amorphous silicon material layer doped with an N-type element is formed on the first side of the processing region.

[0074] S20, performing annealing treatment to form the first doped amorphous silicon material layer into a first doped polysilicon material layer, and to form the second doped amorphous silicon material layer into a second doped polysilicon material layer; wherein the second doped amorphous silicon material layer is doped with carbon element.

[0075] Since the second doped amorphous silicon material layer 51 is doped with carbon, the reaction temperature required for annealing the second doped amorphous silicon material layer 51 is increased to the same as the annealing temperature of the first doped amorphous silicon material layer 21. Therefore, the first doped amorphous silicon material layer 21 and the second doped amorphous silicon material layer 51 can be annealed simultaneously in the same process. Under the same annealing conditions, the diffusion depths of the first doped polycrystalline silicon material layer 22 and the second doped polycrystalline silicon material layer 52 formed thereby are easily kept consistent, thereby improving the passivation performance of the solar cell 100. In addition, compared with the prior art in which the first doped polycrystalline silicon layer 20 and the second doped polycrystalline silicon layer 50 need to be annealed separately, the number of processes can be saved and the cost can be reduced.

[0076] In addition, performing annealing to form the first doped amorphous silicon material layer 21 into the first doped polycrystalline silicon material layer 22 means activating the P-type element in the first doped amorphous silicon material layer 21 and crystallizing the amorphous silicon in the first doped amorphous silicon material layer 21 into polycrystalline silicon. Forming the second doped amorphous silicon material layer 51 into the second doped polycrystalline silicon material layer 52 means activating the N-type element in the second doped amorphous silicon material layer 51 and crystallizing the amorphous silicon in the second doped amorphous silicon material layer 51 into polycrystalline silicon.

[0077] Further, the second doped amorphous silicon material layer 51 is formed by the following steps:

[0078] The second doped amorphous silicon material layer 51 is formed by using reaction gas including carbon source and silicon source, wherein the gas flow ratio of carbon source to silicon source is greater than 0 and less than or equal to 1. Preferably, the gas flow ratio of carbon source to silicon source can be 0.4, 0.65, or 0.9.

[0079] Such configuration can reduce the annealing temperature of the second doped amorphous silicon material layer 51 to the same temperature as the first doped amorphous silicon material layer 21 .

[0080] In a specific implementation, the annealing temperature of the annealing treatment is 910°C-930°C.

[0081] Such a configuration enables both the first doped amorphous silicon material layer 21 and the second doped amorphous silicon material layer 51 to be well crystallized into polysilicon material layers, and the diffusion depth of the doping elements in each layer can also be kept consistent. In specific implementation, the annealing time can be 30 min-120 min, preferably 90 min.

[0082] In the embodiment of the present application, as shown in FIG. 5 , a first tunneling oxide material layer 411 and a first intrinsic amorphous silicon material layer 31 are sequentially disposed between the first region Y and the first doped amorphous silicon material layer 21. A second tunneling oxide material layer 421 and a second intrinsic amorphous silicon material layer 61 are sequentially disposed between the processed region T and the second doped amorphous silicon material layer 51.

[0083] Referring to FIG. 6 , the steps of annealing treatment specifically include:

[0084] Annealing treatment is performed to form the first doped amorphous silicon material layer 21 into the first doped polysilicon material layer 22 , and to diffuse the doping elements in the first doped amorphous silicon material layer 21 into the first intrinsic amorphous silicon material layer 31 , so that the first intrinsic amorphous silicon material layer 31 forms the third doped polysilicon material layer 32 .

[0085] The second doped amorphous silicon material layer 51 forms a second doped polysilicon material layer 52 , and the doping elements in the second doped amorphous silicon material layer 51 diffuse into the second intrinsic amorphous silicon material layer 61 , so that the second intrinsic amorphous silicon material layer 61 forms a fourth doped polysilicon material layer 62 .

[0086] Due to the difference in doping concentration between the first intrinsic amorphous silicon material layer 31 and the first doped amorphous silicon material layer 21 before annealing, the bottom first intrinsic amorphous silicon material layer 31 can isolate the first doped amorphous silicon material layer 21 from the first tunneling oxide material layer 411, prevent the diffusion of doped elements after the activation treatment of the first tunneling oxide material layer 411, and improve the passivation effect of the first tunneling oxide material layer 411. In addition, after annealing, the distribution of doped elements in the third doped polysilicon material layer 32 and the first doped polysilicon material layer 22 can be made more uniform, reduce contact resistivity, and improve battery conversion efficiency. The setting effect of the second intrinsic amorphous silicon material layer 61 and the second doped amorphous silicon material layer 51 is similar to this, and will not be repeated here.

[0087] In the embodiment of the present application, the doping concentration of the third doped polysilicon material layer 32 is less than the doping concentration of the first doped polysilicon material layer 22 , and the doping concentration of the fourth doped polysilicon material layer 62 is less than the doping concentration of the second doped polysilicon material layer 52 .

[0088] In this way, a high-low junction is formed between the first doped polysilicon material layer 22 and the third doped polysilicon material layer 32 , and a high-low junction is also formed between the second doped polysilicon material layer 52 and the fourth doped polysilicon material layer 62 , which can improve the recombination of carriers and improve the passivation performance of the solar cell 100 .

[0089] In the embodiment of the present application, in combination with FIG. 3 , FIG. 4 , and FIG. 5 , the step of providing the substrate 101 includes:

[0090] On the entire surface of the first side F of the substrate 10 , a first tunneling oxide material layer 411 , a first intrinsic amorphous silicon material layer 31 and a first doped amorphous silicon material layer 21 are sequentially stacked and formed.

[0091] The portions of the first tunneling oxide material layer 411 , the first intrinsic amorphous silicon material layer 31 and the first doped amorphous silicon material layer 21 covering the surface of the processing region T are removed, and the portions covering the surface of the first region Y are retained.

[0092] In the processing region T, a second tunneling oxide material layer 421 , a second intrinsic amorphous silicon material layer 61 and a second doped amorphous silicon material layer 51 are sequentially stacked and formed.

[0093] Of course, the step of sequentially stacking a second tunneling oxide material layer 421, a second intrinsic amorphous silicon material layer 61 and a second doped amorphous silicon material layer 51 in the processing area T may specifically include forming a second tunneling oxide material layer 421, a second intrinsic amorphous silicon material layer 61 and a second doped amorphous silicon material layer 51 on the first side of the structure described in FIG. 4 , and then using a mask to remove the second tunneling oxide material layer 421, the second intrinsic amorphous silicon material layer 61 and the second doped amorphous silicon material layer 51 covering the first area Y, and retaining the second tunneling oxide material layer 421, the second intrinsic amorphous silicon material layer 61 and the second doped amorphous silicon material layer 51 covering the processing area T.

[0094] In the embodiment of the present application, in combination with FIG. 1 , FIG. 6 , and FIG. 7 , each processing region T includes a second region R and an isolation region G connected to each other, and an isolation region G is provided between adjacent first regions Y and second regions R. After the annealing step, the following steps are further included:

[0095] The structural layer covering the isolation region G is removed so that the first doped polysilicon material layer 22 forms a first doped polysilicon layer 20, the third doped polysilicon material layer 32 forms a third doped polysilicon layer 30, the second doped polysilicon material layer 52 forms a second doped polysilicon layer 50, and the fourth doped polysilicon material layer 62 forms a fourth doped polysilicon layer 60.

[0096] Further, referring to FIG. 1 and FIG. 7 , after the step of removing the structural layer covering the partial area adjacent to the first area Y on the processing area T, the method further includes:

[0097] The oxide material layer generated on the side surface of the substrate 10 and the surface of the second side S of the substrate 10 during the annealing process is removed, and the second side S is opposite to the first side F.

[0098] The second passivation layer 72 is formed on the surface of the second side S of the substrate 10 , and the first passivation layer 71 is formed on the entire surface of the first side F of the substrate 10 .

[0099] A second anti-reflection layer 82 and a first anti-reflection layer 81 are formed on surfaces of the second passivation layer 72 and the first passivation layer 71 facing away from the substrate 10 , respectively.

[0100] The method for manufacturing a solar cell according to an embodiment of the present application is described below with reference to examples intended to be specific.

[0101] The method includes:

[0102] Step 1: Select an N-type silicon wafer as the substrate 10 and perform double-sided polishing to remove the damaged layer. The used chemical solution includes deionized water, KOH and polishing additives.

[0103] Step 2, referring to Figure 3, the substrate 10 processed in step 1 is cleaned and then placed in PECVD to deposit a first tunneling oxide material layer 411, a first intrinsic amorphous silicon material layer 31, and a first doped amorphous silicon material layer 21 on the surface of the first side F of the substrate 10 in sequence.

[0104] Step 3, referring to Figure 4, after step 2, a green outer picosecond laser is used to perform film opening treatment to remove the first tunneling oxide material layer 411, the first intrinsic amorphous silicon material layer 31 and the first doped amorphous silicon material layer 21 covering the surface of the processing area T, and retain the portion covering the surface of the first area Y.

[0105] Step 4, referring to FIG. 5 , after polishing and cleaning the structure processed in step 4, it is put into PECVD again to deposit a second tunneling oxide material layer 421 , a second intrinsic amorphous silicon material layer 61 and a second doped amorphous silicon material layer 51 on the processing area T.

[0106] Step 5, referring to FIG. 6, the structure treated in step 4 is placed in an annealing furnace for high-temperature annealing (annealing temperature is 910°C-930°C), so that the first doped amorphous silicon material layer 21 is crystallized, and the boron impurities therein are activated and diffused into the first intrinsic amorphous silicon material layer 31, so that the first doped amorphous silicon material layer 21 is formed into a first doped polysilicon material layer 22, and the first intrinsic amorphous silicon material layer 31 is formed into a third doped polysilicon material layer 32, so that the first doped polysilicon material layer 22 and the third doped polysilicon material layer 32 form a high-low junction. At the same time, the second doped amorphous silicon material layer 51 is crystallized, and the phosphorus impurities therein are activated and diffused into the second intrinsic amorphous silicon material layer 61, so that the second doped amorphous silicon material layer 51 is formed into a second doped polysilicon material layer 52, and the second intrinsic amorphous silicon material layer 61 is formed into a fourth doped polysilicon material layer 62, so that the second doped polysilicon material layer 52 and the fourth doped polysilicon material layer 62 form a high-low junction.

[0107] Step 6, referring to FIG. 7 , after step 5, a green picosecond laser is used to perform a film opening process on the isolation region G at the junction of the first region Y and the second region R to form an insulating isolation groove 102 as a non-diffusion region.

[0108] Step 7. After the processing in step 6, the second side S of the substrate 10 is placed in a chain cleaning machine to remove the SiO2 layer on the surface and side of the second side S of the substrate 10. It is further placed in a slot machine for cleaning and texturing to form a velvet structure on the surface of the second side S of the silicon wafer. At the same time, the bottom wall of the insulating isolation groove 102 on the surface of the first side F of the substrate 10 is also texturized, and then RCA cleaning is performed after texturing.

[0109] Step 8: Place the structure after step 7 into an ALD device, form an AlOx layer as the second passivation layer 72 and the first passivation layer 71 on the second side S and the first side F of the substrate 10, respectively, and perform an annealing process.

[0110] Step 9: After step 8, SiNx layers are deposited on the second passivation layer 72 and the first passivation layer 71 as the second anti-reflection layer 82 and the first anti-reflection layer 81 respectively.

[0111] Step 10: After step 9, silver paste is printed at positions of the first anti-reflection layer 81 corresponding to the first doped polysilicon layer 20 and the second doped polysilicon layer 50, and then sintered to form a first electrode 91 and a second electrode 92 made of silver.

[0112] The third aspect of the embodiment of the present application further provides a photovoltaic module, comprising at least one battery string, wherein the battery string comprises at least two aforementioned solar cells 100. The solar cells 100 can be connected together by serial welding.

[0113] A fourth aspect of the embodiments of the present application further provides a photovoltaic system, comprising the above-mentioned photovoltaic component.

[0114] Photovoltaic systems can be used in photovoltaic power stations, such as ground power stations, rooftop power stations, water power stations, etc., and can also be used in equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it is understandable that the application scenarios of photovoltaic systems are not limited to this, that is to say, photovoltaic systems can be used in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.

[0115] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A solar cell, characterized in that: include: A substrate, comprising a first region and a second region alternately arranged on a first side of the substrate along a preset direction, and an isolation region is further provided between adjacent first regions and second regions; and a first doped polysilicon layer and a second doped polysilicon layer, wherein the first doped polysilicon layer is doped with a P-type element and is disposed on a side of the first region away from the substrate, and the second doped polysilicon layer is doped with an N-type element and a carbon element and is disposed on a side of the second region away from the substrate; An insulating isolation trench extending to an isolation region of the substrate is provided between the first doped polysilicon layer and the second doped polysilicon layer.

2. The solar cell according to claim 1, characterized in that The solar cell further comprises: A first tunneling oxide layer and a third doped polysilicon layer are located between the first region and the first doped polysilicon layer, and are sequentially stacked on the surface of the first region; the doping element of the third doped polysilicon layer is the same as that of the first doped polysilicon layer, and the doping element concentration of the third doped polysilicon layer is less than that of the first doped polysilicon layer; and / or The solar cell further comprises: A second tunneling oxide layer and a fourth doped polysilicon layer are located between the second region and the second doped polysilicon layer, and are sequentially stacked on the surface of the second region; the doping element of the fourth doped polysilicon layer is the same as that of the second doped polysilicon layer, and the doping element concentration of the fourth doped polysilicon layer is less than that of the second doped polysilicon layer.

3. The solar cell according to claim 1 or 2, characterized in that: The solar cell further comprises a first passivation layer and a second passivation layer. The first passivation layer is disposed on surfaces of the first doped polysilicon layer and the second doped polysilicon layer away from the substrate. The second passivation layer is disposed on a surface of a second side of the substrate.

4. A method for manufacturing a solar cell, characterized in that: include: A substrate is provided, the substrate comprising a substrate, a surface of a first side of the substrate comprising first regions and a processing region which are staggered and connected to each other along a preset direction, a first doped amorphous silicon material layer doped with a P-type element is formed on the first side of the first region, and a second doped amorphous silicon material layer doped with an N-type element is formed on the first side of the processing region; Performing annealing treatment to form the first doped amorphous silicon material layer into a first doped polysilicon material layer, and to form the second doped amorphous silicon material layer into a second doped polysilicon material layer; Wherein, the second doped amorphous silicon material layer is doped with carbon element.

5. The method for manufacturing a solar cell according to claim 4, characterized in that: The second doped amorphous silicon material layer is formed by the following steps: forming the second doped amorphous silicon material layer using a reaction gas including a carbon source and a silicon source; The gas flow ratio of the carbon source to the silicon source is greater than 0 and less than or equal to 1.

6. The method for manufacturing a solar cell according to claim 4, characterized in that: The annealing temperature of the annealing treatment is 910°C-930°C.

7. The method for manufacturing a solar cell according to claim 6, characterized in that: A first tunneling oxide material layer and a first intrinsic amorphous silicon material layer are sequentially provided between the first region and the first doped amorphous silicon material layer; a second tunneling oxide material layer and a second intrinsic amorphous silicon material layer are sequentially provided between the processing region and the second doped amorphous silicon material layer; The step of performing annealing treatment specifically includes: Performing annealing treatment to form the first doped amorphous silicon material layer into a first doped polysilicon material layer, and diffusing the doping element in the first doped amorphous silicon material layer into the first intrinsic amorphous silicon material layer, so that the first intrinsic amorphous silicon material layer forms a third doped polysilicon material layer; The second doped amorphous silicon material layer is formed into a second doped polysilicon material layer, and the doping elements in the second doped amorphous silicon material layer are diffused into the second intrinsic amorphous silicon material layer, so that the second intrinsic amorphous silicon material layer is formed into a fourth doped polysilicon material layer.

8. The method for manufacturing a solar cell according to claim 7, characterized in that: The doping concentration of the third doped polysilicon material layer is less than the doping concentration of the first doped polysilicon material layer, and the doping concentration of the fourth doped polysilicon material layer is less than the doping concentration of the second doped polysilicon material layer.

9. The method for manufacturing a solar cell according to claim 7, characterized in that: The step of providing a substrate comprises: On the entire surface of the first side of the substrate, a first tunneling oxide material layer, a first intrinsic amorphous silicon material layer and a first doped amorphous silicon material layer are sequentially stacked; removing the first tunneling oxide material layer, the first intrinsic amorphous silicon material layer and the first doped amorphous silicon material layer covering the surface of the processing area; A second tunneling oxide material layer, a second intrinsic amorphous silicon material layer and a second doped amorphous silicon material layer are sequentially stacked in the processing area.

10. The method for manufacturing a solar cell according to claim 9, characterized in that: Each of the processing areas comprises a second area and an isolation area connected to each other, and an isolation area is provided between adjacent first areas and second areas; The step of performing annealing treatment further comprises: The structural layer covering the isolation area is removed so that the first doped polysilicon material layer forms a first doped polysilicon layer, the third doped polysilicon material layer forms a third doped polysilicon layer, the second doped polysilicon material layer forms a second doped polysilicon layer, and the fourth doped polysilicon material layer forms a fourth doped polysilicon layer.

11. The method for manufacturing a solar cell according to claim 10, characterized in that: After the step of removing the structural layer covering the isolation area, the step further includes: removing an oxide material layer generated on a side surface of the substrate and a surface of a second side of the substrate during the annealing process, the second side being an opposite side to the first side; forming a second passivation layer on the surface of the second side of the substrate, and forming a first passivation layer on the entire surface of the first side of the substrate; A second anti-reflection layer and a first anti-reflection layer are respectively formed on surfaces of the second passivation layer and the first passivation layer facing away from the substrate.

12. A photovoltaic module, characterized in that: The invention comprises at least one battery string, wherein the battery string comprises at least two solar cells according to any one of claims 1 to 3.

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