Selective Poly-Si passivation contact TOPCon battery and preparation process

Abstract

The invention relates to the field of photovoltaic technology, and discloses a selective Poly-Si passivation contact TOPCon cell and a preparation process thereof, the selective Poly-Si passivation contact TOPCon cell comprises a polycrystalline silicon Poly-Si layer deposited on the back of the cell, and the polycrystalline silicon Poly-Si layer comprises a polycrystalline silicon thin layer area and a polycrystalline silicon thick layer area; the polycrystalline silicon thick layer area is located in a grid line electrode area, and the thickness is larger than 100 nm. The polycrystalline silicon thin layer area is located in a non-grid line electrode area, and the thickness of the polycrystalline silicon thin layer area is smaller than 95 nm. According to the method, the amorphous silicon film layer larger than 100 nm is deposited on the whole area of the back face of the TOPCon cell, then the non-grid line electrode area is thinned through the laser technology, the thickness of the prepared amorphous silicon film layer grid line electrode area is larger than 100 nm, the thickness of the non-grid line electrode area is smaller than 95 nm, the problem that paste on the back face of the printed and sintered electrode area is burnt through can be solved, and the production efficiency is improved. And meanwhile, the amorphous silicon film layer in the non-electrode region is thinned, so that the near-infrared light absorption of the doped amorphous silicon layer is reduced, and the problem of large parasitic absorption of the amorphous silicon film layer in the large-area non-electrode light receiving region is solved.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a TOPCon cell with selective Poly-Si passivation contact and a preparation process thereof. Background Art

[0002] The crystalline silicon TOPCon cell is a tunneling oxide passivation contact solar cell technology based on the principle of selective carriers. Its cell structure mainly uses n-type silicon as the substrate cell, prepares an ultra-thin silicon oxide layer on the back surface of the cell, and then deposits a phosphorus-doped amorphous silicon film. The two together form a passivation contact structure, in which the phosphorus-doped amorphous silicon layer provides a good field passivation effect and selectively passes through carriers, which plays a vital role in improving the open circuit voltage, short circuit current and fill factor of the cell. However, the doped amorphous silicon layer absorbs near-infrared light, reduces the effective reflection of near-infrared light on the back surface of the cell, and causes light loss on the back surface. The thicker the film, the greater the light loss. Therefore, considering the comprehensive consideration of cell efficiency and manufacturing cost, the low-thickness selective phosphorus-doped amorphous silicon layer is undoubtedly the best choice for the back contact passivation structure of the TOPCon cell.

[0003] However, due to the characteristics of the existing back-side paste, the thickness of the doped amorphous silicon of the TOPCon battery currently prepared by the LPCVD (low-pressure chemical vapor deposition) and PVD (physical vapor deposition) methods needs to be above 100nm to avoid burn-through. During printing and sintering, the auxiliary additives in the silver paste must be sintered at high temperature to contact the doped amorphous silicon layer and conduct current. The low-thickness doped amorphous silicon layer is easily burned through by the paste, thereby destroying the battery structure and deteriorating its passivation characteristics. For this reason, if the paste is adjusted to reduce the content of auxiliary additives in the silver paste, its burn-through performance will decrease while causing a significant increase in contact resistance, which will have an adverse effect on the battery's power generation performance.

[0004] In view of this, this application is hereby filed. Summary of the invention

[0005] The problem in the prior art is that a doped amorphous silicon layer with a low film thickness is very easy to be burned through by the slurry, thereby destroying the battery structure and deteriorating its passivation characteristics, while a thicker amorphous silicon layer will cause a large light loss. The present invention provides a TOPCon battery with selective Poly-Si passivation contact and a preparation process. By depositing an amorphous silicon film layer with a thickness of more than 100nm on the entire area of ​​the back of the TOPCon battery, and then thinning it in the non-gate electrode area with the help of a laser process, a selective poly-Si passivation contact layer with different film thicknesses is obtained, in which the thickness of the amorphous silicon film layer in the gate electrode area is more than 100nm and the thickness of the non-gate electrode area is less than 95nm. This can not only avoid the problem of the slurry burning through the back of the electrode area after printing and sintering, but also the amorphous silicon film layer in the non-electrode area is thinned, thereby reducing the absorption of near-infrared light by the doped amorphous silicon layer, and solving the problem of large parasitic absorption of the amorphous silicon film layer in the large non-electrode light-receiving area.

[0006] The present invention is achieved through the following technical solutions:

[0007] In a first aspect, the present invention provides a TOPCon cell with selective Poly-Si passivation contact, comprising a polycrystalline silicon Poly-Si layer deposited on the back of the cell, wherein the polycrystalline silicon Poly-Si layer comprises a polycrystalline silicon thin layer region and a polycrystalline silicon thick layer region;

[0008] The polysilicon thick layer region is located in the gate line electrode region, and has a thickness of more than 100 nm;

[0009] The polysilicon thin layer region is located in the non-gate line electrode region and has a thickness of less than 95 nm.

[0010] In a specific implementation, the distance between two adjacent polysilicon thick layer regions is 0.05-1 mm.

[0011] In a specific embodiment, it includes a 0.3-2.0 nm ultra-thin oxide layer, a 30-60 nm thin polysilicon layer, a 0.3-1 nm ultra-thin oxide layer, and a 90-120 nm thick polysilicon layer sequentially deposited on the back of the cell;

[0012] The thick polysilicon layer and the gate line electrode corresponding to each other form a polysilicon thick layer area;

[0013] The thickness of the thick polysilicon layer is reduced at a location corresponding to the non-gate line electrode, and together with the thin polysilicon layer, the thick polysilicon layer forms a polysilicon thin layer region.

[0014] In a specific embodiment, it includes a front electrode, a front passivation, an anti-reflection film, an N-type substrate, a tunneling oxide layer, a back selective polysilicon Poly-Si layer, a back anti-reflection film and a back electrode.

[0015] In a second aspect, the present invention provides a method for preparing a TOPCon cell with selective Poly-Si passivation contact, characterized in that the preparation method of the polycrystalline silicon Poly-Si layer is as follows:

[0016] A 100-200nm polysilicon layer is deposited on the back of the battery, and a laser is used to scan and thin the polysilicon layer in the non-gate electrode area to a thickness of less than 95nm.

[0017] In a specific embodiment, the scanning method is to perform pulsed laser bombardment on the non-electrode area of ​​the polysilicon layer, wherein the laser wavelength is 532nm, the spot size is 80-120nm square, the scanning speed is 10000mm / s, and the frequency is 10kHz.

[0018] In a specific embodiment, the preparation method of the TOPCon cell with selective Poly-Si passivation contact is as follows:

[0019] (1) De-damage, surface texturing and cleaning of the N-type silicon substrate;

[0020] (2) forming a light and heavy boron emitter on the front side of the N-type silicon wafer;

[0021] (3) Complete BSG removal cleaning and alkaline polishing on the back side of N-type silicon;

[0022] (4) depositing an ultra-thin oxide layer and polysilicon layer on the back of the cell;

[0023] (5) Selective poly-Si layer preparation, using laser to scan and thin the non-electrode area on the back of the battery to obtain a polycrystalline silicon Poly-Si layer;

[0024] (6) De-poly plating and cleaning;

[0025] (7) Preparation of front passivation, anti-reflection film and back passivation film;

[0026] (8) Electrode preparation;

[0027] (9) The heating sintering process and light injection are completed in the sintering furnace.

[0028] In a third aspect, the present invention provides a method for preparing a TOPCon cell with selective Poly-Si passivation contact, wherein the method for preparing the polycrystalline silicon Poly-Si layer is as follows:

[0029] On the back of the cell, a stack of layers is first deposited, including an ultra-thin oxide layer of 0.3-2.0nm and a thin polysilicon layer of 30-60nm;

[0030] A second stack of layers is deposited on the back of the cell, again, consisting of an ultra-thin oxide layer of 0.3-1nm and a thick polysilicon layer of 90-120nm;

[0031] The laser is used to scan and thin the thick polysilicon layer in the non-gate line electrode area until the total thickness of the thin polysilicon layer is less than 95nm.

[0032] In a specific embodiment, the scanning method is to perform pulsed laser bombardment on the non-electrode area of ​​the thick polysilicon layer, wherein the laser wavelength is 532nm, the spot size is 80-120nm square, the scanning speed is 10000mm / s, and the frequency is 10kHz.

[0033] In a specific embodiment, the preparation method of the TOPCon cell with selective Poly-Si passivation contact is as follows:

[0034] (1) De-damage, surface texturing and cleaning of the N-type silicon substrate;

[0035] (2) forming a light and heavy boron emitter on the front side of the N-type silicon wafer;

[0036] (3) Complete BSG removal cleaning and alkaline polishing on the back side of N-type silicon;

[0037] (4) depositing a stacking layer on the back of the battery, comprising an ultra-thin oxide layer of 0.3-2.0 nm and a polysilicon layer of 30-60 nm; then depositing a second stacking layer on the back of the battery, comprising an ultra-thin oxide layer of 0.3-1 nm and a thick polysilicon layer of 90-120 nm;

[0038] (5) Selective poly-Si layer preparation, using laser scanning to thin the non-electrode area of ​​the thick poly-Si layer on the back of the cell;

[0039] (6) De-poly plating and cleaning;

[0040] (7) Preparation of front passivation and anti-reflection film and back passivation film;

[0041] (8) Electrode preparation;

[0042] (9) The heating sintering process and light injection are completed in the sintering furnace.

[0043] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0044] A TOPCon cell with selective Poly-Si passivation contact and a preparation process provided by an embodiment of the present invention deposits an amorphous silicon film layer with a thickness of >100nm on the entire back side of the TOPCon cell, and then thins it in the non-gate electrode area with the aid of a laser process, so as to obtain a selective poly-Si passivation contact layer with different film thicknesses, wherein the thickness of the amorphous silicon film layer in the gate electrode area is >100nm, and the thickness of the non-gate electrode area is <95nm. This not only avoids the problem of slurry burn-through on the back side of the electrode area after printing and sintering, but also thins the amorphous silicon film layer in the non-electrode area, reduces the absorption of near-infrared light by the doped amorphous silicon layer, and solves the problem of large parasitic absorption of the amorphous silicon film layer in the large non-electrode light-receiving area. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 Schematic diagram of the TOPCon cell structure with selective Poly-Si passivated contact provided in an embodiment of the present invention.

[0047] Reference numerals and component names:

[0048] 1-N-type base silicon wafer, 2-boron-doped emitter layer, 3-ultra-thin oxide layer, 4-polycrystalline silicon thin layer area, 5-polycrystalline silicon thick layer area, 6-aluminum oxide layer, 7-silicon nitride layer, 8-metal electrode. DETAILED DESCRIPTION

[0049] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0050] In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it is apparent to one of ordinary skill in the art that these specific details need not be employed to practice the present invention. In other embodiments, in order to avoid obscuring the present invention, well-known materials or methods are not specifically described.

[0051] Throughout the specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "one embodiment," "an embodiment," "an example," or "an example" appearing in various places throughout the specification do not necessarily all refer to the same embodiment or example. In addition, particular features, structures, or characteristics may be combined in one or more embodiments or examples in any suitable combination and / or subcombination. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0052] The thin-film-thick doped amorphous silicon layer is easily burned through by the slurry, thus destroying the cell structure and deteriorating its passivation characteristics. The thicker amorphous silicon layer will cause greater light loss. In order to solve the above problems:

[0053] First, as Figure 1 As shown, in the first aspect, the present invention provides a TOPCon cell with selective Poly-Si passivation contact, comprising a polycrystalline silicon Poly-Si layer deposited on the back of the cell, wherein the polycrystalline silicon Poly-Si layer comprises a polycrystalline silicon thin layer region and a polycrystalline silicon thick layer region;

[0054] The polysilicon thick layer region is located in the gate line electrode region, and has a thickness of more than 100 nm;

[0055] The polysilicon thin layer region is located in the non-gate line electrode region and has a thickness of less than 95 nm.

[0056] In a specific implementation, the distance between two adjacent polysilicon thick layer regions is 0.05-1 mm.

[0057] In a specific embodiment, it includes a 0.3-2.0 nm ultra-thin oxide layer, a 30-60 nm thin polysilicon layer, a 0.3-1 nm ultra-thin oxide layer, and a 90-120 nm thick polysilicon layer sequentially deposited on the back of the cell;

[0058] The thick polysilicon layer and the gate line electrode corresponding to each other form a polysilicon thick layer area;

[0059] The thickness of the thick polysilicon layer is reduced at a location corresponding to the non-gate line electrode, and together with the thin polysilicon layer, the thick polysilicon layer forms a polysilicon thin layer region.

[0060] In a specific embodiment, it includes a front electrode, a front passivation, an anti-reflection film, an N-type substrate, a tunneling oxide layer, a back selective polysilicon Poly-Si layer, a back anti-reflection film and a back electrode.

[0061] In a second aspect, the present invention provides a method for preparing a TOPCon cell with selective Poly-Si passivation contact, characterized in that the preparation method of the polycrystalline silicon Poly-Si layer is as follows:

[0062] A 100-200nm polysilicon layer is deposited on the back of the battery, and a laser is used to scan and thin the polysilicon layer in the non-gate electrode area to a thickness of less than 95nm.

[0063] In a specific embodiment, the scanning method is to perform pulsed laser bombardment on the non-electrode area of ​​the polysilicon layer, wherein the laser wavelength is 532nm, the spot size is 80-120nm square, the scanning speed is 10000mm / s, and the frequency is 10kHz.

[0064] In a specific embodiment, the preparation method of the TOPCon cell with selective Poly-Si passivation contact is as follows:

[0065] (1) De-damage, surface texturing and cleaning of the N-type silicon substrate;

[0066] (2) forming a light and heavy boron emitter on the front side of the N-type silicon wafer;

[0067] (3) Complete BSG removal cleaning and alkaline polishing on the back side of N-type silicon;

[0068] (4) depositing an ultra-thin oxide layer and polysilicon layer on the back of the cell;

[0069] (5) Selective poly-Si layer preparation, using laser to scan and thin the non-electrode area on the back of the battery to obtain a polycrystalline silicon Poly-Si layer;

[0070] (6) De-poly plating and cleaning;

[0071] (7) Preparation of front passivation, anti-reflection film and back passivation film;

[0072] (8) Electrode preparation;

[0073] (9) The heating sintering process and light injection are completed in the sintering furnace.

[0074] In a third aspect, the present invention provides a method for preparing a TOPCon cell with selective Poly-Si passivation contact, wherein the method for preparing the polycrystalline silicon Poly-Si layer is as follows:

[0075] On the back of the cell, a stack of layers is first deposited, including an ultra-thin oxide layer of 0.3-2.0nm and a thin polysilicon layer of 30-60nm;

[0076] A second stack of layers is deposited on the back of the cell, again, consisting of an ultra-thin oxide layer of 0.3-1nm and a thick polysilicon layer of 90-120nm;

[0077] The laser is used to scan and thin the thick polysilicon layer in the non-gate line electrode area until the total thickness of the thin polysilicon layer is less than 95nm.

[0078] In a specific embodiment, the scanning method is to perform pulsed laser bombardment on the non-electrode area of ​​the thick polysilicon layer, wherein the laser wavelength is 532nm, the spot size is 80-120nm square, the scanning speed is 10000mm / s, and the frequency is 10kHz.

[0079] In a specific embodiment, the preparation method of the TOPCon cell with selective Poly-Si passivation contact is as follows:

[0080] (1) De-damage, surface texturing and cleaning of the N-type silicon substrate;

[0081] (2) forming a light and heavy boron emitter on the front side of the N-type silicon wafer;

[0082] (3) Complete BSG removal cleaning and alkaline polishing on the back side of N-type silicon;

[0083] (4) depositing a stacking layer on the back of the battery, comprising an ultra-thin oxide layer of 0.3-2.0 nm and a polysilicon layer of 30-60 nm; then depositing a second stacking layer on the back of the battery, comprising an ultra-thin oxide layer of 0.3-1 nm and a thick polysilicon layer of 90-120 nm;

[0084] (5) Selective poly-Si layer preparation, using laser scanning to thin the non-electrode area of ​​the thick poly-Si layer on the back of the cell;

[0085] (6) De-poly plating and cleaning;

[0086] (7) Preparation of front passivation and anti-reflection film and back passivation film;

[0087] (8) Electrode preparation;

[0088] (9) The heating sintering process and light injection are completed in the sintering furnace.

[0089] Example 1

[0090] The embodiment of the present invention provides a method for preparing a TOPCon cell with selective Poly-Si passivation contact, comprising the following steps:

[0091] (1) De-damage, surface texturing and cleaning of N-type silicon substrate:

[0092] Taking N-type single crystal silicon as the battery substrate, a 60℃ solution containing KOH and H2O2 is used for damage removal treatment, and a solution containing KOH and texturing auxiliary additives is used at 80℃ for surface texturing to form a pyramid velvet surface with a pyramid scale of 2-5um. It is then cleaned with a mixed solution of hydrofluoric acid and hydrochloric acid, cleaned with deionized water and dried.

[0093] (2) Forming light and heavy boron emitters on the front side of the N-type silicon wafer:

[0094] BCl3 and O2 are introduced into a tubular boron diffusion furnace. Under the conditions of 1040°C and low pressure, boron deposition is completed first, then selective doping is performed through laser, and finally oxidation advancement is completed to form lightly and heavily boron-doped emitters with 100-250 emitters.

[0095] (3) Complete BSG removal cleaning and alkaline polishing on the back of N-type silicon:

[0096] The BSG removal was completed in a chain device with a belt speed of 4.0 m / min and a mixed solution of HF and water with a concentration of 2%-10%.

[0097] (4) Using the LPCVD method or the PVD method, a 0.3-2 nm ultra-thin oxide layer and a 100-200 nm polysilicon layer are deposited on the back of the battery. Doping or activation annealing is performed in a tubular diffusion furnace at 800-920°C and low pressure to complete the doping of the poly-Si layer.

[0098] (5) Selective poly-Si layer preparation:

[0099] The non-electrode area on the back of the battery is scanned and thinned by laser. The scanning method is to perform pulsed laser bombardment on the non-electrode area. The scanning direction is along the electrode direction. The laser wavelength is 532nm, the spot size is 80-120nm square, the scanning speed is 10000mm / s, and the frequency is 10kHz. The poly-Si passivation film on the back is thinned in the area irradiated by the laser spot. Under this condition, in the non-electrode area on the back of the battery, the spacing between two adjacent laser irradiated line areas is 0.9mm, that is, on the strip non-electrode area, there is a strip irradiation area composed of multiple strip lines with a width of 80-120um every 0.9mm, and its width is generally 0.1-0.85mm.

[0100] (6) De-poly plating cleaning:

[0101] First, remove the PSG on one side in a 1%-5% HF mixture in a chain device, then remove the Poly-Si in a mixture of NaOH and auxiliary additives at 65°C, and finally use a mixed solution containing hydrofluoric acid and hydrochloric acid for cleaning, deionized water cleaning and drying.

[0102] (7) Preparation of front passivation and anti-reflection film and back passivation film:

[0103] Atomic layer deposition (ALD) is used to deposit a 5-10nm aluminum oxide layer on the front of the battery, and then silicon nitride is deposited on it with a thickness of 80nm and a refractive index of 2.03 to complete the preparation of the front passivation and anti-reflection film. Enhanced plasma chemical vapor deposition (PECVD) is used to deposit silicon nitride on the back of the battery with a thickness of 100nm and a refractive index of 2.10 to complete the back passivation.

[0104] (8) Electrode preparation: Ag electrodes are applied on the front and back sides of the battery by screen printing.

[0105] (9) Heating, sintering and light injection are completed in the sintering furnace:

[0106] The peak heating temperature is 600-800°C. The preferred peak heating temperature in this embodiment is 700°C. After this step, the battery preparation is completed. The positive electrode fine grid line passes through the passivation film and forms a contact with the N-type silicon substrate, and the negative electrode fine grid contacts the thick poly-Si passivation film area. Light injection repairs defects inside and on the surface of the battery.

[0107] Example 2

[0108] The embodiment of the present invention provides a method for preparing a TOPCon cell with selective Poly-Si passivation contact, comprising the following steps:

[0109] (1) De-damage, surface texturing and cleaning of N-type silicon substrate:

[0110] Taking N-type single crystal silicon as the battery substrate, a 60℃ solution containing KOH and H2O2 is used for damage removal treatment, and a solution containing KOH and texturing auxiliary additives is used at 80℃ for surface texturing to form a pyramid velvet surface with a pyramid scale of 2-5um. It is then cleaned with a mixed solution of hydrofluoric acid and hydrochloric acid, cleaned with deionized water and dried.

[0111] (2) Forming light and heavy boron emitters on the front side of the N-type silicon wafer:

[0112] BCl3 and O2 are introduced into a tubular boron diffusion furnace. Under the conditions of 1040°C and low pressure, boron deposition is completed first, then selective doping is performed through laser, and finally oxidation advancement is completed to form lightly and heavily boron-doped emitters with 100-250 emitters.

[0113] (3) Complete BSG removal cleaning and alkaline polishing on the back of N-type silicon:

[0114] The BSG removal was completed in a chain device with a belt speed of 4.0 m / min and a mixed solution of HF and water with a concentration of 2%-10%.

[0115] (4) Using LPCVD or PVD method, a stack layer is first deposited on the back of the battery, including a 0.3-2.0nm ultra-thin oxide layer and a 30-60nm polysilicon thin layer; then a second stack layer is deposited on the back of the battery again, including a 0.3-1nm ultra-thin oxide layer and a 90-120nm thick polysilicon layer. Finally, doping or activation annealing is completed at 800-920℃ and low pressure in a tubular diffusion furnace to complete the doping of the poly-Si layer.

[0116] (5) Selective poly-Si layer preparation:

[0117] The non-electrode area on the back of the battery is scanned and thinned by laser. The scanning method is to perform pulsed laser bombardment on the non-electrode area. The scanning direction is along the electrode direction. The laser wavelength is 532nm, the spot size is 80-120nm square, the scanning speed is 10000mm / s, and the frequency is 10kHz. The poly-Si passivation film on the back is thinned in the area irradiated by the laser spot. Under this condition, in the non-electrode area on the back of the battery, the spacing between two adjacent laser irradiated line areas is 0.9mm, that is, on the strip non-electrode area, there is a strip irradiation area composed of multiple strip lines with a width of 80-120um every 0.9mm, and its width is generally 0.1-0.85mm.

[0118] (6) De-poly plating cleaning:

[0119] First, remove the PSG on one side in a 1%-5% HF mixture in a chain device, then remove the Poly-Si in a mixture of NaOH and auxiliary additives at 65°C, and finally use a mixed solution containing hydrofluoric acid and hydrochloric acid for cleaning, deionized water cleaning and drying.

[0120] (7) Preparation of front passivation and anti-reflection film and back passivation film:

[0121] Atomic layer deposition (ALD) is used to deposit a 5-10nm aluminum oxide layer on the front of the battery, and then silicon nitride is deposited on it with a thickness of 80nm and a refractive index of 2.03 to complete the preparation of the front passivation and anti-reflection film. Enhanced plasma chemical vapor deposition (PECVD) is used to deposit silicon nitride on the back of the battery with a thickness of 100nm and a refractive index of 2.10 to complete the back passivation.

[0122] (8) Electrode preparation: Ag electrodes are applied on the front and back sides of the battery by screen printing.

[0123] (9) The heating sintering treatment and light injection are completed in the sintering furnace. The peak heating temperature is 600-800°C. The preferred peak heating treatment temperature in this embodiment is 700°C. After this step, the battery preparation is completed. The positive electrode fine grid line passes through the passivation film and forms a contact with the N-type silicon substrate, and the negative electrode fine grid contacts the thick poly-Si passivation film area. Light injection repairs defects inside and on the surface of the battery.

[0124] Comparative Example 1

[0125] This comparative example provides a method for preparing a TOPCon battery, comprising the following steps:

[0126] (1) De-damage, surface texturing and cleaning of N-type silicon substrate:

[0127] Taking N-type single crystal silicon as the battery substrate, a 60℃ solution containing KOH and H2O2 is used for damage removal treatment, and a solution containing KOH and texturing auxiliary additives is used at 80℃ for surface texturing to form a pyramid velvet surface with a pyramid scale of 2-5um. It is then cleaned with a mixed solution of hydrofluoric acid and hydrochloric acid, cleaned with deionized water and dried.

[0128] (2) Forming light and heavy boron emitters on the front side of the N-type silicon wafer:

[0129] BCl3 and O2 are introduced into a tubular boron diffusion furnace. Under the conditions of 1040°C and low pressure, boron deposition is completed first, then selective doping is performed through laser, and finally oxidation advancement is completed to form lightly and heavily boron-doped emitters with 100-250 emitters.

[0130] (3) Complete BSG removal cleaning and alkaline polishing on the back of N-type silicon:

[0131] The BSG removal was completed in a chain device with a belt speed of 4.0 m / min and a mixed solution of HF and water with a concentration of 2%-10%.

[0132] (4) Using the LPCVD method or the PVD method, a 0.3-2 nm ultra-thin oxide layer and a thick polysilicon layer (poly-Si) with a total thickness of 100-200 nm are deposited on the back of the battery. Doping or activation annealing is performed in a tubular diffusion furnace at 800-920°C and low pressure to complete the doping of the poly-Si layer.

[0133] (5) De-poly plating cleaning:

[0134] First, remove the PSG on one side in a 1%-5% HF mixture in a chain device, then remove the Poly-Si in a mixture of NaOH and auxiliary additives at 65°C, and finally use a mixed solution containing hydrofluoric acid and hydrochloric acid for cleaning, deionized water cleaning and drying.

[0135] (6) Preparation of front passivation and anti-reflection film and back passivation film:

[0136] Atomic layer deposition (ALD) is used to deposit a 5-10nm aluminum oxide layer on the front of the battery, and then silicon nitride is deposited on it with a thickness of 80nm and a refractive index of 2.03 to complete the preparation of the front passivation and anti-reflection film. Enhanced plasma chemical vapor deposition (PECVD) is used to deposit silicon nitride on the back of the battery with a thickness of 100nm and a refractive index of 2.10 to complete the back passivation.

[0137] (7) Electrode preparation: Ag electrodes are applied on the front and back sides of the battery by screen printing.

[0138] (8) Heating and sintering treatment is completed in a sintering furnace:

[0139] The peak heating temperature is 600-800°C. The preferred peak heating temperature in this comparative example is 700°C. After this step, the battery preparation is completed. The positive electrode fine grid line passes through the passivation film and forms a contact with the N-type silicon substrate, and the negative electrode fine grid and the thick poly-Si passivation film area.

[0140] Comparative Example 2

[0141] This comparative example provides a method for preparing a TOPCon battery, comprising the following steps:

[0142] (1) Texturing: Select phosphorus-doped N-type single-crystal silicon wafers with a resistivity of 1.0 Ωcm and a thickness of 160 um; use acid-base chemicals to remove organic contamination and metal impurities on the surface of the silicon wafer, form a surface texture on the surface of the silicon wafer, increase the absorption of sunlight and reduce reflection;

[0143] (2) Boron diffusion: BCl3 is diffused at low pressure to form a front PN junction, with a diffusion temperature of 1000°C and a square resistance of 200 ohm / sq.

[0144] (3) BSG: single-sided HF etching to remove the backside BSG;

[0145] (4) Backside etching: Use alkaline solution etching to remove the PN junction formed by parasitic diffusion on the back side to prevent edge leakage;

[0146] (5) LPCVD: LPCVD in-situ oxidation is used to generate a tunnel oxide layer at a temperature of 600°C with a thickness of 1.5 nm, and an intrinsic amorphous silicon layer with a thickness of 50 nm is deposited;

[0147] (6) Phosphorus diffusion: POCl3 is used as the diffusion source, and the diffusion temperature is 850°C to diffuse phosphorus into the back amorphous silicon, and transform it from an amorphous state to a crystalline state to form the first doped polysilicon layer with a doping concentration of 1e 20 cm-3 ;

[0148] (7) PSG: Single-sided HF etching to remove PSG on the front polysilicon surface after diffusion;

[0149] (8) Front etching: removing the plated polysilicon layer by etching with an alkaline solution, and removing the BSG on the front side and the PSG on the back side by cleaning with hydrofluoric acid;

[0150] (9) CVD mask: A layer of SiN is grown on the back side using chemical vapor deposition (CVD) X Mask; introduce appropriate amount of SiH4 and NH3, and after a series of chemical reactions and plasma reactions, a solid film (SiNx) is formed on the surface of the sample; its thickness is 20nm, preparing for the subsequent back-side Poly selective epitaxial deposition;

[0151] (10) LCO: Laser film opening is used to open the SiN layer under the back metal area. X The mask barrier layer is etched and grooved for the purpose of opening the SiNX mask layer to expose the polysilicon and prepare for the subsequent growth of the silicon epitaxial layer;

[0152] (11) HF cleaning: Since the LCO step uses laser film opening to open the SiN X mask layer, so on the back side of the groove

[0153] A thin silicon oxide layer is left on the surface of the first doped polysilicon layer below the metal region; the silicon oxide layer on the surface of the first doped polysilicon layer below the back metal region is removed by HF cleaning;

[0154] (12) Back-side Poly Selective Epitaxial Deposition: Epitaxial growth of silicon was achieved in a monolithic batch reactor by chemical vapor deposition (CVD). The process was carried out under reduced pressure (100 Torr) and at a temperature of 900°C. Dichlorosilane (SiH2Cl2) was used as the silicon source and hydrogen (H2) was used as the carrier gas. PH3 was used as the doping gas, and the growth layer was a phosphorus-doped second doped polysilicon layer with a doping concentration of 1e 21 cm -3 , with a thickness of 100nm; the epitaxial growth of silicon on the crystalline material is affected by the surface chemical potential, so the second doped polysilicon layer only grows on the bare silicon area, and the interface is SiN X No epitaxial deposition occurs on the back surface "covered" by the mask layer.

[0155] (13) Mask removal and cleaning: Since there is a SiNx mask layer on the back metal area, a wet chemical method is used to remove the SiNx mask layer on the surface of the silicon wafer and clean the surface of the silicon wafer;

[0156] (14) ALD: A dense AlOx film is deposited on the front side of the substrate by ALD atomic layer deposition;

[0157] (15) Front PECVD: Depositing a silicon oxynitride stacked film on the front side of the substrate by PECVD;

[0158] (16) Back PECVD: Depositing a silicon oxynitride stacked film on the back side of the substrate by PECVD;

[0159] (17) Printing / sintering / light injection: Print negative electrode Ag / Al paste on the front and electrode Ag paste on the back; co-sinter to form a good ohmic contact; light injection to repair defects inside and on the surface of the battery.

[0160] The batteries prepared in Examples 1-2 and Comparative Examples 1-2 were subjected to performance tests, and the results are shown in Table 1 below.

[0161] Table 1

[0162] Group Count Eta / % Uoc / V Isc / A FF / % Comparative Example 1 1996 26.218 0.7345 14.026 85.16 Comparative Example 2 426 25.07 0.721 13.89054 83.81 Example 1 1876 26.286 0.7342 14.073 85.13 Example 2 1930 26.309 0.7364 14.063 85.01

[0163] Comparing the TOPCon cells prepared above, it can be seen that the cell structure and preparation method provided by the present application are used in Example 1, which has the following advantages: (1) The selective poly-Si passivation contact structure used on the back of the N-type monocrystalline silicon wafer is an integral integrated structure, which includes a thick doped polysilicon layer located below the metal electrode and a thin doped amorphous silicon layer in the non-metallic electrode area. The thick polysilicon layer area can reduce the risk of metal slurry penetrating the tunneling layer during the sintering process, and at the same time can ensure that the metal contact area has a lower contact resistance and obtain a larger fill factor; while the thin polysilicon layer area has a thinner thickness, less parasitic absorption of light, and improves the short-circuit current of the battery; (2) Since the thick polysilicon layer and the thin polysilicon layer under the metal electrode on the back of the N-type silicon wafer are prepared under the same process conditions, the entire preparation method does not add additional process equipment, does not destroy or damage the thick polysilicon layer, and reduces the recombination of the metal contact area; (3) The preparation process of Example 1 is less, simpler, and the industrial mass production cost is lower.

[0164] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A TOPCon cell with selective Poly-Si passivated contact, characterized in that: The method comprises a polycrystalline silicon (Poly-Si) layer deposited on the back of the battery, wherein the polycrystalline silicon (Poly-Si) layer comprises a polycrystalline silicon thin layer region and a polycrystalline silicon thick layer region; The polysilicon thick layer region is located in the gate line electrode region, and has a thickness of more than 100 nm; The polysilicon thin layer region is located in the non-gate line electrode region and has a thickness of less than 95 nm.

2. A TOPCon cell with selective Poly-Si passivated contact according to claim 1, characterized in that: The distance between two adjacent polysilicon thick layer regions is 0.05 to 1 mm.

3. A TOPCon cell with selective Poly-Si passivated contact according to claim 1, characterized in that: It includes a 0.3-2.0nm ultra-thin oxide layer, a 30-60nm thin polysilicon layer, a 0.3-1nm ultra-thin oxide layer and a 90-120nm thick polysilicon layer deposited sequentially on the back of the cell; The thick polysilicon layer and the gate line electrode corresponding to each other form a polysilicon thick layer area; The thickness of the thick polysilicon layer is reduced at a location corresponding to the non-gate line electrode, and together with the thin polysilicon layer, the thick polysilicon layer forms a polysilicon thin layer region.

4. A TOPCon cell with selective Poly-Si passivated contact according to claim 1, characterized in that: It includes a front electrode, a front passivation, an anti-reflection film, an N-type substrate, a tunneling oxide layer, a back selective polysilicon Poly-Si layer, a back anti-reflection film and a back electrode.

5. A method for preparing a TOPCon cell with selective Poly-Si passivation contact, characterized in that: The method for preparing the polycrystalline silicon Poly-Si layer according to claim 1 or 2 is as follows: A 100-200nm polysilicon layer is deposited on the back of the battery, and a laser is used to scan and thin the polysilicon layer in the non-gate electrode area to a thickness of less than 95nm.

6. The method for preparing a TOPCon cell with selective Poly-Si passivation contact according to claim 5, characterized in that: The scanning method is to perform pulsed laser bombardment on the non-electrode area of ​​the polysilicon layer, wherein the laser wavelength is 532nm, the spot size is 80-120nm square, the scanning speed is 10000mm / s, and the frequency is 10kHz.

7. The method for preparing a TOPCon cell with selective Poly-Si passivation contact according to claim 5, characterized in that: The steps include: (1) De-damage, surface texturing and cleaning of the N-type silicon substrate; (2) forming a light and heavy boron emitter on the front side of the N-type silicon wafer; (3) Complete BSG removal cleaning and alkaline polishing on the back side of N-type silicon; (4) depositing an ultra-thin oxide layer and polysilicon layer on the back of the cell; (5) Selective poly-Si layer preparation, using laser to scan and thin the non-electrode area on the back of the battery to obtain a polycrystalline silicon Poly-Si layer; (6) De-poly plating and cleaning; (7) Preparation of front passivation, anti-reflection film and back passivation film; (8) Electrode preparation; (9) The heating sintering process and light injection are completed in the sintering furnace.

8. A method for preparing a TOPCon cell with selective Poly-Si passivation contact, characterized in that: The method for preparing the polycrystalline silicon Poly-Si layer according to claim 3 is as follows: On the back of the cell, a stack of layers is first deposited, including an ultra-thin oxide layer of 0.3-2.0nm and a thin polysilicon layer of 30-60nm; A second stack of layers is deposited on the back of the cell, again, consisting of an ultra-thin oxide layer of 0.3-1nm and a thick polysilicon layer of 90-120nm; The laser is used to scan and thin the thick polysilicon layer in the non-gate line electrode area until the total thickness of the thin polysilicon layer is less than 95nm.

9. A method for preparing a TOPCon cell with selective Poly-Si passivated contact according to claim 8, wherein the scanning method is to perform pulsed laser bombardment on the non-electrode area of ​​the thick polysilicon layer, wherein the laser wavelength is 532nm, the spot size is 80-120nm square, the scanning speed is 10000mm / s, and the frequency is 10kHz.

10. The method for preparing a TOPCon cell with selective Poly-Si passivation contact according to claim 8, characterized in that: The steps include: (1) De-damage, surface texturing and cleaning of the N-type silicon substrate; (2) forming a light and heavy boron emitter on the front side of the N-type silicon wafer; (3) Complete BSG removal cleaning and alkaline polishing on the back side of N-type silicon; (4) depositing a stacking layer on the back of the battery, comprising an ultra-thin oxide layer of 0.3-2.0 nm and a polysilicon layer of 30-60 nm; then depositing a second stacking layer on the back of the battery, comprising an ultra-thin oxide layer of 0.3-1 nm and a thick polysilicon layer of 90-120 nm; (5) Selective poly-Si layer preparation, using laser scanning to thin the non-electrode area of ​​the thick poly-Si layer on the back of the cell; (6) De-poly plating and cleaning; (7) Preparation of front passivation and anti-reflection film and back passivation film; (8) Electrode preparation; (9) The heating sintering process and light injection are completed in the sintering furnace.

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