Heterojunction battery and method for manufacturing the same

Abstract

The present application discloses a heterojunction battery and a method for manufacturing the same, and relates to the field of photovoltaic technology. The heterojunction battery includes a first transparent conductive layer, an n-type doped silicon layer, a first intrinsic silicon layer, a silicon wafer layer, a second intrinsic silicon layer, an oxide layer, a p-type doped silicon layer, and a second transparent conductive layer stacked in sequence, and the heterojunction battery also includes a first electrode and a second electrode, the first electrode is arranged in the first transparent conductive layer, and the second electrode is arranged in the second transparent conductive layer, wherein the oxide layer includes a p-type silicon oxide layer, and the thickness of the oxide layer is 0.5~2.5nm. By inserting a p-type silicon oxide layer between the second intrinsic silicon layer and the p-type doped silicon layer, the energy band discontinuity can be reduced and the fill factor of the battery can be improved. At the same time, since a tunneling path is provided, the hole carrier mobility can be improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a heterojunction battery and a method for manufacturing the same. Background Art

[0002] With the development of high-efficiency battery module technology, heterojunction cells (HJT) have become the mainstream development trend of the photovoltaic industry. At the same time, due to its many advantages such as no light decay, high bifaciality, low-temperature process, high conversion efficiency and low temperature coefficient, it has been recognized by the industry as the next generation of mass-produced photovoltaic cell technology with great market prospects. The silicon heterojunction cell in the related technology includes a silicon wafer layer and an intrinsic silicon layer, a doped silicon layer and a transparent conductive layer deposited on both sides of the silicon wafer layer in sequence. The transparent conductive layer is used to collect photogenerated carriers and transport them to the metal electrode.

[0003] However, the inventors have found that the heterojunction cell in the related art has a large conduction band offset between the intrinsic silicon layer and the p-type doped silicon layer, resulting in a relatively obvious energy band discontinuity, which leads to a low fill factor and low hole carrier mobility of the cell. Summary of the invention

[0004] The purpose of the present application includes providing a heterojunction battery and a method for manufacturing the same, which can significantly improve the fill factor and carrier mobility of the battery.

[0005] The embodiments of the present application can be implemented as follows:

[0006] In a first aspect, the present application provides a heterojunction battery, comprising a first transparent conductive layer, an n-type doped silicon layer, a first intrinsic silicon layer, a silicon wafer layer, a second intrinsic silicon layer, an oxide layer, a p-type doped silicon layer and a second transparent conductive layer stacked in sequence, the heterojunction battery also comprising a first electrode and a second electrode, the first electrode being arranged on the first transparent conductive layer, and the second electrode being arranged on the second transparent conductive layer, wherein the oxide layer comprises a p-type silicon oxide layer, and the thickness of the oxide layer is 0.5~2.5nm.

[0007] In an optional embodiment, the oxide layer further includes an undoped silicon oxide layer, the undoped silicon oxide layer and the p-type silicon oxide layer are stacked, the undoped silicon oxide layer is connected to the second intrinsic silicon layer, and the p-type silicon oxide layer is connected to the p-type doped silicon layer.

[0008] In an optional embodiment, a side of the silicon wafer layer facing the second intrinsic silicon layer is a velvet surface after planarization, and a pyramid base angle of the velvet surface is 10° to 35°.

[0009] In an optional embodiment, the material of the first intrinsic silicon layer and the second intrinsic silicon layer is hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, hydrogenated amorphous silicon oxide or hydrogenated microcrystalline silicon.

[0010] In an optional embodiment, the n-type doped silicon layer and the p-type doped silicon layer are hydrogenated amorphous structures or hydrogenated microcrystalline structures.

[0011] In an optional embodiment, the p-type silicon oxide layer is boron-doped silicon oxide.

[0012] In an optional embodiment, the thickness of the silicon wafer layer is 80-180 μm;

[0013] The thickness of the first intrinsic silicon layer and the second intrinsic silicon layer is 5 to 15 nm;

[0014] The thickness of the n-type doped silicon layer and the p-type doped silicon layer is 20~60nm;

[0015] The thickness of the first transparent conductive layer is 70-150 nm, the thickness of the second transparent conductive layer is 80-180 nm, and the thickness of the second transparent conductive layer is greater than that of the first transparent conductive layer.

[0016] In a second aspect, the present application provides a method for manufacturing a heterojunction battery according to any one of the aforementioned embodiments, comprising:

[0017] Texturing is performed on the front and back sides of the silicon wafer layer;

[0018] Depositing a first intrinsic silicon layer on the front side of the silicon wafer layer, and depositing a second intrinsic silicon layer on the back side of the silicon wafer layer;

[0019] Depositing an oxide layer on the second intrinsic silicon layer using B2H6 gas and SiH4 gas;

[0020] depositing an n-type doped silicon layer on the first intrinsic silicon layer, and depositing a p-type doped silicon layer on the oxide layer;

[0021] Depositing a first transparent conductive layer on the n-type doped silicon layer, and depositing a second transparent conductive layer on the p-type doped silicon layer;

[0022] A first electrode is formed on the first transparent conductive layer, and a second electrode is formed on the second transparent conductive layer.

[0023] In an optional embodiment, the step of depositing an oxide layer on the second intrinsic silicon layer using B2H6 gas and SiH4 gas includes:

[0024] Depositing an undoped silicon oxide layer on the second intrinsic silicon layer using SiH4 gas and N2O gas;

[0025] depositing a p-type silicon oxide layer on the undoped silicon oxide layer using SiH4 gas, B2H6 gas and N2O gas;

[0026] The undoped silicon oxide layer and the p-type silicon oxide layer are hydrogen passivated using a hydrogen plasma treatment process.

[0027] In an optional embodiment, the undoped silicon oxide layer and the p-type silicon oxide layer are both deposited by a very high frequency plasma enhanced chemical vapor deposition process, and the pressure of the reaction chamber during the deposition process is not greater than 10 -3 Pa, the temperature of the second intrinsic silicon layer is 160~200℃.

[0028] In an optional embodiment, before depositing the undoped silicon oxide layer, H2 and SiH4 gases are introduced into the reaction chamber for 5 to 25 seconds.

[0029] In an optional embodiment, the step of performing texturing on the front and back sides of the silicon wafer layer includes:

[0030] Pre-cleaning the silicon wafer layer using a pre-cleaning solution comprising an alkaline solution and hydrogen peroxide;

[0031] The front and back sides of the silicon wafer layer are textured by using a texture-making liquid, so that a textured surface is formed on the front and back sides of the silicon wafer layer;

[0032] Clean the silicon wafer layer, and use a polishing liquid to flatten the back of the silicon wafer layer so that the pyramid base angle of the velvet surface on the back of the silicon wafer layer is reduced to 10°~35°;

[0033] Clean the silicon wafer layer.

[0034] The beneficial effects of the heterojunction battery and the manufacturing method thereof provided in the embodiments of the present application include:

[0035] The heterojunction battery provided by the present application includes a first transparent conductive layer, an n-type doped silicon layer, a first intrinsic silicon layer, a silicon wafer layer, a second intrinsic silicon layer, an oxide layer, a p-type doped silicon layer and a second transparent conductive layer stacked in sequence, and the heterojunction battery also includes a first electrode and a second electrode, the first electrode is arranged in the first transparent conductive layer, and the second electrode is arranged in the second transparent conductive layer, wherein the oxide layer includes a p-type silicon oxide layer, and the thickness of the oxide layer is 0.5~2.5nm. By inserting a p-type silicon oxide layer between the second intrinsic silicon layer and the p-type doped silicon layer, the formed band structure will decompose the large conduction band offset into two smaller conduction band offsets, thereby reducing the band discontinuity and improving the fill factor of the battery. At the same time, since a tunneling path is provided, the hole carrier mobility can be improved. The oxide layer in this application is realized by p-type doped ultra-thin silicon oxide (the total thickness of the oxide layer is 0.5~2.5nm), which reduces the series resistance and thus improves the overall photoelectric conversion efficiency; adjusting the doping concentration can change the energy band matching and microstructure at the interface, reduce the interface state density while increasing the internal electric field strength, thereby improving the efficiency of the battery cell.

[0036] The method for manufacturing a heterojunction battery provided in the embodiment of the present application can be used to manufacture the above-mentioned heterojunction battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 This is a schematic diagram of a heterojunction battery in one embodiment of the present application;

[0039] Figure 2 This is a flow chart of a method for manufacturing a heterojunction battery in one embodiment of the present application.

[0040] Icon: 100 - silicon wafer layer; 210 - first intrinsic silicon layer; 220 - second intrinsic silicon layer; 310 - n-type doped silicon layer; 320 - p-type doped silicon layer; 410 - first transparent conductive layer; 420 - second transparent conductive layer; 510 - first electrode; 520 - second electrode; 600 - oxide layer. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0042] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0043] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0044] In the description of the present application, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, it is based on the orientation or position relationship shown in the drawings, or is the orientation or position relationship in which the product of the invention is usually placed when used. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0045] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0046] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

[0047] Figure 1 Schematic diagram of a heterojunction battery in one embodiment of the present application. Figure 1 As shown, the heterojunction battery provided in the embodiment of the present application includes a first transparent conductive layer 410, an n-type doped silicon layer 310, a first intrinsic silicon layer 210, a silicon wafer layer 100, a second intrinsic silicon layer 220, an oxide layer 600, a p-type doped silicon layer 320 and a second transparent conductive layer 420 which are stacked in sequence, and the heterojunction battery also includes a first electrode 510 and a second electrode 520, the first electrode 510 is arranged on the first transparent conductive layer 410, and the second electrode 520 is arranged on the second transparent conductive layer 420, wherein the oxide layer 600 includes a p-type silicon oxide layer (not shown in the figure), and the thickness of the oxide layer 600 is 0.5~2.5nm.

[0048] The oxide layer 600 can provide excellent surface passivation effect, reduce carrier recombination caused by surface defects, and thus improve the open circuit voltage (Voc) and fill factor (FF). By inserting a p-type silicon oxide layer between the second intrinsic silicon layer 220 and the p-type doped silicon layer 320, the formed band structure will decompose the large conduction band offset into two smaller conduction band offsets, thereby reducing the band discontinuity and improving the fill factor of the battery. At the same time, since a tunneling path is provided, the hole carrier mobility can be improved. The oxide layer 600 in the present application is realized by p-type doped ultra-thin silicon oxide (thickness of 0.5~2.5nm), which reduces the series resistance and thus improves the overall photoelectric conversion efficiency; adjusting the doping concentration can change the band matching and microstructure at the interface, reduce the interface state density while increasing the internal electric field strength, and improve the efficiency of the battery cell.

[0049] In this embodiment, the p-type silicon oxide layer is specifically boron-doped silicon oxide with a doping concentration of 1×10 18 ~1×10 20 cm -3; In other embodiments, it may also be silicon oxide doped with other p-type doping elements. Further, the oxide layer 600 also includes an undoped silicon oxide layer, the undoped silicon oxide layer and the p-type silicon oxide layer are stacked, the undoped silicon oxide layer is connected to the second intrinsic silicon layer 220, and the p-type silicon oxide layer is connected to the p-type doped silicon layer 320. The undoped silicon oxide layer can block the doping elements (such as boron) in the p-type silicon oxide layer, prevent the doping elements from diffusing into the second intrinsic silicon layer 220, affect the electrical and optical properties of the second intrinsic silicon layer 220, and cause the passivation effect to deteriorate.

[0050] In the present embodiment, both the front and back sides of the silicon wafer layer 100 are velvet surfaces, wherein the back side of the silicon wafer layer 100 is specifically a velvet surface after planarization. In the present embodiment, the front side of the silicon wafer layer 100 refers to the side thereof facing the first intrinsic silicon layer 210, and the back side of the silicon wafer layer 100 refers to the side thereof facing the second intrinsic silicon layer 220. In the present embodiment, the pyramid base angle of the velvet surface of the back side of the silicon wafer layer 100 after planarization is 10°~35°. This pyramid structure with a small base angle is obtained by planarizing the back side (such as polishing) after velveting. Since the stress of the pyramid top on the back side of the silicon wafer layer 100 is reduced, and the phenomenon of different pyramid sizes is eliminated, the window of the passivation process of each contact surface is released, so that the processing at the interface is easier to achieve the effect of both high open circuit voltage and high short circuit current, and the film quality is better while improving uniformity, which brings obvious efficiency improvement.

[0051] In this embodiment, the silicon wafer layer 100 is an n-type doped silicon wafer, specifically an n-type doped single crystal silicon wafer. The material of the first intrinsic silicon layer 210 and the second intrinsic silicon layer 220 is hydrogenated amorphous silicon a-Si:H(i), which can effectively passivate the dangling bonds on the surface of crystalline silicon and reduce the surface recombination centers, thereby improving the carrier life and the open circuit voltage (Voc) of the battery. This is due to the presence of hydrogen atoms in the intrinsic amorphous silicon layer. Hydrogen can terminate the dangling bonds of silicon atoms, reduce defects, and improve the transmission efficiency of charge carriers. The n-type doped silicon layer 310 and the p-type doped silicon layer 320 are hydrogenated amorphous structures (specifically hydrogenated amorphous silicon oxide, namely μc-SiO x :H(n+) and μc-SiO x :H(p+)). In other embodiments, the material of the first intrinsic silicon layer 210 and the second intrinsic silicon layer 220 may also be hydrogenated amorphous silicon carbide, hydrogenated amorphous silicon oxide or hydrogenated microcrystalline silicon; the n-type doped silicon layer 310 and the p-type doped silicon layer 320 may also be a hydrogenated amorphous structure.

[0052] In an optional embodiment, the thickness of the silicon wafer layer 100 is 80-180 μm, for example, any value among 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, or an intermediate value between any two points.

[0053] The thickness of the first intrinsic silicon layer 210 and the second intrinsic silicon layer 220 is 5-15 nm, for example, any value among 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm or an intermediate value between any two points.

[0054] The thickness of the n-type doped silicon layer 310 and the p-type doped silicon layer 320 is 20-60 nm, for example, any one of 20 nm, 30 nm, 40 nm, 50 nm, and 60 nm, or an intermediate value between any two values.

[0055] The thickness of the first transparent conductive layer 410 is 70-150 nm, the thickness of the second transparent conductive layer 420 is 80-180 nm, and the thickness of the second transparent conductive layer 420 is greater than that of the first transparent conductive layer 410. In this embodiment, the material of the first transparent conductive layer 410 and the second transparent conductive layer 420 can be ITO.

[0056] The material of the first electrode 510 and the second electrode 520 can be at least one of gold, silver, copper, aluminum, molybdenum, tin, and nickel.

[0057] Figure 2 Flow chart of a method for manufacturing a heterojunction battery in one embodiment of the present application. The method for manufacturing a heterojunction battery provided in the embodiment of the present application can be used to manufacture the above-mentioned heterojunction battery. Figure 2 As shown, the method for manufacturing a heterojunction battery provided in the embodiment of the present application includes:

[0058] Step S100 , texturing is performed on the front and back sides of the silicon wafer layer 100 .

[0059] In the embodiment of the present application, step S100 may specifically include:

[0060] Step S110 , pre-cleaning the silicon wafer layer 100 using a pre-cleaning solution including an alkaline solution and hydrogen peroxide.

[0061] In this embodiment, the pre-cleaning step can effectively remove organic dirt, metal impurities and surface damage layers on the surface of the silicon wafer layer 100. The alkaline solution in the pre-cleaning solution can be one of a potassium hydroxide solution or a sodium hydroxide solution. For example, the volume proportion of the alkaline solution in the pre-cleaning solution is 5%, and the volume proportion of hydrogen peroxide is 8%. Optionally, the concentration range of the alkaline solution (such as potassium hydroxide solution or sodium hydroxide solution) is 15 mol / L~25mol / L, and the concentration range of hydrogen peroxide in hydrogen peroxide is 5mol / L~12mol / L. The temperature of the pre-cleaning process is 45℃~85℃, and the process time is 40s~150s.

[0062] Step S120 , texturing the front and back sides of the silicon wafer layer 100 with a texturing liquid.

[0063] Among them, calculated by volume, the texturing liquid contains 2%~8% potassium hydroxide solution, 0.2%~2% texturing additive, and the balance is deionized water. The texturing temperature is 70℃~90℃, and the texturing time is 400s~800s.

[0064] In the embodiment of the present application, the concentration range of potassium hydroxide solution for preparing the texturing liquid is 15 mol / L~25 mol / L. The texturing additive comprises 0.05%~2.5% potassium polyacrylate, 0.05%~2.5% potassium sorbate, 2%~7% polyethylene glycol, 0.05%~2.5% potassium hydroxide, and the balance is deionized water.

[0065] The equipment used in the texturing step is a texturing tank. Optionally, the circulation flow rate during the texturing process is 50L / m, and the discharge factor is 0.065~0.095.

[0066] Step S130 , cleaning the silicon wafer layer 100 , and flattening the back side of the silicon wafer layer 100 with a polishing liquid, so that the pyramid base angle of the velvet surface on the back side of the silicon wafer layer 100 is reduced to 10° to 35°.

[0067] Wherein, the polishing liquid contains hydrofluoric acid and nitric acid, the polishing temperature is 20℃~50℃, and the polishing time is 45s~150s. Optionally, the concentration of hydrofluoric acid solution is 20mol / L~30mol / L, and the concentration of nitric acid solution is 10mol / L~15mol / L. The temperature range of the polishing process is preferably 20℃~50℃, without specific restrictions. The time of the polishing process is 45s~150s. The polishing process uses a polishing etcher, and the initial HF:HNO3 volume ratio in the etching tank is 1:4~8; the circulating liquid replenishment volume is 1:2~6 for every 1000pcs of liquid replenishment HF:HNO3 volume ratio, and the etching tank opens water film protection; the silicon wafer layer 100 passes through the polishing etcher at a belt speed of 0.5~2.5 m / min to complete the polishing.

[0068] The cleaning method in step S130 may be the same as the pre-cleaning method in step S110 .

[0069] Step S140, cleaning the silicon wafer layer 100. The cleaning method in step S140 may be the same as the pre-cleaning method in step S110.

[0070] Step S200 , depositing a first intrinsic silicon layer 210 on the front side of the silicon wafer layer 100 , and depositing a second intrinsic silicon layer 220 on the back side of the silicon wafer layer 100 .

[0071] In the embodiment of the present application, the first intrinsic silicon layer 210 and the second intrinsic silicon layer 220 can be obtained by plasma enhanced chemical vapor deposition (PECVD). In other embodiments, they can also be obtained by hot wire chemical vapor deposition (HWCVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), rapid plasma deposition (RPD) and other processes.

[0072] In step S300 , an oxide layer 600 is deposited on the second intrinsic silicon layer 220 using B 2 H 6 gas and SiH 4 gas.

[0073] In the embodiment of the present application, step S300 specifically includes:

[0074] Step S310, depositing an undoped silicon oxide layer on the second intrinsic silicon layer 220 using SiH4 gas and N2O gas;

[0075] Step S320, depositing a p-type silicon oxide layer on the undoped silicon oxide layer using SiH4 gas, B2H6 gas and N2O gas;

[0076] Step S330 , hydrogen passivation is performed on the undoped silicon oxide layer and the p-type silicon oxide layer using a hydrogen plasma treatment process.

[0077] In this embodiment, the undoped silicon oxide layer and the p-type silicon oxide layer are both deposited by a very high frequency plasma enhanced chemical vapor deposition process (VHF-PECVD), and the pressure of the reaction chamber during the deposition process is not greater than 10 -3 Pa, the temperature of the second intrinsic silicon layer 220 (as a deposition substrate) is 160-200°C.

[0078] In this embodiment, the oxide layer 600 is made of two layers, wherein the first layer is an undoped silicon oxide layer, in which boron is not doped, so there is no risk of boron diffusing into the second intrinsic silicon layer 220. And when the p-type silicon oxide layer is subsequently deposited, the undoped silicon oxide layer deposited first can play a blocking role, preventing the boron element from diffusing into the second intrinsic silicon layer 220. Optionally, the thickness of the undoped silicon oxide layer is less than the thickness of the p-type silicon oxide layer.

[0079] In this embodiment, using laughing gas N2O instead of carbon dioxide CO2 as the oxygen source for depositing silicon oxide has a significant effect on alleviating the efficiency decay of the cell. The reason is that the valence bond formed by carbon in the microstructure is not stable enough, and the structure is easily destroyed to form internal defects. Nitrogen is more stable than it, and the efficiency decay is only half of the former under the same length of time.

[0080] In a specific embodiment, the flow rate of the process gas SiH4 for preparing the undoped silicon oxide layer is 60 sccm, the flow rate of N2O is 40 sccm, the pressure is 0.5 mbar, and the deposition power is 20-45 mW / cm 2 , the process time is 8s. The p-type silicon oxide layer is prepared by adding doping gas B2H6, the ratio of B2H6 gas flow to SiH4 gas flow is 2.5%~20%; preferably, the ratio of B2H6 gas flow to SiH4 gas flow is 5%~15%, that is, B2H6:SiH4=0.05~0.15. The pressure is 0.3mabr, and the deposition power is 50mW / cm 2 , the process time is 5~15s, and a 1.2nm thick oxide layer 600 can be produced.

[0081] In a specific embodiment, after the p-type silicon oxide layer is prepared, hydrogen passivation is performed using a hydrogen plasma treatment process (HPT), wherein the H2 gas flow rate is 200 sccm, the pressure is 0.6 mbar, and the deposition power is 45 mW / cm 2 , the process time is 5~15s.

[0082] Furthermore, before depositing the oxide layer 600, H2 and SiH4 gases may be introduced into the reaction chamber for 5 to 25 seconds. Optionally, the H2 flow rate is 700 sccm, the SiH4 flow rate is 30 to 55 sccm, the pressure is 0.8 to 2.5 mbar, and the deposition power is 125 mW / cm 2 This step is to perform hydrogen passivation treatment, namely HPT, on the previously prepared second intrinsic silicon layer 220 to ensure the flatness of the deposition interface, which is conducive to ensuring the uniformity of the subsequently deposited oxide layer 600.

[0083] In the embodiment of the present application, since the low temperature process (not higher than 200° C.) is used to make the undoped silicon oxide layer and the p-type silicon oxide layer, the substrate (such as the second intrinsic silicon layer 220) will not be damaged. In other optional embodiments, the undoped silicon oxide layer and the p-type silicon oxide layer can also be made by wet chemical oxidation, thermal oxidation, ozone oxidation, etc.

[0084] In step S400 , an n-type doped silicon layer 310 is deposited on the first intrinsic silicon layer 210 , and a p-type doped silicon layer 320 is deposited on the oxide layer 600 .

[0085] In the embodiment of the present application, the n-type doped silicon layer 310 and the p-type doped silicon layer 320 can be obtained by plasma enhanced chemical vapor deposition (PECVD). In other embodiments, they can also be obtained by hot wire chemical vapor deposition (HWCVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), rapid plasma deposition (RPD) and other processes.

[0086] Step S500 , depositing a first transparent conductive layer 410 on the n-type doped silicon layer 310 , and depositing a second transparent conductive layer 420 on the p-type doped silicon layer 320 .

[0087] In this embodiment, physical vapor deposition (PVD) can be used to form the first transparent conductive layer 410 and the second transparent conductive layer 420. Optionally, the target material of the second transparent conductive layer 420 is In2O3 / SnO2, the mass ratio of In2O3 to SnO2 is 97:3, the film forming temperature is 200°C, and the film thickness is 110nm; the target material of the first transparent conductive layer 410 is In2O3 / SnO2, the mass ratio of In2O3 to SnO2 is 99:1, the film forming temperature is 200°C, and the film thickness is 100nm.

[0088] In step S600 , a first electrode 510 is formed on the first transparent conductive layer 410 , and a second electrode 520 is formed on the second transparent conductive layer 420 .

[0089] In the embodiment of the present application, screen printing technology can be used to manufacture the first electrode 510 and the second electrode 520. A multi-busbar technology solution can be used, for example, the number of battery busbars is 18, that is, 18BB design.

[0090] In summary, the heterojunction battery provided by the present application includes a first transparent conductive layer 410, an n-type doped silicon layer 310, a first intrinsic silicon layer 210, a silicon wafer layer 100, a second intrinsic silicon layer 220, an oxide layer 600, a p-type doped silicon layer 320 and a second transparent conductive layer 420 stacked in sequence, and the heterojunction battery also includes a first electrode 510 and a second electrode 520, the first electrode 510 is arranged on the first transparent conductive layer 410, and the second electrode 520 is arranged on the second transparent conductive layer 420, wherein the oxide layer 600 includes a p-type silicon oxide layer, and the thickness of the oxide layer 600 is 0.5~2.5nm. By inserting a p-type silicon oxide layer between the second intrinsic silicon layer 220 and the p-type doped silicon layer 320, the formed band structure will decompose the large conduction band offset into two smaller conduction band offsets, thereby reducing the band discontinuity and improving the fill factor of the battery. At the same time, since a tunneling path is provided, the hole carrier mobility can be improved. The oxide layer 600 in the present application is realized by p-type doped ultra-thin silicon oxide (the total thickness of the oxide layer 600 is 0.5~2.5nm), which reduces the series resistance and thus improves the overall photoelectric conversion efficiency; adjusting the doping concentration can change the energy band matching and microstructure at the interface, reduce the interface state density while increasing the internal electric field strength, thereby improving the efficiency of the battery cell.

[0091] The method for manufacturing a heterojunction battery provided in the embodiment of the present application can be used to manufacture the above-mentioned heterojunction battery.

[0092] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed in the present application should be included in the protection scope of the present application.

Claims

1. A heterojunction battery, characterized in that: The heterojunction battery comprises a first transparent conductive layer, an n-type doped silicon layer, a first intrinsic silicon layer, a silicon wafer layer, a second intrinsic silicon layer, an oxide layer, a p-type doped silicon layer and a second transparent conductive layer which are stacked in sequence, and the heterojunction battery further comprises a first electrode and a second electrode, wherein the first electrode is arranged on the first transparent conductive layer, and the second electrode is arranged on the second transparent conductive layer, wherein the oxide layer comprises a p-type silicon oxide layer, and the thickness of the oxide layer is 0.5-2.5 nm; The oxide layer further comprises an undoped silicon oxide layer, the undoped silicon oxide layer is stacked with the p-type silicon oxide layer, the undoped silicon oxide layer is connected to the second intrinsic silicon layer, the p-type silicon oxide layer is connected to the p-type doped silicon layer, and the doping concentration of the p-type silicon oxide layer is 1×10 18 ~1×10 20 cm -3 .

2. The heterojunction battery according to claim 1, characterized in that: The side of the silicon sheet layer facing the second intrinsic silicon layer is a velvet surface after planarization, and the pyramid base angle of the velvet surface is 10° to 35°.

3. The heterojunction battery according to claim 1, characterized in that: The first intrinsic silicon layer and the second intrinsic silicon layer are made of hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, hydrogenated amorphous silicon oxide or hydrogenated microcrystalline silicon.

4. The heterojunction battery according to claim 1, characterized in that: The n-type doped silicon layer and the p-type doped silicon layer are hydrogenated amorphous structures or hydrogenated microcrystalline structures.

5. The heterojunction battery according to claim 1, characterized in that: The p-type silicon oxide layer is boron-doped silicon oxide.

6. The heterojunction battery according to any one of claims 1 to 5, characterized in that: The thickness of the silicon wafer layer is 80-180 μm; The thickness of the first intrinsic silicon layer and the second intrinsic silicon layer is 5-15 nm; The thickness of the n-type doped silicon layer and the p-type doped silicon layer is 20-60 nm; The thickness of the first transparent conductive layer is 70-150 nm, the thickness of the second transparent conductive layer is 80-180 nm, and the thickness of the second transparent conductive layer is greater than that of the first transparent conductive layer.

7. The method for manufacturing a heterojunction battery according to any one of claims 1 to 6, characterized in that: include: Texturing is performed on the front and back sides of the silicon wafer layer; Depositing a first intrinsic silicon layer on the front side of the silicon wafer layer, and depositing a second intrinsic silicon layer on the back side of the silicon wafer layer; Depositing an oxide layer on the second intrinsic silicon layer using B2H6 gas and SiH4 gas; Depositing an n-type doped silicon layer on the first intrinsic silicon layer, and depositing a p-type doped silicon layer on the oxide layer; Depositing a first transparent conductive layer on the n-type doped silicon layer, and depositing a second transparent conductive layer on the p-type doped silicon layer; Fabricating a first electrode on the first transparent conductive layer, and fabricating a second electrode on the second transparent conductive layer; The step of depositing an oxide layer on the second intrinsic silicon layer by using B2H6 gas and SiH4 gas comprises: Depositing an undoped silicon oxide layer on the second intrinsic silicon layer using SiH4 gas and N2O gas; Depositing a p-type silicon oxide layer on the undoped silicon oxide layer using SiH4 gas, B2H6 gas and N2O gas; The undoped silicon oxide layer and the p-type silicon oxide layer are hydrogen passivated by using a hydrogen plasma treatment process.

8. The method for manufacturing a heterojunction battery according to claim 7, characterized in that: The undoped silicon oxide layer and the p-type silicon oxide layer are both deposited by a very high frequency plasma enhanced chemical vapor deposition process, and the pressure of the reaction chamber during the deposition process is not greater than 10 -3 Pa, the temperature of the second intrinsic silicon layer is 160-200°C.

9. The method for manufacturing a heterojunction battery according to claim 7, characterized in that: Before depositing the undoped silicon oxide layer, H2 and SiH4 gases are introduced into the reaction chamber for 5 to 25 seconds.

10. The method for manufacturing a heterojunction battery according to claim 7, characterized in that: The steps of texturing the front and back sides of the silicon wafer layer include: Pre-cleaning the silicon wafer layer using a pre-cleaning solution comprising an alkaline solution and hydrogen peroxide; Using a texturing liquid to texturize the front and back sides of the silicon wafer layer, so that a velvet surface is formed on the front and back sides of the silicon wafer layer; Cleaning the silicon wafer layer, and flattening the back side of the silicon wafer layer with a polishing liquid, so that the pyramid base angle of the velvet surface on the back side of the silicon wafer layer is reduced to 10° to 35°; The silicon wafer layer is cleaned.

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