Heterojunction solar cell and method of manufacturing the same

Abstract

The application provides a heterojunction solar cell and a manufacturing method thereof. The cell comprises: an N-type substrate having oppositely arranged front and back surfaces; a front cell structure on the front surface of the N-type substrate, comprising an intrinsic amorphous silicon passivation layer and an N-type doped layer; a back cell structure on the back surface of the N-type substrate, comprising an intrinsic amorphous silicon passivation layer and a P-type doped layer; a front conductive layer covering the front cell structure; and a back conductive layer covering the back cell structure; wherein the front conductive layer is a transparent conductive layer; and the back conductive layer is a composite structure reflective conductive layer, comprising: an indium-free conductive layer in direct contact with the P-type doped layer, a metal reflective layer sputtered on the indium-free conductive layer, and a dense protective layer sputtered on the metal reflective layer, the dense protective layer and the metal reflective layer being metal thin film layers of different substrates. The application reduces the cost of the cell, and improves the electrical performance and stability of the cell.

Description

Technical Field

[0001] This application relates to the field of heterojunction solar cell manufacturing technology, and more specifically, to a heterojunction solar cell and a method for manufacturing the same. Background Technology

[0002] Heterojunction solar cells (HJCs) are typically bifacial cells with an N-type substrate. Each side of the N-type substrate has a passivation layer and different types of amorphous doped layers to form the electric field structure and emitter structure. Both sides are electrically connected via a transparent conductive oxide (TCO) film. HJCs offer advantages such as simple manufacturing processes, high conversion efficiency, low temperature coefficient, and good low-light response. Furthermore, the entire process is carried out at low temperatures, making it suitable for thin-film production. Therefore, they are widely used in ground-mounted and floating solar power plants, as well as in Building Integrated Photovoltaics (BIPV) applications.

[0003] In BIPV applications, where only one side receives light, HJC cells do not require bi-sided power generation. Therefore, to improve conversion efficiency, a back-reflective structure is often added to increase the cell's absorption of light waves. However, in traditional processes, a high-reflectivity metal film is deposited on the encapsulation backplane and then combined with the HJC cell through encapsulation material lamination. This results in the reflective film not forming a good ohmic contact with the HJC cell, affecting the series resistance Rser and fill factor FF. Furthermore, in BIPV applications, continuing to use indium-tin oxide (ITO) conductive film on the bottom increases the cell's production cost and is detrimental to photovoltaic production efficiency. Moreover, simply replacing the ITO layer with a common indium-free film easily leads to moisture erosion, resulting in poor cell stability and rapid deterioration of electrical performance. Therefore, a low-cost cell design suitable for BIPV applications is needed. Summary of the Invention

[0004] This application provides a heterojunction solar cell and a method for manufacturing the same, in order to solve the problems of high production cost of heterojunction solar cells in the prior art and poor ohmic contact in the existing laminated encapsulation back-side structure, which affects the electrical performance of the cell.

[0005] A heterojunction solar cell according to this application includes:

[0006] N-type substrate, the N-type substrate has a front side and a back side that are arranged opposite to each other;

[0007] The front-side battery structure, located on the front side of the N-type substrate, includes an intrinsic amorphous silicon passivation layer and an N-type doped layer;

[0008] The back-side battery structure, located on the back of the N-type substrate, includes an intrinsic amorphous silicon passivation layer and a P-type doped layer;

[0009] A front conductive layer covers the front battery structure.

[0010] A back conductive layer covers the back battery structure.

[0011] The front conductive layer is a transparent conductive layer; the back conductive layer is a composite reflective conductive layer, including: an indium-free conductive layer in direct contact with the P-type doped layer, a metal reflective layer sputtered onto the indium-free conductive layer, and a dense protective layer sputtered onto the metal reflective layer. The dense protective layer and the metal reflective layer are metal thin film layers with different substrates.

[0012] In some embodiments, the metal reflective layer is a Cu, Ag, Pt, Al, Cu / Zn or their alloy base layer; the dense protective layer is an Ag, Pt, Ni, Cr, Sn or their alloy base layer; the thickness of the metal reflective layer is 50-100 nm, and the thickness of the dense protective layer is 30-50 nm.

[0013] In some embodiments, the AZO film layer, which is an indium-free conductive layer and is a composite structure film layer, includes: a modified functional layer that directly contacts the p-type doped layer, and a barrier functional layer that covers the modified functional layer; the thickness of the modified functional layer is 10-20 nm, the thickness of the barrier functional layer is 80-90 nm, and the aluminum doping concentration of the modified functional layer is greater than that of the barrier functional layer; both the modified functional layer and the barrier functional layer are generated by magnetron sputtering, and the modified functional layer is sputtered in a hydrogenated environment and under lower oxygen-argon ratio conditions compared to the barrier functional layer.

[0014] In some embodiments, the front conductive layer is an ITO layer with a thickness of 80-100 nm, the N-type substrate has a thickness of 130-165 μm, the intrinsic amorphous silicon passivation layer has a thickness of 4-10 nm, the N-type doped layer has a thickness of 20-30 nm, and the P-type doped layer has a thickness of 20-30 nm.

[0015] In some embodiments, a front electrode and a back electrode are printed on the outer sides of the front conductive layer and the back conductive layer, respectively.

[0016] According to another aspect of this application, a method for manufacturing a heterojunction solar cell is provided, comprising:

[0017] Step S1: Provide an N-type substrate and perform cleaning and texturing on the N-type substrate;

[0018] Step S2: Deposit and fabricate the front battery structure and the back battery structure on the front and back sides of the N-type substrate, respectively;

[0019] Step S3: Deposit a transparent conductive layer on the front battery structure to form a front conductive layer;

[0020] Step S4: An indium-free conductive layer, a metal reflective layer, and a dense protective layer are deposited sequentially on the back battery structure to form a composite structure back conductive layer.

[0021] In some embodiments, step S4, depositing the indium-free conductive layer includes: depositing a modified functional layer and a barrier functional layer sequentially with different doping concentrations to form an indium-free conductive layer with a composite structure; wherein,

[0022] The modified functional layer is generated by magnetron sputtering in an environment of Ar, O2 and H2. The DC power density of the magnetron sputtering power supply is 4-6 kW / m, the rotating target composition is ZnO:Al2O3=98:2, the temperature is 150-190℃, the pressure is 0.5-1.1 Pa, the oxygen-argon ratio is 0.15%-0.5%, the hydrogen-argon ratio is 0.1%-0.3%, the water vapor partial pressure is below 8.0E-8 mbar, and the magnetron sputtering coating thickness is 10-20 nm.

[0023] The barrier layer is generated using magnetron sputtering in an Ar and O2 environment. The DC power density of the magnetron sputtering power supply is 4-6 kW / m. The rotating target composition is ZnO:Al2O3 = 99.9:0.1. The temperature is 150-190℃, the pressure is 0.8-1.1 Pa, the oxygen-argon ratio is 0.3%-0.8%, the water vapor partial pressure is below 8.0E-8 mbar, and the magnetron sputtering coating thickness is 80-90 nm.

[0024] In some embodiments, in step S4, the metal reflective layer is generated by magnetron sputtering, the sputtering environment is an Ar environment, the power density of the magnetron sputtering DC power supply is 4-6 kW / m, the rotating target is a copper target, the temperature is 150-190°C, the pressure is 0.3-1.1 Pa, the water vapor partial pressure is below 8.0E-8 mbar, the oxygen partial pressure is below 1.0E-9 mbar, and the magnetron sputtering coating thickness is 50-100 nm.

[0025] The dense protective layer is generated by magnetron sputtering in an Ar environment. The power density of the DC power supply for magnetron sputtering is 4-6 kW / m. The composition of the rotating target is Cr:Ni=20:80. The temperature is 150-190℃, the pressure is 0.3-1.1 Pa, the water vapor partial pressure is below 8.0E-8 mbar, the oxygen partial pressure is below 1.0E-9 mbar, and the thickness of the magnetron sputtering coating is 30-50 nm.

[0026] In some embodiments, step S1, cleaning and texturing the N-type substrate includes: cleaning with potassium hydroxide solution to initially remove the mechanically damaged layer, using a tube diffusion furnace for phosphorus diffusion and gettering at a temperature of 600-800°C, using a chain pickling machine and hydrofluoric acid solution to remove the phosphosilicate glass layer, using a potassium hydroxide etchant for anisotropic etching to obtain a pyramid structure, then using a nitric acid / hydrofluoric acid solution to round the pyramid structure, and finally cleaning with a wet chemical cleaning method to obtain a double-textured N-type substrate.

[0027] In some embodiments, the method further includes step S5, which involves screen printing a front electrode and a back electrode onto the front conductive layer and the back conductive layer, respectively.

[0028] By applying the technical solution of this application, the back of the heterojunction solar cell adopts a composite film structure, combining an indium-free conductive layer, a metal reflective layer, and a dense protective layer. By replacing the indium-containing conductive film with an indium-free conductive layer, the production cost of the cell is reduced. At the same time, the metal reflective layer is directly sputtered on the indium-free conductive layer, achieving good ohmic connection while reflecting light, improving the series resistance and fill factor of the cell. Furthermore, a dense protective layer is sputtered on the outside of the metal reflective layer, improving the cell's oxidation resistance and corrosion resistance. This protects the metal reflective layer and the indium-free conductive layer from oxidation and inhibits the penetration of moisture into the indium-free conductive layer, thereby stabilizing the electrical performance of the cell, reducing the cell degradation rate, and significantly improving the cell quality and lifespan. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 A schematic diagram of the structure of a heterojunction solar cell according to an embodiment of this application is shown;

[0032] Figure 2 A schematic flowchart of a heterojunction solar cell manufacturing method according to an embodiment of this application is shown;

[0033] Figure 3 A schematic flowchart of a method for manufacturing a heterojunction solar cell according to another embodiment of this application is shown;

[0034] Figure 4 It shows Figure 3A schematic diagram of the process results of step S1 in the illustrated embodiment;

[0035] Figure 5 It shows Figure 3 A schematic diagram of the process result of step S2 in the embodiment shown;

[0036] Figure 6 It shows Figure 3 A schematic diagram of the process result of step S3 in the embodiment shown;

[0037] Figure 7 It shows Figure 3 A schematic diagram of the process result of step S4 in the illustrated embodiment;

[0038] Figure 8 It shows Figure 3 A schematic diagram of the process result of step S5 in the illustrated embodiment.

[0039] The above figures include the following reference numerals:

[0040] 101. N-type substrate; 102. Intrinsic amorphous silicon passivation layer; 103. N-type doped layer; 104. P-type doped layer; 105. Front conductive layer; 106. Indium-free conductive layer; 1061. Modification functional layer; 1062. Barrier functional layer; 107. Metal reflective layer; 108. Dense protective layer; 109. Back electrode; 110. Front electrode; 10. Front cell structure; 20. Back cell structure; 30. Back conductive layer. Detailed Implementation

[0041] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0042] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0043] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways, rotated 90 degrees, or in other orientations, and the spatial relative descriptions used herein will be interpreted accordingly.

[0044] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0045] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0046] Heterojunction solar cells, employing an amorphous / crystalline silicon heterojunction structure, offer significant advantages in conversion efficiency, process steps, bifaciality, and low degradation, making them a popular research focus in the photovoltaic industry. Typically, heterojunction cells are bifacial power-generating cells, with transparent conductive films on both sides to allow light to enter. However, in building-integrated photovoltaic (BIPV) applications, bifacial power generation is not required, allowing for the addition of a reverse-biased structure to improve conversion efficiency. However, existing laminated reverse-biased structures suffer from poor ohmic bonding, limiting performance parameters such as series resistance and fill factor, and also exhibiting issues like high cost or poor oxidation resistance. Therefore, this application proposes an improved heterojunction solar cell suitable for BIPV applications, enabling low-cost cell manufacturing while simultaneously improving cell stability.

[0047] Figure 1 An embodiment of the heterojunction solar cell of this application is illustrated schematically.

[0048] like Figure 1 As shown, this application discloses a heterojunction solar cell, which includes:

[0049] The N-type substrate 101 has a front side and a back side disposed opposite to each other. The heterojunction solar cell of this application is an N-type cell, with the N-type substrate 101 serving as the main light-absorbing layer to achieve the photogenerated carrier effect. Compared to a P-type substrate, the N-type substrate 101 can generate a higher current density, thus resulting in higher cell performance.

[0050] The front-side battery structure 10, located on the front side of the N-type substrate 101, includes an intrinsic amorphous silicon passivation layer 102 and an N-type doped layer 103. The intrinsic amorphous silicon passivation layer 102 covers both sides of the N-type substrate 101 and is used to passivate dangling bonds on the surface of the N-type substrate 101 to increase the open-circuit voltage Voc and improve battery performance. The N-type doped layer 103 forms an NN electric field structure with the N-type substrate 101 to allow electrons to pass through while blocking holes.

[0051] The back-side battery structure 20, located on the back of the N-type substrate 101, includes an intrinsic amorphous silicon passivation layer 102 and a P-type doped layer 104. The intrinsic amorphous silicon passivation layer 102 covers both sides of the N-type substrate 101 and is used to passivate the dangling bonds on the surface of the N-type substrate 101 to increase the open-circuit voltage Voc and improve battery performance. The P-type doped layer 104 forms a PN junction structure with the N-type substrate 101, constituting the emitter structure, and determines the upper limit of the open-circuit voltage Voc.

[0052] A front conductive layer 105 covers the front battery structure 10. The front conductive layer 105 is a transparent conductive layer used to allow light to enter and to collect charge carriers.

[0053] A back conductive layer 30 covers the back battery structure 20. The back conductive layer 30 is used to collect charge carriers. Furthermore, in this embodiment, the back conductive layer 30 also provides enhanced light reflection capability for the battery, improving the utilization rate of long-wavelength light and increasing battery conversion efficiency by extending the optical path. Wherein, as... Figure 1 As shown, the back conductive layer 30 in this embodiment is a composite structure reflective conductive layer, including: an indium-free conductive layer 106 in direct contact with the P-type doped layer 104, a metal reflective layer 107 sputtered on the indium-free conductive layer 106, and a dense protective layer 108 sputtered on the metal reflective layer 107. The dense protective layer 108 and the metal reflective layer 107 are metal thin film layers with different substrates.

[0054] With the above structure, the back of the heterojunction solar cell in this embodiment adopts a composite film structure, combining an indium-free conductive layer 106, a metal reflective layer 107, and a dense protective layer 108. By replacing the indium-containing conductive film with the indium-free conductive layer 106, the production cost of the battery is reduced. At the same time, the metal reflective layer 107 is directly sputtered on the indium-free conductive layer 106, achieving good ohmic connection while reflecting light, improving the series resistance and fill factor of the battery. Furthermore, a dense protective layer 108 is sputtered on the outside of the metal reflective layer 107, improving the battery's oxidation resistance and corrosion resistance. This protects the metal reflective layer 107 and the indium-free conductive layer 106 from oxidation, inhibits the penetration of moisture into the indium-free conductive layer 106, thereby stabilizing the battery's electrical performance, reducing the battery degradation rate, and significantly improving the battery quality and service life.

[0055] In some embodiments of this application, the metal reflective layer 107 is a base layer of Cu, Ag, Pt, Al, Cu / Zn, or their alloys. These metal elements have strong conductivity, allowing direct contact with the indium-free conductive layer 106, enabling rapid lateral transport of charge carriers. Furthermore, their surfaces can form strong reflections, extending the optical path length within the battery, improving the utilization rate of long-wavelength light, increasing the short-circuit current Isc, and reducing the series resistance Rser. The dense protective layer 108 is a base layer of Ag, Pt, Ni, Cr, Sn, or their alloys. These metals have a dense layer structure, exhibiting strong oxidation and corrosion resistance. They protect the internal metal reflective layer 107 and the indium-free conductive layer 106 from oxidation and degradation, and especially prevent moisture intrusion, avoiding degradation of the relatively reactive AZO film due to moisture intrusion, thereby significantly improving the battery's stability. In some preferred embodiments of this application, considering both cost and performance, the thickness of the metal reflective layer 107 is optimally 50-100 nm, preferably 95, 96, 97, 98, 99, or 100 nm. The thickness of the dense protective layer 108 is optimally 30-50 nm, preferably 46, 47, 48, 49, or 50 nm.

[0056] In some preferred embodiments of this application, the metal reflective layer 107 is a Cu base layer with a thickness of 50-100 nm. The Cu base layer has the advantage of lower cost compared to the Ag base layer, and as a back reflective film, it has strong reflectivity and good conductivity, effectively utilizing long-wavelength light and achieving rapid carrier transport, increasing Isc and reducing Rser. The dense protective layer 108 is a Cr / Ni composite base layer with a thickness of 30-50 nm. The nickel-chromium thin film is the outermost layer on the back of the battery. Its dense atomic arrangement effectively prevents water vapor and oxygen from diffusing into the battery. Furthermore, as the chromium content in the nickel-chromium alloy increases, its oxidation resistance and corrosion resistance are further enhanced, effectively ensuring battery stability. The preferred thickness of the Cu base layer is 95, 96, 97, 98, 99, or 100 nm. A higher thickness ensures the formation of a complete, highly reflective film and improves the bonding ability with the indium-free conductive layer 106 and its lateral conductivity. The preferred thickness of the Cr / Ni composite substrate is 46, 47, 48, 49 or 50 nm. While controlling the overall thickness of the battery, the thickness should be increased as much as possible to improve the resistance to water vapor and oxygen intrusion.

[0057] In some embodiments of this application, the indium-free conductive layer 106 is an AZO film layer with a composite structure, including: a modifying functional layer 1061 directly contacting the p-type doped layer 104, and a barrier functional layer 1062 covering the modifying functional layer 1061. Both the modifying functional layer 1061 and the barrier functional layer 1062 are generated by magnetron sputtering, and the thickness of the barrier functional layer 1062 is greater than that of the modifying functional layer 1061. In heterojunction solar cells, the ITO layer containing the noble metal indium is a cost-sensitive layer. Therefore, by replacing ITO with AZO (zinc aluminum oxide), which has a significantly lower cost, this application can effectively control the cost of the battery and improve battery efficiency. It should be noted that when the AZO film layer is directly used to replace the ITO layer on the back of the battery, the AZO film layer is relatively reactive and easily corroded by moisture. As the battery is used, its electrical performance will deteriorate rapidly, affecting the battery quality. Fortunately, this application utilizes both the back metal reflective layer 107 and the dense protective layer 108 to achieve battery protection. The shielding and anti-oxidation effects of the dual-metal layer suppress the penetration of moisture and oxygen into the AZO film, protecting its stability. Furthermore, to better accommodate the back metal layer and address the challenge of metal atom diffusion caused by direct sputtering of the metal layer onto the AZO film in new processes, this application's embodiments feature a structural design for the AZO film, employing a composite structure layer design with different doping concentrations and thicknesses to stabilize battery performance. The thickness of the modified functional layer 1061 is 10-20 nm, preferably 10, 11, 12, 13, 14, or 15 nm. The quality of the interface contact between the modified functional layer 1061 and the p-type doped layer 104 directly affects the electron tunneling efficiency, thereby influencing the battery's fill factor FF. To achieve a high carrier concentration, the aluminum doping concentration of the modified functional layer 1061 is greater than that of the barrier functional layer 1062. Preferably, a ZnO film with more than 2 wt% Al₂O₃ is formed to act as an interface modifier, utilizing the high aluminum doping concentration to increase the carrier transport velocity. Furthermore, compared to the barrier functional layer 1062, the modified functional layer 1061 is sputtered in a hydrogen-rich environment under lower oxygen-argon ratio conditions. The lower oxygen-argon ratio allows for the formation of more oxygen vacancies during sputtering; while the effective hydrogen doping provides hydrogen donors and also passivates film defects. The thickness of the barrier functional layer 1062 is 80-90 nm, preferably 86, 87, 88, 89, or 90 nm. This thickness is sufficient to prevent metal atoms (such as Cu atoms) from the metal reflective layer 107 from diffusing into the battery, thereby suppressing the diffusion effect of the sputtered metal layer. Meanwhile, the barrier layer 1062 adopts a columnar crystal structure, which enables rapid longitudinal transport of charge carriers and allows them to be laterally transported to the lower resistivity metal reflective layer 107, thereby reducing the series resistance Rser and increasing the fill factor FF. A preferred thickness of the modified functional layer 1061 is 10 nm. To control the overall thickness and volume of the battery, it is recommended to select the minimum thickness that meets electrical performance requirements.The preferred thickness of the barrier functional layer 1062 is 90 nm, which, while maintaining the overall thickness of the battery, prevents the sputtered metal layer from diffusing metal atoms into the battery with the highest possible thickness.

[0058] In other embodiments of this application, the indium-free conductive layer 106 may also be a composite structure film layer with other indium-free doping components. For example, the modified functional layer 1061 is a GZO (gallium-doped zinc oxide) layer or a GAZO (gallium-doped aluminum-doped zinc oxide) layer, formed by sputtering using a similar hydrogen-doped and oxygen-doped gas process. The stop functional layer 1062 is SnO2 and its doped film layer, formed by sputtering using a similar oxygen-doped gas process.

[0059] In some embodiments of this application, the front conductive layer 105 is still an ITO (indium tin oxide) layer with a thickness of 80-100 nm, providing good light transmittance and conductivity. The ITO layer is preferably 88 nm thick. The N-type substrate 101 has a thickness of 130-165 μm, preferably 140 μm, and its size is determined according to the cell size, for example, 166 mm × 166 mm. The intrinsic amorphous silicon passivation layer 102 has a thickness of 4-10 nm, serving to passivate the surface of the N-type substrate 101; its performance is positively correlated with Voc, and its thickness is preferably 9 nm. The N-type doped layer 103 has a thickness of 20-30 nm, preferably 20 nm. The P-type doped layer 104 has a thickness of 20-30 nm, preferably 25 nm. The N-type doped layer 103 and the P-type doped layer 104 form the electric field structure and emitter structure with the N-type substrate 101, respectively, satisfying the basis for the photovoltaic effect.

[0060] In some embodiments of this application, such as Figure 1 As shown, front electrode 110 and back electrode 109 are respectively printed on the outer sides of the front conductive layer 105 and the back conductive layer 30 to achieve current conduction. Both the front electrode 110 and the back electrode 109 are formed by silver paste printed using a chain screen printing machine. The front electrode 110 is a silver electrode with 12 main grid lines and 92 fine grid lines, and the back electrode 109 is a silver electrode with 12 main grid lines and 140 fine grid lines.

[0061] According to another aspect of this application, a method for manufacturing a heterojunction solar cell is provided, such as... Figure 2 and Figure 3 As shown, the method includes:

[0062] Step S1: Provide an N-type substrate 101 and perform cleaning and texturing on the N-type substrate 101. Through cleaning and texturing, a pyramidal textured structure suitable for deposition is formed on the surface of the N-type substrate 101, improving the bonding ability and thus enhancing the electrical performance and structural stability of the battery.

[0063] In step S2, a front-side battery structure 10 and a back-side battery structure 20 are deposited and fabricated on the front and back sides of the N-type substrate 101, respectively. This forms the structural basis for realizing the photovoltaic effect.

[0064] Step S3: A transparent conductive layer is deposited on the front battery structure 10 to form a front conductive layer 105. The front conductive layer 105 is used to enable carrier outflow and incident light transmission.

[0065] In step S4, an indium-free conductive layer 106, a metal reflective layer 107, and a dense protective layer 108 are successively deposited on the back battery structure 20 to form a composite structure back conductive layer 30. The indium-free conductive layer 106 replaces the ITO layer at low cost, reducing battery cost. The metal reflective layer 107 is directly sputtered onto the indium-free conductive layer 106, providing enhanced light reflection to improve battery efficiency, while also enhancing ohmic connection and reducing battery series internal resistance. The dense protective layer 108 covers the back of the battery, preventing moisture and oxygen intrusion through its dense structure, thus improving the battery's oxidation resistance and stability.

[0066] In some embodiments of this application, step S4, depositing the indium-free conductive layer 106, includes depositing a modified functional layer 1061 and a barrier functional layer 1062 sequentially with different doping concentrations to form a composite structure of the indium-free conductive layer 106. The modified functional layer 1061 is generated using magnetron sputtering in an Ar, O2, and H2 environment. The magnetron sputtering DC power density is 4-6 kW / m², the rotating target composition is ZnO:Al2O3 = 98:2, the temperature is 150-190°C, the pressure is 0.5-1.1 Pa, the oxygen-argon ratio is 0.15%-0.5%, the hydrogen-argon ratio is 0.1%-0.3%, the water vapor partial pressure is below 8.0E-8 mbar, and the magnetron sputtering film thickness is 10-20 nm. A high aluminum doping concentration can improve the carrier transport capability of the modified functional layer 1061. Preferably, the sputtering thickness of the modified functional layer 1061 is 10, 11, 12, 13, 14 or 15 nm.

[0067] The barrier layer 1062 is formed using magnetron sputtering in an Ar and O2 environment. The magnetron sputtering DC power density is 4-6 kW / m², the rotating target composition is ZnO:Al₂O₃ = 99.9:0.1, the temperature is 150-190℃, the pressure is 0.8-1.1 Pa, the oxygen-argon ratio is 0.3%-0.8%, the water vapor partial pressure is below 8.0E-8 mbar, and the magnetron sputtering coating thickness is 80-90 nm. The barrier layer 1062 needs to have sufficient thickness to meet the bonding requirements of the metal sputtered layer while suppressing the influence of metal atom diffusion on the battery interior. Preferably, the sputtering thickness of the barrier layer 1062 is 86, 87, 88, 89, or 90 nm.

[0068] In some embodiments of this application, in step S4, the metal reflective layer 107 is generated by magnetron sputtering in an Ar environment. The magnetron sputtering DC power supply has a power density of 4-6 kW / m, the rotating target is a copper target, the temperature is 150-190°C, the pressure is 0.3-1.1 Pa, the water vapor partial pressure is below 8.0E-8 mbar, the oxygen partial pressure is below 1.0E-9 mbar, and the magnetron sputtering coating thickness is 50-100 nm, preferably 95, 96, 97, 98, 99 or 100 nm.

[0069] The dense protective layer 108 is generated by magnetron sputtering in an Ar environment. The power density of the DC power supply for magnetron sputtering is 4-6 kW / m. The rotating target composition is Cr:Ni=20:80. The temperature is 150-190℃, the pressure is 0.3-1.1 Pa, the water vapor partial pressure is below 8.0E-8 mbar, the oxygen partial pressure is below 1.0E-9 mbar, and the thickness of the magnetron sputtered coating is 30-50 nm, preferably 46, 47, 48, 49 or 50 nm.

[0070] In some embodiments of this application, step S1, cleaning and texturing the N-type substrate 101, includes: cleaning with potassium hydroxide solution to initially remove the mechanically damaged layer; using a tube diffusion furnace for phosphorus diffusion and gettering at a temperature of 600-800°C; using a chain pickling machine and hydrofluoric acid solution to remove the phosphosilicate glass (PSG) layer; using a potassium hydroxide etchant for anisotropic etching to obtain a pyramid structure; then using a nitric acid / hydrofluoric acid solution to round the pyramid structure; and finally cleaning with a wet chemical cleaning method (RCA) to obtain a double-textured N-type substrate 101.

[0071] In some embodiments of this application, such as Figure 3 As shown, the method further includes step S5, which involves screen printing a front electrode 110 and a back electrode 109 onto the front conductive layer 105 and the back conductive layer 30, respectively.

[0072] In some embodiments of this application, step S2 involves depositing and fabricating a front-side battery structure 10 and a back-side battery structure 20 on the front and back sides of the N-type substrate 101, respectively. Specifically, step S21 involves using PECVD (chemical vapor deposition) at a 40MHz VHF power supply, 180-200℃, and 0.5-5mbar pressure to deposit an intrinsic amorphous silicon passivation layer 102 with a thickness of 4-10nm on the front and back sides of the N-type substrate 101, respectively. Step S22 involves using PECVD (chemical vapor deposition) to deposit... In step S23, using a PECVD (chemical vapor deposition) process, under conditions of a 40MHz VHF power supply, 180-200℃, and 0.5-5mbar pressure, SiH4, H2, PH3, and CO2 are introduced to deposit an N-type doped layer 103 with a thickness of 20-30nm.

[0073] In some embodiments of this application, in step S3, a transparent conductive layer is deposited on the front battery structure 10 to form a front conductive layer 105. Specifically, this includes: using a PVD (physical vapor deposition) magnetron sputtering process, under the conditions of DC power density of 4-6 kW / m, ITO rotating target, 150-190°C, 0.5-1.1 Pa pressure, oxygen-argon ratio of 0.9%-2%, hydrogen-argon ratio of 0.6%-0.9%, and water vapor partial pressure of 1.0E-7~2.0E-6 mbar, Ar, O2, H2, and H2O are introduced to deposit an ITO layer with a thickness of 80-100 nm.

[0074] In some embodiments of this application, step S5 specifically includes: step S51, using a chain screen printing device to print low-temperature silver paste onto the surface of a dense protective layer 108 (such as a Cr / Ni base layer) through a screen, and then heating it in a chain curing oven at 170-190°C for 15-20 minutes to volatilize the organic filler to form a back electrode 109, which has 12 main grid lines and 140 fine grid lines, forming good ohmic contact with the metal layer; step S52, using a chain screen printing device to print low-temperature silver paste onto the surface of a front conductive layer 105 (such as an ITO layer) through a screen, and then heating it in a chain curing oven at 170-190°C for 15-20 minutes to volatilize the organic filler to form a back electrode 109, which has 12 main grid lines and 92 fine grid lines, forming good ohmic contact with the metal layer. Since the outer metal layer on the back of the battery in this application has good conductivity, the back electrode 109 can be designed to reduce the number of stencils for printing fine grids, thereby reducing the silver consumption of the back electrode 109 compared to existing common battery structures and further reducing costs.

[0075] Example 1

[0076] This application provides a heterojunction solar cell according to the above method, which is manufactured through the following steps:

[0077] (1) An N-type single crystal silicon wafer with a size of 166mm×166mm and a thickness of 140μm was selected as the substrate. The silicon wafer was cleaned with KOH solution to remove the mechanical damage layer. Then it was phosphorus diffused and gotted in a tube diffusion furnace at 800℃. Then it was cleaned with HF solution in a chain pickling machine to remove PSG. Then it was anisotropically etched in KOH solution to obtain a pyramid structure with surface light trapping. Then the pyramid structure was rounded by HF / HNO3 solution. Finally, it was cleaned by RCA method to obtain a double-sided textured N-type substrate 101.

[0078] (2) Intrinsic amorphous silicon passivation layers 102 were prepared on the two surfaces of the N-type substrate 101 using PECVD process. The PECVD equipment used a very high frequency power supply of 40MHz, process gases of SiH4 and H2, a deposition temperature of 200℃, a deposition pressure of 1mbar, and the thickness of the intrinsic amorphous silicon passivation layer 102 was 9nm.

[0079] (3) An N-type doped layer 103 with P is deposited on the intrinsic amorphous silicon passivation layer 102 on the front side using PECVD process. The PECVD equipment uses a very high frequency power supply of 40MHz, process gases of SiH4, H2, PH3 and CO2, deposition temperature of 200℃, deposition pressure of 1mbar, and the thickness of the N-type doped layer 103 is 20nm.

[0080] (4) A BP-type doped layer 104 is deposited on the intrinsic amorphous silicon passivation layer 102 on the back side using PECVD process. The PECVD equipment uses a very high frequency power supply of 40MHz, process gases of SiH4, H2, B2H6 and CO2, deposition temperature of 200℃, deposition pressure of 1mbar, and the thickness of the BP-type doped layer 104 is 25nm.

[0081] (5) A front conductive layer 105 ITO layer was deposited on the N-type doped layer 103 using PVD magnetron sputtering process. The PVD equipment used DC power supply, power density 5kw / m, 99 / 1 doped ITO rotating target, process gases Ar, O2, H2 and H2O, coating temperature 150℃, sputtering pressure 1.0Pa, oxygen-argon ratio 1.0%, hydrogen-argon ratio 0.6%, water vapor partial pressure 1.0E-6mbar, and the thickness of the front conductive layer 105 was 88nm.

[0082] (6) A modified functional layer 1061 AZO layer was deposited on the p-type doped layer 104 using PVD magnetron sputtering. The PVD process used DC power supply, power density of 5 kW / m, AZO (ZnO:Al2O3=98:2) rotating target, process gases Ar, O2 and H2, coating temperature of 150 °C, sputtering pressure of 0.6 Pa, oxygen-argon ratio of 0.4%, hydrogen-argon ratio of 0.1%, water vapor partial pressure of 4.0E-8 mbar, and the thickness of the modified functional layer 1061 was 10 nm.

[0083] (7) A barrier functional layer 1062 AZO layer was deposited on the modified functional layer 1061 using PVD magnetron sputtering process. The PVD equipment used DC power supply, power density 5kw / m, AZO (ZnO:Al2O3=99.9:0.1) rotating target, process gases Ar and O2, coating temperature 150℃, sputtering pressure 0.9Pa, oxygen-argon ratio 0.8%, water vapor partial pressure 4.0E-8mbar, and the thickness of barrier functional layer 1062 was 90nm.

[0084] (8) A reflective metal layer was deposited on the barrier functional layer 1062 using PVD magnetron sputtering process. The PVD equipment used DC power supply, power density 5kw / m, Cu rotating target, process gas Ar, coating temperature 150℃, sputtering pressure 0.3Pa, water vapor partial pressure 4.0E-8mbar, oxygen partial pressure 1.0E-9mbar, and the thickness of the reflective metal layer was 100nm.

[0085] (9) A dense protective layer 108 is deposited on the reflective metal layer using PVD magnetron sputtering process. The PVD equipment uses DC power supply, power density of 5kw / m, Cr / Ni (Cr:Ni=20:80) rotating target, process gas Ar, coating temperature of 150℃, sputtering pressure of 0.3Pa, water vapor partial pressure of 4.0E-8mbar, oxygen partial pressure of 1.0E-9mbar, and the thickness of the dense protective layer 108 is 50nm.

[0086] (10) Using a chain screen printing machine, low-temperature silver paste is printed onto the surface of the dense protective layer 108 through a screen to prepare the back electrode 109. The metallized pattern has 12 main grid lines and 140 fine grid lines. After being heated at 190°C in a chain curing oven for 20 minutes, the organic filler is volatilized, so that the back electrode 109 and the dense protective layer 108 form a good ohmic contact.

[0087] (11) Low-temperature silver paste is printed onto the surface of the front conductive layer 105 using a chain screen printing machine to prepare the front electrode 110. The metallized pattern has 12 main grid lines and 92 fine grid lines. After heating at 190°C in a chain curing oven for 20 minutes, the organic filler is volatilized, so that the front electrode 110 and the front conductive layer 105 form a good ohmic contact.

[0088] Comparison Example

[0089] This application uses an existing high-cost dual-ITO structure heterojunction solar cell as a comparative example, and its specific fabrication method is as follows:

[0090] (1) An N-type single crystal silicon wafer with a size of 166mm×166mm and a thickness of 140μm was selected as the substrate. The original silicon wafer was initially cleaned with KOH solution to remove the mechanical damage layer. It was then phosphorus diffused and gotted in a tube diffusion furnace at 800℃. After that, it was removed from the PSG by HF solution in a chain acid pickling machine. Then, it was anisotropically etched in KOH and additive solution to obtain a pyramid structure with surface light trapping. The pyramid was then rounded by HF / HNO3 acid solution. Finally, it was cleaned by RCA method to obtain a double-sided textured N-type substrate 101.

[0091] (2) Intrinsic amorphous silicon passivation layers 102 (a-Si:H layers) were prepared on two surfaces of a silicon substrate using PECVD process. The PECVD equipment used a very high frequency power supply of 40MHz, process gases of SiH4 and H2, a deposition temperature of 200℃, and a deposition pressure of 1mbar. The thickness of the intrinsic amorphous silicon passivation layer 102 was 9nm.

[0092] (3) A P-doped N-type doped layer 103 (n-μc-SiOx:H layer) was deposited on the intrinsic amorphous silicon passivation layer 102 on the front side using PECVD process. The PECVD equipment used a very high frequency power supply of 40MHz, process gases of SiH4, H2, PH3, and CO2, a deposition temperature of 200℃, a deposition pressure of 1mbar, and the thickness of the N-type doped layer 103 was 20nm.

[0093] (4) A B-doped P-type doped layer 104 (p-μc-SiOx:H layer) was deposited on the intrinsic amorphous silicon passivation layer 102 on the back side using PECVD process. The PECVD equipment used a very high frequency power supply of 40MHz, process gases of SiH4, H2, B2H6, and CO2, a deposition temperature of 200℃, a deposition pressure of 1mbar, and the thickness of the P-type doped layer 104 was 25nm.

[0094] (5) A front-side ITO layer was deposited on the N-type doped layer 103 using PVD magnetron sputtering. The PVD equipment used DC power supply, power density of 5kw / m, 99 / 1 ITO doped rotating target, process gases Ar, O2, H2, H2O, coating temperature of 150℃, sputtering pressure of 1.0Pa, oxygen-argon ratio of 1.0%, hydrogen-argon ratio of 0.6%, water vapor partial pressure of 1.0E-6mbar, and the thickness of the front-side ITO layer was 88nm.

[0095] (6) A back-side ITO layer was deposited on the P-type doped layer 104 using PVD magnetron sputtering. The PVD equipment used a DC power supply, a power density of 5 kW / m, a 99 / 1 ITO doped rotating target, process gases Ar, O2, H2, and H2O, a coating temperature of 150°C, a sputtering pressure of 0.6 Pa, an oxygen-argon ratio of 1.2%, a hydrogen-argon ratio of 0.6%, a water vapor partial pressure of 1.0E-6 mbar, and a back-side ITO layer thickness of 100 nm (this thickness is the same as that of the AZO bilayer composite structure in Example 1 of this application).

[0096] (7) Using a chain screen printing machine, low-temperature silver paste is printed onto the surface of the back ITO layer through a screen to prepare the back electrode 109. The metallization pattern has 12 main grid lines and 140 fine grid lines. After being heated in a chain curing furnace at 190°C for 20 minutes, the organic filler is volatilized, so that the back electrode 109 and the back ITO layer form a good ohmic contact.

[0097] (8) Using a chain screen printing machine, low-temperature silver paste is printed onto the surface of the front ITO layer through a screen to prepare the front electrode 110. The metallization pattern has 12 main grid lines and 92 fine grid lines. After being heated in a chain curing furnace at 190°C for 20 minutes, the organic filler is volatilized, so that the front electrode 110 and the front ITO layer form a good ohmic contact.

[0098] The performance of the heterojunction solar cell of Embodiment 1 of this application and the dual ITO structure heterojunction solar cell of the comparative example were tested, and the test results are shown in the table below.

[0099]

[0100] Table 1 Battery performance test results

[0101] The test results above show that the performance parameters of Embodiment 1 of this application and the existing high-cost bifacial ITO heterojunction cells all meet the electrical performance requirements. Furthermore, the battery in Embodiment 1 of this application has a smaller series resistance Rser, and larger short-circuit current Isc, photocurrent density Jsc, open-circuit voltage Voc, and fill factor FF, resulting in higher battery efficiency. Therefore, this application provides a heterojunction solar cell suitable for BIPV single-sided light-receiving scenarios, which can replace existing bifacial ITO cell solutions at a low cost, improving efficiency for building-integrated photovoltaic applications and facilitating the promotion and application of heterojunction cells in the civilian photovoltaic industry.

[0102] In summary, the heterojunction solar cell of this application overcomes the problems of high cost of existing bifacial ITO and poor stability of single indium-free conductive film. It uses a composite film structure to directly integrate the back reflector with the cell. The composite film structure on the back of the cell combines an indium-free conductive layer, a metal reflective layer, and a dense protective layer. By replacing the indium-containing conductive film with an indium-free conductive layer, the production cost of the cell is reduced. Simultaneously, a metal reflective layer is directly sputtered onto the indium-free conductive layer, achieving good ohmic connection while reflecting light, improving the cell's series resistance and fill factor. Furthermore, a dense protective layer is sputtered outside the metal reflective layer, improving the cell's oxidation and corrosion resistance. This protects the metal reflective layer and the indium-free conductive layer from oxidation and inhibits moisture penetration into the indium-free conductive layer, thereby stabilizing the cell's electrical performance, reducing the cell's degradation rate, and significantly improving the cell's quality and lifespan.

[0103] In a preferred embodiment of this application, based on the principle of small lattice mismatch in similar thin films, indium-free conductive layers are prepared by selecting AZO layers with different doping concentrations. The interface of the P-type doped layer is modified using a high-aluminum-doped functional layer. The high carrier concentration interface increases the carrier tunneling capability and improves the transport capacity. A low-aluminum, high-thickness barrier functional layer is used to achieve a good transition to the metal reflective layer. While improving the bonding quality of the metal reflective film by using columnar crystal layer inlay, the longitudinal carrier transport capacity is improved, and the diffusion effect of metal atoms is overcome, thus achieving better battery electrical performance and stability.

[0104] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A heterojunction solar cell, characterized by, The application relates to a solar cell, which comprises: an N-type substrate (101) having a front surface and a back surface oppositely arranged; a front cell structure (10) located on the front surface of the N-type substrate (101) and comprising an intrinsic amorphous silicon passivation layer (102) and an N-type doped layer (103); a back cell structure (20) located on the back surface of the N-type substrate (101) and comprising an intrinsic amorphous silicon passivation layer (102) and a P-type doped layer (104); a front conductive layer (105) covering the front cell structure (10); a back conductive layer (30) covering the back cell structure (20); wherein the front conductive layer (105) is a transparent conductive layer; the back conductive layer (30) is a composite reflective conductive layer, which comprises an indium-free conductive layer (106) in direct contact with the P-type doped layer (104), a metal reflective layer (107) sputtered on the indium-free conductive layer (106), and a dense protective layer (108) sputtered on the metal reflective layer (107), the dense protective layer (108) and the metal reflective layer (107) being metal film layers of different substrates; the atomic arrangement of the dense protective layer (108) is denser than that of the metal reflective layer (107); the thickness of the metal reflective layer (107) is 50-100 nm, and the thickness of the dense protective layer (108) is 30-50 nm.

2. The heterojunction solar cell according to claim 1, characterized in that, The metal reflective layer (107) is a Cu, Ag, Pt, Al, Cu / Zn or alloy-based layer; and the dense protective layer (108) is an Ag, Pt, Ni, Cr, Sn or alloy-based layer.

3. The heterojunction solar cell according to claim 1, wherein The indium-free conductive layer (106) is an AZO film layer of a composite structure, which comprises a modified functional layer (1061) in direct contact with the P-type doped layer (104) and a blocking functional layer (1062) covering the modified functional layer (1061); the thickness of the modified functional layer (1061) is 10-20 nm, the thickness of the blocking functional layer (1062) is 80-90 nm, the aluminum doping concentration of the modified functional layer (1061) is higher than that of the blocking functional layer (1062); the modified functional layer (1061) and the blocking functional layer (1062) are both formed by a magnetron sputtering process, and the modified functional layer (1061) is sputtered under a hydrogen environment and a lower oxygen / argon ratio condition relative to the blocking functional layer (1062).

4. The heterojunction solar cell according to claim 3, characterized in that, The front conductive layer (105) is an ITO layer with a thickness of 80-100 nm, the thickness of the N-type substrate (101) is 130-165 mu m, the thickness of the intrinsic amorphous silicon passivation layer (102) is 4-10 nm, the thickness of the N-type doped layer (103) is 20-30 nm, and the thickness of the P-type doped layer (104) is 20-30 nm.

5. The heterojunction solar cell according to any one of claims 1 to 4, characterized in that, The outer side of the front conductive layer (105) and the back conductive layer (30) is respectively printed with a front electrode (110) and a back electrode (109).

6. A method for manufacturing a heterojunction solar cell, characterized by, Comprise: Step S1, providing an N-type substrate (101), cleaning and texturing the N-type substrate (101); Step S2, depositing a front cell structure (10) and a back cell structure (20) on the front and back of the N-type substrate (101) respectively; Step S3, depositing a transparent conductive layer on the front cell structure (10) to form a front conductive layer (105); Step S4, depositing an indium-free conductive layer (106), a metal reflection layer (107) and a dense protective layer (108) on the back cell structure (20) in sequence to form a composite back conductive layer (30); the dense protective layer (108) and the metal reflection layer (107) are metal thin film layers of different substrates; the atomic arrangement of the dense protective layer (108) is more dense than that of the metal reflection layer (107); the thickness of the metal reflection layer (107) is 50-100nm, and the thickness of the dense protective layer (108) is 30-50nm.

7. The heterojunction solar cell manufacturing method according to claim 6, wherein In step S4, depositing the indium-free conductive layer (106) comprises: depositing a modification functional layer (1061) and a blocking functional layer (1062) in sequence with different doping concentrations to form a composite indium-free conductive layer (106); wherein, The modification functional layer (1061) is generated by magnetron sputtering process, the sputtering environment is Ar, O2 and H2 environment, the magnetron sputtering direct current power density is 4-6kw / m, the rotating target material component is ZnO:Al2O3=98:2, the temperature is 150-190℃, the pressure is 0.5-1.1Pa, the oxygen to argon ratio is 0.15%-0.5%, the hydrogen to argon ratio is 0.1%-0.3%, the water vapor partial pressure is 8.0E-8mbar or less, and the magnetron sputtering film thickness is 10-20nm; The blocking functional layer (1062) is generated by magnetron sputtering process, the sputtering environment is Ar and O2 environment, the magnetron sputtering direct current power density is 4-6kw / m, the rotating target material component is ZnO:Al2O3=99.9:0.1, the temperature is 150-190℃, the pressure is 0.8-1.1Pa, the oxygen to argon ratio is 0.3%-0.8%, the water vapor partial pressure is 8.0E-8mbar or less, and the magnetron sputtering film thickness is 80-90nm.

8. The heterojunction solar cell manufacturing method according to claim 6, wherein In step S4, the metal reflection layer (107) is generated by magnetron sputtering process, the sputtering environment is Ar environment, the magnetron sputtering direct current power density is 4-6kw / m, the rotating target material is copper target material, the temperature is 150-190℃, the pressure is 0.3-1.1Pa, the water vapor partial pressure is 8.0E-8mbar or less, the oxygen partial pressure is 1.0E-9mbar or less, and the magnetron sputtering film thickness is 50-100nm; The compact protective layer (108) is generated by a magnetron sputtering process in an Ar environment, the magnetron sputtering direct current power density is 4-6 kw / m, the rotating target material component is Cr:Ni=20:80, the temperature is 150-190℃, the pressure is 0.3-1.1 Pa, the water vapor partial pressure is below 8.0E-8 mbar, the oxygen partial pressure is below 1.0E-9 mbar, and the magnetron sputtering film thickness is 30-50 nm.

9. The heterojunction solar cell manufacturing method according to claim 6, wherein In the step S1, the cleaning and texturing treatment of the N-type substrate (101) includes: using a potassium hydroxide solution to wash to remove a mechanical damage layer, using a tube diffusion furnace to phosphorus diffusion at a temperature of 600-800℃, using a chain type pickling machine and a hydrofluoric acid solution to remove a phosphor-silicon glass layer, using a potassium hydroxide etching solution to perform anisotropic etching to obtain a pyramid structure, then performing a rounding treatment on the pyramid structure by using a nitric acid / hydrofluoric acid solution, and finally performing a wet chemical cleaning method to obtain a double-sided textured N-type substrate (101).

10. The heterojunction solar cell manufacturing method according to claim 6, wherein The method further includes: a step S5, screen printing a front electrode (110) and a back electrode (109) on the front conductive layer (105) and the back conductive layer (30) respectively.

Images