Solar cell and preparation method thereof, photovoltaic module and photovoltaic system
By forming a self-assembled molecular layer on the surface of the transparent conductive oxide layer, selective electroplating is achieved, and the problem of insufficient metallized gate line forming accuracy of solar cells is solved, thereby improving battery performance and reducing costs.
Patent Information
- Application Number
- CN202411267954.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-11
- Publication Date
- 2024-12-20
AI Technical Summary
The prior art cannot meet the market's requirements for the formation accuracy of metallized gate lines of solar cells. The traditional method increases the process and printing time, destroys the thin-sheeted silicon wafer structure, and increases the light shielding loss and metallization cost.
A self-assembled molecular layer is formed on the surface of the transparent conductive oxide layer, and high-precision forming of metal gate lines is achieved through selective electroplating. The self-assembled molecular layer hinders the migration of plating ions and ensures that electrodeposition is only carried out in the area to be plating.
The forming accuracy of the metal gate wire structure is improved, production costs are reduced, and the performance of solar cells is improved.
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Figure CN119170671A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof, a photovoltaic module and a photovoltaic system. Background Art
[0002] With the expansion of solar cell production such as tunneling oxide passivation contact (TOPCON) and crystalline silicon heterojunction solar cells (HJT), the battery applications are increasing, and are more and more applied to the field of precision industry. How to improve the forming accuracy of the battery is a hot topic of research today. The metallization link is an important process in the production of photovoltaic cells. It is mainly used to make the electrode grid line of the battery. By closely combining the electrode with the battery cell, an efficient ohmic contact is formed to achieve current output.
[0003] At present, electroplating has gradually become a hot spot for solar cell metallization. However, current technical means still cannot meet the market's requirements for grid line forming accuracy. The traditional method of improving the forming accuracy of conductive grid lines is to use a prefabricated imprinting template and multiple transfer methods. This method increases the process and printing time, reduces production efficiency, and because this method adds a pre-treatment process, it is easy to damage the structure of the thin silicon wafer. In addition, during the electroplating process, the forming accuracy of the grid line is low, and the grid line width needs to be increased, thereby increasing the shading loss and increasing the metallization cost. Summary of the invention
[0004] The embodiments of the present application provide a solar cell and a method for preparing the same, a photovoltaic module, and a photovoltaic system to solve or alleviate the above technical problems. The solar cell of the embodiments of the present application can reduce production costs and improve the forming accuracy of the metal grid structure, thereby improving the performance of the device.
[0005] In a first aspect, an embodiment of the present application provides a method for preparing a solar cell, comprising:
[0006] Providing an n-type single crystal silicon substrate;
[0007] forming a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer in sequence on the upper surface of the n-type single crystal silicon substrate, and forming a second intrinsic amorphous silicon layer and an n-type amorphous silicon layer in sequence on the lower surface of the n-type single crystal silicon substrate;
[0008] forming a transparent conductive oxide layer on a surface of the p-type amorphous silicon layer and / or a surface of the n-type amorphous silicon layer;
[0009] forming a patterned seed layer on the surface of the transparent conductive oxide layer;
[0010] forming a self-assembled molecular layer on a surface of the transparent conductive oxide layer and a surface of the seed layer;
[0011] The seed layer is metallized, and a portion of the self-assembled molecular layer located at the periphery of the seed layer is removed, so as to form a metal grid line at the periphery of the seed layer. Optionally, the transparent conductive oxide layer includes one or more of indium tin oxide, indium zinc oxide, tungsten-doped indium oxide, fluorine-doped tin oxide, cerium-doped indium oxide, aluminum-doped zinc oxide, and boron-doped zinc oxide.
[0012] Optionally, forming a patterned seed layer on the surface of the transparent conductive oxide layer includes:
[0013] The seed layer is formed on the surface of the transparent conductive oxide layer by using a patterned mask.
[0014] Optionally, the seed layer is a silver seed layer or a copper seed layer, and the thickness of the seed layer is 20-500 nm.
[0015] Optionally, forming a self-assembled molecular layer on the surface of the transparent conductive oxide layer and the surface of the seed layer includes:
[0016] The n-type single crystal silicon substrate on which the seed layer is formed is immersed in an octadecyltrichlorosilane solution to form a self-assembled molecular layer on the surface of the transparent conductive oxide layer and the surface of the seed layer.
[0017] Optionally, the concentration of the octadecyltrichlorosilane solution is 10-70%; the solvent of the octadecyltrichlorosilane solution is one or more of water, ethanol and ether.
[0018] Optionally, the thickness of the self-assembled molecular layer is 50-200 nm.
[0019] Optionally, metallizing the seed layer includes:
[0020] The n-type single crystal silicon substrate forming the self-assembled molecular layer is placed in an electroplating solution, and a voltage or current is applied to metallize the seed layer; wherein the voltage is 6-12V; and the current is 5-10A.
[0021] Optionally, after forming the metal grid lines, the method for preparing the solar cell further comprises: forming a protective layer on the surface of the metal grid lines.
[0022] Optionally, the protective layer is a tin electroplating layer or a silver electroplating layer.
[0023] In a second aspect, an embodiment of the present application provides a solar cell, which is prepared by any of the above-mentioned methods for preparing a solar cell.
[0024] In a third aspect, an embodiment of the present application provides a photovoltaic assembly, comprising: at least one battery string, wherein the battery string comprises at least two of the above-mentioned solar cells.
[0025] In a fourth aspect, an embodiment of the present application provides a photovoltaic system, comprising the above-mentioned photovoltaic assembly.
[0026] The above technical solution adopted in the embodiment of the present application may have the following advantages:
[0027] In the embodiment of the present application, a self-assembled molecular layer is formed on the surface of the transparent conductive oxide layer and the surface of the seed layer. The self-assembled molecular layer can hinder the migration of electroplating ions to the transparent conductive oxide layer, thereby achieving selective electroplating, so that electrodeposition only occurs in the seed layer area to be electroplated, thereby improving the forming accuracy of the metal grid line structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.
[0029] Figure 1 This is a schematic diagram of the structure of a solar cell during the preparation process provided in the embodiment of the present application. Figure 1 ;
[0030] Figure 2 This is a schematic diagram of the structure of a solar cell during the preparation process provided in the embodiment of the present application. Figure 2 ;
[0031] Figure 3 This is a schematic diagram of the structure of a solar cell during the preparation process provided in the embodiment of the present application. Figure 3 ;
[0032] Figure 4 This is a schematic diagram of the structure of a solar cell during the preparation process provided in the embodiment of the present application. Figure 4 ;
[0033] Figure 5 This is a schematic diagram of the structure of a solar cell during the preparation process provided in the embodiment of the present application. Figure 5 ;
[0034] Figure 6 This is a schematic diagram of the structure of a solar cell during the preparation process provided in the embodiment of the present application. Figure 6 ;
[0035] Figure 7 This is a schematic diagram of the structure of a solar cell during the preparation process provided in the embodiment of the present application. Figure 7 ;
[0036] Figure 8This is a schematic diagram of the structure of a solar cell during the preparation process provided in the embodiment of the present application. Figure 8 .
[0037] Description of reference numerals:
[0038] 1. n-type single crystal silicon substrate; 2. first intrinsic amorphous silicon layer; 3. p-type amorphous silicon layer; 4. second intrinsic amorphous silicon layer; 5. n-type amorphous silicon layer; 6. transparent conductive oxide layer; 7. seed layer; 8. self-assembled molecular layer; 9. metal gate line; 10. protective layer. DETAILED DESCRIPTION
[0039] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
[0040] The present application will describe the exemplary embodiments according to the present application in more detail with reference to the accompanying drawings. It should be noted that these exemplary embodiments can be implemented in many different forms and should not be construed as being limited to the embodiments described herein.
[0041] like Figure 1-Figure 8 As shown, the embodiment of the present application provides a method for preparing a solar cell, comprising:
[0042] S101: Figure 1 As shown, an n-type single crystal silicon substrate 1 is provided.
[0043] In the embodiment of the present application, the provided n-type single crystal silicon substrate may also be subjected to the following treatments: pre-cleaning, silicon wafer gettering, and texturing cleaning.
[0044] In an optional embodiment, the n-type single crystal silicon substrate is a double-sided velvet surface, and the shapes of the velvet surfaces on both sides are independently pyramid-shaped, the length of the pyramid shape is 1.4-1.6μm, the width of the pyramid shape is 1.4-1.6μm, and the height of the pyramid shape is 0.8-1.2μm. The pyramid-shaped velvet surface can increase the area of the velvet surface and improve the light absorption effect.
[0045] S102: Figure 1 As shown, a first intrinsic amorphous silicon layer 2 and a p-type amorphous silicon layer 3 are sequentially formed on the upper surface of an n-type single crystal silicon substrate 1, and a second intrinsic amorphous silicon layer 4 and an n-type amorphous silicon layer 5 are sequentially formed on the lower surface of the n-type single crystal silicon substrate 1.
[0046] In an optional embodiment, the total thickness of the p-type amorphous silicon layer and the first intrinsic amorphous silicon layer is 20-60 nm, and the total thickness of the n-type amorphous silicon layer and the second intrinsic amorphous silicon layer is 20-60 nm. The p-type amorphous silicon layer, the first intrinsic amorphous silicon layer, the second intrinsic amorphous silicon layer and the n-type amorphous silicon layer can be prepared by low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD) and other methods.
[0047] S103: Figure 2 As shown, a transparent conductive oxide layer 6 is formed on the surface of the p-type amorphous silicon layer 3 and / or the surface of the n-type amorphous silicon layer 5 .
[0048] In an optional embodiment, the transparent conductive oxide layer includes one or more of indium tin oxide (ITO), indium zinc oxide (IZO), tungsten-doped indium oxide (IWO), fluorine-doped tin oxide (FTO), cerium-doped indium oxide (ICO), aluminum-doped zinc oxide (AZO), and boron-doped zinc oxide (BZO). The transparent conductive oxide layer can be prepared by vacuum evaporation, magnetron sputtering, atomic layer deposition, chemical vapor deposition, ion beam deposition, pulsed laser deposition, spin coating, scraping, 3D printing, printing, spraying, etc. The thickness of the transparent conductive oxide layer can be 10-150nm.
[0049] In practical applications, the transparent conductive oxide layer may be formed only on the surface of the p-type amorphous silicon layer, or only on the surface of the n-type amorphous silicon layer, or on the surface of the p-type amorphous silicon layer and the surface of the n-type amorphous silicon layer, respectively. When the transparent conductive oxide layer is formed on the surface of the p-type amorphous silicon layer and the surface of the n-type amorphous silicon layer, respectively, different deposition processes may be used to form the transparent conductive oxide layer, or the same deposition process may be used to form the transparent conductive oxide layer.
[0050] S104: Figure 3 As shown, a patterned seed layer 7 is formed on the surface of the transparent conductive oxide layer 6 .
[0051] In an optional embodiment, a patterned seed layer 7 is formed on the surface of the transparent conductive oxide layer 6 using a patterned mask. The mask is a high temperature resistant mask. Since the mask is patterned, in the process of forming the patterned seed layer, the mask can shield the area corresponding to the non-metallic grid lines on the transparent conductive oxide layer, and expose the area corresponding to the metal grid lines to be formed. In this way, it is possible to form a patterned seed layer only in the area to be electroplated (the area of the metal grid lines to be formed) of the transparent conductive oxide layer, and no seed layer is formed in the area corresponding to the non-metallic grid lines due to the shielding of the mask. After the patterned seed layer is formed, the mask is removed. Therefore, the use of a patterned mask to prepare the seed layer does not require exposure, development, seed layer etching and other processes, the process is simpler, and the cost of electroplating is reduced.
[0052] The seed layer can be deposited on the surface of the transparent conductive oxide layer by physical vapor deposition (PVD), reactive plasma deposition (RPD) or plasma enhanced chemical vapor deposition (PECVD). In addition, since both sides of the silicon substrate may need to be coated to form a seed layer, the seed layers on both sides can be formed by different processes or by the same process.
[0053] In an optional embodiment, the seed layer is a silver seed layer or a copper seed layer, that is, the material of the seed layer is silver or copper. In an optional embodiment, the thickness of the seed layer is 20-500 nm.
[0054] S105: Figure 4 As shown, a self-assembled molecular layer 8 is formed on the surface of the transparent conductive oxide layer 6 and the surface of the seed layer 7 .
[0055] In an optional embodiment, forming a self-assembled molecular layer 8 on the surface of the transparent conductive oxide layer 6 and the surface of the seed layer 7 includes: immersing the n-type single crystal silicon substrate 1 forming the seed layer 7 in an octadecyl trichlorosilane solution, and forming a self-assembled molecular layer 8 on the surface of the transparent conductive oxide layer 6 and the surface of the seed layer 7. The immersion time can be 5-20 minutes, and the thickness of the self-assembled molecular layer can be 50-200nm. The concentration of the octadecyl trichlorosilane solution can be 10-70%. The solvent of the octadecyl trichlorosilane solution can be one or more of water, ethanol, and ether.
[0056] S106: Figure 5 As shown, the seed layer 7 is metallized, and part of the self-assembled molecular layer 8 located at the periphery of the seed layer 7 is removed, and a metal grid line 9 is formed at the periphery of the seed layer.
[0057] In an optional embodiment, if Figure 5 As shown, the seed layer 7 is metallized by electroplating process. Specifically, the n-type single crystal silicon substrate 1 forming the self-assembled molecular layer 8 is placed in the electroplating solution, and voltage or current is applied. The part of the self-assembled molecular layer 8 located at the periphery of the seed layer 7 is removed, and a metal grid line 9 is formed at the periphery of the seed layer 7, and the part of the self-assembled molecular layer 8 away from the seed layer 7 is left. The voltage can be 6-12V; the current can be 5-10A. The thickness of the metal grid line can be 6-7μm. The electroplating solution can be one of silver sulfate or copper sulfate.
[0058] The self-assembled molecular layer formed by the octadecyltrichlorosilane solution can hinder the migration of electroplating ions to the transparent conductive oxide layer, realize selective electroplating, and make the electrodeposition occur only in the seed layer area to be electroplated, thereby improving the forming accuracy of the metal grid line structure.
[0059] In an optional embodiment, before electroplating to form metal grid lines, the surface of the seed layer needs to be cleaned, and acid washing can be performed first and then water washing to remove the oxide layer on the surface of the seed layer, so as to facilitate the smooth formation of the metal grid lines and improve the quality of the solar cell. The acidic cleaning solution can be a hydrofluoric acid solution.
[0060] In an optional embodiment, if Figure 7 As shown, after forming the metal grid lines 9 , the method for preparing the solar cell further includes: forming a protective layer 10 on the surface of the metal grid lines 9 .
[0061] Since the material of the electroplated metal grid line may be oxidized, which may affect the normal use of the solar cell, after the metal grid line is formed, a protective layer may be formed on the surface of the metal grid line to protect the metal grid line from oxidation. The protective layer may be a tin electroplating layer or a silver electroplating layer, and the thickness of the protective layer may be 0.2-1 μm. Since tin or silver has good conductivity and is not easily oxidized, forming a tin electroplating layer or a silver electroplating layer on the surface of the metal grid line can effectively prevent the metal grid line from oxidation and extend the service life of the solar cell.
[0062] S107: Figure 6 and Figure 8 As shown, the remaining self-assembled molecular layer 8 is removed to form a solar cell.
[0063] In an optional embodiment, the method for removing the self-assembled molecular layer is ultraviolet irradiation, plasma cleaning or ultrasonic cleaning, wherein the ultrasonic cleaning can be performed in an acetone solution.
[0064] Based on the same inventive concept, the present invention also provides a solar cell, which is prepared by the solar cell preparation method provided by the above embodiments, and can be referenced to the solar cell preparation method described above, and will not be repeated here.
[0065] The following specific examples further illustrate the present application, but should not be construed as limiting the present application. Without departing from the spirit and substance of the present application, modifications or replacements made to the methods, steps or conditions of the present application are within the scope of the present application.
[0066] [Example 1]
[0067] like Figure 8 As shown, a structure of a solar cell includes: a transparent conductive oxide layer 6, an n-type amorphous silicon layer 5, a second intrinsic amorphous silicon layer 4, an n-type single crystal silicon substrate 1, a first intrinsic amorphous silicon layer 2, a p-type amorphous silicon layer 3, a transparent conductive oxide layer 6, a seed layer 7 located on the surface of the transparent conductive oxide layer 6, a metal grid line 9 located on the surface of the seed layer 7, and a protective layer 10 located on the surface of the metal grid line 9, which are stacked in sequence.
[0068] like Figure 1-Figure 5 and Figure 7-Figure 8 As shown, a method for preparing a solar cell comprises:
[0069] S201: Reference Figure 1 , providing an n-type single crystal silicon substrate 1, and performing pre-cleaning, silicon wafer gettering, and texturing cleaning;
[0070] S202: Reference Figure 1 , forming a first intrinsic amorphous silicon layer 2 and a p-type amorphous silicon layer 3 on the upper surface of the n-type single crystal silicon substrate 1, and forming a second intrinsic amorphous silicon layer 4 and an n-type amorphous silicon layer 5 on the lower surface of the n-type single crystal silicon substrate 1; the total thickness of the p-type amorphous silicon layer 3 and the first intrinsic amorphous silicon layer 2 is 30 nm, and the total thickness of the n-type amorphous silicon layer 5 and the second intrinsic amorphous silicon layer 4 is 30 nm;
[0071] S203: Reference Figure 2 , forming a transparent conductive oxide layer 6 on the surface of the p-type amorphous silicon layer 3 and the surface of the n-type amorphous silicon layer 5, the material of the transparent conductive oxide layers on both sides is indium tin oxide (ITO), and the thickness of the transparent conductive oxide layers 6 on both sides is 100 nm;
[0072] S204: Reference Figure 3 , using a patterned mask and an RPD process, a patterned seed layer 7 is formed on the surface of the transparent conductive oxide layer 6; the seed layer 7 is a copper seed layer, and the thickness of the seed layer 7 is 100 nm;
[0073] S205: Reference Figure 4 , immersing the n-type single crystal silicon substrate 1 forming the seed layer 7 in a 50% octadecyltrichlorosilane solution for 15 minutes, forming a self-assembled molecular layer 8 on the surface of the transparent conductive oxide layer 6 and the surface of the seed layer 7; the thickness of the self-assembled molecular layer 8 is 120 nm;
[0074] S206: The surface of the seed layer 7 is firstly pickled with a hydrofluoric acid solution and then washed with water to remove the oxide layer on the surface of the seed layer;
[0075] S207: Reference Figure 5 , placing the n-type single crystal silicon substrate 1 with the self-assembled molecular layer 8 formed thereon in the electroplating solution, applying a voltage of 8V to metallize the seed layer 7, removing part of the self-assembled molecular layer 8 located at the periphery of the seed layer 7, and forming a metal gate line 9 at the periphery of the seed layer 7; the thickness of the metal gate line 9 is 6μm;
[0076] S208: Reference Figure 7 , forming a protective layer 10 on the surface of the metal grid line 9, the protective layer 10 is a tin electroplating layer, and the thickness of the protective layer 10 is 0.5 μm;
[0077] S209: Reference Figure 8 , using acetone solution ultrasound to remove the remaining self-assembled molecular layer 8 to form a solar cell.
[0078] [Example 2]
[0079] like Figure 6 As shown, a structure of a solar cell includes: a transparent conductive oxide layer 6, an n-type amorphous silicon layer 5, a second intrinsic amorphous silicon layer 4, an n-type single crystal silicon substrate 1, a first intrinsic amorphous silicon layer 2, a p-type amorphous silicon layer 3, a transparent conductive oxide layer 6, a seed layer 7 located on the surface of the transparent conductive oxide layer 6, and a metal grid line 9 located on the surface of the seed layer 7, which are stacked in sequence.
[0080] like Figure 1-Figure 6 As shown, a method for preparing a solar cell comprises:
[0081] S301: Reference Figure 1 , providing an n-type single crystal silicon substrate 1, and performing pre-cleaning, silicon wafer gettering, and texturing cleaning;
[0082] S302: Reference Figure 1 , forming a first intrinsic amorphous silicon layer 2 and a p-type amorphous silicon layer 3 on the upper surface of the n-type single crystal silicon substrate 1, and forming a second intrinsic amorphous silicon layer 4 and an n-type amorphous silicon layer 5 on the lower surface of the n-type single crystal silicon substrate 1; the total thickness of the p-type amorphous silicon layer 3 and the first intrinsic amorphous silicon layer 2 is 35 nm, and the total thickness of the n-type amorphous silicon layer 5 and the second intrinsic amorphous silicon layer 4 is 35 nm;
[0083] S303: Reference Figure 2 , forming a transparent conductive oxide layer 6 on the surface of the p-type amorphous silicon layer 3 and the surface of the n-type amorphous silicon layer 5, the material of the transparent conductive oxide layers on both sides is indium tin oxide (ITO), and the thickness of the transparent conductive oxide layers 6 on both sides is 120nm;
[0084] S304: Reference Figure 3 , using a patterned mask and an RPD process, a patterned seed layer 7 is formed on the surface of the transparent conductive oxide layer 6; the seed layer 7 is a copper seed layer, and the thickness of the seed layer 7 is 90 nm;
[0085] S305: Reference Figure 4 , immersing the n-type single crystal silicon substrate 1 forming the seed layer 7 in a 60% octadecyltrichlorosilane solution for 10 minutes, forming a self-assembled molecular layer 8 on the surface of the transparent conductive oxide layer 6 and the surface of the seed layer 7; the thickness of the self-assembled molecular layer 8 is 110 nm;
[0086] S306: The surface of the seed layer 7 is firstly pickled with a hydrofluoric acid solution and then washed with water to remove the oxide layer on the surface of the seed layer;
[0087] S307: Reference Figure 5 , placing the n-type single crystal silicon substrate 1 with the self-assembled molecular layer 8 formed thereon in an electroplating solution, applying a current of 7A to metallize the seed layer 7, removing part of the self-assembled molecular layer 8 located at the periphery of the seed layer 7, and forming a metal gate line 9 at the periphery of the seed layer 7; the thickness of the metal gate line 9 is 6.2 μm;
[0088] S308: Reference Figure 6 , using acetone solution ultrasound to remove the remaining self-assembled molecular layer 8 to form a solar cell.
[0089] [Comparative Example 1]
[0090] A conventional HJT.
[0091] The conventional HJT preparation method includes:
[0092] S401: providing an n-type single crystal silicon substrate, and performing pre-cleaning, silicon wafer gettering, and texturing cleaning;
[0093] S402: forming a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer on the upper surface of the n-type single crystal silicon substrate, and forming a second intrinsic amorphous silicon layer and an n-type amorphous silicon layer on the lower surface of the n-type single crystal silicon substrate;
[0094] S403: forming a transparent conductive oxide layer on the surface of the p-type amorphous silicon layer and the surface of the n-type amorphous silicon layer;
[0095] S404: using photolithography technology (coating, curing, exposing, and developing) to form a patterned seed layer on the surface of the transparent conductive oxide layer;
[0096] S405: using an electroplating process to form metal grid lines on the surface of the seed layer; and using photolithography technology to adjust the width of the metal grid lines to form a solar cell.
[0097] The following solar cells are provided for performance testing of Examples 1-2 and Comparative Example 1 of the present application, so as to obtain the short-circuit current Jsc, open-circuit voltage Voc, fill factor FF, and efficiency EFF of the corresponding battery devices. The test results are shown in Table 1.
[0098] Table 1 Performance test results of solar cells of Examples 1-2 and Comparative Example 1
[0099]
[0100]
[0101] It can be seen from Table 1 that, compared with Comparative Example 1, the solar cells of Examples 1-2 of the present application have higher short-circuit current, fill factor and efficiency.
[0102] In summary, the embodiments of the present application form a self-assembled molecular layer on the surface of the transparent conductive oxide layer and the surface of the seed layer. The self-assembled molecular layer can hinder the migration of electroplating ions to the transparent conductive oxide layer, thereby achieving selective electroplating, so that electrodeposition only occurs in the seed layer area to be electroplated, thereby improving the forming accuracy of the metal grid line structure and thus improving the performance of the device.
[0103] An embodiment of the present application provides a photovoltaic assembly (not shown), including at least one battery string, the battery string includes at least two of the above-mentioned solar cells, and adjacent solar cells can be connected together by series welding.
[0104] The embodiment of the present application can provide a photovoltaic system, including the photovoltaic components in any of the above embodiments. The advantages of the above photovoltaic components are also possessed by the photovoltaic system, which will not be repeated here. The above photovoltaic system has a wide range of applications, not only limited to photovoltaic power stations, such as ground power stations, rooftop power stations and water power stations, but also includes various equipment and devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars and solar buildings. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to this, that is to say, the photovoltaic system can be used in all fields where solar energy is required for power generation. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components may form multiple photovoltaic arrays. The photovoltaic array is connected to a junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.
[0105] It should be noted that the terms "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The orientation words "inside" and "outside" refer to the inside and outside relative to the outline of each component itself. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Therefore, the exemplary term "above..." can include both "above..." and "below..." orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used here are interpreted accordingly.
[0106] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0107] It should also be noted that "one embodiment", "another embodiment", "embodiment", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Further, when describing a specific feature, structure or characteristic in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.
[0108] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0109] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A method for preparing a solar cell, characterized in that: include: Providing an n-type single crystal silicon substrate; forming a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer in sequence on the upper surface of the n-type single crystal silicon substrate, and forming a second intrinsic amorphous silicon layer and an n-type amorphous silicon layer in sequence on the lower surface of the n-type single crystal silicon substrate; forming a transparent conductive oxide layer on a surface of the p-type amorphous silicon layer and / or a surface of the n-type amorphous silicon layer; forming a patterned seed layer on the surface of the transparent conductive oxide layer; forming a self-assembled molecular layer on a surface of the transparent conductive oxide layer and a surface of the seed layer; Metallizing the seed layer, removing a portion of the self-assembled molecular layer located at the periphery of the seed layer, and forming a metal grid line at the periphery of the seed layer; The remaining self-assembled molecular layer is removed to form a solar cell.
2. The method for preparing a solar cell according to claim 1, characterized in that: The transparent conductive oxide layer includes one or more of indium tin oxide, indium zinc oxide, tungsten-doped indium oxide, fluorine-doped tin oxide, cerium-doped indium oxide, aluminum-doped zinc oxide, and boron-doped zinc oxide.
3. The method for preparing a solar cell according to claim 1, characterized in that: Forming a patterned seed layer on the surface of the transparent conductive oxide layer, comprising: The seed layer is formed on the surface of the transparent conductive oxide layer by using a patterned mask.
4. The method for preparing a solar cell according to claim 1, characterized in that: The seed layer is a silver seed layer or a copper seed layer, and the thickness of the seed layer is 20-500 nm.
5. The method for preparing a solar cell according to claim 1, characterized in that: Forming a self-assembled molecular layer on the surface of the transparent conductive oxide layer and the surface of the seed layer, comprising: The n-type single crystal silicon substrate on which the seed layer is formed is immersed in an octadecyltrichlorosilane solution to form a self-assembled molecular layer on the surface of the transparent conductive oxide layer and the surface of the seed layer.
6. The method for preparing a solar cell according to claim 5, characterized in that: The concentration of the octadecyltrichlorosilane solution is 10-70%; the solvent of the octadecyltrichlorosilane solution is one or more of water, ethanol and ether.
7. The method for preparing a solar cell according to claim 1, characterized in that: The thickness of the self-assembled molecular layer is 50-200 nm.
8. The method for preparing a solar cell according to claim 1, characterized in that: Metallizing the seed layer, comprising: The n-type single crystal silicon substrate forming the self-assembled molecular layer is placed in an electroplating solution, and a voltage or current is applied to metallize the seed layer; wherein the voltage is 6-12V; and the current is 5-10A.
9. The method for preparing a solar cell according to claim 1, characterized in that: After forming the metal grid lines, the method for preparing the solar cell further includes: forming a protective layer on the surface of the metal grid lines.
10. The method for preparing a solar cell according to claim 9, characterized in that: The protective layer is a tin electroplating layer or a silver electroplating layer.
11. A solar cell, characterized in that: The solar cell is prepared by the method for preparing the solar cell according to any one of claims 1 to 10.
12. A photovoltaic module, characterized in that: include: At least one cell string, the cell string comprising at least two solar cells according to claim 11.
13. A photovoltaic system, characterized in that: Comprising the photovoltaic module as claimed in claim 12.