Preparation method of solar cell and solar cell

Abstract

The invention relates to a preparation method of a solar cell and the solar cell, and the method comprises the steps: forming a first tunneling oxide layer, a first doped polycrystalline silicon layer and a first passivation layer on a part of the back surface of a silicon substrate, wherein the first tunneling oxide layer, the first doped polycrystalline silicon layer and the first passivation layer are sequentially stacked; insulating isolation layers close to the side walls of the first tunneling oxide layer, the first doped polycrystalline silicon layer and the first passivation layer are arranged on the exposed part of the silicon substrate, so that a second tunneling oxide layer, a second doped polycrystalline silicon layer and a second passivation layer which are stacked in sequence are formed; the second tunneling oxide layer covers the exposed back surface of the silicon substrate, the surface, deviating from the silicon substrate, of the insulating isolation layer, the surface, deviating from the first doped polycrystalline silicon layer and the partial surface, deviating from the first doped polycrystalline silicon layer, of the first passivation layer, and a first electrode is formed on the surface of the first passivation layer; and forming a second electrode on the surface, deviating from the second doped polycrystalline silicon layer, of the second passivation layer. Physical isolation between the N region and the P region of the solar cell can be realized, and the risk of electric leakage is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of interdigitated back contact cells, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0002] As the efficiency of traditional PERC, TOPCon and other solar cells gradually approaches the theoretical efficiency limit, researchers are gradually focusing on interdigitated back contact cells in pursuit of higher efficiency cells. The back surface of the interdigitated back contact cell is designed with crossed n-type and p-type layers, and the positive and negative electrodes are arranged in an interdigitated manner on the backlight side of the cell, which can greatly improve the light absorption and conversion efficiency.

[0003] Traditional interdigitated back-contact cells often require many processes to achieve alternating arrangements of n / p regions. Therefore, lengthy processes and high costs have always been the main problems in manufacturing interdigitated back-contact cells. In addition, isolation problems that arise during the formation of metallization contacts and gate lines must also be considered.

[0004] In the prior art, in order to ensure the quality of the interdigitated back contact battery, different manufacturing methods are usually used to manufacture the interdigitated back contact battery. However, the current manufacturing methods have some defects. For example, laser doping or film opening makes the isolation between the N region and the P region unstable. Summary of the invention

[0005] Based on this, it is necessary to provide a method for preparing a solar cell that can reduce the risk of leakage.

[0006] In a first aspect, the present application discloses a method for preparing a solar cell, the method for preparing a solar cell comprising:

[0007] Forming a first tunneling oxide layer, a first doped polysilicon layer and a first passivation layer stacked in sequence on a portion of the back side of the silicon substrate;

[0008] An insulating isolation layer is provided on the exposed portion of the silicon substrate; the insulating isolation layer is close to the side walls of the first tunneling oxide layer, the first doped polysilicon layer and the first passivation layer;

[0009] A second tunneling oxide layer, a second doped polysilicon layer and a second passivation layer are formed, which are stacked in sequence; the second tunneling oxide layer covers the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate and the surface away from the first doped polysilicon layer, and a portion of the surface of the first passivation layer away from the first doped polysilicon layer; wherein the second doped polysilicon layer and the first doped polysilicon layer have different doping types;

[0010] A first electrode is formed on a portion of the surface of the first passivation layer exposed to the second tunneling oxide layer, and a second electrode is formed on a surface of the second passivation layer away from the second doped polysilicon layer.

[0011] In one embodiment, forming a first tunneling oxide layer, a first doped polysilicon layer, and a first passivation layer stacked in sequence on a portion of the back side of the silicon substrate comprises:

[0012] Forming the first tunneling oxide layer, the first doped polysilicon layer and the first passivation layer stacked in sequence on the entire back surface of the silicon substrate;

[0013] The first tunneling oxide layer, the first doped polysilicon layer, and the first passivation layer in a first preset region are removed.

[0014] In one embodiment, removing the first tunneling oxide layer, the first doped polysilicon layer, and the first passivation layer in the first preset region includes:

[0015] Removing the first passivation layer in the first preset area by laser etching technology;

[0016] The first doped polysilicon layer and the first tunneling oxide layer in the first preset region are removed by wet etching technology.

[0017] In one of the embodiments, the forming of a second tunneling oxide layer, a second doped polysilicon layer and a second passivation layer stacked in sequence; the second tunneling oxide layer covers the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate and the surface away from the first doped polysilicon layer, and a portion of the surface of the first passivation layer away from the first doped polysilicon layer comprises:

[0018] The second tunneling oxide layer is formed on the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate and the surface away from the first doped polysilicon layer, and the surface of the first passivation layer away from the first doped polysilicon layer.

[0019] The second doped polysilicon layer and the second passivation layer are sequentially stacked on the surface of the second tunneling oxide layer.

[0020] The second tunneling oxide layer, the second doped polysilicon layer and the second passivation layer in the second preset region are removed to form an opening leaking out of the first passivation layer.

[0021] In one embodiment, removing the second tunneling oxide layer, the second doped polysilicon layer, and the second passivation layer in the second preset region to form an opening leaking out of the first passivation layer includes:

[0022] Removing the second passivation layer in the second preset area by laser etching technology;

[0023] The second doped polysilicon layer and the second tunneling oxide layer in the second preset region are removed by wet etching technology to form an opening leaking out of the first passivation layer.

[0024] In a second aspect, the present application further discloses a solar cell, comprising:

[0025] Silicon substrate;

[0026] A first tunneling oxide layer, wherein the first tunneling oxide layer is disposed on a portion of the back side of the silicon substrate;

[0027] a first doped polysilicon layer, wherein the first doped polysilicon layer is disposed on a surface of the first tunnel oxide layer facing away from the silicon substrate;

[0028] a first passivation layer, the first passivation layer being stacked with the first doped polysilicon layer, and the first passivation layer being disposed on a surface of the first doped polysilicon layer facing away from the tunneling oxide layer;

[0029] an insulating isolation layer, the insulating isolation layer being close to side walls of the first tunneling oxide layer, the first doped polysilicon layer and the first passivation layer;

[0030] a second tunneling oxide layer, wherein the second tunneling oxide layer covers the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate and the surface away from the first doped polysilicon layer, and a portion of the surface of the first passivation layer away from the first doped polysilicon layer;

[0031] a second doped polysilicon layer, which is stacked between the second doped polysilicon layer and the second tunneling oxide layer and is disposed on a surface of the second tunneling oxide layer facing away from the silicon substrate;

[0032] a second passivation layer, which is stacked between the second passivation layer and the second doped polysilicon layer and is disposed on a surface of the second doped polysilicon layer away from the second tunneling oxide layer;

[0033] An opening exposing the first passivation layer is provided on the second tunneling oxide layer, the second doped polysilicon layer and the second passivation layer, a first electrode is formed on a portion of the surface of the first passivation layer exposed to the second tunneling oxide layer, and a second electrode is formed on a surface of the second passivation layer away from the second doped polysilicon layer.

[0034] In one embodiment, the insulating isolation layer is used to isolate the N region and the P region of the solar cell.

[0035] In one embodiment, the thickness of the insulating isolation layer is consistent with the sum of the thicknesses of the first tunneling oxide layer, the first doped polysilicon layer and the first passivation layer.

[0036] In one embodiment, the width of the opening is greater than the width of the first electrode.

[0037] In one embodiment, the difference between the width of the opening and the width of the first electrode is 30 um to 60 um.

[0038] The method for preparing the solar cell comprises the following steps: providing a first tunneling oxide layer on the back side of a silicon substrate portion so that the back side of another portion of the silicon substrate is exposed, and sequentially stacking a first doped polysilicon layer and a first passivation layer on the surface of the first tunneling oxide layer on the side away from the silicon substrate, providing an insulating isolation layer close to the side walls of the first tunneling oxide layer, the first doped polysilicon layer and the first passivation layer on the exposed portion of the back side of the silicon substrate, forming a second tunneling oxide layer on the second tunneling oxide layer covering the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate and the surface away from the first doped polysilicon layer, and the partial surface of the first passivation layer away from the first doped polysilicon layer, and stacking a second doped polysilicon layer and a second passivation layer of different doping types from the first doped polysilicon layer on the entire surface of the second tunneling oxide layer away from the silicon substrate, providing an opening for exposing a portion of the first passivation layer on the second tunneling oxide layer, the second doped polysilicon layer and the second passivation layer, forming a first electrode on the first passivation layer at the opening, and forming a second electrode on the surface of the second passivation layer away from the second doped polysilicon layer. By providing an insulating isolation layer between the first doped polysilicon layer and the second doped polysilicon layer, the N region and the P region of the solar cell are separated, so that the N region and the P region of the solar cell are physically isolated and the risk of leakage is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 is a schematic diagram of a process for preparing a solar cell in one embodiment;

[0041] Figure 2 is a schematic flow chart of step 101 in one embodiment;

[0042] Figure 3is a schematic flow chart of step 202 in one embodiment;

[0043] Figure 4 is a schematic flow chart of step 103 in one embodiment;

[0044] Figure 5 is a schematic diagram of a flow chart of step 402 in one embodiment;

[0045] Figure 6 is a schematic structural diagram of a solar cell in one embodiment;

[0046] Figure 7 is a schematic structural diagram of a solar cell in another embodiment;

[0047] Figure 8 is a schematic structural diagram of a solar cell in another embodiment;

[0048] Fig. 9 FIG. 4 is a schematic diagram of the structure of a solar cell in another embodiment.

[0049] Description of reference numerals:

[0050] A first tunneling oxide layer 101, a first doped polysilicon layer 102, and a first passivation layer 103;

[0051] Insulating isolation layer 201;

[0052] A second tunneling oxide layer 301, a second doped polysilicon layer 302, and a second passivation layer 303;

[0053] A first electrode 401 and a second electrode 402 . DETAILED DESCRIPTION

[0054] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0056] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first electrode may be referred to as a second electrode, and similarly, a second electrode may be referred to as a first electrode. Both the first electrode and the second electrode are electrodes, but they are not the same electrode.

[0057] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0058] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0059] Traditional interdigitated back contact cells often require many processes to achieve alternating arrangement of n / p regions, which has the problems of lengthy processes, high costs, and isolation problems in the process of forming metallized contacts and gate lines. In the prior art, in order to ensure the quality of interdigitated back contact cells, different manufacturing methods are usually used to manufacture interdigitated back contact cells. However, the current manufacturing methods all have some defects, for example, the isolation between the N region and the P region is unstable when using laser doping or film opening.

[0060] In an exemplary embodiment, Figure 1 As shown, a method for preparing a solar cell is provided, and the method is applied to a solar cell manufacturing device as an example for description, and includes the following steps 101 to 104. Among them:

[0061] Step 101 : forming a first tunneling oxide layer, a first doped polysilicon layer and a first passivation layer stacked in sequence on a portion of the back side of a silicon substrate.

[0062] Optionally, on the back side of the silicon substrate, a tunneling oxide layer, a doped polysilicon layer and a passivation layer are sequentially deposited by a preset deposition technology, and redundant tunneling oxide layer, doped polysilicon layer and passivation layer are removed by a preset etching technology, thereby forming a first tunneling oxide layer, a first doped polysilicon layer and a first passivation layer that are stacked. The first doped polysilicon layer includes one of a boron-doped polysilicon layer and a phosphorus-doped polysilicon layer.

[0063] In addition, the tunnel oxide layer, the doped polysilicon layer and the passivation layer can be independently deposited and generated by different deposition techniques, for example: chemical vapor deposition technology can deposit the tunnel oxide layer and the doped polysilicon layer, atomic layer deposition technology can deposit the tunnel oxide layer, and physical vapor deposition technology can deposit the doped polysilicon layer and the passivation layer. The deposition technology is not specifically limited in this application. The excess parts of the tunnel oxide layer, the doped polysilicon layer and the passivation layer can be independently removed by different etching techniques, for example: wet chemical etching technology can remove the tunnel oxide layer and the doped polysilicon layer, dry etching technology can remove the tunnel oxide layer and the doped polysilicon layer, and laser etching technology can remove the tunnel oxide layer, the doped polysilicon layer and the passivation layer. The etching technology is not specifically limited in this application.

[0064] Step 102: Disposing an insulating isolation layer on the exposed portion of the silicon substrate; the insulating isolation layer is close to the side walls of the first tunneling oxide layer, the first doped polysilicon layer and the first passivation layer.

[0065] The insulating isolation layer is generated by printing through screen printing technology, and the screen printing technology uses the mesh holes of the graphic part on the screen to allow the slurry to pass through, while the mesh holes of the non-graphic part are not transparent to the slurry. The scraper moves while applying pressure to squeeze the slurry onto the surface of the silicon substrate to form an electrode pattern insulating isolation layer. In addition, the slurry used is an insulating slurry, and the slurry is not specifically limited in this application.

[0066] Optionally, in the exposed portion of the silicon substrate, starting from the bottom of the exposed portion of the silicon substrate, printing is performed on the side walls close to the first tunneling oxide layer, the first doped polysilicon layer and the first passivation layer through screen printing technology, so as to achieve physical isolation of the n-region and the p-region of the solar cell and avoid leakage.

[0067] Step 103, forming a second tunneling oxide layer, a second doped polysilicon layer and a second passivation layer which are stacked in sequence; the second tunneling oxide layer covers the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate and the surface away from the first doped polysilicon layer, and a portion of the surface of the first passivation layer away from the first doped polysilicon layer; wherein the second doped polysilicon layer and the first doped polysilicon layer have different doping types.

[0068] Optionally, a tunneling oxide layer, a doped polysilicon layer and a passivation layer are sequentially deposited on the back side of the exposed portion of the silicon substrate, the surface of the insulating isolation layer facing away from the silicon substrate, the surface of the first doped polysilicon layer facing away from the first doped polysilicon layer, and the surface of the first passivation layer facing away from the first doped polysilicon layer by a preset deposition technology, and corresponding portions of the tunneling oxide layer, the doped polysilicon layer and the passivation layer are removed by a preset etching technology, so that the removed portions form an opening, thereby forming a second tunneling oxide layer, a second doped polysilicon layer and a second passivation layer that are stacked, wherein a portion of the surface of the first passivation layer is exposed in the opening.

[0069] In addition, the second doped polysilicon layer includes one of a boron-doped polysilicon layer and a phosphorus-doped polysilicon layer. When the first doped polysilicon layer includes a boron-doped polysilicon layer, the second doped polysilicon layer includes a phosphorus-doped polysilicon layer. When the first doped polysilicon layer includes a phosphorus-doped polysilicon layer, the second doped polysilicon layer includes a boron-doped polysilicon layer.

[0070] Step 104 , forming a first electrode on a portion of the surface of the first passivation layer exposed to the second tunneling oxide layer, and forming a second electrode on a surface of the second passivation layer away from the second doped polysilicon layer.

[0071] Optionally, at the opening, a portion of the surface of the first passivation layer is exposed to the second tunneling oxide layer, and a first electrode is formed on the exposed surface of the first passivation layer, and a second electrode is correspondingly formed on the surface of the second passivation layer away from the second doped polysilicon layer.

[0072] In this embodiment, a first tunneling oxide layer is provided on the back side of a portion of the silicon substrate so that the back side of another portion of the silicon substrate is exposed, and a first doped polysilicon layer and a first passivation layer are sequentially stacked on the surface of the first tunneling oxide layer on the side away from the silicon substrate, an insulating isolation layer close to the side walls of the first tunneling oxide layer, the first doped polysilicon layer and the first passivation layer is provided on the exposed portion of the back side of the silicon substrate, a second tunneling oxide layer is formed on the second tunneling oxide layer covering the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate and the surface away from the first doped polysilicon layer, and a portion of the surface of the first passivation layer away from the first doped polysilicon layer, and a second doped polysilicon layer and a second passivation layer of different doping types from the first doped polysilicon layer are stacked on the entire surface of the second tunneling oxide layer on the side away from the silicon substrate, an opening exposing a portion of the first passivation layer is provided in the second tunneling oxide layer, the second doped polysilicon layer and the second passivation layer, a first electrode is formed on the first passivation layer at the opening, and a second electrode is formed on the surface of the second passivation layer away from the second doped polysilicon layer. By providing an insulating isolation layer between the first doped polysilicon layer and the second doped polysilicon layer, the N region and the P region of the solar cell are separated, so that the N region and the P region of the solar cell are physically isolated and the risk of leakage is reduced.

[0073] In an exemplary embodiment, Figure 2 As shown, step 101 includes steps 201 to 202, wherein:

[0074] Step 201 : forming a first tunneling oxide layer, a first doped polysilicon layer and a first passivation layer stacked in sequence on the entire back surface of a silicon substrate.

[0075] Optionally, a tunneling oxide layer is deposited on the entire back side of the silicon substrate by a preset deposition technology, a doped polysilicon layer is deposited on the surface of the tunneling oxide layer facing away from the silicon substrate by a preset deposition technology, and a passivation layer is deposited on the surface of the doped polysilicon layer facing away from the tunneling oxide layer by a preset deposition technology, thereby forming a first tunneling oxide layer, a first doped polysilicon layer and a first passivation layer that are stacked.

[0076] Specifically, on the back side of the silicon substrate, PECVD technology is used to activate reaction gases such as silane and oxygen to form a corresponding plasma, and the plasma undergoes a chemical reaction on the back side of the silicon substrate to generate silicon oxide and deposit it on the back side of the silicon substrate to form a first tunneling oxide layer.

[0077] Taking the first doped polysilicon layer including a boron-doped polysilicon layer as an example, after the deposition of the first tunnel oxide layer is completed, on the surface of the first tunnel oxide layer facing away from the silicon substrate, the PECVD technology is used to activate reaction gases such as silane and borane trihydride to form a corresponding plasma. The plasma undergoes a chemical reaction on the surface of the first tunnel oxide layer facing away from the silicon substrate to generate a boron-doped polysilicon film and deposit it on the surface of the first tunnel oxide layer facing away from the silicon substrate to form a first doped polysilicon layer.

[0078] After the deposition of the first doped polysilicon layer is completed, on the surface of the first doped polysilicon layer facing away from the first tunnel oxide layer, the PECVD technology is used to activate reaction gases such as silane and oxygen to form a corresponding plasma. The plasma undergoes a chemical reaction on the surface of the first doped polysilicon layer facing away from the first tunnel oxide layer to generate silicon dioxide, which is deposited on the surface of the first doped polysilicon layer facing away from the first tunnel oxide layer to form a first passivation layer.

[0079] Among them, PECVD technology, or plasma enhanced chemical vapor deposition technology, is a thin film growth technology that uses plasma to deposit at a lower temperature. PECVD technology deposits a solid film on the surface of a silicon wafer through a chemical reaction of gas mixture.

[0080] Step 202 , removing the first tunneling oxide layer, the first doped polysilicon layer and the first passivation layer in the first preset region.

[0081] Optionally, the first passivation layer in the first preset area is removed by a preset first etching technology, the first doped polysilicon layer in the first preset area is removed by a preset second etching technology, and the first tunneling oxide layer in the first preset area is removed by a preset second etching technology.

[0082] In this embodiment, a first tunnel oxide layer is deposited on the entire back side of the silicon substrate by using the PECVD technology, and after the deposition of the first tunnel oxide layer is completed, a first doped polysilicon layer and a first passivation layer are sequentially deposited by using the PECVD technology, and the first tunnel oxide layer in the first preset area is removed by using a preset first etching technology. After the removal of the first tunnel oxide layer in the first preset area is completed, the first doped polysilicon layer and the first passivation layer in the first preset area are removed by using a preset second etching technology. The boron-doped polysilicon layer and the passivation layer can be deposited in one step by using the PECVD technology, which greatly shortens the process and reduces the cost.

[0083] In an exemplary embodiment, Figure 3 As shown, step 202 includes steps 301 to 302, wherein:

[0084] Step 301: remove the first passivation layer in the first preset area by laser etching technology.

[0085] Among them, the preset first etching technology may include laser etching technology. Laser etching technology is a technology that uses lasers to perform fine processing on various materials. Through the interaction of laser beams with materials, specific patterns or structures are formed on the surface or inside of the material.

[0086] Specifically, a laser beam is irradiated onto the first passivation layer in the first preset area by laser etching technology, and the first passivation layer in the first preset area is rapidly evaporated or decomposed by photothermal effect or photochemical effect. For example: the laser beam may include 550nm picosecond green light, and the first passivation layer in the first preset area is irradiated with 550nm picosecond green light to decompose the first passivation layer in the first preset area. Among them, the laser beam can be set to other lasers and other wavelengths according to actual needs, and the laser and the wavelength of the laser are not specifically limited in this application. The width of the removed first passivation layer can include 540μm to 600μm, and the width of the removed first passivation layer can also be set to other width ranges according to actual needs, and the width of the removed first passivation layer is not specifically limited in this application.

[0087] Step 302: remove the first doped polysilicon layer and the first tunnel oxide layer in the first preset region by wet etching technology.

[0088] The preset second etching technology may include a wet etching technology, which is a technology that utilizes a chemical reaction between a specific solution and a thin film to remove a corresponding portion of the thin film, thereby achieving an etching purpose.

[0089] Specifically, taking the first doped polysilicon layer including a boron-doped polysilicon layer as an example, after the first passivation layer in the first preset area is removed, in the wet etching technology, an alkaline solution such as hydrofluoric acid or potassium hydroxide reacts chemically with the substance in the first doped polysilicon layer to gradually dissolve the first doped polysilicon layer in the first preset area.

[0090] After the first doped polysilicon layer in the first preset region is removed, the first tunnel oxide layer in the first preset region is etched by chemically reacting hydrofluoric acid with silicon oxide in a wet etching technique.

[0091] In this embodiment, the first passivation layer in the first preset area is decomposed by laser using a preset laser etching technology. After the first passivation layer in the first preset area is removed, the first doped polysilicon layer and the first tunneling oxide layer in the first preset area are gradually dissolved by hydrofluoric acid in a preset wet etching technology, so that the tunneling oxide layer, the doped polysilicon layer and the passivation layer in the N region or the P region can be accurately removed.

[0092] In an exemplary embodiment, Figure 4 As shown, step 103 includes steps 401 to 403, wherein:

[0093] Step 401 , forming a second tunneling oxide layer on the entire surface of the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate and the surface away from the first doped polysilicon layer, and the surface of the first passivation layer away from the first doped polysilicon layer.

[0094] Optionally, a tunneling oxide layer is deposited on the entire surface of the exposed back side of the silicon substrate, the surface of the insulating isolation layer facing away from the silicon substrate, the surface of the insulating isolation layer facing away from the first doped polysilicon layer, and the surface of the first passivation layer facing away from the first doped polysilicon layer by a preset deposition technology to form a second tunneling oxide layer.

[0095] Specifically, on the exposed back side of the silicon substrate, the surface of the insulating isolation layer facing away from the silicon substrate, the surface of the insulating isolation layer facing away from the first doped polysilicon layer, and the surface of the first passivation layer facing away from the first doped polysilicon layer, PECVD technology is used to activate reaction gases such as silane and oxygen to form corresponding plasmas, and the plasma undergoes a chemical reaction on the corresponding surfaces to generate silicon oxide and deposit it on the corresponding surfaces to form a second tunneling oxide layer.

[0096] Step 402: A second doped polysilicon layer and a second passivation layer are sequentially stacked on the surface of the second tunnel oxide layer.

[0097] Optionally, a doped polysilicon layer is deposited on the surface of the tunneling oxide layer away from the silicon substrate by a preset deposition technology, and a passivation layer is deposited on the surface of the doped polysilicon layer away from the tunneling oxide layer by a preset deposition technology, thereby forming a second doped polysilicon layer and a second passivation layer that are stacked.

[0098] Taking the second doped polysilicon layer including a phosphorus-doped polysilicon layer as an example, after the deposition of the second tunnel oxide layer is completed, on the surface of the second tunnel oxide layer facing away from the silicon substrate, the PECVD technology is used to activate reaction gases such as silane and phosphine trihydride to form a corresponding plasma. The plasma undergoes a chemical reaction on the surface of the second tunnel oxide layer facing away from the silicon substrate to generate a phosphorus-doped polysilicon film and deposit it on the surface of the second tunnel oxide layer facing away from the silicon substrate to form a second doped polysilicon layer.

[0099] After the deposition of the second doped polysilicon layer is completed, on the surface of the second doped polysilicon layer facing away from the second tunnel oxide layer, PECVD technology is used to activate reaction gases such as silane and oxygen to form a corresponding plasma. The plasma undergoes a chemical reaction on the surface of the second doped polysilicon layer facing away from the second tunnel oxide layer to generate silicon dioxide, which is deposited on the surface of the second doped polysilicon layer facing away from the second tunnel oxide layer to form a second passivation layer.

[0100] Step 403 , removing the second tunneling oxide layer, the second doped polysilicon layer and the second passivation layer in the second preset region to form an opening leaking out of the first passivation layer.

[0101] Optionally, the second passivation layer in the second preset area is removed by a preset first etching technology, the second doped polysilicon layer in the second preset area is removed by a preset second etching technology, and the second tunneling oxide layer in the second preset area is removed by a preset second etching technology.

[0102] In this embodiment, a second tunneling oxide layer is deposited on the entire surface of the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate, the surface of the insulating isolation layer away from the first doped polysilicon layer, and the surface of the first passivation layer away from the first doped polysilicon layer by PECVD technology. After the deposition of the second tunneling oxide layer is completed, a stacked second doped polysilicon layer and a second passivation layer are sequentially deposited by PECVD technology. The second tunneling oxide layer in the second preset area is removed by a preset first etching technology. After the removal of the second tunneling oxide layer in the second preset area is completed, the second doped polysilicon layer and the second passivation layer in the second preset area are removed by a preset second etching technology. The boron-phosphorus-doped polysilicon layer and the passivation layer can be deposited in one step by PECVD technology, which greatly shortens the process and reduces costs.

[0103] In an exemplary embodiment, Figure 5 As shown, step 403 includes steps 501 to 502, wherein:

[0104] Step 501: remove the second passivation layer in the second preset area by laser etching technology.

[0105] Specifically, a laser beam is irradiated to the second passivation layer in the second preset area by laser etching technology, and the second passivation layer in the second preset area is rapidly evaporated or decomposed by photothermal effect or photochemical effect. An opening is formed by laser opening the second passivation layer, which can prevent the first electrode of the P region from contacting the phosphorus-doped polysilicon layer.

[0106] Step 502: remove the second polysilicon layer and the second tunnel oxide layer in the second preset area by wet etching technology to form an opening leaking out of the first passivation layer.

[0107] Specifically, taking the second doped polysilicon layer including the phosphorus-doped polysilicon layer as an example, after the second passivation layer in the second preset area is removed, in the wet etching technology, a mixed solution of hydrofluoric acid and nitric acid reacts chemically with the substance in the second doped polysilicon layer to gradually dissolve the second doped polysilicon layer in the second preset area. After the second doped polysilicon layer in the second preset area is removed, in the wet etching technology, hydrofluoric acid reacts chemically with silicon oxide to etch the second tunneling oxide layer in the second preset area. By wet etching the exposed phosphorus-doped polysilicon layer and the second tunneling oxide layer to expose the first passivation layer, the phosphorus-doped polysilicon layer in the entire P region does not need to be removed, which shortens the process time and reduces laser damage while ensuring that the boron-doped polysilicon is passivated intact.

[0108] In this embodiment, the second passivation layer in the second preset area is decomposed by laser using a preset laser etching technology. After the second passivation layer in the second preset area is removed, the second doped polysilicon layer in the second preset area is gradually dissolved by a mixed solution of hydrofluoric acid and nitric acid in a preset wet etching technology. The second tunneling oxide layer in the second preset area is gradually dissolved by a hydrofluoric acid solution, and the tunneling oxide layer, the doped polysilicon layer and the passivation layer at the electrode are accurately removed.

[0109] It should be noted that, by removing part of the second doped polysilicon layer in the N region or the P region to connect the first electrode to the first passivation layer, it is not necessary to remove all of the second doped polysilicon layer in the N region or the P region, which can reduce the second doped polysilicon layer removed in the N region or the P region and shorten the process time. Wherein, when the second doped polysilicon layer is a phosphorus-doped polysilicon layer, part of the phosphorus-doped polysilicon layer in the P region is removed, and when the second doped polysilicon layer is a boron-doped polysilicon layer, part of the boron-doped polysilicon layer in the N region is removed.

[0110] In an exemplary embodiment, Figure 6 As shown, on the back side of the silicon substrate, a tunneling oxide layer is deposited on the entire surface by PECVD technology, on the surface of the tunneling oxide layer away from the silicon substrate, a doped polysilicon layer is deposited by PECVD technology, and on the surface of the doped polysilicon layer away from the tunneling oxide layer, a passivation layer is deposited by PECVD technology, thereby forming a first tunneling oxide layer 101, a first doped polysilicon layer 102 and a first passivation layer 103 which are stacked.

[0111] In an exemplary embodiment, Figure 7 As shown, taking the first doped polysilicon layer 102 including a boron-doped polysilicon layer as an example, the first passivation layer 103 in the first preset area is decomposed by laser etching technology. After the first passivation layer 103 in the first preset area is removed, in the wet etching technology, the first doped polysilicon layer 102 and the first tunneling oxide layer 101 in the first preset area are dissolved by an alkaline solution such as hydrofluoric acid or potassium hydroxide. In the exposed portion of the silicon substrate, that is, in the first preset area, starting from the bottom of the exposed portion of the silicon substrate, the sidewall 103 close to the first tunneling oxide layer 101, the first doped polysilicon layer 102 and the first passivation layer is printed by screen printing technology to form an insulating isolation layer 201. Among them, the first preset area includes Figure 7 The portion where no layer is formed and the portion where the insulating isolation layer 201 is provided.

[0112] In an exemplary embodiment, Figure 8As shown, a tunneling oxide layer is deposited on the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate, the surface of the insulating isolation layer away from the first doped polysilicon layer, and the surface of the first passivation layer away from the first doped polysilicon layer by PECVD technology; a doped polysilicon layer is deposited on the surface of the tunneling oxide layer away from the silicon substrate by PECVD technology; and a passivation layer is deposited on the surface of the doped polysilicon layer away from the tunneling oxide layer by PECVD technology, thereby forming a second tunneling oxide layer 301, a second doped polysilicon layer 302, and a second passivation layer 303 which are stacked.

[0113] In an exemplary embodiment, Fig. 9 As shown, taking the second doped polysilicon layer 302 including a phosphorus-doped polysilicon layer as an example, the second passivation layer 303 in the second preset region is decomposed by a preset laser etching technology. After the second passivation layer 303 in the second preset region is removed, the second doped polysilicon layer 302 in the second preset region is gradually dissolved by a mixed solution of hydrofluoric acid and nitric acid in a preset wet etching technology, and the second tunneling oxide layer 301 in the second preset region is gradually dissolved by a hydrofluoric acid solution, thereby forming an opening exposing the first passivation layer 103, forming a first electrode 401 on the surface of the first passivation layer 103 at the opening, and correspondingly forming a second electrode 402 on the surface of the second passivation layer 303 away from the second doped polysilicon layer 302. The second preset region is Fig. 9 The middle opening part.

[0114] In addition, in an exemplary embodiment, Fig. 9As shown, a solar cell is also provided, the solar cell comprising: a silicon substrate, a first tunneling oxide layer 101, the first tunneling oxide layer 101 is arranged on a part of the back side of the silicon substrate. A first doped polysilicon layer 102, the first doped polysilicon layer 102 is arranged on the surface of the first tunneling oxide layer 101 away from the silicon substrate. A first passivation layer 103, the first passivation layer 103 and the first doped polysilicon layer 102 are stacked, the first passivation layer 103 is arranged on the surface of the first doped polysilicon 102 layer away from the tunneling oxide layer 101. An insulating isolation layer 201, the insulating isolation layer 201 is close to the first tunneling oxide layer 101, the first doped polysilicon layer 102 and the sidewalls of the first passivation layer 102. The second tunneling oxide layer 301 covers the exposed back side of the silicon substrate, the surface of the insulating isolation layer 201 away from the silicon substrate and the surface away from the first doped polysilicon layer 102, and the partial surface of the first passivation layer 103 away from the first doped polysilicon layer 102. The second doped polysilicon layer 302 is stacked between the second doped polysilicon layer 302 and the second tunneling oxide layer 301, and is arranged on the surface of the second tunneling oxide layer 301 away from the silicon substrate. The second passivation layer 303 is stacked between the second passivation layer 303 and the second doped polysilicon layer 302, and is arranged on the surface of the second doped polysilicon layer 302 away from the second tunneling oxide layer 301.

[0115] An opening exposing the first passivation layer 103 is provided on the second tunneling oxide layer 301, the second doped polysilicon layer 302 and the second passivation layer 303, a first electrode 401 is formed on a portion of the surface of the first passivation layer 103 exposed to the second tunneling oxide layer 301, and a second electrode 402 is formed on a surface of the second passivation layer 303 facing away from the second doped polysilicon layer 302.

[0116] Wherein, the first electrode 401 and the second electrode 402 are both metal electrodes, the polarity of the first electrode 401 is different from the polarity of the second electrode 402, and the polarity of the first electrode 401 and the polarity of the second electrode 402 are both related to the set layer, for example: when the first electrode 401 is a positive polarity, the first electrode 401 is connected to the boron-doped polysilicon layer, and when the first electrode 401 is a negative polarity, the first electrode 401 is connected to the phosphorus-doped polysilicon layer. Similarly, when the second electrode 402 is a positive polarity, the second electrode 402 is connected to the boron-doped polysilicon layer, and when the second electrode 402 is a negative polarity, the second electrode 402 is connected to the phosphorus-doped polysilicon layer.

[0117] In an exemplary embodiment, Fig. 9 As shown, the insulating isolation layer 201 is used to isolate the N region and the P region of the solar cell.

[0118] The insulating isolation layer 201 realizes physical isolation between the N region and the P region of the solar cell.

[0119] In an exemplary embodiment, Fig. 9 As shown, the thickness of the insulating isolation layer 201 is consistent with the sum of the thicknesses of the first tunneling oxide layer 101 , the first doped polysilicon layer 102 and the first passivation layer 103 .

[0120] The width of the insulating isolation layer 201 may be 20 μm to 80 μm, or the width of the insulating isolation layer 201 may be limited according to actual needs. The width of the insulating isolation layer 201 is not specifically limited in the present application.

[0121] In an exemplary embodiment, Fig. 9 As shown, the width of the opening is greater than the width of the first electrode 401 .

[0122] Wherein, when the first electrode 401 is of positive polarity, the width of the opening is greater than the width of the first electrode 401 so that the first battery 401 does not touch the phosphorus-doped polysilicon layer. When the first electrode 401 is of negative polarity, the width of the opening is greater than the width of the first electrode 401 so that the first battery 401 does not touch the boron-doped polysilicon layer.

[0123] In an exemplary embodiment, Fig. 9 As shown, the difference between the width of the opening and the width of the first electrode 401 is comprised between 30 um and 60 um.

[0124] Among them, the difference between the width of the opening and the width of the first electrode 401 needs to be within a preset range so that the first electrode 401 cannot touch the phosphorus-doped polysilicon layer or the boron-doped polysilicon layer. The limit range of the difference between the width of the opening and the width of the first electrode 401 can be set according to actual needs. In this application, the limit range of the difference between the width of the opening and the width of the first electrode 401 is not specifically limited.

[0125] It is understandable that the above-mentioned solar cell preparation method and solar cell may also adopt other forms, not limited to the forms mentioned in the above-mentioned embodiments, as long as they can achieve physical isolation between the N region and the P region of the solar cell and reduce the risk of leakage.

[0126] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0127] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0128] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for preparing a solar cell, characterized in that: The method for preparing the solar cell comprises: Forming a first tunneling oxide layer, a first doped polysilicon layer and a first passivation layer stacked in sequence on a portion of the back side of the silicon substrate; An insulating isolation layer is provided on the exposed portion of the silicon substrate; the insulating isolation layer is close to the side walls of the first tunneling oxide layer, the first doped polysilicon layer and the first passivation layer; A second tunneling oxide layer, a second doped polysilicon layer and a second passivation layer are formed, which are stacked in sequence; the second tunneling oxide layer covers the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate and the surface away from the first doped polysilicon layer, and a portion of the surface of the first passivation layer away from the first doped polysilicon layer; wherein the second doped polysilicon layer and the first doped polysilicon layer have different doping types; A first electrode is formed on a portion of the surface of the first passivation layer exposed to the second tunneling oxide layer, and a second electrode is formed on a surface of the second passivation layer away from the second doped polysilicon layer.

2. The method for preparing a solar cell according to claim 1, characterized in that: The method of forming a first tunneling oxide layer, a first doped polysilicon layer and a first passivation layer stacked in sequence on a portion of the back side of the silicon substrate comprises: Forming the first tunneling oxide layer, the first doped polysilicon layer and the first passivation layer stacked in sequence on the entire back surface of the silicon substrate; The first tunneling oxide layer, the first doped polysilicon layer, and the first passivation layer in a first preset region are removed.

3. The method for preparing a solar cell according to claim 2, characterized in that: The removing the first tunneling oxide layer, the first doped polysilicon layer, and the first passivation layer in the first preset region comprises: Removing the first passivation layer in the first preset area by laser etching technology; The first doped polysilicon layer and the first tunneling oxide layer in the first preset region are removed by wet etching technology.

4. The method for preparing a solar cell according to claim 1, characterized in that: The forming of a second tunneling oxide layer, a second doped polysilicon layer and a second passivation layer stacked in sequence; wherein the second tunneling oxide layer covers the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate and the surface away from the first doped polysilicon layer, and a portion of the surface of the first passivation layer away from the first doped polysilicon layer comprises: The second tunneling oxide layer is formed on the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate and the surface away from the first doped polysilicon layer, and the surface of the first passivation layer away from the first doped polysilicon layer. The second doped polysilicon layer and the second passivation layer are sequentially stacked on the surface of the second tunneling oxide layer. The second tunneling oxide layer, the second doped polysilicon layer and the second passivation layer in the second preset region are removed to form an opening leaking out of the first passivation layer.

5. The method for preparing a solar cell according to claim 4, characterized in that: The removing the second tunneling oxide layer, the second doped polysilicon layer, and the second passivation layer in the second preset region to form an opening leaking out of the first passivation layer comprises: Removing the second passivation layer in the second preset area by laser etching technology; The second doped polysilicon layer and the second tunneling oxide layer in the second preset region are removed by wet etching technology to form an opening leaking out of the first passivation layer.

6. A solar cell, characterized in that: The solar cell comprises: Silicon substrate; A first tunneling oxide layer, wherein the first tunneling oxide layer is disposed on a portion of the back side of the silicon substrate; a first doped polysilicon layer, wherein the first doped polysilicon layer is disposed on a surface of the first tunnel oxide layer facing away from the silicon substrate; a first passivation layer, the first passivation layer being stacked with the first doped polysilicon layer, and the first passivation layer being disposed on a surface of the first doped polysilicon layer facing away from the tunneling oxide layer; an insulating isolation layer, the insulating isolation layer being close to side walls of the first tunneling oxide layer, the first doped polysilicon layer and the first passivation layer; a second tunneling oxide layer, wherein the second tunneling oxide layer covers the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate and the surface away from the first doped polysilicon layer, and a portion of the surface of the first passivation layer away from the first doped polysilicon layer; a second doped polysilicon layer, which is stacked between the second doped polysilicon layer and the second tunneling oxide layer and is disposed on a surface of the second tunneling oxide layer facing away from the silicon substrate; a second passivation layer, which is stacked between the second passivation layer and the second doped polysilicon layer and is disposed on a surface of the second doped polysilicon layer away from the second tunneling oxide layer; An opening exposing the first passivation layer is provided on the second tunneling oxide layer, the second doped polysilicon layer and the second passivation layer, a first electrode is formed on a portion of the surface of the first passivation layer exposed to the second tunneling oxide layer, and a second electrode is formed on a surface of the second passivation layer away from the second doped polysilicon layer.

7. The solar cell according to claim 6, characterized in that: The insulating isolation layer is used to isolate the N region and the P region of the solar cell.

8. The solar cell according to claim 6, characterized in that: The thickness of the insulating isolation layer is consistent with the sum of the thicknesses of the first tunneling oxide layer, the first doped polysilicon layer and the first passivation layer.

9. The solar cell according to claim 6, characterized in that: The width of the opening is greater than the width of the first electrode.

10. The solar cell according to claim 9, characterized in that: A difference between a width of the opening and a width of the first electrode is comprised between 30 um and 60 um.

Images