Photovoltaic cell and preparation method thereof

Abstract

The invention provides a photovoltaic cell and a preparation method thereof, and relates to the technical field of photovoltaics. The photovoltaic cell preparation method comprises the steps that a substrate is provided, the substrate is provided with a first surface and a second surface which are opposite, and the first surface comprises a first area, a second area and a third area located between the first area and the second area; sequentially stacking a first tunneling oxide layer, an intrinsic polycrystalline silicon layer and a first doping layer on the first surface; removing the first tunneling oxide layer, the intrinsic polycrystalline silicon layer and the first doping layer on the second region and the third region to form a third surface of the substrate; diffusing a first doping element of the first doping layer to the intrinsic polycrystalline silicon layer to form a first doping polycrystalline silicon layer opposite to the first region; a second tunneling oxide layer and a second doped polycrystalline silicon layer are sequentially stacked on the part, corresponding to the second area, of the third surface; and removing a part, opposite to the first region, of the first doping layer. The preparation method can reduce the loss of the substrate.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a photovoltaic cell and a preparation method thereof. Background Art

[0002] The statements in this section merely provide background art related to the present invention and do not necessarily constitute prior art.

[0003] The TOPCon technology in the Tunnel Oxide Passivated Contact (TOPCon) photovoltaic cell can be applied to the interdigitated back contact photovoltaic cell (IBC) to form a new type of cell to improve the efficiency of the photovoltaic cell, for example, the tunneling oxide passivated contact back contact cell (TBC). In the preparation process of photovoltaic cells such as TBC, the silicon substrate needs to be etched and chemically cleaned multiple times, resulting in high losses. Summary of the invention

[0004] The object of the present invention is to provide a photovoltaic cell and a method for preparing the same, so as to solve the technical problem of high silicon substrate loss in the method for preparing the photovoltaic cell.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] In a first aspect, the present invention provides a method for preparing a photovoltaic cell, comprising:

[0007] Providing a substrate, the substrate having a first surface and a second surface opposite to each other, the first surface comprising a first region, a second region, and a third region located between the first region and the second region;

[0008] A first tunneling oxide layer, an intrinsic polysilicon layer and a first doping layer are sequentially stacked on the first surface;

[0009] removing the first tunneling oxide layer, the intrinsic polysilicon layer, and the first doping layer on the second region and the third region to form a third surface of the substrate;

[0010] diffusing the first doping element of the first doping layer into the intrinsic polysilicon layer to form a first doped polysilicon layer opposite to the first region;

[0011] stacking a second tunneling oxide layer and a second doped polysilicon layer in sequence on a portion of the third surface corresponding to the second region;

[0012] A portion of the first doping layer opposite to the first region is removed.

[0013] According to at least one embodiment of the present invention, before sequentially stacking the first tunneling oxide layer, the intrinsic polysilicon layer and the first doping layer on the first surface, the preparation method further includes:

[0014] forming a first velvet surface on the first surface; and / or,

[0015] A second textured surface is formed on the second surface.

[0016] According to at least one embodiment of the present invention, after sequentially stacking a second tunneling oxide layer and a second doped polysilicon layer on the portion of the third surface corresponding to the second region, and before removing the portion of the first doped layer corresponding to the first region, the preparation method further includes:

[0017] A third textured surface is formed on a portion of the third surface corresponding to the third area.

[0018] According to at least one embodiment of the present invention, when a second tunneling oxide layer and a second doped polysilicon layer are sequentially stacked on a portion of the third surface corresponding to the second region, the preparation method comprises:

[0019] The second tunneling oxide layer and the second doped polysilicon layer are sequentially stacked on a side of the first doped layer facing away from the substrate and on the third surface;

[0020] A portion of the second tunneling oxide layer opposite to the first region and the third region and a portion of the second doped polysilicon layer opposite to the first region and the third region are removed.

[0021] According to at least one embodiment of the present invention, a second doped layer is further formed on a side of the second doped polysilicon layer facing away from the substrate;

[0022] Before removing the portion of the second tunneling oxide layer opposite to the first region and the third region and the portion of the second doped polysilicon layer opposite to the first region and the third region, the preparation method further includes:

[0023] A portion of the second doping layer opposite to the first region and the third region is removed.

[0024] According to at least one embodiment of the present invention, when removing the portion of the first doping layer opposite to the first region, the preparation method further includes:

[0025] A portion of the second doping layer opposite to the second region is removed.

[0026] According to at least one embodiment of the present invention, after removing the portion of the first doping layer opposite to the first region, the preparation method further includes:

[0027] stacking a first passivation anti-reflection layer on the first doped polysilicon layer, the second doped polysilicon layer, and a portion of the third surface corresponding to the third region;

[0028] A first electrode is arranged along the stacking direction, penetrating a portion of the first passivation anti-reflection layer located on the first doped polysilicon layer, and connected to the first doped polysilicon layer;

[0029] A second electrode is disposed to penetrate a portion of the first passivation anti-reflection layer located on the second doped polysilicon layer and to form a connection with the second doped polysilicon layer.

[0030] According to at least one embodiment of the present invention, when a first passivation anti-reflection layer is stacked on the first doped polysilicon layer, the second doped polysilicon layer, and a portion of the third surface corresponding to the third region, the preparation method further includes:

[0031] A second passivation anti-reflection layer is stacked on the second surface or the second suede surface.

[0032] According to at least one embodiment of the present invention, the first doped layer is a borosilicate glass layer, and the step of diffusing a first doping element of the first doped layer into the intrinsic polysilicon layer to form a first doped polysilicon layer opposite to the first region includes:

[0033] diffusing the borosilicate glass layer as a boron source into the intrinsic polysilicon layer to form the first doped polysilicon layer doped with boron; or,

[0034] The first doped layer is a phosphosilicate glass layer, and the step of diffusing a first doping element of the first doped layer into the intrinsic polysilicon layer to form a first doped polysilicon layer opposite to the first region includes:

[0035] The phosphosilicate glass layer is used as a phosphorus source and diffused into the intrinsic polysilicon layer to form the first doped polysilicon layer doped with phosphorus.

[0036] According to at least one embodiment of the present invention, the second doped polysilicon layer includes one of a phosphorus-doped second doped polysilicon layer or a boron-doped second doped polysilicon layer.

[0037] In a second aspect, the present invention further provides a photovoltaic cell, which is prepared by the preparation method described in the first aspect.

[0038] Among the one or more technical solutions provided in the exemplary embodiments of the present invention, at least one of the following beneficial effects can be achieved.

[0039] In the photovoltaic cell preparation method of the exemplary embodiment of the present invention, a first tunneling oxide layer, an intrinsic polysilicon layer and a first doped layer are sequentially stacked on the first surface of the substrate, and then the three-layer structure in the second region and the third region is removed, and the three-layer structure in the first region is retained. The first doped polysilicon layer is formed on the first region by diffusing the first doping element of the first doped layer into the intrinsic polysilicon layer, and the second doped polysilicon layer on the third region is formed in a subsequent process. In the prior art, a first tunneling oxide layer, a first doped polysilicon layer and a first doped layer are sequentially formed on the entire region of the first surface of the substrate, and then the first tunneling oxide layer, the first doped polysilicon layer and the first doped layer on the second region and the third region are removed, and the first tunneling oxide layer and the first doped polysilicon layer on the first region are retained, thereby inevitably forming a shallowly doped doped base layer on the substrate in the entire region of the first surface, and the portion of the doped base layer located in the second region and the third region needs to be removed in a subsequent process, thereby increasing the loss of the substrate.

[0040] Compared with the prior art, in the preparation method of the exemplary embodiment of the present invention, after removing the first tunneling oxide layer, the intrinsic polysilicon layer and the first doped layer in the second region and the third region, the first doped polysilicon layer is formed on the first region, thereby avoiding the formation of a doped base layer on the second region and the third region, and thus avoiding the removal of this part of the doped base layer in the subsequent process. Based on this, the preparation method of the exemplary embodiment of the present invention can minimize the loss of the substrate, and for the same substrate, can improve the power generation efficiency of the substrate compared with the preparation method of the prior art.

[0041] At the same time, in the photovoltaic cell prepared by the method of the exemplary embodiment of the present invention, one less doped matrix layer is removed from the second region and the third region compared with the prior art, so the height difference between the second region and the first region is reduced. In the process of forming the gate line in the second region in the subsequent process, the amount of gate line slurry used is reduced, and it is not easy to have a bad gate line shape.

[0042] Furthermore, a laser etching process is usually used in the process of removing the second region and the third region. The preparation method of the exemplary embodiment of the present invention requires removing the intrinsic polysilicon layer of the above-mentioned region, while the prior art requires removing the first doped polysilicon layer of the above-mentioned region. Since the laser energy required for removing the intrinsic polysilicon layer is lower than that of the first doped polysilicon layer, the difficulty of laser etching can be effectively reduced and the cost is lower. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings illustrate exemplary embodiments of the present invention and together with the description serve to explain the principles of the present invention, and these drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification;

[0044] Figure 1 is a schematic flow chart of a method for preparing a photovoltaic cell according to an embodiment of the present invention;

[0045] Figures 2 to 11 is a schematic cross-sectional diagram of a process structure corresponding to each step in a method for preparing a photovoltaic cell according to an embodiment of the present invention;

[0046] Figures 12 to 19 It is a schematic diagram of the corresponding process structure cross-section after each step in the photovoltaic cell preparation method in the comparative example is completed.

[0047] Reference numerals: 10, substrate; 11, first surface; 12, second surface; 13, third surface;

[0048] 21. first tunneling oxide layer; 22. intrinsic polysilicon layer; 22a. first doped polysilicon layer; 22b. doped base layer; 23. first doped layer;

[0049] 31. second tunneling oxide layer; 32. second doped polysilicon layer; 33. second doped layer;

[0050] 42, second suede side; 43, third suede side;

[0051] 51. a first passivation anti-reflection layer; 52. a second passivation anti-reflection layer;

[0052] 61. First electrode; 62. Second electrode. DETAILED DESCRIPTION

[0053] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0054] Before introducing the embodiments of the present invention, the following definitions are given for the relevant terms involved in the embodiments of the present invention:

[0055] Fill Factor (FF) can be used to measure the impact of internal resistance and electron loss on the performance of photovoltaic devices in photovoltaic cells and other optoelectronic devices. Fill factor is a characteristic of the current-voltage (IV) curve. Fill factor represents the ratio of the maximum output power ImVm to the limit output power IscVoc, that is: FF = ImVm / IscVoc.

[0056] The fill factor ranges from 0 to 1. The closer it is to 1, the better the performance of the optoelectronic device. The fill factor is mainly determined by the series resistance, bypass resistance and PN junction characteristics. When the series resistance increases, the bypass resistance decreases, and there are defects and impurities in the PN junction, the FF will become smaller. In addition, the fill factor increases with the increase of the bandgap width of the battery material.

[0057] Short Circuit Current Density (Jsc) refers to the current density per unit area generated by a photovoltaic cell in a short circuit state. In the short circuit state, the two electrodes of the photovoltaic cell are directly connected together without external load. Its value is expressed as the intercept size of the vertical axis in the JV curve diagram, and the unit is mA / cm 2 Jsc is mainly affected by the intensity of incident light and the size of the material absorption band gap. The smaller the band gap, the stronger the ability to convert photons into electrical energy. In addition, the thickness of the device, the quality of each layer of film, and the carrier transmission capacity will also affect the size of Jsc.

[0058] Open circuit voltage (Voc) refers to the voltage difference between the two electrodes when the photovoltaic cell is not connected to any load. The specific value of the open circuit voltage is expressed as the intercept length on the horizontal axis in the JV curve diagram, and its unit is generally mV or V.

[0059] The calculation of conversion efficiency ETA (η) is usually used to measure the ability of photovoltaic cells to convert solar energy into electrical energy. Photovoltaic cell conversion efficiency η = (electrical energy generated by the cell / solar radiation energy irradiating the cell) × 100%.

[0060] The IBC cell structure is highly compatible with other high-efficiency cell structures. The tunneling oxide passivation contact technology of TOPCon photovoltaic cells can solve the problem of high recombination in the metal contact area on the back of N-type cells. It separates the N-type crystalline silicon substrate from the doped polysilicon layer through an ultra-thin tunneling oxide layer. Since the tunneling oxide layer is very thin, it will not hinder the transmission of majority carriers, but it will hinder minority carriers from reaching the interface, which can significantly reduce the recombination of the interface, and the highly doped polysilicon layer can form a good ohmic contact with the metal electrode.

[0061] Applying TOPCon technology to IBC cells can further improve the efficiency of solar cells. For example, TBC photovoltaic cells prepared using the above technology are currently a hot research topic. In the TBC production process, multiple laser etching and alkaline and acid cleaning processes are required, which will increase the loss of silicon substrates.

[0062] Figure 1is a schematic flow chart of a method for preparing a photovoltaic cell according to an embodiment of the present invention; Figures 2 to 11 1 is a schematic cross-sectional view of the process structure corresponding to each step in the photovoltaic cell preparation method according to the embodiment of the present invention. Figure 1 As shown, an exemplary embodiment of the present invention provides a method for preparing a photovoltaic cell, which may include the following steps:

[0063] Step 101: Provide a substrate 10, the substrate 10 having a first surface 11 and a second surface 12 opposite to each other, the first surface 11 including a first area E1, a second area E2 and a third area E3 located between the first area E1 and the second area E2, such as Figure 2 shown.

[0064] Exemplarily, the substrate 10 may be a silicon substrate, such as a p-type silicon substrate or an n-type silicon substrate. The front side (light-receiving side) of the substrate 10 is the second surface 12 , and the back side is the first surface 11 .

[0065] It should be noted that Figure 2 The substrate 10 does not have only one set of the first region E1, the second region E2 and the third region E3, but may have a plurality of sets of the above regions.

[0066] For example, the first surface 11 may have a first area E1, a third area E3, a second area E2, a third area E3, a first area E1, a third area E3, and a second area E2 arranged in sequence, and reciprocatingly; or, the first surface 11 may have a first area E1, a third area E3, a second area E2, a third area E3, a second area E2, a third area E3, and a first area E1 arranged in sequence, and reciprocatingly, that is, there is a third area E3 between each group of areas.

[0067] Step 102: stacking a first tunneling oxide layer 21, an intrinsic polysilicon layer 22 and a first doping layer 23 on the first surface 11 in sequence, such as Figure 3 shown.

[0068] The first tunnel oxide layer 21, the intrinsic polysilicon layer 22 and the first doping layer 23 may be deposited in sequence on the substrate 10 by deposition on the entire area of ​​the first surface 11. The deposition process may be vacuum evaporation, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD) or a combination of multiple deposition methods for sequential preparation.

[0069] An example is given for explanation in which a p region (positive electrode region) is formed in the first region E1 , an n region (negative electrode region) is formed in the second region E2 , and a spacer region between the p region and the n region is formed in the third region E3 .

[0070] Exemplarily, the first tunneling oxide layer 21 is a silicon oxide layer, and its thickness can be 0.5nn~3.0nm, for example, 0.7nm, 1nm, 1.5nm, 2nm, 2.5nm, etc. By reasonably controlling the thickness of the first tunneling oxide layer 21, the probability of collecting majority carriers can be increased, thereby improving the photoelectric conversion efficiency of the battery; the first doped layer 23 is a borosilicate glass layer (BoronSilicon Glass, BSG), and the process and cost of using a borosilicate glass layer are relatively low; the intrinsic polysilicon layer 22 is an undoped polysilicon layer.

[0071] Step 103: remove the first tunneling oxide layer 21, the intrinsic polysilicon layer 22 and the first doping layer 23 on the second area E2 and the third area E3 to form a third surface 13 of the substrate 10. Figure 4 shown.

[0072] For example, a method combining one or more methods of laser lift-off or chemical cleaning and etching may be used to remove the first tunneling oxide layer 21 , the intrinsic polysilicon layer 22 , and the first doping layer 23 on the second region E2 and the third region E3 .

[0073] For example, the specific process of laser stripping is to emit laser through a laser, bombard the surface with laser to remove the first doping layer 23 on the second area E2 and the third area E3; then, a chemical cleaning and etching method is used to remove the intrinsic polysilicon layer 22 and the first tunneling oxide layer 21 on the second area E2 and the third area E3, specifically, an alkaline cleaning solution, such as sodium hydroxide, is printed on the second area E2 and the third area E3 by a roller, and the intrinsic polysilicon layer 22 of the above-mentioned area is removed by corrosion, and then an acid cleaning solution, such as hydrofluoric acid, is printed on the above-mentioned area to remove the first tunneling oxide layer 21 of the above-mentioned area by corrosion.

[0074] In the process of removing the stacked structure on the second area E2 and the third area E3, the substrate 10 may be etched to a certain depth, thereby forming a third surface 13 of the substrate 10. The third surface 13 has a certain height difference H1 with the portion of the first surface 11 located in the first area E1, such as Figure 4 It is understandable that the above H1 can also be 0, that is, the third surface 13 can be flush with the first surface 11.

[0075] It should be noted that, in step 102, during the deposition of the stacked structure on the first surface 11, due to process reasons, a portion of the first tunneling oxide layer 21, the intrinsic polysilicon layer 22, and the first doping layer 23 may be plated on the second surface 12 of the substrate 10. Therefore, in this step 103, the above three materials plated on the second surface 12 need to be removed by chemical cleaning and etching.

[0076] Step 104: diffuse the first doping element of the first doping layer 23 into the intrinsic polysilicon layer 22 to form a first doped polysilicon layer 22a opposite to the first region E1. Figure 5 shown.

[0077] By adopting a high temperature annealing method, the borosilicate glass layer is used as a boron source to perform a diffusion process on the intrinsic polysilicon layer 22, so as to obtain a boron-doped polysilicon layer on the first area E1.

[0078] Exemplarily, in this step, the annealing temperature is 850°C to 1100°C, such as 900°C, 950°C, 1000°C, 1050°C, etc. Under the above annealing temperature conditions, the doping concentration of the first doped polysilicon layer 22a can be optimized. Exemplarily, the thickness of the first doped polysilicon layer 22a can be 50nm to 300nm, such as 60nm, 70nm, 80nm, 100nm, 150nm, 200nm, 250nm, etc.

[0079] Step 105: stacking a second tunneling oxide layer 31 and a second doped polysilicon layer 32 in sequence on a portion of the third surface 13 corresponding to the second region E2 to form Fig. 9 The structure shown.

[0080] Step 1051: A second tunneling oxide layer 31 and a second doped polysilicon layer 32 are sequentially stacked on the side of the first doped layer 23 facing away from the substrate 10 and on the third surface 13 to form a Figure 6 The structure shown.

[0081] The second tunneling oxide layer 31 and the second doped polysilicon layer 32 are stacked on the side of the first doped layer 23 away from the substrate 10, that is, the portion of the back side of the substrate 10 located in the first area E1, and the third surface 13, that is, the portion of the back side of the substrate 10 located in the third area E3 and the second area E2; in other words, a second tunneling oxide layer 31 is first deposited on the entire back side of the substrate 10 by deposition, and then a second doped polysilicon layer 32 is deposited. This embodiment can avoid the use of a mask process, and the preparation process is relatively simple and effective.

[0082] The second tunneling oxide layer 31 may be a silicon oxide layer, and its thickness may be 0.5 nm to 3.0 nm, for example, 0.7 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, etc. By reasonably controlling the thickness of the second tunneling oxide layer 31, the probability of collecting majority carriers may be increased, thereby improving the photoelectric conversion efficiency of the battery.

[0083] The thickness of the second doped polysilicon layer 32 may be 50 nm to 300 nm, such as 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, etc. Exemplarily, the thickness of the second doped polysilicon layer 32 may be consistent with or inconsistent with the thickness of the first doped polysilicon layer 22 a.

[0084] The second doping element of the second doped polysilicon layer 32 is different from the first doping element. When the first doping element is boron, the second doping element is phosphorus, that is, the second doped polysilicon layer 32 is a phosphorus-doped second doped polysilicon layer 32. In the final battery, the first region E1 forms a p-region, and the second region E2 forms an n-region.

[0085] When the first doping element is phosphorus, the second doping element is boron, that is, the second doped polysilicon layer 32 is a boron-doped second doped polysilicon layer 32, and in the battery finally formed, the first region E1 forms an n region, and the second region E2 forms a p region. In this embodiment, since the temperature of boron diffusion is higher than the temperature of phosphorus diffusion, phosphorus is first diffused in the first region E1 to form an n region, and then boron is diffused in the second region E2 to form a p region, which will affect the concentration of the active layer in the n region, and thus be detrimental to the photoelectric conversion efficiency of the battery.

[0086] Illustratively, in step 1051, the deposition process can be prepared in sequence by using any one of vacuum evaporation, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition and single atomic layer deposition, or a combination of multiple deposition methods.

[0087] In an optional embodiment, in step 1051, a mask plate is used to mask the corresponding portions of the first area E1 and the third area E3 on the back side of the substrate 10, and then a second tunneling oxide layer 31 and a second doped polysilicon layer 32 are stacked in sequence on the portion of the third surface 13 corresponding to the second area E2 through a deposition process.

[0088] Exemplarily, in this step 1051 , a second doped layer 33 is further formed on the side of the second doped polysilicon layer 32 facing away from the substrate 10 .

[0089] In the process of forming the second doped polysilicon layer 32 on the second tunnel oxide layer 31, the second doped layer 33 is naturally formed. Taking the second doped polysilicon layer 32 as a phosphorus-doped second doped polysilicon layer 32 as an example, a phosphorus silicon glass layer (PSG) is naturally formed on the second doped polysilicon layer 32. Figure 6 shown.

[0090] Step 1052: removing the portion of the second tunnel oxide layer 31 opposite to the first region E1 and the third region E3 and the portion of the second doped polysilicon layer 32 opposite to the first region E1 and the third region E3, to form Figure 7 The structure shown.

[0091] Exemplarily, a method combining one or more methods of laser stripping or chemical cleaning and etching can be used to remove the portion of the second tunneling oxide layer 31 opposite to the first region E1 and the third region E3 and the portion of the second doped polysilicon layer 32 opposite to the first region E1 and the third region E3.

[0092] For example, the specific process of laser stripping is to emit laser through a laser and bombard the surface with laser to remove the portion of the second doped polysilicon layer 32 opposite to the first area E1 and the third area E3, and the portion of the second tunneling oxide layer 31 opposite to the first area E1 and the third area E3, so as to expose the first doped layer 23 opposite to the first area E1 and the portion of the third surface 13 located in the third area E3.

[0093] When the second doped layer 33 is formed during the formation of the second doped polysilicon layer 32, in step 1052, the photovoltaic cell preparation method further includes removing the portion of the second doped layer 33 that is opposite to the first region E1 and the third region E3.

[0094] Since the second doped layer 33 is located on the side of the second doped polysilicon layer 32 facing away from the substrate 10, in order to remove the portion of the second doped polysilicon layer 32 opposite to the first region E1 and the third region E3, and the portion of the second tunneling oxide layer 31 opposite to the first region E1 and the third region E3, the second doped layer 33 needs to be removed first.

[0095] For example, the portion of the second doping layer 33 opposite to the first region E1 and the third region E3 may be removed by etching in a laser lift-off manner.

[0096] Exemplarily, the portion of the second doping layer 33 opposite to the first area E1 and the third area E3 can also be removed by pickling, for example, by printing a hydrofluoric acid solution to etch away the second doping layer 33. Specifically, the hydrofluoric acid solution is printed on the first area E1 and the third area E3 by a roller to etch away the second doping layer 33 on the two areas.

[0097] Step 1053: forming a third velvet surface 43 on a portion of the third surface 13 corresponding to the third area E3, such as Figure 8 shown.

[0098] Exemplarily, when the third pile surface 43 is formed on the portion of the third surface 13 corresponding to the third area E3 , the second pile surface 42 is also formed on the second surface 12 .

[0099] For example, by alkaline washing, such as a method of etching by reacting a sodium hydroxide solution with the surface of the substrate 10 , a textured surface is formed on the portion of the third surface 13 corresponding to the third area E3 and on the second surface 12 .

[0100] It should be noted that before this step 1053, the second surface 12 of the substrate 10 may be coated with a second doped layer 33, a second doped polysilicon layer 32 and a second tunneling oxide layer 31. Therefore, before the velvet surface is formed on the second surface 12, it is necessary to remove the layers of the second surface 12 by acid washing or alkaline washing to expose the silicon base of the substrate 10.

[0101] Step 106: removing the portion of the first doping layer 23 opposite to the first region E1 to form Fig. 9 The structure shown.

[0102] After step 1052, a portion of the first doped layer 23 opposite to the first region E1 is exposed. The portion of the first doped layer 23 needs to be removed to expose the first doped polysilicon layer 22a for subsequent formation of a battery structure.

[0103] When the second doped layer 33 is formed during the formation of the second doped polysilicon layer 32, in this step 106, the photovoltaic cell preparation method further includes removing the portion of the second doped layer 33 that is opposite to the second region E2. For example, the portion of the second doped layer 33 that is opposite to the second region E2 can be etched away by laser stripping or pickling. The specific etching method is the same as that of removing the corresponding portion of the second doped layer 33 in step 105, and will not be described in detail herein.

[0104] Step 107: After removing the portion of the first doping layer 23 opposite to the first region E1, the method for preparing the photovoltaic cell further includes stacking a first passivation anti-reflection layer 51 on the back side and forming an electrode.

[0105] Step 1071: stacking a first passivation anti-reflection layer 51 on the first doped polysilicon layer 22a, the second doped polysilicon layer 32, and a portion of the third surface corresponding to the third region E3.

[0106] The first passivation anti-reflection layer 51 is deposited on the entire back side of the substrate 10 , that is, the first passivation anti-reflection layer 51 covers the first doped polysilicon layer 22 a , the second doped polysilicon layer 32 , and a portion of the third surface corresponding to the third region E3 .

[0107] Exemplarily, the material of the first passivation anti-reflection layer 51 may be one or more of aluminum oxide, silicon nitride, silicon oxynitride or silicon oxide.

[0108] Step 1072: When the first passivation anti-reflection layer 51 is stacked on both the first doped polysilicon layer 22a and the second doped polysilicon layer 32, the preparation method further comprises: stacking the second passivation anti-reflection layer 52 on the second surface 12 or the second velvet surface 42 to form a Fig.10 The structure shown.

[0109] The method of stacking the second passivation anti-reflection layer 52 is the same as the method of stacking the first passivation anti-reflection layer 51 in step 1071 , which will not be described again. The material of the second passivation anti-reflection layer 52 can be the same as or different from that of the first passivation anti-reflection layer 51 .

[0110] Step 1073: Along the stacking direction, a first electrode 61 is arranged to penetrate a portion of the first passivation anti-reflection layer 51 located at the first doped polysilicon layer 22a, and is connected to the first doped polysilicon layer 22a; a second electrode 62 is arranged to penetrate a portion of the first passivation anti-reflection layer 51 located at the second doped polysilicon layer 32, and is connected to the second doped polysilicon layer 32, so as to form a Fig.11 The structure shown.

[0111] The stacking direction is perpendicular to the first surface 11 of the substrate 10, and the corresponding metal electrodes are prepared on the first region E1 and the second region E2 by printing electrode paste. For example, one end of the first electrode 61 is located outside the first passivation anti-reflection layer 51, and the other end penetrates the first passivation anti-reflection layer 51 and extends to the first doped polysilicon layer 22a to form an electrical connection therewith; one end of the second electrode 62 is located outside the first passivation anti-reflection layer 51, and the other end penetrates the first passivation anti-reflection layer 51 and extends to the second doped polysilicon layer 32 to form an electrical connection therewith, thereby forming a photovoltaic cell.

[0112] Exemplarily, when the first doped polysilicon layer 22 a is a boron-doped first doped polysilicon layer 22 a , the first electrode 61 is a positive electrode, and correspondingly, the second electrode 62 is a negative electrode.

[0113] In some embodiments, when the first doped polysilicon layer 22 a is a phosphorus-doped first doped polysilicon layer 22 a , the first electrode 61 is a negative electrode, and correspondingly, the second electrode 62 is a positive electrode.

[0114] In some embodiments, before step 102 and after step 101, the photovoltaic cell preparation method of the exemplary embodiment of the present invention further includes a texturing step and a polishing step.

[0115] Illustratively, before stacking the first tunneling oxide layer 21 , the intrinsic polysilicon layer 22 and the first doping layer 23 in sequence on the first surface 11 , a first velvet surface (not shown in the figure) is formed on the first surface 11 of the substrate 10 , and optionally, a second velvet surface 42 is formed on the second surface 12 .

[0116] For example, a velvet surface can be formed on both the first surface 11 and the second surface 12 of the substrate 10 by alkaline washing, and at the same time, dirt, impurities, metal ions, etc. on the surface of the substrate 10 can be removed by alkaline washing or acid washing for polishing.

[0117] The surface of the substrate 10 is textured before step 102, so that the stacked structure formed later on the first region E1, the first tunneling oxide layer 21, the first doped polysilicon layer 22a and the first passivation anti-reflection layer 51 all have a textured effect, and the photoelectric conversion efficiency is improved by using the light trapping effect. If the texture is formed in a subsequent process, such as step 1053, the first region E1 of the substrate 10 is already covered with a stacked structure, and the texture cannot be formed on the first region E1 of the substrate 10, and the photoelectric conversion efficiency is reduced.

[0118] Examples and comparative examples are given below to illustrate the technical effects of the preparation method of the exemplary embodiment of the present invention.

[0119] Example 1

[0120] like Figure 2-Figure 11 As shown, a method for preparing a TBC photovoltaic cell comprises the following steps:

[0121] Step 201: Double-sided texturing is performed on the first surface 11 and the second surface 12 of the silicon substrate 10, wherein the first surface 11 has at least one group of regions, each group of regions is divided into a first region E1, a second region E2, and a third region E3 located between the first region E1 and the second region E2 as a spacer. The silicon substrate 10 is an n-type silicon base.

[0122] Step 202: depositing a first tunneling oxide layer 21, an intrinsic polysilicon layer 22 and a borosilicate glass layer on the first surface 11 in sequence, wherein the first tunneling oxide layer 21 is silicon oxide and has a thickness of 1.8 nm.

[0123] Step 203: Use laser to remove the borosilicate glass layer, the first tunneling oxide layer 21, and the intrinsic polysilicon layer 22 in the second area E2 and the third area E3. The height difference between the first area E1 and the second area E2 is H1, H1 = 0.5 μm; wherein the laser wavelength is 355 nm, the output power is 3 W, and the scanning speed is 2000 mm / s.

[0124] The borosilicate glass layer and the first tunnel oxide layer 21 on the second surface 12 are removed by acid washing; and the intrinsic polysilicon layer 22 is removed by alkali washing.

[0125] Step 204: high temperature annealing at 1000° C., using the borosilicate glass layer as a boron source to diffuse the intrinsic polysilicon layer 22 , to obtain a p-type first doped polysilicon layer 22 a with a thickness of 120 nm.

[0126] Step 205: A second tunneling oxide layer 31 (silicon oxide) with a thickness of 1.8 nm and an n-type second doped polysilicon layer 32 (phosphorus doped) with a thickness of 120 nm are sequentially deposited on the back side of the silicon substrate 10 to naturally form a phosphorus silicon glass layer.

[0127] Step 206 : removing the second tunneling oxide layer 31 , the second doped polysilicon layer 32 and the phosphosilicate glass layer in the first region E1 and the third region E3 by laser.

[0128] Step 207: remove the phosphosilicate glass layer, the second tunnel oxide layer 31, and the second doped polysilicon layer 32 on the second surface 12. Form a textured surface on the second surface 12 and the third surface 13 corresponding to the third area E3.

[0129] Step 208: Acid cleaning, using a hydrofluoric acid solution to remove the borosilicate glass layer in the first area E1 and the phosphosilicate glass layer in the second area E2.

[0130] Step 209: depositing a second passivation anti-reflection layer 52 and a first passivation anti-reflection layer 51 on the second surface 12 and the back surface of the substrate 10 , respectively, wherein the second passivation anti-reflection layer 52 and the first passivation anti-reflection layer 51 are aluminum oxide layers, respectively.

[0131] Step 210: preparing a first electrode 61 on the first region E1, which penetrates the first passivation anti-reflection layer 51 and is electrically connected to the first doped polysilicon layer 22a;

[0132] A second electrode 62 is prepared on the second region E2 , which penetrates the first passivation anti-reflection layer 51 and is electrically connected to the second doped polysilicon layer 32 , thereby preparing a TBC photovoltaic cell.

[0133] Example 2

[0134] The difference between this embodiment and embodiment 1 is only that:

[0135] In step 203 , the height difference H1 between the first region E1 and the second region E2 is 1.0 μm.

[0136] Example 3

[0137] The difference between this embodiment and embodiment 1 is only that:

[0138] In step 203 , the height difference H1 between the first region E1 and the second region E2 is 1.5 μm.

[0139] Comparative Example

[0140] Figure 12-Figure 19 The schematic diagram of the cross-sectional process structure corresponding to each step in the photovoltaic cell preparation method in the comparative example is shown. A TBC photovoltaic cell preparation method comprises the following steps:

[0141] Step 301: Double-sided texturing is performed on the first surface 11 and the second surface 12 of the silicon substrate 10, wherein the first surface 11 has at least one group of regions, each group of regions is divided into a first region E1, a second region E2, and a third region E3 located between the first region E1 and the second region E2 as a spacer. The silicon substrate 10 is an n-type silicon base.

[0142] Step 302: depositing a first tunneling oxide layer 21, a first doped polysilicon layer 22a and a first doped layer 23 on the first surface 11 in sequence, wherein the first doped layer 23 is a borosilicate glass layer naturally formed when the first doped polysilicon layer 22a is formed; the first tunneling oxide layer 21 is silicon oxide and has a thickness of 1.8 nm. Fig.12 shown.

[0143] Step 303: laser removal of the borosilicate glass layer, the first tunneling oxide layer 21, the first doped polysilicon layer 22a, and the doped base layer 22b in the second region E2 and the third region E3. The height difference between the first region E1 and the second region E2 is H2. Since the doped base layer 22b must be removed, at this time, H2=3μm, H2>H1, and the damage amount of the silicon substrate 10 is greater than that of the embodiment, as shown in FIG. Fig.13 As shown; wherein, the laser wavelength is 355nm, the output power is 3W, and the scanning speed is 2000mm / s.

[0144] The borosilicate glass layer and the first tunneling oxide layer 21 on the second surface 12 are removed by acid washing; and the first doped polysilicon layer 22a is removed by alkali washing.

[0145] Step 304: A second tunneling oxide layer 31 (silicon oxide) with a thickness of 1.8 nm and an n-type second doped polysilicon layer 32 (phosphorus doped) with a thickness of 120 nm are sequentially deposited on the back side of the silicon substrate 10 to naturally form a phosphorus silicon glass layer. Fig.14 shown.

[0146] Step 305: laser removal of the second tunnel oxide layer 31, the second doped polysilicon layer 32 and the phosphosilicate glass layer in the first region E1 and the third region E3. Fig.15 shown.

[0147] Step 306: remove the phosphosilicate glass layer, the second tunnel oxide layer 31, and the second doped polysilicon layer 32 on the second surface 12. Form a velvet surface on the second surface 12 and the third surface 13 corresponding to the third area E3, such as Fig.16 shown.

[0148] Step 307: Acid cleaning, using a hydrofluoric acid solution to remove the borosilicate glass layer in the first region E1 and the phosphosilicate glass layer in the second region E2. Fig.17 shown.

[0149] Step 308: depositing a second passivation anti-reflection layer 52 and a first passivation anti-reflection layer 51 on the second surface 12 and the back side of the substrate 10, respectively, wherein the second passivation anti-reflection layer 52 and the first passivation anti-reflection layer 51 are aluminum oxide layers, respectively. Fig.18 shown.

[0150] Step 309: preparing a first electrode 61 on the first area E1, which penetrates the first passivation anti-reflection layer 51 and is electrically connected to the first doped polysilicon layer 22a;

[0151] A second electrode 62 is prepared on the second region E2, which penetrates the first passivation anti-reflection layer 51 and is electrically connected to the second doped polysilicon layer 32, so as to prepare a TBC photovoltaic cell. Fig.19 shown.

[0152] Table 1 Electrical performance data of TBC photovoltaic cells

[0153] <![CDATA[Jsc(mA / cm 2 )]]> Voc(mV) FF(%) Eta(%) Example 1 43.27 734.6 81.38 25.87 Example 2 43.25 734.7 81.29 25.83 Example 3 43.27 734.8 81.21 25.82 Comparative Example 43.26 734.6 80.67 25.64

[0154] Table 2 Fine grid slurry consumption of TBC photovoltaic cells

[0155]

[0156]

[0157] As shown in Table 1, in the photovoltaic cells prepared by the TBC photovoltaic cell preparation methods of Examples 1 to 3, the short-circuit current density of Examples 1 and 3 was increased by 0.01 mA / cm2 compared with the photovoltaic cells prepared in the comparative example. 2 , the filling factor of Example 1 to Example 3 is increased by 0.71% at most, and the photoelectric conversion efficiency of Example 1 to Example 3 is increased by 0.23% at most. It can be seen that the photovoltaic cell preparation method of the exemplary embodiment of the present invention improves the conversion efficiency of the cell on the basis of reducing the loss of the silicon substrate.

[0158] As shown in Table 2, the photovoltaic cell prepared by the TBC photovoltaic cell preparation method of the embodiment has a 14% reduction in the amount of fine grid slurry used in the N region (second region) and a 3.5% reduction in the amount of fine grid slurry used in the P region (first region) relative to the photovoltaic cell prepared in the comparative example. It can be seen that the photovoltaic cell preparation method of the exemplary embodiment of the present invention reduces the loss of the silicon substrate, that is, reduces the height difference between the first region E1 and the second region E2 (H2>H1), and avoids the problem of excessive use of fine grid slurry in the N region with a lower height as much as possible. At the same time, reducing the height difference can also avoid the occurrence of poor grid line shape as much as possible.

[0159] As can be seen from the above, in the comparative example, a first tunneling oxide layer 21, a first doped polysilicon layer 22a and a borosilicate glass layer are sequentially formed on the entire area of ​​the first surface 11 of the substrate 10, and then the first tunneling oxide layer 21, the first doped polysilicon layer 22a and the borosilicate glass layer on the second area E2 and the third area E3 are removed, and the first tunneling oxide layer 21 and the first doped polysilicon layer 22a on the first area E1 are retained. As a result, a layer of shallowly doped doped base layer 22b is inevitably formed on the substrate 10 on the entire area of ​​the first surface 11, and the portion of the doped base layer 22b located in the second area E2 and the third area E3 needs to be removed in a subsequent process, thereby increasing the loss of the substrate 10, that is, the height difference H2 between the first area E1 and the second area E2 is large.

[0160] In the preparation methods of Examples 1 to 3 of the present invention, after removing the first tunneling oxide layer 21, the intrinsic polysilicon layer 22, and the borosilicate glass layer in the second region E2 and the third region E3, the first doped polysilicon layer 22a is formed on the first region E1, thereby avoiding the formation of the doped base layer 22b on the second region E2 and the third region E3, and thus avoiding the removal of the doped base layer 22b in the subsequent process, that is, the height difference H1 between the first region E1 and the second region E2 is reduced relative to H2 in the prior art. Based on this, the preparation method of the exemplary embodiment of the present invention can minimize the loss of the substrate, and for the same substrate, the power generation efficiency of the substrate can be improved relative to the preparation method of the prior art.

[0161] The exemplary embodiment of the present invention further provides a photovoltaic cell, which is manufactured using the photovoltaic cell manufacturing method of the above embodiment.

[0162] An exemplary embodiment of the present invention further provides a photovoltaic cell assembly, comprising the photovoltaic cell of the above embodiment.

[0163] The technical advantages of the above-mentioned photovoltaic cells and photovoltaic cell modules over the prior art are the same as the advantages of the above-mentioned photovoltaic cell preparation method, which will not be repeated here.

[0164] It should be understood by those skilled in the art that the above embodiments are only for the purpose of clearly illustrating the present invention, and are not intended to limit the scope of the present invention. For those skilled in the art, other changes or modifications may be made based on the above disclosure, and these changes or modifications are still within the scope of the present invention.

Claims

1. A method for preparing a photovoltaic cell, characterized in that: include: Providing a substrate, the substrate having a first surface and a second surface opposite to each other, the first surface comprising a first region, a second region, and a third region located between the first region and the second region; A first tunneling oxide layer, an intrinsic polysilicon layer and a first doping layer are sequentially stacked on the first surface; removing the first tunneling oxide layer, the intrinsic polysilicon layer, and the first doping layer on the second region and the third region to form a third surface of the substrate; diffusing a first doping element of the first doping layer into the intrinsic polysilicon layer to form a first doped polysilicon layer opposite to the first region; stacking a second tunneling oxide layer and a second doped polysilicon layer in sequence on a portion of the third surface corresponding to the second region; A portion of the first doping layer opposite to the first region is removed.

2. The preparation method according to claim 1, characterized in that: Before sequentially stacking a first tunneling oxide layer, an intrinsic polysilicon layer, and a first doping layer on the first surface, the preparation method further includes: forming a first velvet surface on the first surface; and / or, A second textured surface is formed on the second surface.

3. The preparation method according to claim 1, characterized in that: After sequentially stacking a second tunneling oxide layer and a second doped polysilicon layer on the portion of the third surface corresponding to the second region, and before removing the portion of the first doped layer corresponding to the first region, the preparation method further includes: A third textured surface is formed on a portion of the third surface corresponding to the third area.

4. The preparation method according to claim 1, characterized in that: When a second tunneling oxide layer and a second doped polysilicon layer are sequentially stacked on a portion of the third surface corresponding to the second region, the preparation method comprises: The second tunneling oxide layer and the second doped polysilicon layer are sequentially stacked on a side of the first doped layer facing away from the substrate and on the third surface; A portion of the second tunneling oxide layer opposite to the first region and the third region and a portion of the second doped polysilicon layer opposite to the first region and the third region are removed.

5. The preparation method according to claim 4, characterized in that: A second doped layer is also formed on a side of the second doped polysilicon layer facing away from the substrate; Before removing the portion of the second tunneling oxide layer opposite to the first region and the third region and the portion of the second doped polysilicon layer opposite to the first region and the third region, the preparation method further includes: A portion of the second doping layer opposite to the first region and the third region is removed.

6. The preparation method according to claim 5, characterized in that: When removing the portion of the first doping layer opposite to the first region, the preparation method further includes: A portion of the second doping layer opposite to the second region is removed.

7. The preparation method according to claim 2, characterized in that: After removing the portion of the first doping layer opposite to the first region, the preparation method further includes: stacking a first passivation anti-reflection layer on the first doped polysilicon layer, the second doped polysilicon layer, and a portion of the third surface corresponding to the third region; A first electrode is arranged along the stacking direction, penetrating a portion of the first passivation anti-reflection layer located on the first doped polysilicon layer, and connected to the first doped polysilicon layer; A second electrode is disposed to penetrate a portion of the first passivation anti-reflection layer located on the second doped polysilicon layer and to form a connection with the second doped polysilicon layer.

8. The preparation method according to claim 7, characterized in that: When a first passivation anti-reflection layer is stacked on the first doped polysilicon layer, the second doped polysilicon layer, and a portion of the third surface corresponding to the third region, the preparation method further includes: A second passivation anti-reflection layer is stacked on the second surface or the second suede surface.

9. The preparation method according to claim 5, characterized in that: The first doped layer is a borosilicate glass layer, and the step of diffusing a first doping element of the first doped layer into the intrinsic polysilicon layer to form a first doped polysilicon layer opposite to the first region includes: diffusing the borosilicate glass layer as a boron source into the intrinsic polysilicon layer to form the first doped polysilicon layer doped with boron; Preferably, the second doped polysilicon layer includes one of a phosphorus-doped second doped polysilicon layer or a boron-doped second doped polysilicon layer.

10. A photovoltaic cell, characterized in that: The method is prepared by the method according to any one of claims 1 to 9.

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