Preparation method of solar cell and solar cell
By setting up a stacked structure and an insulating isolation layer on the silicon substrate of the solar cell, combined with a passivation and anti-reverse layer, the problem of poor isolation of the n/p region of the interdigital back contact battery is solved, reducing the risk of leakage and improving the battery rigorous isolation.
Patent Information
- Application Number
- CN202411270744.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-11
- Publication Date
- 2024-12-20
AI Technical Summary
Existing interdigital back contact solar cells have poor effect in the n/p zone isolation, resulting in a risk of leakage.
By forming a first tunneling oxide layer and a first doped polysilicon layer arranged in sequence on the back of a portion of the silicon substrate, and an insulating isolation layer is provided on its side walls, and then a second tunnel is formed on the exposed back of the silicon substrate. The oxide layer and the second doped polysilicon layer are respectively enclosed with the passivation and reverse reduction layer to enhance the isolation tightness between the n/p regions.
It effectively reduces the risk of leakage of solar cells between n/p zones and improves the isolation of the battery.
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Figure CN119170702A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of interdigitated back contact cells, and in particular to a method for preparing a solar cell and a solar cell. Background Art
[0002] As the efficiency of traditional PERC, TOPCon and other solar cells gradually approaches the theoretical efficiency limit, researchers are gradually focusing on interdigitated back contact cells in pursuit of higher efficiency cells. At present, back contact solar cells usually require more complex processes to achieve n / p region isolation, but the effect of n / p region isolation is not good.
[0003] In the related art, in order to minimize the impact of leakage current, n / p region isolation is achieved by combining laser film opening and wet processing. However, the solar cells made by this method still have the problem that the n / p regions cannot be completely isolated, resulting in the risk of leakage current. Summary of the invention
[0004] Based on this, it is necessary to provide a method for preparing a solar cell and a solar cell that can reduce the risk of leakage.
[0005] In a first aspect, the present application discloses a method for preparing a solar cell, the method for preparing a solar cell comprising:
[0006] Forming a first tunneling oxide layer and a first doped polysilicon layer stacked in sequence on a portion of the back side of the silicon substrate;
[0007] An insulating isolation layer is provided on the exposed portion of the silicon substrate; the insulating isolation layer is close to the sidewalls of the first tunneling oxide layer and the first doped polysilicon layer;
[0008] Forming a second tunneling oxide layer and a second doped polysilicon layer stacked in sequence; the second tunneling oxide layer covers the exposed back side of the silicon substrate; wherein the second doped polysilicon layer and the first doped polysilicon layer have different doping types;
[0009] A passivation anti-reflection layer is formed on a surface of the first doped polysilicon layer away from the first tunneling oxide layer, a part of the sidewall of the insulating isolation layer and a surface away from the silicon substrate, and a surface of the second doped polysilicon layer away from the second tunneling oxide layer.
[0010] In one embodiment, forming a first tunneling oxide layer and a first doped polysilicon layer stacked in sequence on a portion of the back side of the silicon substrate comprises:
[0011] Forming the first tunneling oxide layer, the first doped polysilicon layer and the first glass layer stacked in sequence on the entire back surface of the silicon substrate;
[0012] The first tunneling oxide layer, the first doped polysilicon layer, and the first glass layer in a first preset region are removed.
[0013] In one embodiment, forming the first tunneling oxide layer, the first doped polysilicon layer and the first glass layer stacked and arranged in sequence on the entire back surface of the silicon substrate comprises:
[0014] Depositing the first tunneling oxide layer and the first intrinsic polysilicon layer in sequence on the entire back surface of the silicon substrate;
[0015] Boron diffusion is performed on the first intrinsic polysilicon layer to form the first doped polysilicon layer and the first glass layer located on the surface of the first doped polysilicon layer.
[0016] In one embodiment, removing the first tunneling oxide layer, the first doped polysilicon layer, and the first glass layer in the first preset region includes:
[0017] Removing the first glass layer in the first preset area by laser etching technology;
[0018] The first doped polysilicon layer and the first tunneling oxide layer in the first preset region are removed by wet etching technology.
[0019] In one embodiment, forming a second tunneling oxide layer and a second doped polysilicon layer stacked in sequence comprises:
[0020] forming the second tunneling oxide layer and the second doped polysilicon layer stacked in sequence; the second tunneling oxide layer covers the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate, and the surface of the first glass layer away from the first doped polysilicon layer;
[0021] forming a second glass layer on a surface of the second doped polysilicon layer away from the second tunneling oxide layer, a portion of the sidewall of the insulating isolation layer, a sidewall of the second tunneling oxide layer on a preset side, and a sidewall of the second doped polysilicon layer on the preset side; the second glass layer and the first glass layer have different doping types;
[0022] The first glass layer, the second glass layer, the second tunneling oxide layer in the second preset area, and the second doped polysilicon layer in the second preset area are removed.
[0023] In one embodiment, forming the second tunneling oxide layer and the second doped polysilicon layer stacked in sequence comprises:
[0024] Depositing the second tunneling oxide layer and the second intrinsic polysilicon layer in sequence on the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate, and the surface of the first glass layer away from the first doped polysilicon layer;
[0025] Phosphor diffusion is performed on the second intrinsic polysilicon layer to form the second doped polysilicon layer.
[0026] In one embodiment, removing the first glass layer, the second glass layer, the second tunneling oxide layer in the second preset area, and the second doped polysilicon layer in the second preset area includes:
[0027] removing the second glass layer in the second preset area by laser etching technology;
[0028] removing the second doped polysilicon layer and the second tunneling oxide layer in the second preset area by wet etching technology;
[0029] The first glass layer and the remaining second glass layer are removed by wet etching technology.
[0030] In a second aspect, the present application discloses a solar cell, the solar cell comprising:
[0031] Silicon substrate;
[0032] A first tunneling oxide layer, wherein the first tunneling oxide layer is disposed on a portion of the back side of the silicon substrate;
[0033] a first doped polysilicon layer, which is stacked between the first doped polysilicon layer and the first tunneling oxide layer and is disposed on a surface of the first tunneling oxide layer that is away from the silicon substrate;
[0034] an insulating isolation layer, the insulating isolation layer being close to side walls of the first tunneling oxide layer and the first doped polysilicon layer;
[0035] a second tunneling oxide layer, wherein the second tunneling oxide layer covers the exposed back side of the silicon substrate;
[0036] a second doped polysilicon layer, which is stacked between the second doped polysilicon layer and the second tunneling oxide layer and is disposed on a surface of the second tunneling oxide layer facing away from the silicon substrate;
[0037] A passivation anti-reflection layer, wherein the passivation anti-reflection layer covers a surface of the first doped polysilicon layer facing away from the first tunneling oxide layer, a portion of the sidewall of the insulating isolation layer and a surface of the insulating isolation layer facing away from the silicon substrate, and a surface of the second doped polysilicon layer facing away from the second tunneling oxide layer.
[0038] In one embodiment, the thickness of the insulating isolation layer is greater than the sum of the thicknesses of the first tunneling oxide layer and the first doped polysilicon layer, and the thickness of the insulating isolation layer is greater than the sum of the thicknesses of the second tunneling oxide layer and the second doped polysilicon layer.
[0039] In one embodiment, the width of the insulating isolation layer is 30um to 60um.
[0040] The preparation method and solar cell of the solar cell are as follows: a first tunneling oxide layer is arranged on a part of the back side of the silicon substrate, so that the back side of another part of the silicon substrate is exposed, and a first doped polysilicon layer is stacked on the surface of the first tunneling oxide layer on the side away from the silicon substrate, an insulating isolation layer close to the first tunneling oxide layer and the sidewalls of the first doped polysilicon layer is arranged on the exposed part of the back side of the silicon substrate, a second tunneling oxide layer is formed on the remaining part exposed on the back side of the silicon substrate, and a second doped polysilicon layer of a different doping type from the first doped polysilicon layer is stacked on the entire surface of the second tunneling oxide layer on the side away from the silicon substrate, and a passivation anti-reflection layer is formed on the surface of the first doped polysilicon layer away from the first tunneling oxide layer, on the part of the sidewalls of the insulating isolation layer and the surface away from the silicon substrate, and on the surface of the second doped polysilicon layer away from the second tunneling oxide layer. The first doped polysilicon layer and the second doped polysilicon layer are isolated by an insulating isolation layer, and the surface of the first doped polysilicon layer away from the first tunneling oxide layer, part of the side wall of the insulating isolation layer and the surface away from the silicon substrate, and the surface of the second doped polysilicon layer away from the second tunneling oxide layer are covered by the formed passivation anti-reflection layer, so that the first doped polysilicon layer and the second doped polysilicon layer are respectively sealed in different positions, which can improve the tightness of the isolation between the N region and the P region of the solar cell, thereby reducing the risk of leakage. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0042] Figure 1 is a schematic diagram of a process for preparing a solar cell in one embodiment;
[0043] Figure 2 is a schematic flow chart of step 101 in one embodiment;
[0044] Figure 3 is a schematic flow chart of step 201 in one embodiment;
[0045] Figure 4 is a schematic flow chart of step 202 in one embodiment;
[0046] Figure 5 is a schematic flow chart of step 103 in one embodiment;
[0047] Figure 6 is a schematic flow chart of step 501 in one embodiment;
[0048] Figure 7 is a schematic flow chart of step 503 in one embodiment;
[0049] Figure 8 is a schematic structural diagram of a solar cell in one embodiment;
[0050] Fig. 9 is a schematic structural diagram of a solar cell in another embodiment;
[0051] Fig.10 is a schematic structural diagram of a solar cell in another embodiment;
[0052] Fig.11 FIG. 4 is a schematic diagram of the structure of a solar cell in another embodiment.
[0053] Description of reference numerals:
[0054] A first tunneling oxide layer 101, a first doped polysilicon layer 102, and a first glass layer 103;
[0055] Insulating isolation layer 201;
[0056] A second tunneling oxide layer 301, a second doped polysilicon layer 302, and a second glass layer 303;
[0057] Passivation anti-reflection layer 401 . DETAILED DESCRIPTION
[0058] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0060] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first glass layer may be referred to as a second glass layer, and similarly, a second glass layer may be referred to as a first glass layer without departing from the scope of this application. Both the first glass layer and the second glass layer are glass layers, but they are not the same glass layer.
[0061] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.
[0062] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.
[0063] The efficiency of traditional PERC, TOPCon and other solar cells is gradually approaching the theoretical efficiency limit. In order to pursue higher efficiency cells, researchers are gradually focusing on interdigitated back-contact cells. Back-contact solar cells usually require more complex processes to achieve n / p region isolation, but the effect of n / p region isolation is not good. In related technologies, the n / p region isolation is achieved by combining laser film opening and wet process to remove part of the phosphorus-doped polysilicon layer in the N region, but the solar cells made by this method still have the problem that the n / p regions cannot be completely isolated, resulting in the risk of leakage.
[0064] In an exemplary embodiment, Figure 1 As shown, a method for preparing a solar cell is provided, and the method is applied to a solar cell manufacturing device as an example for description, and includes the following steps 101 to 104. Among them:
[0065] Step 101: forming a first tunneling oxide layer and a first doped polysilicon layer stacked in sequence on a portion of the back side of a silicon substrate.
[0066] Among them, Fig.11 As shown, a first tunneling oxide layer 101 is disposed on a portion of the back side of the silicon substrate, and a first doped polysilicon layer 102 is stacked.
[0067] Optionally, on the back side of the silicon substrate, a tunneling oxide layer and a doped polysilicon layer are deposited by a preset deposition technology, and redundant tunneling oxide layer and doped polysilicon layer are removed by a preset etching technology, thereby forming a first tunneling oxide layer and a first doped polysilicon layer stacked. The first doped polysilicon layer includes one of a boron-doped polysilicon layer or a phosphorus-doped polysilicon layer.
[0068] In addition, the tunnel oxide layer and the doped polysilicon layer can be independently deposited and generated by different deposition techniques, for example: chemical vapor deposition technology can deposit the tunnel oxide layer and the doped polysilicon layer, atomic layer deposition technology can deposit the tunnel oxide layer, and physical vapor deposition technology can deposit the doped polysilicon layer. The deposition technology is not specifically limited in this application. The excess parts of the tunnel oxide layer and the doped polysilicon layer can be independently removed by different etching techniques, for example: wet chemical etching technology can remove the tunnel oxide layer and the doped polysilicon layer, plasma etching technology can remove the tunnel oxide layer, and laser etching technology can remove the tunnel oxide layer and the doped polysilicon layer. The etching technology is not specifically limited in this application.
[0069] Step 102: Disposing an insulating isolation layer on the exposed portion of the silicon substrate; the insulating isolation layer is close to the side walls of the first tunneling oxide layer and the first doped polysilicon layer.
[0070] Among them, Fig.11 As shown, the insulating isolation layer 201 is disposed near the sidewalls of the first tunneling oxide layer 101 and the first doped polysilicon layer 102 .
[0071] The insulating isolation layer is generated by printing through the screen printing technology. The screen printing technology uses the mesh holes of the graphic part on the screen to allow the slurry to pass through, while the mesh holes of the non-graphic part are not transparent to the slurry. The scraper moves while applying pressure to squeeze the slurry onto the surface of the silicon substrate to form an insulating isolation layer. In addition, the slurry used is an insulating slurry, and the slurry is not specifically limited in this application.
[0072] It should be noted that when the first tunneling oxide layer and the first doped polysilicon layer are formed, a glass layer is also generated. Among them, the glass layer is two impurity layers formed in the manufacturing process of solar cells, including a borosilicate glass layer (BSG layer) or a phosphosilicate glass layer (PSG layer). The borosilicate glass layer is an impurity layer formed during the diffusion process when a PN junction is made on an N-type silicon wafer. The phosphosilicate glass layer is formed when a PN junction is made on a P-type silicon wafer, and the P2O5 produced by the decomposition of POCl3 is deposited on the surface of the silicon wafer. It is a mixture of phosphorus atoms, silicon dioxide, and P2O5.
[0073] Optionally, in the exposed portion of the silicon substrate, starting from the bottom of the exposed portion of the silicon substrate, a screen printing technique is used to print along the sidewalls of the first tunneling oxide layer, the first doped polysilicon layer and the glass layer to generate an insulating isolation layer, which can achieve physical isolation between the n-region and the p-region of the solar cell and avoid leakage. The thickness of the insulating isolation layer is consistent with the sum of the thicknesses of the first tunneling oxide layer, the first doped polysilicon layer and the glass layer.
[0074] Step 103, forming a second tunneling oxide layer and a second doped polysilicon layer stacked in sequence; the second tunneling oxide layer covers the exposed back side of the silicon substrate; wherein the second doped polysilicon layer and the first doped polysilicon layer have different doping types.
[0075] Among them, Fig.11 As shown, the second tunneling oxide layer 301 is disposed on the remaining area of the back side of the silicon substrate, and a second doped polysilicon layer 302 is stacked thereon.
[0076] Optionally, a tunneling oxide layer and a doped polysilicon layer are sequentially deposited on the back side of the exposed portion of the silicon substrate by a preset deposition technology, thereby forming a second tunneling oxide layer and a second doped polysilicon layer that are stacked.
[0077] In addition, the second doped polysilicon layer includes one of a boron-doped polysilicon layer and a phosphorus-doped polysilicon layer. When the first doped polysilicon layer includes a boron-doped polysilicon layer, the second doped polysilicon layer includes a phosphorus-doped polysilicon layer. When the first doped polysilicon layer includes a phosphorus-doped polysilicon layer, the second doped polysilicon layer includes a boron-doped polysilicon layer.
[0078] Step 104 , forming a passivation anti-reflection layer on the surface of the first doped polysilicon layer away from the first tunnel oxide layer, part of the sidewall and the surface of the insulating isolation layer away from the silicon substrate, and the surface of the second doped polysilicon layer away from the second tunnel oxide layer.
[0079] Among them, Fig.11 As shown, the passivation anti-reflection layer 401 covers the surface of the first doped polysilicon layer 102 , part of the sidewall and the corresponding bottom surface of the insulating isolation layer 201 , and the surface of the second doped polysilicon layer 302 .
[0080] A passivation anti-reflection layer is a key technical layer used in semiconductor devices, especially in solar cells, to improve efficiency. The passivation anti-reflection layer combines two main functions: surface passivation and reducing light reflection. In addition, the passivation anti-reflection layer can be deposited by different deposition techniques, such as chemical vapor deposition technology, atomic layer deposition technology or physical vapor deposition technology, etc. The deposition technology is not specifically limited in this application.
[0081] Optionally, a passivation anti-reflection layer is deposited on a surface of the first doped polysilicon layer facing away from the first tunnel oxide layer, a portion of the sidewall of the insulating isolation layer and a surface facing away from the silicon substrate, and a surface of the second doped polysilicon layer facing away from the second tunnel oxide layer by a preset deposition technology.
[0082] In this embodiment, a first tunneling oxide layer is disposed on a portion of the back side of the silicon substrate so that the back side of another portion of the silicon substrate is exposed, and a first doped polysilicon layer is stacked on the surface of the first tunneling oxide layer on a side facing away from the silicon substrate, an insulating isolation layer close to the first tunneling oxide layer and the sidewalls of the first doped polysilicon layer is disposed on the portion exposed on the back side of the silicon substrate, a second tunneling oxide layer is formed on the remaining portion exposed on the back side of the silicon substrate, and a second doped polysilicon layer of a different doping type from the first doped polysilicon layer is stacked on the entire surface of the second tunneling oxide layer on a side facing away from the silicon substrate, and a passivation anti-reflection layer is formed on the surface of the first doped polysilicon layer facing away from the first tunneling oxide layer, on a portion of the sidewalls of the insulating isolation layer and a surface facing away from the silicon substrate, and on the surface of the second doped polysilicon layer facing away from the second tunneling oxide layer. The first doped polysilicon layer and the second doped polysilicon layer are isolated by an insulating isolation layer, and the surface of the first doped polysilicon layer away from the first tunneling oxide layer, part of the side wall of the insulating isolation layer and the surface away from the silicon substrate, and the surface of the second doped polysilicon layer away from the second tunneling oxide layer are covered by the formed passivation anti-reflection layer, so that the first doped polysilicon layer and the second doped polysilicon layer are respectively sealed in different positions, which can improve the tightness of the isolation between the N region and the P region of the solar cell, thereby reducing the risk of leakage.
[0083] In an exemplary embodiment, Figure 2 As shown, step 101 includes steps 201 to 202, wherein:
[0084] Step 201 : forming a first tunneling oxide layer, a first doped polysilicon layer and a first glass layer stacked in sequence on the entire back surface of a silicon substrate.
[0085] Optionally, on the back side of the silicon substrate, a tunneling oxide layer is deposited on the entire surface by a preset deposition technology, on the surface of the tunneling oxide layer facing away from the silicon substrate, a doped polysilicon layer is deposited by a preset deposition technology combined with a preset doping process, and on the surface of the doped polysilicon layer facing away from the tunneling oxide layer, a glass layer is formed by a preset deposition technology and a preset doping process, thereby forming a stacked first tunneling oxide layer, a first doped polysilicon layer and a first glass layer.
[0086] Step 202: removing the first tunneling oxide layer, the first doped polysilicon layer and the first glass layer in the first preset region.
[0087] Optionally, the first glass layer in the first preset area is removed by a preset first etching technology, the first doped polysilicon layer in the first preset area is removed by a preset second etching technology, and the first tunneling oxide layer in the first preset area is removed by a preset second etching technology.
[0088] In this embodiment, a first tunneling oxide layer is deposited on the entire back side of the silicon substrate by a preset deposition technology, and after the deposition of the first tunneling oxide layer is completed, a first doped polysilicon layer and a first glass layer are sequentially deposited in a stacked manner by a preset deposition technology combined with a preset doping process, and the first glass layer in the first preset area is removed by a preset first etching technology. After the first glass layer in the first preset area is removed, the first doped polysilicon layer and the first tunneling oxide layer in the first preset area are removed by a preset second etching technology. The doped polysilicon layer and the glass layer can be deposited in one step by combining the deposition technology with the doping process, which greatly shortens the process and reduces the cost.
[0089] In an exemplary embodiment, Figure 3 As shown, step 201 includes steps 301 to 302, wherein:
[0090] Step 301 : depositing a first tunneling oxide layer and a first intrinsic polysilicon layer in sequence on the entire back surface of a silicon substrate.
[0091] Specifically, on the back side of the silicon substrate, a silicon source gas and a reaction gas such as oxygen are activated by a low pressure chemical vapor deposition (LPCVD) technique to form a corresponding plasma, and the plasma undergoes a chemical reaction on the back side of the silicon substrate to generate silicon oxide and deposit it on the back side of the silicon substrate to form a first tunneling oxide layer. The silicon source gas may include silane gas, dichlorosilane gas, or trichlorosilane gas, and the silicon source gas is not specifically limited in this application.
[0092] After the deposition of the first tunnel oxide layer is completed, on the surface of the first tunnel oxide layer facing away from the silicon substrate, the silicon source gas is decomposed by LPCVD technology to form silicon atoms, and the silicon atoms are deposited on the surface of the first tunnel oxide layer facing away from the silicon substrate to form a first intrinsic polysilicon layer.
[0093] Among them, LPCVD technology is a low-pressure chemical vapor deposition technology that is widely used in the manufacture of microelectronic devices. LPCVD technology mainly uses heating to make gaseous compounds react and deposit on the substrate surface under low pressure conditions to form a stable solid film.
[0094] Step 302 : Boron-diffusion is performed on the first intrinsic polysilicon layer to form a first doped polysilicon layer and a first glass layer located on the surface of the first doped polysilicon layer.
[0095] Taking the first doped polysilicon layer including a boron-doped polysilicon layer as an example, after the first intrinsic polysilicon layer is deposited, the boron source gas is decomposed by LPCVD technology to form boron atoms, and the first intrinsic polysilicon layer is subjected to high-temperature boron diffusion, that is, the boron atoms are diffused into the first intrinsic polysilicon layer by high temperature, thereby generating a boron-doped first doped polysilicon layer. The boron source gas may include boron trichloride, borane or borohydride, etc., and the boron source gas is not specifically limited in this application.
[0096] Taking the first glass layer including a borosilicate glass layer as an example, on the surface of the first doped polysilicon layer facing away from the first tunneling oxide layer, boron atoms react chemically with silicon atoms to generate borosilicate compounds and deposit on the surface of the first doped polysilicon layer facing away from the first tunneling oxide layer, thereby forming a borosilicate glass layer, i.e., the first glass layer.
[0097] In this embodiment, the first tunnel oxide layer is deposited on the entire back side of the silicon substrate by LPCVD technology, and after the deposition of the first tunnel oxide layer is completed, the first doped polysilicon layer and the first glass layer of the stacked arrangement are sequentially deposited by LPCVD technology combined with high-temperature diffusion technology. The boron-doped polysilicon layer and the glass layer can be deposited in one step by LPCVD technology combined with high-temperature diffusion technology, which greatly shortens the process and reduces costs.
[0098] In an exemplary embodiment, Figure 4 As shown, step 202 includes steps 401 to 402, wherein:
[0099] Step 401: remove the first glass layer in the first preset area by laser etching technology.
[0100] Among them, the preset first etching technology may include laser etching technology. Laser etching technology is a technology that uses lasers to perform fine processing on various materials. Through the interaction of laser beams with materials, specific patterns or structures are formed on the surface or inside of the material.
[0101] Specifically, a laser beam is irradiated onto the first glass layer in the first preset area by laser etching technology, and the first glass layer in the first preset area is rapidly evaporated or decomposed by photothermal effect or photochemical effect. For example: the laser beam may include 500nm picosecond green light, and 500nm picosecond green light is irradiated onto the first glass layer in the first preset area to decompose the first glass layer in the first preset area. Among them, the laser beam can be set to other lasers and other wavelengths according to actual needs, and the laser and the wavelength of the laser are not specifically limited in this application. The width of the removed first glass layer can include 540μm to 600μm, and the width of the removed first glass layer can also be set to other width ranges according to actual needs, and the width of the removed first glass layer is not specifically limited in this application.
[0102] Step 402: remove the first doped polysilicon layer and the first tunnel oxide layer in the first preset region by wet etching technology.
[0103] The preset second etching technology may include a wet etching technology, which is a technology that utilizes a chemical reaction between a specific solution and a thin film to remove a corresponding portion of the thin film, thereby achieving an etching purpose.
[0104] Specifically, taking the first doped polysilicon layer including a boron-doped polysilicon layer as an example, after the first glass layer in the first preset area is removed, in the wet etching technology, an alkaline solution such as hydrofluoric acid or potassium hydroxide reacts chemically with the substance in the first doped polysilicon layer to gradually dissolve the first doped polysilicon layer in the first preset area.
[0105] After the first doped polysilicon layer in the first preset region is removed, the first tunnel oxide layer in the first preset region is etched by chemically reacting hydrofluoric acid with silicon oxide in a wet etching technique.
[0106] In this embodiment, the first glass layer in the first preset area is decomposed by laser using a preset laser etching technology. After the first glass layer in the first preset area is removed, the first doped polysilicon layer and the first tunneling oxide layer in the first preset area are gradually dissolved by hydrofluoric acid in a preset wet etching technology, so that the tunneling oxide layer, the doped polysilicon layer and the glass layer in the N region or the P region can be accurately removed.
[0107] In an exemplary embodiment, Figure 5 As shown, step 103 includes steps 501 to 503, wherein:
[0108] Step 501, forming a second tunneling oxide layer and a second doped polysilicon layer stacked in sequence; the second tunneling oxide layer covers the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate, and the surface of the first glass layer away from the first doped polysilicon layer.
[0109] Optionally, a tunnel oxide layer is deposited on the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate, and the surface of the first glass layer away from the first doped polysilicon layer by a preset deposition technology to form a second tunnel oxide layer. A doped polysilicon layer is deposited on the surface of the tunnel oxide layer away from the silicon substrate by a preset deposition technology to form a stacked second doped polysilicon layer.
[0110] Step 502, forming a second glass layer on the surface of the second doped polysilicon layer away from the second tunneling oxide layer, a portion of the sidewall of the insulating isolation layer, the sidewall of the second tunneling oxide layer on a preset side, and the sidewall of the second doped polysilicon layer on a preset side; the second glass layer and the first glass layer have different doping types.
[0111] Optionally, a glass layer is formed on a surface of the second doped polysilicon layer facing away from the second tunneling oxide layer, on a portion of the side wall of the insulating isolation layer, on the side wall of the second tunneling oxide layer on a preset side, and on the side wall of the second doped polysilicon layer on a preset side by a preset deposition technology and a preset doping process, thereby forming a stacked second glass layer.
[0112] Taking the second glass layer including a phosphosilicate glass layer as an example, on the surface of the second doped polysilicon layer away from the second tunnel oxide layer, phosphorus atoms and silicon atoms chemically react to generate phosphosilicate compounds and deposit on the surface of the second doped polysilicon layer away from the second tunnel oxide layer, thereby forming a phosphosilicate glass layer, i.e., the second glass layer. The phosphorus atoms and silicon atoms are obtained when the second tunnel oxide layer and the second doped polysilicon layer are generated.
[0113] In addition, the second glass layer includes one of a borosilicate glass layer and a phosphosilicate glass layer. When the first glass layer includes a borosilicate glass layer, the second glass layer includes a phosphosilicate glass layer. When the first glass layer includes a phosphosilicate glass layer, the second glass layer includes a borosilicate glass layer.
[0114] Step 503 , removing the first glass layer, the second glass layer, the second tunneling oxide layer in the second preset region, and the second doped polysilicon layer in the second preset region.
[0115] Optionally, the second glass layer in the second preset area is removed by a preset first etching technology, the second doped polysilicon layer in the second preset area is removed by a preset second etching technology, the second tunneling oxide layer in the second preset area is removed by a preset second etching technology, and the first glass layer and the remaining second glass layer are removed by a preset second etching technology.
[0116] In this embodiment, the second tunneling oxide layer is deposited on the entire surface of the exposed back side of the silicon substrate covered by the second tunneling oxide layer, the surface of the insulating isolation layer facing away from the silicon substrate, and the surface of the first glass layer facing away from the first doped polysilicon layer by LPCVD technology, and after the second tunneling oxide layer is deposited, on the surface of the tunneling oxide layer facing away from the silicon substrate, a stacked second doped polysilicon layer is deposited by LPCVD technology combined with a high-temperature diffusion process, on the surface of the second doped polysilicon layer facing away from the second tunneling oxide layer, on part of the sidewall of the insulating isolation layer, on the sidewall of the second tunneling oxide layer on a preset side, and on the sidewall of the second doped polysilicon layer on a preset side, The second glass layer of the stacked arrangement is deposited by LPCVD technology combined with a high-temperature diffusion process, the second glass layer in the second preset area is removed by a preset first etching technology, after the second glass layer in the second preset area is removed, the second doped polysilicon layer and the second tunnel oxide layer in the second preset area are removed by a preset second etching technology, after the second doped polysilicon layer and the second tunnel oxide layer in the second preset area are removed, the first glass layer and the remaining second glass layer are removed by a preset second etching technology, the phosphorus-doped polysilicon layer and the glass layer can be deposited in one step by LPCVD technology, which greatly shortens the process and reduces costs.
[0117] In an exemplary embodiment, Figure 6 As shown, step 501 includes steps 601 to 602, wherein:
[0118] Step 601 , depositing a second tunneling oxide layer and a second intrinsic polysilicon layer in sequence on the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate, and the surface of the first glass layer away from the first doped polysilicon layer.
[0119] Specifically, on the exposed back side of the silicon substrate, the surface of the insulating isolation layer facing away from the silicon substrate, and the surface of the first glass layer facing away from the first doped polysilicon layer, the silicon source gas and reaction gases such as oxygen are activated by LPCVD technology to form corresponding plasmas. The plasma undergoes a chemical reaction on the corresponding surfaces to generate silicon oxide and deposit it on the corresponding surfaces to form a second tunneling oxide layer.
[0120] After the deposition of the second tunnel oxide layer is completed, on the surface of the second tunnel oxide layer facing away from the silicon substrate, the silicon source gas is decomposed by LPCVD technology to form silicon atoms, and the silicon atoms are deposited on the surface of the second tunnel oxide layer facing away from the silicon substrate to form a second intrinsic polysilicon layer.
[0121] Step 602 , performing phosphorus diffusion on the second intrinsic polysilicon layer to form a second doped polysilicon layer.
[0122] Specifically, taking the second doped polysilicon layer including a phosphorus-doped polysilicon layer as an example, after the second intrinsic polysilicon layer is deposited, the phosphorus source gas is decomposed by the LPCVD technology to form phosphorus atoms, and the second intrinsic polysilicon layer is subjected to high-temperature phosphorus diffusion, that is, the phosphorus atoms are diffused into the second intrinsic polysilicon layer by high temperature, thereby generating a phosphorus-doped second doped polysilicon layer. The phosphorus source gas may include phosphine, phosphorus oxychloride or phosphine, etc., and the phosphorus source gas is not specifically limited in this application.
[0123] In this embodiment, a second tunneling oxide layer is deposited on the entire surface of the exposed back side of the silicon substrate, the surface of the insulating isolation layer facing away from the silicon substrate, and the surface of the first glass layer facing away from the first doped polysilicon layer by LPCVD technology. After the deposition of the second tunneling oxide layer is completed, a stacked second doped polysilicon layer is deposited by LPCVD technology combined with high-temperature diffusion technology. The phosphorus-doped polysilicon layer can be quickly deposited by LPCVD technology combined with high-temperature diffusion technology, which greatly shortens the process and reduces costs.
[0124] In an exemplary embodiment, Figure 7 As shown, step 503 includes steps 701 to 703, wherein:
[0125] Step 701: remove the second glass layer in the second preset area by laser etching technology.
[0126] Optionally, a laser beam is irradiated onto the second glass layer in the second preset area by laser etching technology, so that the second glass layer in the second preset area is rapidly evaporated or decomposed by photothermal effect or photochemical effect.
[0127] Step 702: remove the second doped polysilicon layer and the second tunnel oxide layer in the second preset region by wet etching technology.
[0128] Optionally, taking the example that the second doped polysilicon layer includes a phosphorus-doped polysilicon layer, after the second glass layer in the second preset area is removed, in the wet etching technology, a mixed solution of hydrofluoric acid and nitric acid chemically reacts with the substance in the second doped polysilicon layer to gradually dissolve the second doped polysilicon layer in the second preset area.
[0129] After the second doped polysilicon layer in the second preset region is removed, the second tunnel oxide layer in the second preset region is etched by chemically reacting hydrofluoric acid with silicon oxide in a wet etching technique.
[0130] Step 703: remove the first glass layer and the remaining second glass layer by wet etching technology.
[0131] Optionally, taking the case where the first glass layer includes a borosilicate glass layer and the second glass layer includes a phosphosilicate glass layer as an example, a predetermined dissolving liquid reacts chemically with a substance in the first glass layer and a substance in the remaining second glass layer to gradually dissolve the first glass layer and the remaining second glass layer. The dissolving liquid may include hydrofluoric acid (HF), nitric acid (HNO3) or other mixed acid solutions, and the dissolving liquid is not specifically limited in the present application.
[0132] In this embodiment, the second glass layer in the second preset area is decomposed by laser using a preset laser etching technology. After the second glass layer in the second preset area is removed, the second doped polysilicon layer in the second preset area is gradually dissolved by a mixed solution of hydrofluoric acid and nitric acid in a preset wet etching technology, and the second tunneling oxide layer in the second preset area is gradually dissolved by a hydrofluoric acid solution. In the preset wet etching technology, the first glass layer and the remaining second glass layer are gradually dissolved by a preset dissolving solution, so that the excess layers in the N region or the P region can be accurately removed, thereby reducing the risk of contact between different doped layers.
[0133] In an exemplary embodiment, Figure 8 As shown, on the back side of the silicon substrate, a tunneling oxide layer is deposited on the entire surface by LPCVD technology, on the surface of the tunneling oxide layer away from the silicon substrate, a doped polysilicon layer is deposited by LPCVD technology combined with a high-temperature diffusion process, and on the surface of the doped polysilicon layer away from the tunneling oxide layer, a glass layer is deposited by LPCVD technology combined with a high-temperature diffusion process, thereby forming a first tunneling oxide layer 101, a first doped polysilicon layer 102 and a first glass layer 103 that are stacked.
[0134] In an exemplary embodiment, Fig. 9As shown, taking the first doped polysilicon layer 102 including a boron-doped polysilicon layer as an example, the first glass layer 103 in the first preset area is decomposed by laser etching technology. After the first glass layer 103 in the first preset area is removed, in the wet etching technology, the first doped polysilicon layer 102 and the first tunneling oxide layer 101 in the first preset area are dissolved by an alkaline solution such as hydrofluoric acid or potassium hydroxide. In the exposed portion of the silicon substrate, that is, in the first preset area, starting from the bottom of the exposed portion of the silicon substrate, the sidewalls close to the first tunneling oxide layer 101, the first doped polysilicon layer 102 and the first glass layer 103 are printed by screen printing technology to form an insulating isolation layer 201. Among them, the first preset area includes Fig. 9 For the portion where no layer is formed and the portion where the insulating isolation layer 201 is set, the width of the first preset area may include 540um to 600um. The width of the first preset area can also be set according to actual needs. The width of the first preset area is not specifically limited in the present application.
[0135] In an exemplary embodiment, Fig.10 As shown, a whole-surface tunneling oxide layer is deposited on the exposed back side of the silicon substrate, on the surface of the insulating isolation layer 201 facing away from the silicon substrate, and on the surface of the first glass layer 103 facing away from the first doped polysilicon layer 102 by the LPCVD technology; a whole-surface doped polysilicon layer is deposited on the surface of the tunneling oxide layer facing away from the silicon substrate and on the surface facing away from the first glass layer 103 by the LPCVD technology; and a whole-surface glass layer is deposited on the surface of the doped polysilicon layer facing away from the tunneling oxide layer by the LPCVD technology, thereby forming a second tunneling oxide layer 301, a second doped polysilicon layer 302, and a second glass layer 303 which are stacked.
[0136] In an exemplary embodiment, Fig.11 As shown, taking the second doped polysilicon layer 302 including a phosphorus-doped polysilicon layer as an example, the second glass layer 303 in the second preset region is decomposed by a preset laser etching technology. After the second glass layer 303 in the second preset region is removed, the second doped polysilicon layer 302 in the second preset region is gradually dissolved by a mixed solution of hydrofluoric acid and nitric acid in a preset wet etching technology, and the second tunnel oxide layer 301 in the second preset region is gradually dissolved by a hydrofluoric acid solution. In the preset wet etching technology, the first glass layer 103 in the P region and the remaining second glass layer 303 in the N region are gradually dissolved by a preset dissolving solution. On the surface of the first doped polysilicon layer 102 away from the first tunnel oxide layer 101, the partial sidewall of the insulating isolation layer 201 and the surface away from the silicon substrate, and the surface of the second doped polysilicon layer 302 away from the second tunnel oxide layer 301, a passivation anti-reflection layer 401 is deposited by a preset deposition technology. Wherein, the width of the second preset region includes Fig.10 The sum of the width of the middle insulating isolation layer 201 and the width of the first glass layer 103, the thickness of the second preset area includes Fig.10 The thickness of the second tunnel oxide layer 301, the thickness of the second doped polysilicon layer 302 and the thickness of the second glass layer 303 are summed.
[0137] In addition, in an exemplary embodiment, Fig.11 As shown, a solar cell is also provided, and the solar cell includes: a silicon substrate. A first tunneling oxide layer 101, the first tunneling oxide layer 101 is arranged on a part of the back side of the silicon substrate. A first doped polysilicon layer 102, the first doped polysilicon layer 102 is stacked with the first tunneling oxide layer 101, and is arranged on the surface of the first tunneling oxide layer 101 away from the silicon substrate. An insulating isolation layer 201, the insulating isolation layer 201 is close to the sidewalls of the first tunneling oxide layer 101 and the first doped polysilicon layer 102. A second tunneling oxide layer 301, the second tunneling oxide layer 301 covers the exposed back side of the silicon substrate. A second doped polysilicon layer 302, the second doped polysilicon layer 302 is stacked with the second tunneling oxide layer 301, and is arranged on the surface of the second tunneling oxide layer 301 away from the silicon substrate. The passivation anti-reflection layer 401 covers the surface of the first doped polysilicon layer 102 facing away from the first tunneling oxide layer 101, part of the sidewall of the insulating isolation layer 201 and the surface of the insulating isolation layer 201 facing away from the silicon substrate, and the surface of the second doped polysilicon layer 302 facing away from the second tunneling oxide layer 301.
[0138] The thickness of the passivation anti-reflection layer 401 may range from 40 nm to 80 nm. The thickness of the passivation anti-reflection layer 401 may also be set according to actual needs. The thickness of the passivation anti-reflection layer 401 is not specifically limited in the present application.
[0139] In this embodiment, the N region and the P region of the solar cell are separated by the insulating isolation layer 201, and the doped polysilicon layers of the N region and the P region are respectively sealed in different areas by the passivation anti-reflection layer 401, thereby improving the tightness of the isolation between the N region and the P region of the solar cell, thereby reducing the risk of leakage.
[0140] In an exemplary embodiment, Fig. 9 As shown, the thickness of the insulating isolation layer 201 is greater than the sum of the thicknesses of the first tunneling oxide layer 101 and the first doped polysilicon layer 102 , and the thickness of the insulating isolation layer 201 is greater than the sum of the thicknesses of the second tunneling oxide layer and the second doped polysilicon layer.
[0141] The thickness of the insulating isolation layer 201 includes the sum of the thicknesses of the first tunneling oxide layer 101 , the first doped polysilicon layer 102 and the first glass layer 103 , or the thickness of the insulating isolation layer 201 includes the sum of the thicknesses of the second tunneling oxide layer 301 , the second doped polysilicon layer 302 and the second glass layer 303 .
[0142] In an exemplary embodiment, the width of the insulating isolation layer 201 is 30 um to 60 um.
[0143] The width of the insulating isolation layer 201 may also be set according to actual needs, and the width of the insulating isolation layer 201 is not specifically limited in the present application.
[0144] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.
[0145] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0146] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. A method for preparing a solar cell, characterized in that: The method for preparing the solar cell comprises: Forming a first tunneling oxide layer and a first doped polysilicon layer stacked in sequence on a portion of the back side of the silicon substrate; An insulating isolation layer is provided on the exposed portion of the silicon substrate; the insulating isolation layer is close to the sidewalls of the first tunneling oxide layer and the first doped polysilicon layer; Forming a second tunneling oxide layer and a second doped polysilicon layer stacked in sequence; the second tunneling oxide layer covers the exposed back side of the silicon substrate; wherein the second doped polysilicon layer and the first doped polysilicon layer have different doping types; A passivation anti-reflection layer is formed on a surface of the first doped polysilicon layer away from the first tunneling oxide layer, a part of the sidewall of the insulating isolation layer and a surface away from the silicon substrate, and a surface of the second doped polysilicon layer away from the second tunneling oxide layer.
2. The method for preparing a solar cell according to claim 1, characterized in that: The method of forming a first tunneling oxide layer and a first doped polysilicon layer stacked and arranged in sequence on a portion of the back side of the silicon substrate comprises: Forming the first tunneling oxide layer, the first doped polysilicon layer and the first glass layer stacked in sequence on the entire back surface of the silicon substrate; The first tunneling oxide layer, the first doped polysilicon layer, and the first glass layer in a first preset region are removed.
3. The method for preparing a solar cell according to claim 2, characterized in that: The first tunneling oxide layer, the first doped polysilicon layer and the first glass layer are stacked and arranged in sequence on the entire back surface of the silicon substrate, comprising: Depositing the first tunneling oxide layer and the first intrinsic polysilicon layer in sequence on the entire back surface of the silicon substrate; Boron diffusion is performed on the first intrinsic polysilicon layer to form the first doped polysilicon layer and the first glass layer located on the surface of the first doped polysilicon layer.
4. The method for preparing a solar cell according to claim 2, characterized in that: The removing the first tunneling oxide layer, the first doped polysilicon layer, and the first glass layer in the first preset area comprises: Removing the first glass layer in the first preset area by laser etching technology; The first doped polysilicon layer and the first tunneling oxide layer in the first preset region are removed by wet etching technology.
5. The method for preparing a solar cell according to claim 2, characterized in that: The forming of a second tunneling oxide layer and a second doped polysilicon layer stacked in sequence comprises: forming the second tunneling oxide layer and the second doped polysilicon layer stacked in sequence; the second tunneling oxide layer covers the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate, and the surface of the first glass layer away from the first doped polysilicon layer; forming a second glass layer on a surface of the second doped polysilicon layer away from the second tunneling oxide layer, a portion of the sidewall of the insulating isolation layer, a sidewall of the second tunneling oxide layer on a preset side, and a sidewall of the second doped polysilicon layer on the preset side; the second glass layer and the first glass layer have different doping types; The first glass layer, the second glass layer, the second tunneling oxide layer in the second preset area, and the second doped polysilicon layer in the second preset area are removed.
6. The method for preparing a solar cell according to claim 5, characterized in that: The forming of the second tunneling oxide layer and the second doped polysilicon layer stacked in sequence comprises: Depositing the second tunneling oxide layer and the second intrinsic polysilicon layer in sequence on the exposed back side of the silicon substrate, the surface of the insulating isolation layer away from the silicon substrate, and the surface of the first glass layer away from the first doped polysilicon layer; Phosphor diffusion is performed on the second intrinsic polysilicon layer to form the second doped polysilicon layer.
7. The method for preparing a solar cell according to claim 5, characterized in that: The removing of the first glass layer, the second glass layer, the second tunneling oxide layer in the second preset area, and the second doped polysilicon layer in the second preset area comprises: removing the second glass layer in the second preset area by laser etching technology; removing the second doped polysilicon layer and the second tunneling oxide layer in the second preset area by wet etching technology; The first glass layer and the remaining second glass layer are removed by wet etching technology.
8. A solar cell, characterized in that: The solar cell comprises: Silicon substrate; A first tunneling oxide layer, wherein the first tunneling oxide layer is disposed on a portion of the back side of the silicon substrate; a first doped polysilicon layer, which is stacked between the first doped polysilicon layer and the first tunneling oxide layer and is disposed on a surface of the first tunneling oxide layer that is away from the silicon substrate; an insulating isolation layer, the insulating isolation layer being close to side walls of the first tunneling oxide layer and the first doped polysilicon layer; a second tunneling oxide layer, wherein the second tunneling oxide layer covers the exposed back side of the silicon substrate; a second doped polysilicon layer, which is stacked between the second doped polysilicon layer and the second tunneling oxide layer and is disposed on a surface of the second tunneling oxide layer facing away from the silicon substrate; A passivation anti-reflection layer, wherein the passivation anti-reflection layer covers a surface of the first doped polysilicon layer facing away from the first tunneling oxide layer, a portion of the sidewall of the insulating isolation layer and a surface of the insulating isolation layer facing away from the silicon substrate, and a surface of the second doped polysilicon layer facing away from the second tunneling oxide layer.
9. The solar cell according to claim 8, characterized in that The thickness of the insulating isolation layer is greater than the sum of the thicknesses of the first tunneling oxide layer and the first doped polysilicon layer, and the thickness of the insulating isolation layer is greater than the sum of the thicknesses of the second tunneling oxide layer and the second doped polysilicon layer.
10. The solar cell according to claim 8, characterized in that The width of the insulating isolation layer is in the range of 30um to 60um.