ADS-B transceiver integrated chip and ADS-B transceiver

Abstract

The present application relates to an ADS‑B transceiver integrated chip and an ADS‑B transceiver. The chip includes a radio frequency receiving link module, a radio frequency transmitting link module, a clock management module, a digital baseband and a controller; the radio frequency receiving link module includes a self-calibration bandpass filter; the self-calibration bandpass filter uses the bandwidth control signal output by the on-chip filter self-calibration circuit to calibrate the filter bandwidth, the radio frequency receiving link module performs low-noise amplification, mixer down-conversion, filtering in the filter after the bandwidth calibration, and analog-to-digital conversion on the input radio frequency signal in sequence to obtain a digital signal, and sends the digital signal to the digital baseband, and the radio frequency transmitting link module decodes the PPM coded signal output by the digital baseband to control SCPA to obtain an ADS‑B radio frequency signal. The present invention can provide an ADS‑B transceiver integrated chip with a small area, low power consumption, high stability and more reliable performance.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an ADS-B transceiver integrated chip and an ADS-B transceiver. Background Art

[0002] ADS-B (Automatic Dependent Surveillance - Broadcast) is a broadcast-based automatic dependent surveillance. Aircraft use broadcasting to transmit their own position, speed, heading and other information in all directions to achieve functions such as aircraft monitoring, air traffic control, and air-to-air collision avoidance.

[0003] At present, the implementation of ADS-B receivers in China is mainly built through discrete components. There are two typical methods: RF discrete devices + FPGA + MCU and AD9361 + FPGA. The use of discrete components has defects such as large area, high power consumption and low stability, which is not conducive to application scenarios such as drones and space-based payloads that have strict requirements on area, power consumption and reliability. Summary of the invention

[0004] Based on this, it is necessary to provide an ADS-B transceiver integrated chip and an ADS-B transceiver to address the above technical problems.

[0005] An ADS-B transceiver integrated chip, the transceiver integrated chip comprising a radio frequency receiving link module, a radio frequency transmitting link module, a clock management module, a digital baseband and a controller; the radio frequency receiving link module comprises a self-calibration bandpass filter;

[0006] The clock management module is used to control the frequency synthesizer to provide the first local oscillation frequency and the second local oscillation frequency to the radio frequency receiving link module and the radio frequency transmitting link module respectively in a time-sharing manner;

[0007] The self-calibration bandpass filter comprises an on-chip filter self-calibration circuit and a bandpass filter, and is used to calibrate the bandwidth of the bandpass filter according to a bandwidth control signal output by the on-chip filter self-calibration circuit;

[0008] The RF receiving link module is used to perform low-noise amplification, mixer down-conversion, filtering in a filter after calibrating the bandwidth, and analog-to-digital conversion on the input RF signal in sequence to obtain a digital signal, and send the digital signal to the digital baseband;

[0009] The digital baseband is used to perform digital signal demodulation on the digital signal to obtain a demodulated signal, send the demodulated signal to the controller to send the demodulated signal to the external loading platform, and perform PPM encoding on the relevant parameters obtained by the controller from the external loading platform to obtain a PPM encoded signal;

[0010] The radio frequency transmission link module is used to modulate the PPM coded signal output by the digital baseband to obtain an ADS-B radio frequency signal.

[0011] In one embodiment, the on-chip filter self-calibration circuit includes a bias module, a comparator module and a SAR logic circuit module; the bias module includes a reference current bias submodule, a reference resistor and a switch capacitor array; the reference current bias submodule is used to provide a bias current to the reference resistor and the switch capacitor array; the same-direction input terminal and the inverting input terminal of the comparator module are respectively connected to the switch capacitor array and the reference resistor, and are used to compare the voltages on the switch capacitor array and the reference resistor, and output a comparison result; the SAR logic circuit module performs a binary search on the switch capacitor array according to the comparison result to obtain a bandwidth control signal corresponding to the calibrated switch capacitor array; and the self-calibration bandpass filter adjusts the bandwidth according to the bandwidth control signal.

[0012] In one embodiment, the reference current bias submodule includes a first branch, a second branch and a third branch connected in parallel; the first branch includes a first MOS tube, a second MOS tube, a bias resistor and a reference current generating circuit connected in series, the second branch includes a third MOS tube, a fourth MOS tube, a first charging switch and a reset switch connected in series, the first charging switch is connected in series with the switch capacitor array, the reset switch is connected in parallel with the switch capacitor array, the third branch includes a fifth MOS tube, a sixth MOS tube and a second charging switch connected in series, the second charging switch is connected in series with the reference resistor; the gate of the first MOS tube is respectively connected to the gate of the third MOS tube, the gate of the fifth MOS tube and the input end of the bias resistor; the gate of the second MOS tube is respectively connected to the gate of the fourth MOS tube, the gate of the sixth MOS tube and the output end of the bias resistor; the first branch is used to provide bias current for the second branch and the third branch.

[0013] In one of the embodiments, when the reference clock is at a high level, the SAR logic circuit module controls the first charging switch and the second charging switch to be turned on, the currents of the second branch and the third branch act on the reference resistor and the switch capacitor array respectively, and the switch capacitor and the reference resistor provide input signals and reference voltages to the comparator module respectively; the first charging switch and the second charging switch are respectively connected to the SAR logic circuit module.

[0014] In one of the embodiments, when the reference clock is at a low level, the comparator module converts the voltage difference between the two input terminals into a digital signal and sends it to the SAR logic circuit module. The SAR logic circuit module switches the switch capacitor array according to the digital signal and controls the reset switch to be turned on. The reset switch is connected to the SAR logic circuit module.

[0015] In one embodiment, the switch capacitor array and the reference resistor are obtained by respectively replicating the capacitors and resistors in the bandpass filter in equal proportion.

[0016] In one embodiment, the RF receiving link module includes a low noise amplifier, an orthogonal mixer, the self-calibration bandpass filter, a variable gain amplifier and an analog-to-digital converter connected in sequence; the low noise amplifier is used to amplify the RF signal, suppress out-of-band noise and convert it into a differential signal; the orthogonal mixer is used to down-convert the input RF signal to obtain an intermediate frequency signal; the self-calibration bandpass filter is used to perform image suppression processing and out-of-band noise filtering on the intermediate frequency signal within the calibrated bandwidth; the variable gain amplifier is used to amplify the intermediate frequency signal output by the self-calibration bandpass filter; and the analog-to-digital converter is used to perform analog-to-digital conversion processing.

[0017] In one embodiment, the radio frequency transmission link module includes a digital variable gain controller, a decoding control circuit, an SCPA control drive circuit and an SCPA connected in sequence; the SCPA control drive circuit is connected to the clock management module; the digital variable gain controller is used to receive the transmission power configuration parameters transmitted by the controller, decode according to the transmission power configuration parameters, and generate a control bit for controlling the power consumption of the SCPA; the decoding control circuit is used to convert the control bit into a high-order thermometer code and a low-order binary code, and then merge it with the PPM coded signal to obtain the SCPA control signal; the SCPA control drive circuit is used to mix the SCPA control signal with a second local oscillation frequency to obtain the SCPA signal, and drive the SCPA by synchronizing the SCPA control signal and enhancing the driving capability; the SCPA is used to output the SCPA signal as an ADS-B radio frequency signal.

[0018] In one embodiment, the ADS-B transceiver chip also includes a power management module; the power management module includes multiple LDO sub-modules, each LDO sub-module is respectively connected to the RF receiving link module, the RF transmitting link module, the clock management module, the digital baseband and the controller, and is used to power each module in the ADS-B transceiver chip.

[0019] In one embodiment, an ADS-B transceiver including the above-mentioned ADS-B transceiver integrated chip is also provided.

[0020] The above-mentioned ADS-B transceiver integrated chip and ADS-B transceiver provide the first local oscillator frequency and the second local oscillator frequency to the RF receiving link module and the RF transmitting link module through the clock management module, which can reduce the chip area. The self-calibration bandpass filter includes calibrating the filter bandwidth using the bandwidth control signal output by the on-chip filter self-calibration circuit, which can improve the filter bandwidth calibration accuracy and is beneficial to improving the performance of the transceiver. The RF receiving link module is used to perform low-noise amplification, mixer down-conversion, filtering processing and analog-to-digital conversion processing on the input RF signal in sequence to obtain a digital signal, and send the digital signal to the digital baseband. The digital baseband is used to demodulate the digital signal to obtain a demodulated signal, and send the demodulated signal to the controller to send the modulation signal to the external loading platform. The relevant parameters obtained by the controller from the external loading platform are PPM-encoded to obtain a PPM-encoded signal. The RF transmitting link module is used to modulate the PPM-encoded signal output by the digital baseband to obtain an ADS-B RF signal. The embodiments of the present invention can provide an ADS-B transceiver integrated chip with small area, low power consumption, high stability and more reliable performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the structure of an ADS-B transceiver integrated chip in one embodiment;

[0022] Figure 2 is a schematic diagram of the structure of an on-chip filter self-calibration circuit in one embodiment;

[0023] Figure 3 is a schematic structural diagram of a radio frequency transmission link module in one embodiment;

[0024] Figure 4 FIG. 4 is a schematic diagram of the structure of a power management module in an embodiment. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0026] A bandpass filter is often provided at the front end of the RF transmitter. When designing a bandpass filter in a CMOS integrated circuit, process deviations and temperature changes may lead to uncertainty in resistance and capacitance values, thus affecting the filter bandwidth. Therefore, real-time monitoring and adjustment of circuit parameters helps ensure that the performance of the bandpass filter is always within the design specifications under different process conditions and temperature ranges.

[0027] The current bandpass filter calibration method requires an additional circuit to generate a reference voltage, or a reference current with relatively high accuracy. The additional current and voltage will have a large error impact due to the influence of process, power supply voltage and temperature, thereby affecting the accuracy of the calibration. If the filter bandwidth is too small, the useful signals in the receiving and transmitting channel bands will be filtered out. The reduction of useful signals directly deteriorates the signal-to-noise ratio of the channel. If the filter bandwidth is too large, the receiving channel will not be able to suppress out-of-band blocks and interference signals sufficiently, and the receiving channel will be easily blocked. At the same time, the transmitting channel will find it difficult to control the leakage of in-band signals, which may interfere with users of adjacent channels. The bandwidth accuracy of the filter will affect the reliability of the RF transceiver.

[0028] In one embodiment, Figure 1 As shown, an ADS-B transceiver integrated chip is provided, including:

[0029] RF receiving link module, RF transmitting link module, clock management module, digital baseband and controller; the RF receiving link module includes a self-calibrating bandpass filter;

[0030] The clock management module is used to control the frequency synthesizer to provide the first local oscillation frequency and the second local oscillation frequency to the radio frequency receiving link module and the radio frequency transmitting link module respectively in a time-sharing manner;

[0031] The self-calibration bandpass filter comprises an on-chip filter self-calibration circuit and a bandpass filter, and is used to calibrate the bandwidth of the bandpass filter according to a bandwidth control signal output by the on-chip filter self-calibration circuit;

[0032] The RF receiving link module is used to perform low-noise amplification, mixer down-conversion, filtering in a filter after calibrating the bandwidth, and analog-to-digital conversion on the input RF signal in sequence to obtain a digital signal, and send the digital signal to the digital baseband;

[0033] The digital baseband is used to perform digital signal demodulation on the digital signal to obtain a demodulated signal, send the demodulated signal to the controller to send the demodulated signal to the external loading platform, perform PPM encoding on the relevant parameters obtained by the controller from the external loading platform to obtain a PPM encoded signal;

[0034] The RF transmission link module is used to modulate the PPM coded signal output by the digital baseband to obtain the ADS-B RF signal.

[0035] In the above-mentioned ADS-B transceiver integrated chip, the clock management module provides the first local oscillator frequency and the second local oscillator frequency to the RF receiving link module and the RF transmitting link module, which can reduce the chip area, the self-calibration bandpass filter includes calibrating the filter bandwidth using the bandwidth control signal output by the on-chip filter self-calibration circuit, which can improve the filter bandwidth calibration accuracy, which is beneficial to improving the performance of the transceiver, and the RF receiving link module is used to perform low-noise amplification, mixer down-conversion, filtering and analog-to-digital conversion on the input RF signal in sequence, and obtain a digital signal, and send the digital signal to the digital baseband, the digital baseband is used to demodulate the digital signal to obtain a demodulated signal, send the demodulated signal to the controller to send the modulation signal to the external loading platform, and perform PPM encoding on the relevant parameters obtained by the controller from the external loading platform to obtain a PPM encoded signal, and the RF transmitting link module is used to modulate the PPM encoded signal output by the digital baseband to obtain an ADS-B RF signal. The embodiment of the present invention can provide an ADS-B transceiver integrated chip with a small area, low power consumption, high stability and more reliable performance.

[0036] In one embodiment, Figure 2 As shown, a structural schematic diagram of an on-chip filter self-calibration circuit is provided, and the on-chip filter self-calibration circuit includes a bias module, a comparator module and a SAR logic circuit module; the bias module includes a reference current bias submodule, a reference resistor and a switch capacitor array; the reference current bias submodule is used to provide a bias current to the reference resistor and the switch capacitor array; the same-direction input terminal and the reverse-phase input terminal of the comparator module are respectively connected to the switch capacitor array and the reference resistor, and are used to compare the magnitude of the voltage on the switch capacitor array and the reference resistor, and output a comparison result; the SAR logic circuit module performs a binary search on the switch capacitor array according to the comparison result, and obtains a bandwidth control signal corresponding to the calibrated switch capacitor array; the self-calibration bandpass filter adjusts the bandwidth according to the bandwidth control signal.

[0037] In this embodiment, the reference voltage is generated by a reference resistor, which can reduce the influence of the external reference voltage on the process parameters, thereby improving the accuracy of bandwidth calibration.

[0038] In one embodiment, the reference current bias submodule includes a first branch, a second branch and a third branch connected in parallel; the first branch includes a first MOS tube, a second MOS tube, a bias resistor and a reference current generating circuit connected in series, the second branch includes a third MOS tube, a fourth MOS tube, a first charging switch and a reset switch connected in series, the first charging switch is connected in series with the switch capacitor array, the reset switch is connected in parallel with the switch capacitor array, the third branch includes a fifth MOS tube, a sixth MOS tube and a second charging switch connected in series, the second charging switch is connected in series with the reference resistor; the gate of the first MOS tube is respectively connected to the gate of the third MOS tube, the gate of the fifth MOS tube and the input end of the bias resistor; the gate of the second MOS tube is respectively connected to the gate of the fourth MOS tube, the gate of the sixth MOS tube and the output end of the bias resistor; the first branch is used to provide bias current for the second branch and the third branch.

[0039] In this embodiment, if Figure 2 As shown, the first MOS transistor Q1, the second MOS transistor Q2, the bias resistor R2 and the reference current generating circuit constitute the first branch, the third MOS transistor Q3, the fourth MOS transistor Q4, the first charging switch SW1 and the reset switch SW3 constitute the second branch, the fifth MOS transistor Q5, the sixth MOS transistor Q6 and the second charging switch SW2 constitute the third branch, wherein the seventh MOS transistor Q7, the eighth MOS transistor Q8, the ninth MOS transistor Q9, the tenth MOS transistor Q10, the eleventh MOS transistor Q11 and the resistor R0 constitute the reference current generating circuit. The same current can flow through the switch capacitor array and the reference resistor R1, thereby reducing the error caused by the current, and improving the bandwidth calibration accuracy of the filter. At the same time, the entire calibration circuit does not require any external reference voltage.

[0040] In one embodiment, when the reference clock is at a high level, the SAR logic circuit module controls the first charging switch and the second charging switch to be turned on, and the currents of the second branch and the third branch act on the reference resistor and the switch capacitor array respectively, and the switch capacitor and the reference resistor provide input signals and reference voltages to the comparator module respectively; the first charging switch and the second charging switch are respectively connected to the SAR logic circuit module; when the reference clock is at a low level, the comparator module converts the voltage difference between the two input terminals into a digital signal and sends it to the SAR logic circuit module, and the SAR logic circuit module switches the switch capacitor array according to the digital signal, and controls the reset switch to be turned on at the same time; the reset switch is connected to the SAR logic circuit module.

[0041] Specifically, Figure 2As shown, the calibration clock frequency CLK is input (for the convenience of calculation, the clock frequency is 1MHz here). When the calibration frequency is high, the first charging switch SW1 and the second charging switch SW2 will be turned on. Two accurately copied currents act on the reference resistor and the switch capacitor array respectively: one current charges the capacitor array as the input VIN at one end of the comparator, and the other current generates the reference voltage VREF of the comparator on the reference resistor. At the moment when the calibration clock becomes low, the comparator compares the voltages at both ends of the reference resistor and the switch capacitor array, and outputs the comparison result to the SAR logic control circuit. The SAR logic control circuit resets the switch capacitor array after sampling the comparison output result, and selects the capacitor array to be connected to the charge through the binary search method: first, the high-order capacitor is selected to participate in the charging, and the capacitor is connected according to the value after the comparison is completed. The second high-order capacitor is selected, and so on until the lowest-order capacitor. When all capacitors participate in the comparison process, the EOC output signal in the SAR logic circuit will be pulled high to indicate that a conversion is completed, and the signal is output to the switch capacitor array for reset.

[0042] When the calibration clock changes from high level to low level, the voltage across the switched capacitor array is ,in To calibrate the clock high time, specifically , is the charging current, is the total capacitance of the connected charging capacitor array, ,in is the minimum unit capacitance, is 0 or 1, indicating whether the capacitor is connected. At the same time, the voltage across the reference resistor is ,in is the negative input resistor of the comparator, used to generate a reference voltage. When the comparator output starts to turn high, ,get .

[0043] In one embodiment, the switched capacitor array and the reference resistor are obtained by respectively replicating the capacitors and resistors in the bandpass filter in equal proportion. In this embodiment, the bandwidth of the bandpass filter is inversely proportional to the filter time constant. , , since the bandwidth and center frequency of the filter are , Therefore, the resistors and capacitors in the filter and the resistor and capacitor arrays in the calibration circuit are selected from the same type of devices and matched on the layout. In this way, when the product of the resistors and the connected capacitors on the calibration circuit is a fixed value, the corresponding resistors and capacitor arrays in the same proportion inside the filter will also be a fixed design value, that is, only need to The bandwidth of the filter can be calibrated by multiplying the product of

[0044] In one embodiment, Figure 1 As shown, a structural schematic diagram of the transceiver link in an ADS-B transceiver integrated chip is provided, wherein the RF receiving link module and the RF transmitting link module are both connected to the clock management module; the clock management module is used to control the frequency synthesizer to provide the first local oscillator frequency and the second local oscillator frequency respectively in time-sharing; the RF receiving link module and the RF transmitting link module are also respectively connected to the digital baseband and the controller; the digital demodulation baseband is connected to the controller.

[0045] In this embodiment, a fast-locking frequency synthesizer is integrated in the clock management module, which generates the first local oscillator signal (1086MHz) required for receiving signals and the second local oscillator signal (1090MHz) required for transmission respectively by time-division multiplexing. According to the characteristics of the ADS-B transceiver, when the transceiver is in the transmission OUT state, the receiving link will also receive the high-power consumption signal received by the transceiver at the same time, resulting in the inability to receive other low-power ADS-B radio frequency signals. Therefore, the receiving link can be closed at this time, and the clock management module generates an ADS-B local oscillator frequency of 1090MHz. Using the clock management module to provide frequency sources for the RF receiving link module and the RF transmitting link module at the same time can reduce the chip area and power consumption, and also reduce the risk of multiple frequency sources interfering with other circuits.

[0046] On the receiving link: the RF receiving link module performs low-noise amplification, mixer down-conversion, filtering in a filter after calibrating the bandwidth, and analog-to-digital conversion on the input RF signal in sequence to obtain a digital signal, which is sent to the digital baseband and demodulated in the digital baseband to obtain a demodulated signal; the demodulated signal is input to the controller, and the demodulated signal is sent to the external loading platform through the interface conversion of the controller.

[0047] In one embodiment, the RF receiving link module includes a low-noise amplifier, an orthogonal mixer, a self-calibration bandpass filter, a variable gain amplifier and an analog-to-digital converter connected in sequence; the low-noise amplifier is used to amplify the RF signal, suppress out-of-band noise and convert it into a differential signal; the orthogonal mixer is used to down-convert the input RF signal to obtain an intermediate frequency signal; the self-calibration bandpass filter is used to perform image suppression processing and out-of-band noise filtering on the intermediate frequency signal within the calibrated bandwidth; the variable gain amplifier is used to amplify the intermediate frequency signal output by the self-calibration bandpass filter; and the analog-to-digital converter is used to perform analog-to-digital conversion processing.

[0048] Specifically, the low noise amplifier adopts a common source negative feedback structure broadband low noise amplifier with noise cancellation technology, which can achieve lower NF under the same power consumption compared with the traditional low noise amplifier structure. NF is the total noise factor of the receiver. The function of the complex domain bandpass filter is to suppress the image signal and thus improve the signal-to-noise ratio. It is connected to the four phase signals 0°, 90°, 180°, and 360° output by the phase-locked loop. The polarity of the signal after down-conversion must be clear in order to determine the specific connection method of the complex domain bandpass filter. If the local oscillator signal frequency is greater than the RF signal carrier frequency, and the local oscillator signal is a positive polarity input (moved in the positive frequency direction), then the output signal after down-conversion is a positive polarity sequence (the spectrum is at the positive frequency); if the local oscillator signal is a negative polarity input (moved in the negative frequency direction), then the output signal after down-conversion is a negative polarity sequence (the spectrum is at the negative frequency); if the local oscillator signal frequency is less than the RF signal carrier frequency, and the local oscillator signal is a positive polarity input, then the output signal after down-conversion is a negative polarity sequence; if the local oscillator signal is a negative polarity input, then the output signal after down-conversion is a positive polarity sequence.

[0049] In this embodiment, the self-calibration bandpass filter includes an anti-aliasing complex domain filter and an on-chip filter self-calibration circuit. The anti-aliasing complex domain filter is used to perform image suppression and anti-aliasing filtering. Before processing, the anti-aliasing complex domain filter adjusts the bandwidth through the on-chip filter self-calibration circuit, thereby filtering interference signals at a precise bandwidth and retaining useful signals, which can further improve the efficiency of RF signal reception and reduce the possibility of in-band leakage and adjacent channel interference in the transmission channel, which is beneficial to improving the transceiver performance of the ADS-B transceiver integrated chip.

[0050] On the transmission link: the controller collects the position parameters and sensor parameters of the external loading platform, and sends the position parameters and sensor parameters to the digital baseband; the digital baseband performs PPM encoding on the position parameters and sensor parameters to obtain a PPM encoded signal, and sends the PPM encoded signal to the RF transmission link module; the RF transmission link module modulates the PPM encoded signal to obtain an ADS-B RF signal.

[0051] In one embodiment, Figure 3As shown, a structural schematic diagram of a radio frequency transmission link module is provided, and the radio frequency transmission link module includes a digital variable gain controller, a decoding control circuit, an SCPA control driving circuit and an SCPA connected in sequence; the SCPA control driving circuit is connected to the clock management module; the digital variable gain controller is used to receive the transmission power configuration parameters transmitted by the controller, decode according to the transmission power configuration parameters, and generate a control bit for controlling the power consumption of the SCPA; the decoding control circuit is used to convert the control bit into a high-order thermometer code and a low-order binary code, and then merge it with the PPM coding signal to obtain the SCPA control signal; the SCPA control driving circuit is used to mix the SCPA control signal with the second local oscillation frequency to obtain the SCPA signal, and drive the SCPA by synchronizing the SCPA control signal and enhancing the driving capability; the SCPA is used to output the SCPA digital control signal as an ADS-B radio frequency signal.

[0052] Specifically, DVGA decodes the transmission power required by the system configuration, generates the control bit required to control the power consumption of the SCPA amplifier, converts it into a high-order thermometer code and a low-order binary code through the decoding circuit, and combines it with the ADS-B baseband PPM signal generated by the baseband to generate an SCPA control signal, which is mixed with the 1090MHz clock and amplified and transmitted by the SCPA. Its transmission power is shown in the following formula:

[0053] ;

[0054] in, Indicates the total number of capacitors, Indicates the number of capacitors turned on, VDD indicates the pulse amplitude, Indicates the equivalent output impedance value of the selected matching network.

[0055] According to the ADS-B system, the signal transmission interval is about 0.5S, and the data transmission length is 120us. Therefore, during the period of external signal transmission, the clock management module can quickly switch to output 1090MHz frequency. When the transmission is completed, the original output frequency is quickly switched to 1086MHz and provided to the receiving link.

[0056] In this embodiment, the conventional technology adopts the architecture of an analog transmitter, which either requires the integration of two frequency synthesizers for providing two different transmit and receive local oscillator frequencies, or the transmitter and receiver share the local oscillator frequency of 1086 MHz. The transmitter needs to directly divide the 1086 MHz frequency with the reference clock to obtain an intermediate frequency of 4 MHz for up-conversion to obtain a 1090 MHz signal, so that the selection of the peripheral reference clock is limited to 4 times the intermediate frequency. The present invention utilizes the characteristics of the ADS-B system with short transmission signals and long intervals, adopts a clock management module, and realizes the transmission and reception of different local oscillator frequencies through frequency switching, thereby reducing power consumption, area and cost. At the same time, the transmission link adopts a pure digital transmitter architecture, which can further reduce area and power consumption.

[0057] In one embodiment, Figure 4 As shown, a structural schematic diagram of a power management module is provided, and the ADS-B transceiver integrated chip also includes a power management module; the power management module includes multiple LDO sub-modules, each LDO sub-module is respectively connected to the RF receiving link module, the RF transmitting link module, the clock management module, the digital baseband and the controller, and is used to power each module in the ADS-B transceiver integrated chip.

[0058] In this embodiment, the power management module has multiple LDO modules built in to supply power to different modules inside the chip respectively, so that only a single power supply voltage is required outside the chip. The power supplies of each module are isolated through the internal LDO, which reduces mutual interference and thus reduces noise, improves the sensitivity of the entire chip, reduces the board-level peripheral power supply LDO circuit, reduces the cost of the receiver, and improves reliability.

[0059] In one embodiment, an ADS-B transceiver is also provided, including: the ADS-B transceiver integrated chip in the above embodiment. The chip adopts a low intermediate frequency structure, which has the advantages of being simple in structure, not requiring a high-frequency high-Q value image suppression filter, not requiring direct current elimination, and being easy to integrate. The ADS-B transceiver integrated chip can provide the ADS-B transceiver with lower power consumption, smaller area, fewer peripheral devices, and more flexible system-level design.

[0060] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0061] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. An ADS-B transceiver integrated chip, characterized in that: The transceiver integrated chip includes a radio frequency receiving link module, a radio frequency transmitting link module, a clock management module, a digital baseband and a controller; the radio frequency receiving link module includes a self-calibration bandpass filter; The clock management module is used to control the frequency synthesizer to provide the first local oscillation frequency and the second local oscillation frequency to the radio frequency receiving link module and the radio frequency transmitting link module respectively in a time-sharing manner; The self-calibration bandpass filter comprises an on-chip filter self-calibration circuit and a bandpass filter, and is used to calibrate the bandwidth of the bandpass filter according to a bandwidth control signal output by the on-chip filter self-calibration circuit; The RF receiving link module is used to perform low-noise amplification, mixer down-conversion, filtering in a filter after calibrating the bandwidth, and analog-to-digital conversion on the input RF signal in sequence to obtain a digital signal, and send the digital signal to the digital baseband; The digital baseband is used to perform digital signal demodulation on the digital signal to obtain a demodulated signal, send the demodulated signal to the controller to send the demodulated signal to the external loading platform, and perform PPM encoding on the relevant parameters obtained by the controller from the external loading platform to obtain a PPM encoded signal; The radio frequency transmission link module is used to modulate the PPM coded signal output by the digital baseband to obtain an ADS-B radio frequency signal.

2. The ADS-B transceiver integrated chip according to claim 1, characterized in that: The on-chip filter self-calibration circuit includes a bias module, a comparator module and a SAR logic circuit module; the bias module includes a reference current bias submodule, a reference resistor and a switch capacitor array; The reference current bias submodule is used to provide a bias current to the reference resistor and the switch capacitor array; The non-inverting input terminal and the inverting input terminal of the comparator module are respectively connected to the switch capacitor array and the reference resistor, and are used to compare the voltages on the switch capacitor array and the reference resistor, and output a comparison result; The SAR logic circuit module performs a binary search on the switch capacitor array according to the comparison result to obtain a bandwidth control signal corresponding to the calibrated switch capacitor array; The self-calibration bandpass filter performs bandwidth adjustment according to the bandwidth control signal.

3. The ADS-B transceiver integrated chip according to claim 2, characterized in that: The reference current bias submodule comprises a first branch, a second branch and a third branch connected in parallel; The first branch includes a first MOS transistor, a second MOS transistor, a bias resistor and a reference current generating circuit connected in series, the second branch includes a third MOS transistor, a fourth MOS transistor, a first charging switch and a reset switch connected in series, the first charging switch is connected in series with the switch capacitor array, the reset switch is connected in parallel with the switch capacitor array, the third branch includes a fifth MOS transistor, a sixth MOS transistor and a second charging switch connected in series, and the second charging switch is connected in series with the reference resistor; The gate of the first MOS tube is respectively connected to the gate of the third MOS tube, the gate of the fifth MOS tube and the input end of the bias resistor; The gate of the second MOS tube is respectively connected to the gate of the fourth MOS tube, the gate of the sixth MOS tube and the output end of the bias resistor; The first branch is used to provide a bias current for the second branch and the third branch.

4. The ADS-B transceiver integrated chip according to claim 3, characterized in that: When the reference clock is at a high level, the SAR logic circuit module controls the first charging switch and the second charging switch to be turned on, the currents of the second branch and the third branch act on the reference resistor and the switch capacitor array respectively, and the switch capacitor and the reference resistor provide input signals and reference voltages to the comparator module respectively; the first charging switch and the second charging switch are respectively connected to the SAR logic circuit module.

5. The ADS-B transceiver integrated chip according to claim 3, characterized in that: When the reference clock is at a low level, the comparator module converts the voltage difference between the two input terminals into a digital signal and sends it to the SAR logic circuit module. The SAR logic circuit module switches the switch capacitor array according to the digital signal and controls the reset switch to be turned on. The reset switch is connected to the SAR logic circuit module.

6. The ADS-B transceiver integrated chip according to claim 5, characterized in that: The switch capacitor array and the reference resistor are obtained by respectively replicating the capacitors and resistors in the bandpass filter in equal proportion.

7. The ADS-B transceiver integrated chip according to claim 2, characterized in that: The radio frequency receiving link module includes a low noise amplifier, an orthogonal mixer, the self-calibration bandpass filter, a variable gain amplifier and an analog-to-digital converter connected in sequence; The low noise amplifier is used to amplify the radio frequency signal, suppress out-of-band noise and convert it into a differential signal; The orthogonal mixer is used to perform down-conversion processing on the input radio frequency signal to obtain an intermediate frequency signal; The self-calibration bandpass filter is used to perform image suppression processing and out-of-band noise filtering on the intermediate frequency signal under the calibrated bandwidth; The variable gain amplifier is used to amplify the intermediate frequency signal output by the self-calibration bandpass filter; The analog-to-digital converter is used for performing analog-to-digital conversion processing.

8. The ADS-B transceiver integrated chip according to claim 2, characterized in that: The radio frequency transmission link module includes a digital variable gain controller, a decoding control circuit, an SCPA control driving circuit and an SCPA connected in sequence; the SCPA control driving circuit is connected to the clock management module; The digital variable gain controller is used to receive the transmit power configuration parameters transmitted by the controller, decode according to the transmit power configuration parameters, and generate a control bit for controlling the power consumption of the SCPA; The decoding control circuit is used to convert the control bit into a high-order thermometer code and a low-order binary code, and then combine it with the PPM code signal to obtain the SCPA control signal; The SCPA control driving circuit is used to mix the SCPA control signal with the second local oscillation frequency to obtain the SCPA signal, and to drive the SCPA by synchronizing the SCPA control signal and enhancing the driving capability; The SCPA is used to output the SCPA signal as an ADS-B radio frequency signal.

9. The ADS-B transceiver integrated chip according to any one of claims 1 to 8, characterized in that: The ADS-B transceiver chip also includes a power management module; The power management module includes multiple LDO sub-modules, each of which is respectively connected to the RF receiving link module, the RF transmitting link module, the clock management module, the digital baseband and the controller, and is used to power each module in the ADS-B transceiver integrated chip.

10. An ADS-B transceiver, characterized in that: include: The ADS-B transceiver integrated chip according to any one of claims 1 to 9.

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