TDD synchronous circuit, chip and radio frequency coverage unit

Abstract

The invention provides a TDD synchronization circuit, a chip and a radio frequency coverage unit, the TDD synchronization circuit comprises a detection circuit and a comparison circuit, the input end of the detection circuit receives a TDD coupling signal, and the detection circuit carries out detection processing on the TDD coupling signal and outputs a TDD modulation signal without carrier waves. The comparison circuit receives the first reference voltage signal and the TDD modulation signal and performs logic processing on the first reference voltage signal and the TDD modulation signal to enlarge the voltage range of the TDD modulation signal and obtain a TDD driving signal, and the TDD driving signal is more beneficial to driving a next-stage circuit, realizing recovery of a TDD time slot signal and participating in switching control of radio frequency uplink and downlink; and the TDD time slot control is accurately carried out. A complex processor and the like are not arranged in the TDD synchronous circuit, the device type selection range is wide, implementation is easy, the response speed is high, TDD synchronization does not need to be conducted through a modem, cost is saved, interference is avoided, and practicability is high.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a TDD synchronization circuit, a chip and a radio frequency coverage unit. Background Art

[0002] With the development of information technology and the increasing needs of users, mobile communication technology has become a research hotspot with the greatest development potential and the broadest market prospects in the field of contemporary communications. In the field of communications, for example, 4G networks or 5G networks can use time division duplexing (TDD) or frequency division duplexing (FDD) to transmit uplink and downlink data. Among them, TDD enables the transmission and reception of signals in different time slots of the same frequency channel. In a variety of communication scenarios, the base station and the radio frequency coverage unit (RU) are physically far apart. In this disclosure, the base station can be referred to as a proximal device and the radio frequency coverage unit can be referred to as a remote device. When the communication system is working, it is necessary to synchronize the uplink and downlink working time switching of the radio frequency coverage unit with the base station.

[0003] In order to enable the radio frequency coverage unit to achieve uplink and downlink working time switching and base station synchronization, it is necessary to obtain information such as the uplink and downlink time slot ratio of TDD. The current main method is to use a modem (Modem) of a TDD baseband synchronization module in the radio frequency coverage unit to perform cell search and wireless signaling processing of the TDD wireless network, obtain accurate TDD uplink and downlink time slot timing, uplink and downlink time ratio and other information, and output uplink and downlink time slot indication signals.

[0004] However, the price of the modem is high and only a portion of the modem's functions are used. Summary of the invention

[0005] The present disclosure provides a TDD synchronization circuit, a chip and a radio frequency coverage unit to solve the problem of high cost when performing TDD synchronization between a current base station and a radio frequency coverage unit, thereby reducing the cost of performing TDD synchronization on the radio frequency coverage unit.

[0006] In a first aspect, the present disclosure provides a TDD synchronization circuit, comprising: a detection circuit and a comparison circuit; an output end of the detection circuit is electrically connected to a first input end of the comparison circuit;

[0007] The input end of the detection circuit is used to receive a time division duplex (TDD) coupling signal; the detection circuit is used to perform detection processing on the TDD coupling signal to obtain a TDD modulation signal with the carrier removed; the comparison circuit is used to receive a first reference voltage signal and the TDD modulation signal, and perform logic processing on the first reference voltage signal and the TDD modulation signal to increase the voltage range of the TDD modulation signal to obtain a TDD drive signal.

[0008] In a possible design, the TDD synchronization circuit further includes a bypass amplifier circuit; the output end of the bypass amplifier circuit is electrically connected to the input end of the detection circuit;

[0009] The input end of the bypass amplifier circuit is used to receive the TDD coupled signal; the bypass amplifier circuit is used to amplify the TDD coupled signal when the TDD coupled signal is less than or equal to the first preset threshold, and output the processed TDD coupled signal; accordingly, the input end of the detection circuit is specifically used to: receive the processed TDD coupled signal; the detection circuit is specifically used to perform detection processing on the processed TDD coupled signal to obtain a TDD modulated signal with the carrier removed.

[0010] In one possible design, the band bypass amplifier circuit includes a first band bypass amplifier and a second band bypass amplifier connected in sequence;

[0011] The input end of the first bypass amplifier is used to receive the TDD coupling signal; the first bypass amplifier is used to amplify the TDD coupling signal when the TDD coupling signal is less than or equal to the first preset threshold, and output the TDD coupling signal after the primary processing;

[0012] The second bypass amplifier is used to amplify the TDD coupled signal after the first-stage processing and output the processed TDD coupled signal when the TDD coupled signal after the first-stage processing is less than or equal to the first preset threshold.

[0013] In a possible design, the TDD synchronization circuit further includes: a level conversion circuit; the output end of the comparison circuit is electrically connected to the input end of the level conversion circuit;

[0014] The input end of the level conversion circuit is used to receive the TDD driving signal, and the level conversion circuit is used to process the TDD driving signal to obtain a TDD level signal.

[0015] In one possible design, the comparison circuit includes a multiplication comparator; a first input terminal of the multiplication comparator is electrically connected to an output terminal of the detection circuit; and an output terminal of the multiplication comparator is electrically connected to the level conversion circuit.

[0016] In one possible design, the comparison circuit includes a multiplication comparator and a subtraction comparator; the first input terminal of the multiplication comparator is electrically connected to the output terminal of the detection circuit; the output terminal of the multiplication comparator is electrically connected to the first input terminal of the subtraction comparator; the output terminal of the subtraction comparator is electrically connected to the level conversion circuit;

[0017] The multiplication comparator is used to receive a first reference voltage signal and the TDD modulation signal, and perform multiplication processing on the first reference voltage signal and the TDD modulation signal to obtain an amplified TDD driving signal;

[0018] The subtraction comparator is used to receive the second reference voltage signal and the amplified TDD driving signal, and perform subtraction processing on the voltage of the amplified TDD driving signal and the second reference voltage signal to obtain the TDD driving signal.

[0019] In a possible design, the comparison circuit includes a multiplication comparator and a driving amplifier electrically connected in sequence; the first input end of the multiplication comparator is electrically connected to the output end of the detection circuit; the output end of the multiplication comparator is electrically connected to the input end of the driving amplifier; the output end of the driving amplifier is electrically connected to the input end of the level conversion circuit;

[0020] The multiplication comparator is used to receive a first reference voltage signal and the TDD modulation signal, perform multiplication processing on the first reference voltage signal and the TDD modulation signal, and output an amplified TDD driving signal;

[0021] The driving amplifier is used to increase the power of the amplified TDD driving signal and output the TDD driving signal.

[0022] In a possible design, the comparison circuit includes a multiplication comparator, a subtraction comparator and a driving amplifier; the first input end of the multiplication comparator is electrically connected to the output end of the detection circuit; the output end of the multiplication comparator is electrically connected to the input end of the subtraction comparator; the output end of the subtraction comparator is electrically connected to the input end of the driving amplifier; the output end of the driving amplifier is electrically connected to the input end of the level conversion circuit;

[0023] The multiplication comparator is used to receive a first reference voltage signal and the TDD modulation signal, perform multiplication processing on the first reference voltage signal and the TDD modulation signal, and output an amplified TDD driving signal;

[0024] The subtraction comparator is used to receive the second reference voltage signal and the increased TDD driving signal, and perform subtraction processing on the voltage of the increased TDD driving signal and the second reference voltage signal to obtain the reduced TDD driving signal;

[0025] The driving amplifier is used to increase the power of the reduced TDD driving signal and output the TDD driving signal.

[0026] The TDD synchronization circuit provided by the embodiment of the present disclosure includes a detection circuit and a comparison circuit. The input end of the detection circuit receives the TDD coupling signal, and the detection circuit performs detection processing on the TDD coupling signal to output a TDD modulation signal without a carrier. The comparison circuit receives a first reference voltage signal and the TDD modulation signal, and performs logic processing on the first reference voltage signal and the TDD modulation signal to increase the voltage range of the TDD modulation signal to obtain a TDD drive signal. The TDD drive signal is more conducive to driving the next level circuit, realizing the recovery of the TDD time slot signal, participating in the switch control of the RF uplink and downlink, and accurately performing the TDD time slot control. There is no complex processor in the TDD synchronization circuit, the device selection range is wide, the implementation is simple, the response speed is fast, and there is no need to use a modem for TDD synchronization, which saves costs, does not cause interference, and is highly practical.

[0027] In a second aspect, the present disclosure provides a TDD synchronization chip, characterized in that the TDD synchronization chip includes the TDD synchronization circuit as described in the first aspect above.

[0028] The beneficial effects of the TDD synchronization chip provided in the above second aspect and each possible design of the above second aspect can be referred to the beneficial effects brought about by the above first aspect and each possible implementation method of the first aspect, which will not be repeated here.

[0029] In a third aspect, the present disclosure provides a radio frequency coverage unit, wherein the radio frequency coverage unit includes the TDD synchronization circuit as described in the first aspect.

[0030] The beneficial effects of the radio frequency coverage unit provided in the third aspect and each possible design of the third aspect can be referred to the beneficial effects brought about by the first aspect and each possible implementation manner of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1A schematic diagram of the structure of a communication system is provided for an embodiment of the present disclosure;

[0032] Figure 2 A schematic diagram of a generation principle of a TDD coupling signal provided in an embodiment of the present disclosure;

[0033] Figure 3 A schematic diagram of a topological structure of a TDD synchronization circuit provided in an embodiment of the present disclosure;

[0034] Figure 4 A schematic diagram of a topological structure of another TDD synchronization circuit provided in an embodiment of the present disclosure;

[0035] Figure 5 A schematic diagram of a topological structure of another TDD synchronization circuit provided in an embodiment of the present disclosure;

[0036] Figure 6 A schematic diagram of a topological structure of another TDD synchronization circuit provided in an embodiment of the present disclosure;

[0037] Figure 7 A schematic diagram of a topological structure of another TDD synchronization circuit provided in an embodiment of the present disclosure;

[0038] Figure 8 A schematic diagram of a topological structure of another TDD synchronization circuit provided in an embodiment of the present disclosure;

[0039] Fig. 9 A schematic diagram of a topological structure of another TDD synchronization circuit provided in an embodiment of the present disclosure;

[0040] Reference numerals:

[0041] 110: base station; 120: radio frequency coverage unit; 130: radio frequency coverage unit; 140: radio frequency coverage unit; 111: logic circuit; 112: radio frequency switch; 311: detection circuit; 312: comparison circuit; 320: radio frequency switch; 330: amplifier; 340: power amplifier; 313: bypass amplifier circuit; 3131: first bypass amplifier; 3132: second bypass amplifier; 314: level conversion circuit; 3121: multiplication comparator; 3122: subtraction comparator; 3123: driving amplifier. DETAILED DESCRIPTION

[0042] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0043] In the present disclosure, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a alone, b alone, or c alone can represent: a alone, b alone, c alone, a and b in combination, a and c in combination, b and c in combination, or a, b, and c in combination, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0044] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present disclosure and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present disclosure.

[0045] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure may refer to not only a physical connection, but also an electrical connection or a signal connection. For example, it may be a direct connection, i.e. a physical connection, or it may be an indirect connection through at least one intermediate element, as long as the circuit is connected. It may also be the internal connection of two elements. In addition to signal connection through a circuit, signal connection may also refer to signal connection through a media medium, such as radio waves. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure may be understood according to specific circumstances.

[0046] The terms used in the present disclosure are explained below.

[0047] TDD means that the transmission and reception of signals are carried out in different time slots of the same frequency channel, and a certain guaranteed time is used to distinguish them from each other. It can be understood as a "two-way traffic" running on a "one-way street", and the traffic can only be controlled by time, allowing the download traffic to pass through at one time and the upload traffic to pass at another time.

[0048] The TDD synchronization circuit provided by the present disclosure can be applied to a communication system. The following describes a communication system provided by the present disclosure. Figure 1 , Figure 1A structural diagram of a communication system is provided for an embodiment of the present disclosure. The communication system provided in this embodiment may include: a base station 110 and at least one radio frequency coverage unit. The base station 110 may also be referred to as a baseband processing unit, and the radio frequency coverage unit may also be referred to as a radio frequency remote coverage unit. The base station 110 is connected to at least one radio frequency coverage unit via an optical fiber or a radio frequency line. The optical fiber may be an analog optical fiber. Figure 1 3 radio frequency coverage units are shown as an example, namely radio frequency coverage unit 120, radio frequency coverage unit 130 and radio frequency coverage unit 140, that is, base station 110 is electrically connected to radio frequency coverage unit 120, radio frequency coverage unit 130 and radio frequency coverage unit 140 respectively. It should be noted that, Figure 1 The number of radio frequency coverage units connected to the base station 110 is only an example, and the number of radio frequency coverage units connected to the base station 110 is not disclosed and is not limited. Figure 1 The communication system provided by the present disclosure is introduced as an example. When deploying the network, the base station 110, the core network, and the wireless network control equipment can be concentrated in the machine room, and connected to the radio frequency remote unit deployed at the planned site through optical fiber to complete the network coverage and provide services for the terminal equipment, thereby reducing the construction and maintenance costs and improving efficiency. It can be understood that Figure 1 The core network and terminal equipment are not shown.

[0049] The above-mentioned terminal equipment may refer to user equipment, access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, wireless communication equipment, user agent or user device. The terminal device may also be a satellite phone, a cellular phone, a smart phone, a wireless data card, a wireless modem, a machine type communication device, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA), a handheld device with wireless communication function, a computing device or other processing device connected to a wireless modem, a vehicle-mounted device or a wearable device, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, a terminal device in a 5G network, a terminal device in a 6G network, or a terminal device in a future communication network, etc. In addition, the terminal device may also be a terminal device in an Internet of Things (IoT) system.

[0050] Among them, the communication system provided in this embodiment adopts TDD mode for uplink and downlink data transmission. The uplink and downlink working switching time of the radio frequency coverage unit needs to be synchronized with the uplink and downlink working switching time of the base station 110, otherwise it will cause insufficient uplink and downlink isolation and mutual interference, resulting in the entire communication system being unable to work normally. Usually, in order to enable the radio frequency coverage unit to achieve uplink and downlink working time switching and synchronization with the base station 110, the base station 110, as a signal source, provides the radio frequency coverage unit with a corresponding TDD synchronization signal, and the radio frequency coverage unit obtains the uplink and downlink time slot ratio and other information from the TDD synchronization signal sent by the base station 110, so as to realize TDD synchronization between the base station 110 and the radio frequency coverage unit.

[0051] The main TDD synchronization method at present is: using a modem with a TDD baseband synchronization module in the RF coverage unit to perform cell search and wireless signaling processing of the TDD wireless network, obtain accurate TDD uplink and downlink time slot timing, uplink and downlink time ratio and other information, and output a TDD drive signal for indicating the uplink and downlink time slots.

[0052] However, the modem itself is used as a data card. If it is used for TDD synchronization, the price is relatively high. In addition, when using the modem for TDD synchronization, only part of the modem's functions are used, and the modem is not fully utilized, resulting in a waste of resources.

[0053] In the process of TDD synchronization of the communication system provided by the present disclosure, the base station 110 superimposes the TDD time slot signal on the radio frequency signal to obtain a TDD coupling signal, and sends the TDD coupling signal to the radio frequency coverage unit. Figure 2 The schematic diagram of the generation principle of the TDD coupling signal shown in FIG. 1 is used as an example to illustrate. It can be understood that Figure 2 The generation method of the TDD coupling signal shown does not constitute a limitation to the present disclosure.

[0054] See also Figure 2 , Figure 2 A schematic diagram of the generation principle of a TDD coupling signal provided in an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the generation process of the TDD coupling signal is performed by a base station, which may be the above-mentioned base station Figure 1 The base station 110 in the communication system shown is described below by taking the base station 110 as an example. The base station 110 includes a logic circuit 111 and a radio frequency switch 112. The logic circuit 111 determines the switching time point from TDD uplink to downlink according to the characteristics of the TDD signal frame structure, such as TDD time slot ratio information, and outputs a TDD time slot signal, which can be a synchronization pulse signal. By controlling the radio frequency switch 112, the TDD time slot signal is loaded onto the radio frequency carrier signal, and a radio frequency carrier signal carrying the TDD time slot signal is output, that is, a TDD coupling signal is output, and the TDD coupling signal is sent to the radio frequency coverage unit through the optical fiber. Among them, the radio frequency carrier signal can be as follows Figure 2 The 960 MHz RF signal shown as an example may also be a RF signal of other frequencies, which is not limited in the present disclosure. If the RF carrier signal is a 960 MHz RF signal, the output TDD coupled signal is also a 960 MHz RF signal.

[0055] Exemplarily, the logic circuit 111 may include a Field Programmable Gate Array (FPGA) or a Microcontroller Unit (MCU).

[0056] The base station 110 sends the TDD coupling signal to the radio frequency coverage unit, and the radio frequency coverage unit recovers the TDD time slot signal from the TDD coupling signal, thereby obtaining the TDD time slot information for driving the next level of transceiver circuit. It can be understood that each radio frequency coverage unit receives the TDD coupling signal. The following takes the TDD synchronization circuit in any radio frequency coverage unit in each radio frequency coverage unit as an example to introduce in detail the processing process of the TDD coupling signal by the radio frequency coverage unit.

[0057] See also Figure 3 , Figure 3 A schematic diagram of a topological structure of a TDD synchronization circuit provided in an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the TDD synchronization circuit 310 may include but is not limited to: a detection circuit 311 and a comparison circuit 312 , and the output end of the detection circuit 311 is electrically connected to the first input end of the comparison circuit 312 .

[0058] The input end of the detection circuit 311 is used to receive the TDD coupled signal. The detection circuit 311 is used to perform detection processing on the TDD coupled signal to obtain a TDD modulated signal with the carrier removed.

[0059] The TDD coupling signal may be sent by the base station 1101. Figure 2 The base station 110 is shown as superimposing the TDD time slot signal on the radio frequency carrier signal to obtain a TDD coupled signal.

[0060] In this embodiment, the detection circuit 311 can perform detection processing on the received TDD coupled signal. The detection processing refers to removing the RF carrier signal from the TDD coupled signal to detect the low-frequency TDD time slot signal. The detection circuit 311 outputs the TDD modulated signal without the carrier.

[0061] Exemplarily, the detection circuit 311 may be implemented by a detector.

[0062] The comparison circuit 312 is used to receive the first reference voltage signal and the TDD modulation signal, and perform logic processing on the first reference voltage signal and the TDD modulation signal to increase the voltage range of the TDD modulation signal to obtain a TDD driving signal.

[0063] The first reference voltage signal is a preset voltage signal, and the first reference voltage signal is connected to the second input terminal of the comparison circuit 312 .

[0064] In this embodiment, the input end of the comparison circuit 312 includes at least a first input end and a second input end. By performing a logical operation on the TDD modulation signal input to the first input end and the first reference voltage signal input to the second input end, the voltage range of the TDD modulation signal is increased, thereby obtaining a TDD driving signal.

[0065] Exemplarily, the TDD modulation signal can be multiplied by the first reference voltage signal, so that the voltage range of the TDD modulation signal is increased. For example, the voltage range of the TDD modulation signal is 0.25 to 1.1V, and the voltage value of the first reference voltage signal is 3V, then the comparison circuit 312 amplifies the voltage of the TDD modulation signal by 3 times, and the voltage range of the TDD drive signal output by the comparison circuit 312 is 0.75 to 3.3V.

[0066] Furthermore, the TDD driving signal output by the TDD synchronization circuit 310 can be used to drive the next level circuit to send uplink and downlink data, wherein the next level circuit electrically connected to the TDD synchronization circuit 310 may include devices such as a RF switch, a low noise amplifier, and a power amplifier. Figure 3 exemplarily shows the next level circuit to which the TDD synchronization circuit 310 is electrically connected. It can be understood that Figure 3 The next-stage circuit electrically connected to the TDD synchronization circuit 310 in FIG. 1 is only an example and does not constitute a limitation of the present disclosure. Figure 3 As shown, the next stage circuit may include: a radio frequency switch 320, an amplifier 330 and a power amplifier 340. The output end of the comparison circuit 312 is electrically connected to the input ends of the radio frequency switch 320, the amplifier 330 and the power amplifier 340 respectively.

[0067] The RF switch 320 is used to control the transmission and reception of uplink and downlink data according to the level of the received TDD driving signal.

[0068] The branch where the amplifier 330 is located is used to control the transmission and reception of uplink data.

[0069] For example, the amplifier 330 may include a low noise amplifier.

[0070] The branch where the power amplifier 340 is located is used to control the transmission and reception of downlink data.

[0071] In this embodiment, the levels of the enable amplifier 330 and the power amplifier 340 are opposite, so that the amplifier 330 and the power amplifier 340 can be driven simultaneously by the TDD drive signal to ensure that only uplink data or downlink data is transmitted and received at the same time, thereby realizing the orderly transmission and reception of uplink and downlink data of TDD.

[0072] In practical applications, the base station superimposes the TDD time slot signal on the radio frequency signal to obtain a TDD coupling signal, and sends the TDD coupling signal to the radio frequency coverage unit. The radio frequency coverage unit receives and processes the TDD coupling signal through the TDD synchronization circuit 310. Specifically, the input end of the detection circuit 311 in the TDD synchronization circuit 310 receives the TDD coupling signal, and the detection circuit 311 removes the radio frequency carrier signal from the TDD coupling signal, thereby detecting the low-frequency TDD modulation signal. The detection circuit 311 outputs the TDD modulation signal at the output end, and the output end of the detection circuit 311 is electrically connected to the first input end of the comparison circuit 312. The comparison circuit 312 performs a logical operation on the input TDD modulation signal and the first reference voltage signal, amplifies the voltage range of the TDD modulation signal, and outputs a TDD drive signal. The TDD drive signal corresponds to the TDD time slot signal generated by the base station, and realizes the recovery of the TDD time slot signal generated by the base station in the radio frequency coverage unit, and accurately performs TDD time slot control in the radio frequency coverage unit.

[0073] A TDD synchronization circuit provided in this embodiment includes a detection circuit and a comparison circuit. The input end of the detection circuit receives a TDD coupling signal. The detection circuit performs detection processing on the TDD coupling signal and outputs a TDD modulation signal without a carrier. The comparison circuit receives a first reference voltage signal and the TDD modulation signal, and performs logic processing on the first reference voltage signal and the TDD modulation signal to increase the voltage range of the TDD modulation signal to obtain a TDD drive signal. The TDD drive signal is more conducive to driving the next level circuit, realizing the recovery of the TDD time slot signal, participating in the switch control of the RF uplink and downlink, and accurately performing the TDD time slot control. There is no complex processor in the TDD synchronization circuit, the device selection range is wide, the implementation is simple, the response speed is fast, and there is no need to use a modem for TDD synchronization, which saves costs, does not cause interference, and is highly practical.

[0074] In one possible implementation, see Figure 4 , Figure 4 A schematic diagram of a topological structure of another TDD synchronization circuit provided in an embodiment of the present disclosure, Figure 4 is Figure 3 Based on the embodiment shown, further, as Figure 4 As shown, the TDD synchronization circuit 310 provided in this embodiment further includes a bypass amplifier circuit 313. The output end of the bypass amplifier circuit 313 is electrically connected to the input end of the detection circuit.

[0075] The input end of the bypass amplifier circuit 313 is used to receive the TDD coupling signal. The bypass amplifier circuit 313 is used to amplify the TDD coupling signal when the TDD coupling signal is less than or equal to the first preset threshold, and output the processed TDD coupling signal. Correspondingly, the input end of the detection circuit is specifically used to receive the processed TDD coupling signal. The detection circuit is specifically used to perform detection processing on the processed TDD coupling signal to obtain a TDD modulated signal without a carrier.

[0076] In addition, the bypass amplifier circuit 313 has a bypass function, that is, when the received TDD coupling signal is greater than the first preset threshold, the TDD coupling signal is transparently transmitted through the bypass of the bypass amplifier circuit 313, that is, the TDD coupling signal is not amplified, and a processed TDD coupling signal is output, which is substantially the same as the TDD coupling signal.

[0077] In practical applications, the size of the TDD coupling signal received by the radio frequency coverage unit is uncertain. In some cases, the received TDD coupling signal is larger, and in other cases, the received TDD coupling signal is smaller. The TDD coupling signal is first input to the bypass amplifier circuit 313, and the bypass amplifier circuit 313 can choose whether to turn on its own amplification function through an internal switch. Specifically, when the bypass amplifier circuit 313 determines that the TDD coupling signal is less than or equal to the first preset threshold, that is, when the TDD coupling signal is small, it turns on its own amplification function, amplifies the TDD coupling signal, and outputs the processed TDD coupling signal. When the bypass amplifier circuit 313 determines that the TDD coupling signal is greater than the first preset threshold, that is, when the TDD coupling signal is large, it can turn off its own amplification function so that the TDD coupling signal is transparently transmitted through the bypass, and the TDD coupling signal is not amplified, and the processed TDD coupling signal is output.

[0078] A TDD synchronization circuit provided in this embodiment includes a bypass amplifier circuit, a detection circuit and a comparison circuit. The input end of the bypass amplifier circuit receives a TDD coupling signal. When the TDD coupling signal is less than or equal to a first preset threshold, the bypass amplifier circuit amplifies the TDD coupling signal and outputs the processed TDD coupling signal. The detection circuit performs detection processing on the processed TDD coupling signal and outputs a TDD modulation signal without a carrier. The comparison circuit receives a first reference voltage signal and the TDD modulation signal, and performs logic processing on the first reference voltage signal and the TDD modulation signal to increase the voltage range of the TDD modulation signal to obtain a TDD drive signal. The TDD drive signal is more conducive to driving the next level circuit, realizing the recovery of the TDD time slot signal, participating in the switch control of the RF uplink and downlink, and accurately performing the TDD time slot control. There is no complex processor in the TDD synchronization circuit, the device selection range is wide, the implementation is simple, the response speed is fast, and there is no need to use a modem for TDD synchronization, which saves costs, does not cause interference, and has strong practicality. The received TDD coupled signal is processed using a bypass amplifier circuit, which can process smaller signals and make the application scenarios of the TDD synchronization circuit more extensive.

[0079] In a possible design, the bypass amplifier circuit 313 includes two stages of bypass amplifiers, thereby ensuring the amplification effect of a smaller TDD coupling signal.

[0080] Please continue reading Figure 4 In the TDD synchronization circuit provided in this embodiment, the band bypass amplifier circuit 313 includes a first band bypass amplifier 3131 and a second band bypass amplifier 3132 which are connected in sequence.

[0081] The input end of the first bypass amplifier 3131 is used to receive the TDD coupling signal. The first bypass amplifier 3131 is used to amplify the TDD coupling signal when the TDD coupling signal is less than or equal to the first preset threshold, and output the TDD coupling signal after primary processing.

[0082] In addition, the first-band bypass amplifier 3131 has a bypass function, that is, when the received TDD coupling signal is greater than the first preset threshold, the TDD coupling signal is transparently transmitted through the bypass of the first-band bypass amplifier 3131, that is, the TDD coupling signal is not amplified, and a first-stage processed TDD coupling signal is output, which is substantially the same as the TDD coupling signal.

[0083] The second bypass amplifier 3132 is used to amplify the TDD coupled signal after the primary processing and output the processed TDD coupled signal when the TDD coupled signal after the primary processing is less than or equal to the first preset threshold.

[0084] In addition, the second bypass amplifier 3132 has a bypass function, that is, when the received TDD coupled signal after the first-stage processing is greater than the first preset threshold, the TDD coupled signal after the first-stage processing is transparently transmitted through the bypass of the second bypass amplifier 3132, that is, the TDD coupled signal after the first-stage processing is not amplified, and the processed TDD coupled signal is output, which is substantially the same as the TDD coupled signal after the first-stage processing.

[0085] In practical applications, the first bypass amplifier 3131 receives the TDD coupling signal sent by the base station, and the first bypass amplifier circuit 313 can select whether to turn on its own amplification function through an internal switch. Specifically, when the first bypass amplifier 3131 determines that the TDD coupling signal is less than or equal to the first preset threshold, that is, when the TDD coupling signal is small, it turns on its own amplification function, amplifies the TDD coupling signal, and outputs the TDD coupling signal after the first stage of processing. When the first bypass amplifier 3131 determines that the TDD coupling signal is greater than the first preset threshold, that is, when the TDD coupling signal is large, it can turn off its own amplification function so that the TDD coupling signal is transparently transmitted through the bypass, and the TDD coupling signal is not amplified, and the TDD coupling signal after the first stage of processing is output. In some cases, the TDD coupling signal is small, and after being amplified by the first bypass amplifier 3131, the output TDD coupling signal after the first stage of processing is still small, then the second bypass amplifier 3132 is set to further amplify the TDD coupling signal after the first stage of processing. The second bypass amplifier 3132 receives the TDD coupled signal after the primary processing, and the second bypass amplifier circuit 313 can choose whether to turn on its own amplification function through an internal switch. Specifically, when the second bypass amplifier 3132 determines that the TDD coupled signal is less than or equal to the first preset threshold, that is, when the TDD coupled signal is small, it turns on its own amplification function, amplifies the TDD coupled signal, and outputs the TDD coupled signal after the primary processing. When the second bypass amplifier 3132 determines that the TDD coupled signal is greater than the first preset threshold, that is, when the TDD coupled signal is large, it can turn off its own amplification function so that the TDD coupled signal is transparently transmitted through the bypass, the TDD coupled signal is not amplified, and the TDD coupled signal after the primary processing is output.

[0086] A TDD synchronization circuit provided in this embodiment includes a first bypass amplifier, a second bypass amplifier, a detection circuit and a comparison circuit. The input end of the first bypass amplifier receives a TDD coupling signal. When the TDD coupling signal is less than or equal to a first preset threshold, the first bypass amplifier amplifies the TDD coupling signal and outputs a TDD coupling signal after primary processing. When the TDD coupling signal after primary processing is less than or equal to a first preset threshold, the second bypass amplifier amplifies the TDD coupling signal after primary processing and outputs the processed TDD coupling signal. The detection circuit performs detection processing on the processed TDD coupling signal and outputs a TDD modulation signal without a carrier. The comparison circuit receives a first reference voltage signal and the TDD modulation signal, and performs logic processing on the first reference voltage signal and the TDD modulation signal to increase the voltage range of the TDD modulation signal to obtain a TDD drive signal. The TDD drive signal is more conducive to driving the next level circuit, realizing the recovery of the TDD time slot signal, participating in the switch control of the RF uplink and downlink, and accurately performing the TDD time slot control. The TDD synchronization circuit does not have complex processors, etc., has a wide range of device selection, is simple to implement, has a fast response speed, does not require a modem for TDD synchronization, saves costs, does not cause interference, and is highly practical. The received TDD coupled signal is amplified using a two-stage bypass amplifier, which can process smaller signals and ensure the effect of amplifying smaller signals, making the application scenarios of the TDD synchronization circuit more extensive.

[0087] In one possible implementation, see Figure 5 , Figure 5 A schematic diagram of a topological structure of another TDD synchronization circuit provided in an embodiment of the present disclosure, Figure 5 is Figure 3 or Figure 4 Based on the embodiment shown, further, as Figure 5 As shown, the TDD synchronization circuit 310 provided in this embodiment further includes a level conversion circuit 314. The output end of the comparison circuit 312 is electrically connected to the input end of the level conversion circuit 314.

[0088] The input end of the level conversion circuit 314 is used to receive the TDD driving signal. The level conversion circuit 314 is used to process the TDD driving signal to obtain a TDD level signal.

[0089] In practical applications, the level conversion circuit 314 receives the TDD driving signal output by the comparison circuit 312, and converts the TDD driving signal into a TDD level signal, that is, the TDD level signal includes high and low levels, and the TDD time slot can be determined by the high and low levels in the TDD level signal, that is, the switching moment of uplink and downlink data transmission can be determined. For example, the TDD level signal output is a high level, indicating that uplink data transmission is currently being performed, and correspondingly, the TDD level signal output is a low level, indicating that downlink data transmission is currently being performed. Alternatively, the TDD level signal output is a high level, indicating that downlink data transmission is currently being performed, and correspondingly, the TDD level signal output is a low level, indicating that uplink data transmission is currently being performed.

[0090] A TDD synchronization circuit provided in this embodiment includes a detection circuit, a comparison circuit and a level conversion circuit. The input end of the detection circuit receives a TDD coupling signal, and the detection circuit performs detection processing on the TDD coupling signal to output a TDD modulation signal without a carrier. The comparison circuit receives a first reference voltage signal and the TDD modulation signal, and performs logic processing on the first reference voltage signal and the TDD modulation signal to increase the voltage range of the TDD modulation signal to obtain a TDD drive signal. The TDD drive signal is more conducive to driving the next level circuit, realizing the recovery of the TDD time slot signal, participating in the switch control of the RF uplink and downlink, and accurately performing the TDD time slot control. The level conversion circuit processes the TDD drive signal to obtain a TDD level signal, so that the RF devices in the next level circuit can be controlled more flexibly and more accurately. There is no complex processor in the TDD synchronization circuit, the device selection range is wide, the implementation is simple, the response speed is fast, and there is no need to use a modem for TDD synchronization, which saves costs, does not cause interference, and is highly practical.

[0091] In one possible design, see Figure 6 , Figure 6 A schematic diagram of a topological structure of another TDD synchronization circuit provided in an embodiment of the present disclosure, Figure 6 is Figure 3-Figure 5 Based on any of the embodiments shown, further, as Figure 6 As shown, the comparison circuit 312 in the TDD synchronization circuit 310 provided in this embodiment includes a multiplication comparator 3121. The first input terminal of the multiplication comparator 3121 is electrically connected to the output terminal of the detection circuit 311. In the case where the TDD synchronization circuit 310 includes a level conversion circuit 314, the output terminal of the multiplication comparator 3121 is electrically connected to the level conversion circuit 314. In the case where the TDD synchronization circuit 310 does not include a level conversion circuit 314, the output terminal of the multiplication comparator 3121 can be electrically connected to the next stage circuit.

[0092] The multiplication comparator 3121 is used for receiving the first reference voltage signal and the TDD modulation signal, and performing logic processing on the first reference voltage signal and the TDD modulation signal to increase the voltage range of the TDD modulation signal to obtain a TDD driving signal.

[0093] In this embodiment, the multiplication comparator 3121 includes two input terminals, which may be a first input terminal and a second input terminal. The TDD modulation signal input to the first input terminal and the first reference voltage signal input to the second input terminal are multiplied to increase the voltage range of the TDD modulation signal as a whole, thereby obtaining a TDD driving signal.

[0094] In practical applications, the multiplication comparator 3121 receives the TDD modulation signal output by the detection circuit 311 and performs multiplication operation on the TDD modulation signal and the first reference voltage signal to increase the voltage range of the TDD modulation signal as a whole, thereby outputting a TDD driving signal.

[0095] Exemplarily, the voltage range of the TDD modulation signal is 0.25-1.1V, and the voltage value of the first reference voltage signal is 3V, then the multiplication comparator 3121 amplifies the voltage of the TDD modulation signal by 3 times, and the voltage range of the TDD drive signal output by the multiplication comparator 3121 is 0.75-3.3V.

[0096] Further, when the TDD synchronization circuit 310 includes the level conversion circuit 314 , the level conversion circuit 314 includes a level conversion chip.

[0097] A TDD synchronization circuit provided in this embodiment includes a detection circuit and a multiplication comparator. The input end of the detection circuit receives a TDD coupling signal. The detection circuit performs detection processing on the TDD coupling signal and outputs a TDD modulation signal without a carrier. The multiplication comparator receives a first reference voltage signal and the TDD modulation signal, and performs multiplication processing on the first reference voltage signal and the TDD modulation signal to increase the voltage range of the TDD modulation signal to obtain a TDD drive signal. The TDD drive signal is more conducive to driving the next level circuit, realizing the recovery of the TDD time slot signal, participating in the switch control of the RF uplink and downlink, and accurately performing the TDD time slot control. The level conversion circuit processes the TDD drive signal to obtain a TDD level signal, so that the RF devices in the next level circuit can be controlled more flexibly and more accurately. The detection circuit and the multiplication comparator are used in the TDD synchronization circuit, and there is no complex processor, etc. The device selection range is wide, the implementation is simple, the response speed is fast, and there is no need to use a modem for TDD synchronization, which saves costs, does not cause interference, and is highly practical.

[0098] In one possible design, see Figure 7 , Figure 7A schematic diagram of a topological structure of another TDD synchronization circuit provided in an embodiment of the present disclosure, Figure 7 is Figure 3-Figure 5 Based on any of the embodiments shown, further, as Figure 7 As shown, the comparison circuit 312 in the TDD synchronization circuit 310 provided in this embodiment includes a multiplication comparator 3121 and a subtraction comparator 3122. The subtraction comparator 3122 may also be referred to as a subtractor. The first input terminal of the multiplication comparator 3121 is electrically connected to the output terminal of the detection circuit; the output terminal of the multiplication comparator 3121 is electrically connected to the first input terminal of the subtraction comparator 3122; and the output terminal of the subtraction comparator 3122 is electrically connected to the level conversion circuit.

[0099] The multiplication comparator 3121 is used for receiving the first reference voltage signal and the TDD modulation signal, and performing multiplication processing on the first reference voltage signal and the TDD modulation signal to obtain an amplified TDD driving signal.

[0100] In this embodiment, the multiplication comparator 3121 includes two input terminals, which may be a first input terminal and a second input terminal. By multiplying the TDD modulation signal input to the first input terminal and the first reference voltage signal input to the second input terminal, the voltage range of the TDD modulation signal is increased as a whole, thereby obtaining an increased TDD drive signal.

[0101] The subtraction comparator 3122 is used to receive the second reference voltage signal and the amplified TDD driving signal, and perform subtraction processing on the voltage of the amplified TDD driving signal and the second reference voltage signal to obtain the TDD driving signal.

[0102] It should be noted that, when the TDD synchronization circuit 310 includes a level conversion circuit 314, the output end of the subtraction comparator 3122 is electrically connected to the level conversion circuit 314. When the TDD synchronization circuit 310 does not include a level conversion circuit 314, the output end of the subtraction comparator 3122 can be electrically connected to the next stage circuit.

[0103] In this embodiment, the subtraction comparator 3122 includes two input terminals, which may be a first input terminal and a second input terminal. By performing a subtraction operation on the amplified TDD drive signal input to the first input terminal and the second reference voltage signal input to the second input terminal, the voltage range of the amplified TDD modulation signal is linearly reduced, thereby obtaining a TDD drive signal.

[0104] In practical applications, the multiplication comparator 3121 receives the TDD modulation signal output by the detection circuit 311, and performs a multiplication operation on the TDD modulation signal and the first reference voltage signal to increase the voltage range of the TDD modulation signal as a whole, thereby outputting an increased TDD drive signal. The subtraction comparator 3122 performs a subtraction operation on the increased TDD drive signal and the second reference voltage signal, so that the voltage range of the increased TDD modulation signal is linearly reduced, thereby obtaining a TDD drive signal.

[0105] Exemplarily, the voltage range of the TDD modulation signal is 0.25 to 1.1V, and the voltage value of the first reference voltage signal is 3V. The multiplication comparator 3121 amplifies the voltage of the TDD modulation signal by 3 times, and the voltage range of the TDD drive signal output by the multiplication comparator 3121 is 0.75 to 3.3V. Since the 0.75V voltage is relatively high, it may affect the control accuracy of the RF chip enable pin, and can be adjusted by the subtraction comparator 3122. The 0.75 to 3.3V signal is subtracted by 0.5V through the subtraction comparator 3122, and the subtraction comparator 3122 outputs 0.25 to 2.7V, thereby making the low voltage lower and the high voltage higher, leaving more margin for the subsequent high and low level control. Furthermore, the 0.25-2.7V output by the subtraction comparator 3122 is input to the level conversion circuit, and the output level of the level conversion circuit is 0 or 1, that is, 0V or 3.1V, so that the enabling control of the RF device of the next stage circuit is more sensitive.

[0106] Further, when the TDD synchronization circuit 310 includes the level conversion circuit 314 , the level conversion circuit 314 includes a level conversion chip.

[0107] A TDD synchronization circuit provided in this embodiment includes a detection circuit, a multiplication comparator and a subtraction comparator. The input end of the detection circuit receives a TDD coupling signal, and the detection circuit performs detection processing on the TDD coupling signal to output a TDD modulation signal without a carrier. The multiplication comparator receives a first reference voltage signal and the TDD modulation signal, and performs multiplication processing on the first reference voltage signal and the TDD modulation signal to increase the voltage range of the TDD modulation signal to obtain an increased TDD drive signal. The subtraction comparator linearly reduces the voltage range of the increased TDD drive signal and outputs a TDD drive signal. The TDD drive signal has a higher enable control accuracy for the next level circuit, is more conducive to driving the next level circuit, realizes the recovery of the TDD time slot signal, participates in the switch control of the RF uplink and downlink, and accurately performs the TDD time slot control. The level conversion circuit processes the TDD drive signal to obtain a TDD level signal, so that the RF devices in the next level circuit can be controlled more flexibly and accurately. The TDD synchronization circuit uses a detection circuit and a multiplication comparator, and does not have a complex processor. The device selection range is wide, the implementation is simple, the response speed is fast, and there is no need to use a modem for TDD synchronization, which saves costs, does not cause interference, and is highly practical.

[0108] In one possible design, see Figure 8 , Figure 8 A schematic diagram of a topological structure of another TDD synchronization circuit provided in an embodiment of the present disclosure, Figure 8 is Figure 3-Figure 5 Based on any of the embodiments shown, further, as Figure 8 As shown, the comparison circuit 312 in the TDD synchronization circuit 310 provided in this embodiment includes a multiplication comparator 3121 and a driving amplifier 3123. The first input terminal of the multiplication comparator 3121 is electrically connected to the output terminal of the detection circuit; the output terminal of the multiplication comparator 3121 is electrically connected to the input terminal of the driving amplifier 3123.

[0109] The multiplication comparator 3121 is used for receiving the first reference voltage signal and the TDD modulation signal, performing multiplication processing on the first reference voltage signal and the TDD modulation signal, and outputting an amplified TDD driving signal.

[0110] The principle and function of the multiplication comparator 3121 are similar to those of the multiplication comparator 3121 in the above embodiment, and will not be described in detail here.

[0111] The driving amplifier 3123 is used to increase the power of the amplified TDD driving signal and output the TDD driving signal. The signal strength and quality of the output TDD driving signal better meet the requirements of the devices in the next level circuit for the input signal.

[0112] It should be noted that, when the TDD synchronization circuit 310 includes a level conversion circuit 314, the output end of the driver amplifier 3123 is electrically connected to the level conversion circuit 314. When the TDD synchronization circuit 310 does not include a level conversion circuit 314, the output end of the driver amplifier 3123 may be electrically connected to the next stage circuit.

[0113] Exemplarily, the voltage range of the TDD modulation signal is 0.25 to 1.1 V, and the voltage value of the first reference voltage signal is 3 V. The multiplication comparator 31213121 amplifies the voltage of the TDD modulation signal by 3 times, and the voltage range of the TDD driving signal output by the multiplication comparator 31213121 is 0.75 to 3.3 V. The signal in the voltage range of 0.75 to 3.3 V is driven and amplified by the driving amplifier 3123 to control the next stage circuit.

[0114] Further, when the TDD synchronization circuit 310 includes the level conversion circuit 314 , the level conversion circuit 314 includes an analog triode.

[0115] A TDD synchronization circuit provided in this embodiment includes a detection circuit, a multiplication comparator and a subtraction comparator. The input end of the detection circuit receives a TDD coupling signal, and the detection circuit performs detection processing on the TDD coupling signal to output a TDD modulation signal without a carrier. The multiplication comparator receives a first reference voltage signal and the TDD modulation signal, and performs multiplication processing on the first reference voltage signal and the TDD modulation signal to increase the voltage range of the TDD modulation signal to obtain an increased TDD drive signal. The drive amplifier drives and amplifies the increased TDD drive signal. The signal strength and quality of the output TDD drive signal are more in line with the requirements of the device in the next level circuit for the input signal, and meet the driving capability of the enable control pin of the device in the next level circuit, so that the TDD drive signal has a higher enable control accuracy for the next level circuit, which is more conducive to driving the next level circuit, realizing the recovery of the TDD time slot signal, participating in the switch control of the RF uplink and downlink, and accurately performing the TDD time slot control. The level conversion circuit processes the TDD drive signal to obtain a TDD level signal, so that the RF device in the next level circuit can be controlled more flexibly and accurately. The TDD synchronization circuit uses a detection circuit and a multiplication comparator, and does not have a complex processor. The device selection range is wide, the implementation is simple, the response speed is fast, and there is no need to use a modem for TDD synchronization, which saves costs, does not cause interference, and is highly practical.

[0116] In one possible design, see Fig. 9 , Fig. 9 A schematic diagram of a topological structure of another TDD synchronization circuit provided in an embodiment of the present disclosure, Fig. 9 is Figure 3-Figure 5Based on any of the embodiments shown, further, as Fig. 9 As shown, the comparison circuit 312 in the TDD synchronization circuit 310 provided in this embodiment includes a multiplication comparator 3121, a subtraction comparator 3122 and a driving amplifier 3123. The first input terminal of the multiplication comparator 3121 is electrically connected to the output terminal of the detection circuit; the output terminal of the multiplication comparator 3121 is electrically connected to the input terminal of the subtraction comparator 3122; the output terminal of the subtraction comparator 3122 is electrically connected to the input terminal of the driving amplifier 3123; the output terminal of the driving amplifier 3123 is electrically connected to the input terminal of the level conversion circuit;

[0117] The multiplication comparator 3121 is used for receiving the first reference voltage signal and the TDD modulation signal, performing multiplication processing on the first reference voltage signal and the TDD modulation signal, and outputting an amplified TDD driving signal.

[0118] The principle and function of the multiplication comparator 3121 are similar to those of the multiplication comparator in the above embodiment, and will not be described again here.

[0119] The subtraction comparator 3122 is used to receive the second reference voltage signal and the increased TDD driving signal, and perform subtraction processing on the voltage of the increased TDD driving signal and the second reference voltage signal to obtain the reduced TDD driving signal.

[0120] The principle and function of the subtraction comparator 3122 are similar to those of the subtraction comparator in the above embodiment, and will not be described in detail here.

[0121] The driving amplifier 3123 is used to increase the power of the reduced TDD driving signal and output the TDD driving signal.

[0122] The principle and function of the driving amplifier 3123 are similar to those of the driving amplifier in the above embodiment, and will not be described again here.

[0123] A TDD synchronization circuit provided in this embodiment includes a detection circuit, a multiplication comparator and a subtraction comparator, wherein the input end of the detection circuit receives a TDD coupling signal, the detection circuit performs detection processing on the TDD coupling signal, and outputs a TDD modulation signal with the carrier removed. The multiplication comparator receives a first reference voltage signal and the TDD modulation signal, and performs multiplication processing on the first reference voltage signal and the TDD modulation signal to increase the voltage range of the TDD modulation signal to obtain an increased TDD drive signal, the subtraction comparator linearly reduces the voltage range of the increased TDD drive signal, and outputs a reduced TDD drive signal, the drive amplifier drives and amplifies the reduced TDD drive signal, and the signal strength and quality of the output TDD drive signal are more in line with the requirements of the device in the next level circuit for the input signal, and meet the driving capability of the enable control pin of the device in the next level circuit, so that the TDD drive signal has a higher enable control accuracy for the next level circuit, which is more conducive to driving the next level circuit, realizing the recovery of the TDD time slot signal, participating in the switch control of the RF uplink and downlink, and accurately performing the TDD time slot control. The level conversion circuit processes the TDD drive signal to obtain the TDD level signal, so that the RF devices in the next level circuit can be controlled more flexibly and accurately. The TDD synchronization circuit uses a detection circuit and a multiplication comparator, and does not have a complex processor. The device selection range is wide, the implementation is simple, the response speed is fast, and there is no need to use a modem for TDD synchronization, which saves costs, does not cause interference, and is highly practical.

[0124] The present disclosure provides a TDD synchronization chip, which includes the above-mentioned Figure 3-Figure 9 Any of the TDD synchronization circuits shown.

[0125] A TDD synchronization chip provided in this embodiment includes a detection circuit and a comparison circuit. The input end of the detection circuit receives a TDD coupling signal, and the detection circuit performs detection processing on the TDD coupling signal to output a TDD modulation signal without a carrier. The comparison circuit receives a first reference voltage signal and the TDD modulation signal, and performs logic processing on the first reference voltage signal and the TDD modulation signal to increase the voltage range of the TDD modulation signal to obtain a TDD drive signal. The TDD drive signal is more conducive to driving the next level circuit, realizing the recovery of the TDD time slot signal, participating in the switch control of the RF uplink and downlink, and accurately performing the TDD time slot control. There is no complex processor in the TDD synchronization circuit, the device selection range is wide, the implementation is simple, the response speed is fast, and there is no need to use a modem for TDD synchronization, which saves costs, does not cause interference, and is highly practical.

[0126] The present disclosure provides a radio frequency coverage unit, which includes the above-mentioned Figure 3-Figure 9 Any of the TDD synchronization circuits shown.

[0127] A radio frequency coverage unit provided in this embodiment includes a TDD synchronization circuit, and the TDD synchronization circuit includes a detection circuit and a comparison circuit. The input end of the detection circuit receives a TDD coupling signal, and the detection circuit performs detection processing on the TDD coupling signal, and outputs a TDD modulation signal without a carrier. The comparison circuit receives a first reference voltage signal and the TDD modulation signal, and performs logic processing on the first reference voltage signal and the TDD modulation signal to increase the voltage range of the TDD modulation signal to obtain a TDD drive signal. The TDD drive signal is more conducive to driving the next level circuit, realizing the recovery of the TDD time slot signal, participating in the switch control of the radio frequency uplink and downlink, and accurately performing the TDD time slot control. The carrier signal carrying TDD information is amplified, detected, compared, driven and amplified, and level-converted inside the remote radio frequency coverage unit to generate the uplink and downlink switch signals required by the entire synchronization device. There is no complex processor in the TDD synchronization circuit, the device selection range is wide, the implementation is simple, the response speed is fast, and there is no need to use a modem for TDD synchronization, which saves costs, does not cause interference, and is highly practical.

[0128] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

Claims

1. A TDD synchronization circuit, characterized in that: include: Detection circuit and comparison circuit; The output end of the detection circuit is electrically connected to the first input end of the comparison circuit; The input end of the detection circuit is used to receive a time division duplex (TDD) coupling signal; The detection circuit is used to perform detection processing on the TDD coupled signal to obtain a TDD modulated signal with the carrier removed; The comparison circuit is used to receive a first reference voltage signal and the TDD modulation signal, and perform logic processing on the first reference voltage signal and the TDD modulation signal to increase the voltage range of the TDD modulation signal to obtain a TDD driving signal.

2. The TDD synchronization circuit according to claim 1, characterized in that: The TDD synchronization circuit also includes a bypass amplifier circuit; the output end of the bypass amplifier circuit is electrically connected to the input end of the detection circuit; The input end of the bypass amplifier circuit is used to receive the TDD coupled signal; the bypass amplifier circuit is used to amplify the TDD coupled signal when the TDD coupled signal is less than or equal to the first preset threshold, and output the processed TDD coupled signal; accordingly, the input end of the detection circuit is specifically used to: receive the processed TDD coupled signal; the detection circuit is specifically used to perform detection processing on the processed TDD coupled signal to obtain a TDD modulated signal with the carrier removed.

3. The TDD synchronization circuit according to claim 2, characterized in that: The band bypass amplifier circuit comprises a first band bypass amplifier and a second band bypass amplifier connected in sequence; The input end of the first bypass amplifier is used to receive the TDD coupling signal; the first bypass amplifier is used to amplify the TDD coupling signal when the TDD coupling signal is less than or equal to the first preset threshold, and output the TDD coupling signal after the primary processing; The second bypass amplifier is used to amplify the TDD coupled signal after the first-stage processing and output the processed TDD coupled signal when the TDD coupled signal after the first-stage processing is less than or equal to the first preset threshold.

4. The TDD synchronization circuit according to claim 1, characterized in that: The TDD synchronization circuit further includes: a level conversion circuit; the output end of the comparison circuit is electrically connected to the input end of the level conversion circuit; The input end of the level conversion circuit is used to receive the TDD driving signal, and the level conversion circuit is used to process the TDD driving signal to obtain a TDD level signal.

5. The TDD synchronization circuit according to claim 4, characterized in that: The comparison circuit comprises a multiplication comparator; a first input terminal of the multiplication comparator is electrically connected to an output terminal of the detection circuit; and an output terminal of the multiplication comparator is electrically connected to the level conversion circuit.

6. The TDD synchronization circuit according to claim 4, characterized in that: The comparison circuit includes a multiplication comparator and a subtraction comparator; the first input end of the multiplication comparator is electrically connected to the output end of the detection circuit; the output end of the multiplication comparator is electrically connected to the first input end of the subtraction comparator; the output end of the subtraction comparator is electrically connected to the level conversion circuit; The multiplication comparator is used to receive a first reference voltage signal and the TDD modulation signal, and perform multiplication processing on the first reference voltage signal and the TDD modulation signal to obtain an amplified TDD driving signal; The subtraction comparator is used to receive the second reference voltage signal and the amplified TDD driving signal, and perform subtraction processing on the voltage of the amplified TDD driving signal and the second reference voltage signal to obtain the TDD driving signal.

7. The TDD synchronization circuit according to claim 4, characterized in that: The comparison circuit comprises a multiplication comparator and a driving amplifier which are electrically connected in sequence; the first input terminal of the multiplication comparator is electrically connected to the output terminal of the detection circuit; the output terminal of the multiplication comparator is electrically connected to the input terminal of the driving amplifier; the output terminal of the driving amplifier is electrically connected to the input terminal of the level conversion circuit; The multiplication comparator is used to receive a first reference voltage signal and the TDD modulation signal, perform multiplication processing on the first reference voltage signal and the TDD modulation signal, and output an amplified TDD driving signal; The driving amplifier is used to increase the power of the amplified TDD driving signal and output the TDD driving signal.

8. The TDD synchronization circuit according to claim 4, characterized in that: The comparison circuit includes a multiplication comparator, a subtraction comparator and a driving amplifier; the first input end of the multiplication comparator is electrically connected to the output end of the detection circuit; the output end of the multiplication comparator is electrically connected to the input end of the subtraction comparator; the output end of the subtraction comparator is electrically connected to the input end of the driving amplifier; the output end of the driving amplifier is electrically connected to the input end of the level conversion circuit; The multiplication comparator is used to receive a first reference voltage signal and the TDD modulation signal, perform multiplication processing on the first reference voltage signal and the TDD modulation signal, and output an amplified TDD driving signal; The subtraction comparator is used to receive the second reference voltage signal and the increased TDD driving signal, and perform subtraction processing on the voltage of the increased TDD driving signal and the second reference voltage signal to obtain the reduced TDD driving signal; The driving amplifier is used to increase the power of the reduced TDD driving signal and output the TDD driving signal.

9. A TDD synchronization chip, characterized in that: The TDD synchronization chip comprises the TDD synchronization circuit as claimed in any one of claims 1 to 8.

10. A radio frequency coverage unit, characterized in that: The radio frequency coverage unit comprises the TDD synchronization circuit according to any one of claims 1 to 8.

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