Semiconductor element and manufacturing method thereof
By forming an intermetal dielectric layer, a barrier layer and a spin track torque layer on the substrate, and building a magnetic tunneling junction, the chip area, high cost and electricity consumption in existing MRAM and magnetic field sensing technologies is solved. The problem of insufficient sensitivity has achieved a more compact and efficient semiconductor component design.
Patent Information
- Application Number
- CN202310837094.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-06-20
- Filing Date
- 2023-07-10
- Publication Date
- 2024-12-20
AI Technical Summary
The existing magnetoresistive random access memory (MRAM) and magnetic field sensing technologies have problems such as large chip area, expensive manufacturing process, high power consumption, insufficient sensitivity and susceptibility to temperature changes.
A method of making semiconductor elements is adopted, including forming an intermetallic dielectric layer on the substrate, forming contact holes and filling it with a barrier layer and a metal layer, planarizing the metal layer, forming a spin orbit torque layer, and A magnetic tunneling junction (MTJ) structure is constructed on it.
A more compact chip design is achieved, reducing production costs and energy consumption, improving sensitivity and reducing the impact on temperature changes.
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Figure CN119173043A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular to a magnetoresistive random access memory (MRAM) and a manufacturing method thereof. Background Art
[0002] It is known that the magnetoresistance (MR) effect is the effect that the resistance of a material changes with the change of an external magnetic field. The definition of its physical quantity is the resistance difference in the presence and absence of a magnetic field divided by the original resistance, which is used to represent the resistance change rate. At present, the magnetoresistance effect has been successfully used in hard disk production and has important commercial application value. In addition, by utilizing the characteristics of giant magnetoresistance materials having different resistance values under different magnetization states, magnetic random access memory (MRAM) can also be made. Its advantage is that the stored data can continue to be retained when no power is supplied.
[0003] The magnetoresistance effect is also used in the field of magnetic field sensors. For example, the electronic compass components of the global positioning system (GPS) in mobile phones are used to provide information such as the user's moving position. Currently, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned prior art generally include: more chip area, more expensive manufacturing process, more power consumption, insufficient sensitivity, and susceptibility to temperature changes, etc., and further improvement is necessary. Summary of the invention
[0004] An embodiment of the present invention discloses a method for manufacturing a semiconductor device, which mainly forms an intermetallic dielectric layer on a substrate, then forms a contact hole in the intermetallic dielectric layer, forms a barrier layer and a metal layer in the contact hole, flattens the metal layer, forms a spin orbit torque (SOT) layer on the barrier layer and the metal layer, and then forms a magnetic tunneling junction (MTJ) on the SOT layer.
[0005] Another embodiment of the present invention discloses a semiconductor element, which mainly includes an intermetallic dielectric layer disposed on a substrate, a metal interconnect disposed in the intermetallic dielectric layer and the metal interconnect includes a barrier layer disposed in the intermetallic dielectric layer and extending to the surface of the intermetallic dielectric layer and a metal layer disposed on the barrier layer, a spin orbit torque (SOT) layer disposed on the barrier layer and the metal layer and a magnetic tunneling junction (MTJ) disposed on the SOT layer.
[0006] Another embodiment of the present invention discloses a semiconductor device, which mainly includes an intermetallic dielectric layer disposed on a substrate, a metal interconnect disposed on the intermetallic dielectric layer, a spin orbit torque (SOT) layer disposed on the metal interconnect, an interface layer disposed on the SOT layer, and a magnetic tunneling junction (MTJ) disposed on the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figures 1 to 6 A schematic diagram of a method for manufacturing an MRAM cell according to an embodiment of the present invention;
[0008] Figures 7 to 14 FIG. 4 is a schematic diagram of a method for manufacturing an MRAM cell according to an embodiment of the present invention.
[0009] Explanation of symbols
[0010] 12: Base
[0011] 14: MRAM area
[0012] 16: Interlayer dielectric layer
[0013] 18: Metal interconnect structure
[0014] 20: Metal interconnect structure
[0015] 22: Intermetallic dielectric layer
[0016] 24: Metal interconnects
[0017] 26: Stop layer
[0018] 28: Intermetallic dielectric layer
[0019] 30: Metal interconnect
[0020] 32: Metal interconnect
[0021] 34: Barrier layer
[0022] 36:Metal layer
[0023] 38: Interface layer
[0024] 40: Doping process
[0025] 42: Interface layer
[0026] 48:MTJ stacking structure
[0027] 50:SOT layer
[0028] 52 free layers
[0029] 54: Barrier layer
[0030] 56: Fixed layer
[0031] 58:MTJ
[0032] 60: Covering layer
[0033] 62: Hard mask
[0034] 64: Covering layer
[0035] 66: Intermetallic dielectric layer
[0036] 68:Metal interconnect
[0037] 70: Barrier layer
[0038] 72:Metal layer
[0039] 74: Stop layer
[0040] 82: Barrier layer
[0041] 84: Barrier layer
[0042] 86:Metal Byproducts
[0043] 88: Oxidation byproducts
[0044] 90: Damaged layer
[0045] 92: Angle DETAILED DESCRIPTION
[0046] Please refer to Figures 1 to 6 , Figures 1 to 6 A schematic diagram of a method for manufacturing a semiconductor device, or more specifically, an MRAM cell, according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from a group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region (not shown) are preferably defined on the substrate 12.
[0047] The substrate 12 may include active (active) components such as metal-oxide semiconductor (MOS) transistors, passive (passive) components, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 16 covering the substrate 12. More specifically, the substrate 12 may include planar or non-planar (such as fin-structured transistors) MOS transistor components, wherein the MOS transistor may include a gate structure (such as a metal gate) and transistor components such as source / drain regions, spacers, epitaxial layers, and contact hole etch stop layers. The interlayer dielectric layer 16 may be disposed on the substrate 12 and cover the MOS transistor, and the interlayer dielectric layer 16 may have a plurality of contact plugs electrically connected to the gate and / or source / drain regions of the MOS transistor. Since the related manufacturing processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they are not further described here.
[0048] Then, metal interconnect structures 18 and 20 are sequentially formed on the interlayer dielectric layer 16 to electrically connect the aforementioned contact plugs, wherein the metal interconnect structure 18 includes an intermetallic dielectric layer 22 and a metal interconnect 24 embedded in the intermetallic dielectric layer 22, and the metal interconnect structure 20 includes a stop layer 26, an intermetallic dielectric layer 28 and a plurality of metal interconnects 30 and 32 embedded in the stop layer 26 and the intermetallic dielectric layer 28.
[0049] In the present embodiment, each metal interconnect 24 in the metal interconnect structure 18 preferably comprises a trench conductor, and the metal interconnects 30 and 32 in the metal interconnect structure 20 preferably comprise via conductors. In addition, each metal interconnect 24, 30 and 32 in each metal interconnect structure 18 and 20 may be embedded in the intermetallic dielectric layers 22 and 28 and / or the stop layer 26 according to a single damascene process or a dual damascene process and electrically connected to each other. For example, each metal interconnect 24, 30, 32 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but not limited thereto. Since the single damascene or dual damascene manufacturing process is a well-known technique in the art, it will not be described in detail here. In addition, in the present embodiment, the metal layer 36 in the metal interconnect 24 preferably comprises copper, the metal layer 36 in the metal interconnects 30 and 32 preferably comprises tungsten, the intermetallic dielectric layers 22 and 28 preferably comprise silicon oxide or an ultra-low dielectric constant dielectric layer, and the stop layer 26 comprises nitrogen doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.
[0050] It is worth noting that Figure 1 As shown, in the present embodiment, when forming metal interconnects 30 and 32 in the intermetal dielectric layer 28, it is preferred to first use photolithography and etching processes to remove part of the intermetal dielectric layer 28 and part of the stop layer 26 to form a contact hole (not shown) to expose the metal interconnect 24 underneath, and then sequentially form at least one barrier layer 34 and a metal layer 36 in the contact hole, wherein the barrier layer 34 is preferably formed on the surface of the intermetal dielectric layer 28 and the sidewalls and bottom of the contact hole, and the metal layer 36 is disposed on the barrier layer 34 and fills the contact hole.
[0051] In the present embodiment, the barrier layer 34 preferably comprises a double-layer structure, wherein the lower barrier layer 82 close to and contacting the intermetallic dielectric layer 28 preferably comprises titanium and the upper barrier layer 84 preferably comprises titanium nitride. However, this order or material combination is not limited thereto. According to other embodiments of the present invention, each barrier layer 82, 84 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN), and the present invention may arbitrarily adjust the material composition of each barrier layer according to the manufacturing process or product requirements, and these variations are all within the scope of the present invention.
[0052] In addition, although the present embodiment takes the double-layer barrier layers 82 and 84 as an example, the present invention is not limited thereto. According to other embodiments of the present invention, the barrier layer 34 may be a single-layer structure disposed between the intermetallic dielectric layer 28 and the metal layer 36, wherein the single-layer barrier layer 34 may also be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN). In other words, if the barrier layer 34 is a single-layer structure, the bottom surface of the barrier layer 34 composed of, for example, titanium nitride preferably contacts the intermetallic dielectric layer 28 or the metal interconnect 24, and the top surface of the barrier layer 34 also composed of titanium nitride contacts the upper metal layer 36 composed of tungsten.
[0053] Then as Figure 2 As shown, a planarization process such as chemical mechanical polishing (CMP) is performed to remove a portion of the metal layer 36 until the top surface of the barrier layer 34 is exposed. In other words, after the planarization process is used to remove a portion of the metal layer 36 and expose the top surface of the barrier layer 34, it is preferably stopped at the surface of the barrier layer 34, so that the top surface of the remaining metal layer 36 is approximately aligned with the top surface of the barrier layer 34, and the top surfaces of both the barrier layer 34 and the metal layer 36 are higher than the top surface of the intermetallic dielectric layer 28. Since the planarization process performed in this stage preferably does not remove any barrier layer 34, after the planarization process is completed, the surfaces of the intermetallic dielectric layer 28 on both sides of the contact hole are still covered with the barrier layer 34, and the top surface of the remaining metal layer 36 in the contact hole is preferably slightly higher than the top surface of the intermetallic dielectric layer 28 and aligned with the top surface of the barrier layer 34.
[0054] like Figure 3 As shown, after the planarization process is completed and in the process of waiting for the subsequent process, the top surface of the metal layer 36 in the contact hole is preferably partially oxidized by contact with the external air to form an interface layer 38 composed of metal oxide. In this embodiment, since the metal layer 36 preferably includes tungsten, the interface layer 38 oxidized by the top surface of the metal layer 36 after contact with oxygen preferably includes tungsten oxide.
[0055] Then as Figure 4As shown, a doping process 40 is performed to implant nitrogen-based dopants into the surface of the metal layer 36, thereby converting the interface layer 38 on the surface of the metal layer 36 into another interface layer 42. In this embodiment, the nitrogen-based dopants may include nitrogen (N2) or ammonia (NH3), and based on the above-mentioned example where the interface layer 38 formed includes tungsten oxide, the interface layer 42 newly formed after the interface layer 38 is implanted with nitrogen-based dopants by the doping process 40 preferably includes tungsten nitride. In this embodiment, the top surface of the interface layer 42 is preferably aligned with the top surface of the barrier layers 34 on both sides, and the thickness of the interface layer 42 may be approximately equal to the sum of the thicknesses of the two barrier layers 82, 84. However, it is not limited thereto. According to other embodiments of the present invention, the thickness of the interface layer 42 may be less than, equal to, or even greater than the sum of the thicknesses of the two barrier layers 82, 84, or less than, equal to, or greater than the thickness of a single barrier layer 34, and these variations are all within the scope of the present invention.
[0056] like Figure 5 As shown, a spin orbit torque (SOT) layer 50 is then formed on the barrier layer 34 and the interface layer 42 surface, an MTJ stack structure 48 is formed on the SOT layer 50, and then a cap layer 60 and a patterned hard mask 62 are formed on the MTJ stack structure 48.
[0057] In the present embodiment, the MTJ stack structure 48 is formed by first sequentially forming a free layer 52, a barrier layer 54, and a pinned layer 56 on the SOT layer 50. First, the free layer 52 can be made of a ferromagnetic material, such as iron, cobalt, nickel, or its alloys such as cobalt-iron-boron (CoFeB), but not limited thereto. The magnetization direction of the free layer 52 will be "freely" changed by the external magnetic field. The barrier layer 54 can be made of an insulating material including an oxide, such as aluminum oxide (AlO x ) or magnesium oxide (MgO), but not limited thereto. The fixed layer 56 can be composed of an antiferromagnetic (AFM) material, such as iron manganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), etc., to fix or limit the magnetic moment direction of the adjacent layer. It should be noted that since this embodiment is preferably used to prepare a spin orbit torque (SOT) MRAM, the free layer 52 is preferably located at the bottom layer and directly contacts the SOT layer 50.
[0058] In addition, the SOT layer 50 is preferably used as a channel of a spin-orbit torque MRAM, so its material may include tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), bismuth selenide (Bi x Se 1-x ) or a combination thereof. In terms of materials, the capping layer 60 of the present embodiment preferably comprises a metal such as tantalum (Ta), and the hard mask 62 preferably comprises a conductive material such as a metal or a metal nitride, wherein the metal may comprise titanium and the metal nitride may comprise titanium nitride. However, it is not limited thereto, and the capping layer 60 or the hard mask 62 may comprise a conductive or dielectric material such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al) or a combination thereof.
[0059] Then as Figure 6 As shown, one or more etching processes are performed with the patterned hard mask 62 as a mask to remove part of the MTJ stack structure 48 and even part of the SOT layer 50 to form the MTJ 58 on the SOT layer 50, and then a cap layer 64 is formed on the hard mask 62, the MTJ 58 and the surface of the SOT layer 50. In the present embodiment, the SOT layer 50 can be etched or not etched during the patterning of the MTJ stack structure 48, so after the MTJ 58 is formed, the top surface of the SOT layer 50 directly below the MTJ 58 can be selected to be flush with the top surface of the SOT layer 50 on both sides of the MTJ 58 or slightly higher than the top surface of the SOT layer 50 on both sides of the MTJ 58, which are all within the scope of the present invention. In addition, the cap layer 64 can include but is not limited to a nitrogen-doped carbide layer (NDC), silicon nitride (SiN) or silicon carbide nitride (SiCN), and more preferably includes silicon nitride.
[0060] Then, an intermetallic dielectric layer 66 is formed on the surface of the cap layer 64, and one or more photolithography and etching processes are performed to remove part of the intermetallic dielectric layer 66 and part of the cap layer 64 to form a contact hole (not shown). Then, a conductive material is filled into the contact hole and a planarization process such as CMP is performed to form a metal interconnect 68 connected to the hard mask 62 below, and another stop layer 74 is formed on the surface of the metal interconnect 68. Like the metal interconnect 24 formed above, the metal interconnect 68 disposed in the intermetallic dielectric layer 66 can be embedded in the intermetallic dielectric layer 66 according to a single damascene process or a dual damascene process. For example, the metal interconnect 68 may further include a barrier layer 70 and a metal layer 72, wherein the barrier layer 70 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN), and the metal layer 72 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto.
[0061] In addition, in the present embodiment, the intermetallic dielectric layer 66 preferably comprises an ultra-low dielectric constant layer, for example, a porous dielectric material such as but not limited to silicon oxycarbide (SiOC), and the stop layer 74 may comprise but not limited to nitrogen-doped carbide layer (NDC), silicon nitride (SiN) or silicon nitride carbide (SiCN) and more preferably comprises silicon nitride, but not limited thereto. Thus, the fabrication of the semiconductor device of one embodiment of the present invention is completed.
[0062] Please refer to Figure 6 , Figure 6 The present invention also discloses a schematic diagram of the structure of an MRAM unit according to an embodiment of the present invention. Figure 6 As shown, the MRAM cell mainly includes an intermetallic dielectric layer 28 disposed on the substrate 12, metal interconnects 30, 32 disposed in the intermetallic dielectric layer 28 and each metal interconnect 30, 32 includes at least one barrier layer 34 disposed in the intermetallic dielectric layer 28 and extending to the surface of the intermetallic dielectric layer 28 and a metal layer 36 disposed on the barrier layer 34, a SOT layer 50 disposed on the metal interconnects 30, 32 and an MTJ 58 disposed on the SOT layer 50.
[0063] From a detailed perspective, the MRAM cell further includes an interface layer 42 disposed on the surface of the metal layer 36, wherein the top surface of the interface layer 42 is preferably aligned with the top surface of the barrier layer 34 so that both top surfaces are higher than the top surface of the intermetallic dielectric layer 28, and the bottom of the SOT layer 50 is preferably in contact with both the barrier layer 34 and the interface layer 42 but not in contact with the intermetallic dielectric layer 28. In this embodiment, the interface layer 42 and the barrier layer 34 preferably include different materials, wherein the interface layer 42 preferably includes a metal nitride such as tungsten nitride and the barrier layer 34 preferably includes a metal nitride such as titanium nitride, but the present invention is not limited thereto.
[0064] Please continue to refer to Figures 7 to 14 , Figures 7 to 14 This is a schematic diagram of a method for manufacturing an MRAM unit according to an embodiment of the present invention. In order to correspond to the above-mentioned implementation, the same components in this embodiment and the above-mentioned embodiment preferably use the same reference numerals. Figure 7 As shown, first compare Figure 1 The manufacturing process provides a substrate 12, such as a substrate 12 made of semiconductor material, wherein the semiconductor material can be selected from a group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region (not shown) are preferably defined on the substrate 12.
[0065] The substrate 12 may include active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 16 covering the substrate 12. More specifically, the substrate 12 may include planar or non-planar (such as fin-structured transistors) MOS transistor devices, wherein the MOS transistor may include a gate structure (such as a metal gate) and transistor devices such as source / drain regions, spacers, epitaxial layers, and contact hole etch stop layers. The interlayer dielectric layer 16 may be disposed on the substrate 12 and cover the MOS transistor, and the interlayer dielectric layer 16 may have a plurality of contact plugs electrically connected to the gate and / or source / drain regions of the MOS transistor. Since the related manufacturing processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they are not further described here.
[0066] Then, metal interconnect structures 18 and 20 are sequentially formed on the interlayer dielectric layer 16 to electrically connect the aforementioned contact plugs, wherein the metal interconnect structure 18 includes an intermetallic dielectric layer 22 and a metal interconnect 24 embedded in the intermetallic dielectric layer 22, and the metal interconnect structure 20 includes a stop layer 26, an intermetallic dielectric layer 28 and a plurality of metal interconnects 30 and 32 embedded in the stop layer 26 and the intermetallic dielectric layer 28.
[0067] As in the above-mentioned embodiment, each metal interconnect 24 in the metal interconnect structure 18 preferably comprises a trench conductor, and the metal interconnects 30 and 32 in the metal interconnect structure 20 preferably comprise via conductors. In addition, each metal interconnect 24, 30 and 32 in each metal interconnect structure 18 and 20 may be embedded in the intermetallic dielectric layer 22 and 28 and / or the stop layer 26 according to a single damascene process or a dual damascene process and electrically connected to each other. For example, each metal interconnect 24, 30, 32 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but not limited thereto. Since the single damascene or dual damascene manufacturing process is a well-known technique in the art, it will not be described in detail here. In addition, in the present embodiment, the metal layer 36 in the metal interconnect 24 preferably comprises copper, the metal layer 36 in the metal interconnects 30 and 32 preferably comprises tungsten, the intermetallic dielectric layers 22 and 28 preferably comprise silicon oxide or an ultra-low dielectric constant dielectric layer, and the stop layer 26 comprises nitrogen doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.
[0068] Then, a spin orbit torque (SOT) layer 50 is formed on the surface of the metal interconnects 30, 32 and the intermetallic dielectric layer 28, wherein the SOT layer 50 is preferably used as a channel of a spin orbit torque MRAM. In the present embodiment, the SOT layer 50 preferably comprises tungsten or platinum, but is not limited thereto. According to other embodiments of the present invention, the SOT layer 50 may comprise other materials such as tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), bismuth selenide (Bi x Se 1-x ) or a combination thereof.
[0069] Then, a doping process 40 is performed to implant nitrogen or oxygen-based dopants into the surface of the SOT layer 50, thereby converting a portion of the surface of the SOT layer 50 into an interface layer 42. In this embodiment, the nitrogen-based dopants may include nitrogen (N2) or ammonia (NH3), and the oxygen-based dopants may include oxygen. Based on the aforementioned example of the SOT layer 50 formed to include tungsten or platinum, the newly formed interface layer 42 after the SOT layer 50 is implanted with nitrogen or oxygen-based dopants through the doping process 40 may include tungsten nitride, platinum nitride, tungsten oxide, or platinum oxide.
[0070] Then Figure 8 As shown, an MTJ stack structure 48 is formed on the SOT layer 50, and then a cap layer 60 and a patterned hard mask 62 are formed on the MTJ stack structure 48. As in the aforementioned embodiment, the method of forming the MTJ stack structure 48 can first sequentially form a free layer 52, a barrier layer 54 and a pinned layer 56 on the SOT layer. First, the free layer 52 can be composed of a ferromagnetic material, such as iron, cobalt, nickel or its alloys such as cobalt-iron-boron (CoFeB), but not limited to this. Among them, the magnetization direction of the free layer 52 will be "freely" changed by the external magnetic field. The barrier layer 54 can be composed of an insulating material containing an oxide, such as aluminum oxide (AlO x ) or magnesium oxide (MgO), but not limited thereto. The fixed layer 56 can be made of an antiferromagnetic (AFM) material, such as iron manganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), etc., to fix or limit the magnetic moment direction of the adjacent layer. It should be noted that since this embodiment is preferably used to prepare a spin orbit torque (SOT) MRAM, the free layer 52 is preferably located at the bottom layer and directly contacts the SOT layer 50.
[0071] In terms of materials, the capping layer 60 preferably includes a metal such as tantalum (Ta), and the hard mask 62 preferably includes a conductive material such as a metal or a metal nitride, wherein the metal may include titanium and the metal nitride may include titanium nitride. However, it is not limited thereto, and the capping layer 60 or the hard mask 62 may include a conductive or dielectric material such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or a combination thereof.
[0072] like Fig. 9As shown, another etching process such as an inductively coupled plasma (ICP) reactive ion etching (RIE) process is then performed to remove a portion of the capping layer 60 and a portion of the MTJ stack structure 48 using the patterned hard mask 62 as a mask to form an MTJ 58, and simultaneously form a metal byproduct 86 next to the MTJ 58. In this embodiment, when the ICP-RIE process is used to pattern the stack structure at this stage, a gas component based on CFH or CHOH may be used, but is not limited thereto.
[0073] like Fig.10 As shown, step (a) is then performed, for example, an oxidation process is performed to convert the metal byproduct 86 into an oxidized byproduct 88. It should be noted that the oxidation process performed in this stage may include an in-situ oxidation process, which may use nitrous oxide (N2O) to convert the metal byproduct 86 into an oxidized byproduct 88. From a structural point of view, the thickness of the oxidized byproduct 88 converted in this stage is preferably slightly higher than Figure 2 The formed metal byproducts 86 and oxidation byproducts 88 are not only disposed on the sidewalls of the MTJ 58 , the sidewalls of the capping layer 60 and the sidewalls of the hard mask 62 , but also preferably cover the top surface of the hard mask 62 and the top surface of the interface layer 42 on both sides of the MTJ 58 .
[0074] like Fig.11 As shown, step (b) is then performed, such as performing an etching process to convert the oxidation byproduct 88 into a damaged layer 90. In detail, the etching process performed at this stage preferably includes an inductively coupled plasma reactive ion etching process (ICP-RIE), which preferably uses a hydrogen (H2)-based etching gas to convert the oxidation byproduct 88 into a damaged layer 90 containing hydrogen atoms. From a structural point of view, the thickness of the damaged layer 90 formed by the conversion at this stage can be slightly lower than the thickness of the aforementioned oxidation byproduct 88.
[0075] like Fig.12 As shown, step (c) is then performed, such as performing an etching process to remove the damaged layer 88. More specifically, the etching process performed at this stage preferably includes an inductively coupled plasma reactive ion etching process (ICP-RIE), which preferably uses an argon (Ar)-based etching gas to completely remove the damaged layer 88. It should be noted that when the ICP-RIE process is used to remove the damaged layer 88 at this stage, the interface layer 42 on both sides of the MTJ 58 can be removed at the same time and the surface of the SOT layer 50 below can be exposed.
[0076] like Fig.13As shown, step (d) is then performed, such as performing an etching process to trim the MTJ 58. In this embodiment, the etching process performed at this stage preferably includes an ion beam etching process (IBE), which preferably uses low energy at a high angle such as angle 92 to trim the sidewall of the MTJ 58.
[0077] Then Fig.14 As shown, the present invention can repeat the above Figures 10 to 13 Steps (a) to (d) are repeated n times or more, wherein n≥1. More specifically, the present invention can be carried out from Fig.10 A series of etching processes are initially performed to convert the metal byproduct 86 into an oxidized byproduct 88, and the oxidized byproduct 88 into a damaged layer 90. The damaged layer 90 is removed, and then a low-energy high-angle IBE etching process is used to trim the sidewall of the MTJ 58. Finally, these four process steps are repeated once or more than once, such as twice, three times, or even four times, to shape the MTJ 58 and form sidewalls of different slopes of the MTJ 58 (not specifically shown in the figure).
[0078] Then, a capping layer 64 and an intermetallic dielectric layer 66 are sequentially formed on the MTJ 58, and then one or more photolithography and etching processes are performed to remove a portion of the intermetallic dielectric layer 66 to form a contact hole (not shown) to expose the hard mask 62. Then, a conductive material is filled into the contact hole and a planarization process such as CMP is performed to form a metal interconnect 68 connected to the hard mask 62 below, and then another stop layer 74 is formed on the surface of the metal interconnect 68. Like the metal interconnect 24 formed above, the metal interconnect 68 disposed in the intermetallic dielectric layer 66 can be embedded in the intermetallic dielectric layer 66 according to a single damascene process or a dual damascene process. For example, the metal interconnect 68 may further include a barrier layer 70 and a metal layer 72, wherein the barrier layer 70 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN), and the metal layer 72 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto.
[0079] In addition, in the present embodiment, the intermetallic dielectric layer 66 preferably comprises an ultra-low dielectric constant layer, for example, a porous dielectric material such as but not limited to silicon oxycarbide (SiOC), and the stop layer 74 may comprise but not limited to nitrogen-doped carbide layer (NDC), silicon nitride (SiN) or silicon nitride carbide (SiCN) and more preferably comprises silicon nitride, but not limited thereto. Thus, the fabrication of the semiconductor device of one embodiment of the present invention is completed.
[0080] Please refer to Fig.14 , Fig.14 The present invention also discloses a schematic diagram of the structure of an MRAM unit according to an embodiment of the present invention. Fig.14 As shown, the MRAM cell mainly includes an intermetallic dielectric layer 28 disposed on the substrate 12 , metal interconnects 30 , 32 disposed in the intermetallic dielectric layer 28 , a SOT layer 50 disposed on the metal interconnects 30 , 32 , an interface layer 42 disposed on the SOT layer 50 , and an MTJ 58 disposed on the interface layer 42 .
[0081] Compared to the aforementioned embodiment in which part of the barrier layer 34 of the metal interconnects 30 and 32 extends on the surface of the intermetallic dielectric layer 28, the barrier layers 34 of the metal interconnects 30 and 32 in the present embodiment are all disposed in the contact holes and the top surface of the barrier layer 34 is not higher than the top surface of the intermetallic dielectric layer 28 on both sides. In addition, the interface layer 42 of the present embodiment is preferably disposed between the SOT layer 50 and the MTJ 58, wherein the interface layer 42 can be the material of the underlying SOT layer 50 plus a nitride or oxide dopant, for example, the interface layer 42 can include but is not limited to tungsten nitride, platinum nitride, tungsten oxide or platinum oxide.
[0082] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: Include: forming an intermetallic dielectric layer on the substrate; forming a contact hole in the intermetal dielectric layer; forming a barrier layer and a metal layer in the contact hole; planarizing the metal layer; forming a spin-orbit torque formula on the barrier layer and the metal layer; and A magnetic tunnel junction is formed on the spin-orbit torque type layer. 2 . The method of claim 1 , further comprising performing a doping process on the barrier layer and the metal layer. The method of claim 2 , wherein the doping process comprises nitrogen. 4 . The method of claim 2 , further comprising performing the doping process to form an interface layer on the metal layer. The method of claim 4 , wherein the interface layer comprises tungsten nitride. The method of claim 1 , wherein the barrier layer comprises titanium nitride.
7. A semiconductor element, characterized in that: Include: An intermetallic dielectric layer is disposed on the substrate; A metal interconnect is disposed in the inter-metal dielectric layer, wherein the metal interconnect comprises: a barrier layer disposed in the intermetal dielectric layer and extending to a surface of the intermetal dielectric layer; and The metal layer is disposed on the barrier layer; A spin-orbit torque type layer is disposed on the barrier layer and the metal layer; and The magnetic tunnel junction is arranged on the spin-orbit torque type layer. 8 . The semiconductor device as claimed in claim 7 , further comprising an interface layer disposed on the metal layer.
9. The semiconductor device as claimed in claim 8, wherein the interface layer comprises tungsten nitride. 10 . The semiconductor device as claimed in claim 8 , wherein a top surface of the interface layer is flush with a top surface of the barrier layer. The semiconductor device as claimed in claim 7 , wherein the barrier layer comprises titanium nitride. 12 . The semiconductor device as claimed in claim 7 , wherein a top surface of the barrier layer is higher than a top surface of the intermetal dielectric layer.
13. A semiconductor element, characterized in that: Include: An intermetallic dielectric layer is disposed on the substrate; A metal interconnect is disposed on the inter-metal dielectric layer; A spin-orbit torque layer is disposed on the metal interconnect; an interface layer disposed on the spin-orbit torque type layer; and The magnetic tunnel junction is arranged on the interface layer. The semiconductor device as claimed in claim 13 , wherein the interface layer comprises metal nitride. The semiconductor device as claimed in claim 13 , wherein the interface layer comprises metal oxide. The semiconductor device as claimed in claim 13 , wherein the interface layer width is smaller than the spin-orbit torque type layer width. 17 . The semiconductor device as claimed in claim 13 , wherein a sidewall of the magnetic tunnel junction is flush with a sidewall of the interface layer.