High-bandwidth flash memory, data reading method and storage chip

Abstract

The present application provides a high-bandwidth flash memory, a data reading method and a memory chip, including: a plurality of memory devices, the memory devices including a memory cell array and a page buffer; the memory cell array including a plurality of memory cell strings, a plurality of bit lines and a plurality of word lines, each memory cell string including a plurality of memory cells, each memory cell corresponding to a bit line and a word line; the page buffer including a plurality of latch sharing circuits; each latch sharing circuit only includes one latch, the latch is connected to at least two bit lines in the memory cell array via a sensing node, and the latch is used to latch the data of at least two bit lines at different time points. In this way, the bandwidth of the memory is improved by arranging a plurality of memory cell arrays, so that it can directly participate in related calculations as a system memory, reducing the manufacturing cost, and at the same time, multiple bit lines share one latch, reducing the area requirement when manufacturing the chip, further reducing the cost.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic digital data processing, and in particular relates to a high-bandwidth flash memory, a data reading method and a storage chip. Background Art

[0002] DDR (Double Data Rate SDRAM) is a memory with high-speed cache characteristics, which is often used as system memory to participate in parallel computing in AI (Artificial Intelligence) models. However, the storage capacity of DDR is relatively small, and usually multiple DDRs are required to meet the capacity required for parallel computing tasks, and the price is relatively expensive.

[0003] Compared with DDR, 3D NAND Flash (a three-dimensional stacked flash memory) has the advantages of large capacity and high parallelism due to its unique three-dimensional storage structure, and its price is relatively low. If 3D NAND Flash can replace DDR as system memory to directly participate in parallel computing in AI models, it will greatly reduce manufacturing costs.

[0004] However, computing chips require huge memory bandwidth when performing parallel calculations in AI models, and the bandwidth of existing 3D NAND Flash is insufficient to meet computing requirements. Summary of the invention

[0005] The embodiments of the present application provide a high-bandwidth flash memory, a data reading method, and a storage chip, in order to solve the problem of insufficient bandwidth of existing flash memories, so that the flash memories can directly participate in parallel computing in AI models as system memory, thereby reducing manufacturing costs.

[0006] In a first aspect, an embodiment of the present application provides a high-bandwidth flash memory, comprising: a plurality of memory devices, wherein the memory devices include a memory cell array and a page buffer; wherein:

[0007] The memory cell array comprises a plurality of memory cell strings, a plurality of bit lines and a plurality of word lines, each memory cell string comprises a plurality of memory cells, each memory cell corresponds to a bit line and a word line; and

[0008] The page buffer includes a plurality of latch sharing circuits, wherein each latch sharing circuit includes only one latch, the latch is connected to at least two bit lines in the memory cell array via a sensing node, and the latch is used to latch data of the at least two bit lines at different time points.

[0009] Furthermore, the latch sharing circuit includes a pre-charging circuit, the pre-charging circuit is connected to the at least two bit lines, and the pre-charging circuit is used to generate a pre-charging voltage in a pre-charging phase to charge the at least two bit lines.

[0010] Furthermore, the pre-charging circuit includes only one charging control switch, the charging control switch is connected to the at least two bit lines, and the charging control switch is used to be turned on in the pre-charging stage to charge the at least two bit lines simultaneously.

[0011] Furthermore, the latch sharing circuit includes at least two control switches corresponding to the at least two bit lines; wherein the first end of each control switch is connected to the corresponding bit line, and the second end is connected to the latch via the sensing node; the at least two control switches are used to be turned on at different time points so that the latch latches the data of the at least two bit lines at different time points.

[0012] Furthermore, the latch sharing circuit includes at least two protection switches corresponding to the at least two bit lines; wherein the first end of each protection switch is connected to the corresponding bit line, and the second end is connected to the control switch on the corresponding bit line; the at least two protection switches are used to protect the low-voltage elements in the high-bandwidth flash memory when the potential of the at least two bit lines is high.

[0013] Furthermore, the latch sharing circuit is arranged corresponding to the word line.

[0014] In a second aspect, an embodiment of the present application provides a method for reading data from a high-bandwidth flash memory, the method comprising:

[0015] Determining a target word line and a plurality of bit lines corresponding to a target read operation, wherein the plurality of bit lines are connected to latches in a target latch sharing circuit in a page buffer via sensing nodes, wherein the target latch sharing circuit includes only one latch;

[0016] Determine at least two target bit lines from the plurality of bit lines, the target bit lines being bit lines corresponding to the target memory cells selected by the target read operation;

[0017] The data of the at least two target bit lines are latched into the latch at different time points.

[0018] Furthermore, determining at least two target bit lines from the multiple bit lines includes: turning on the charging control switch in the pre-charging stage to load the pre-charging voltage to the multiple bit lines; turning off the charging control switch to store the pre-charging voltage in the multiple bit lines through the bit line capacitors of the multiple bit lines; and determining the at least two target bit lines according to the voltage states of the multiple bit lines.

[0019] Furthermore, latching the data of the at least two target bit lines into the latch at different time points includes: performing the following operations on the at least two target bit lines in sequence at different time points: turning on the control switch corresponding to the target bit line currently being processed so that the target bit line currently being processed is coupled to the latch; latching the data of the target bit line currently being processed into the latch; and repeating the above operations until all the at least two target bit lines are processed.

[0020] In a third aspect, an embodiment of the present application provides a memory chip, including:

[0021] The high-bandwidth flash memory as described in the first aspect of the embodiment of the present application;

[0022] A controller is connected to the high-bandwidth flash memory, and the controller is used to execute the method described in the second aspect of the embodiment of the present application.

[0023] It can be seen that the high-bandwidth flash memory involved in the embodiment of the present application includes multiple memory devices, each of which includes a memory cell array and a page buffer; wherein the memory cell array includes multiple memory cell strings, multiple bit lines and multiple word lines, each memory cell string includes multiple memory cells, and each memory cell corresponds to a bit line and a word line; in this way, by arranging multiple memory cell arrays, the number of bit lines in the memory is increased, thereby improving the bandwidth of the memory, so that it can meet the bandwidth requirements of parallel computing. At the same time, the page buffer includes multiple latch sharing circuits, each latch sharing circuit only includes one latch, and the latch is connected to at least two bit lines in the memory cell array via a sensing node to latch the data of at least two bit lines at different time points; in this way, multiple bit lines can share one latch, which greatly reduces the number of latches required, thereby reducing the number of electronic components used in the page buffer, solving the problem that a large amount of chip area is required to arrange the page buffer due to the increase in the number of memory cell arrays and bit lines, and further reducing the cost. It can be seen that the high-bandwidth flash memory involved in the embodiments of the present application overcomes the problem of insufficient bandwidth of the existing 3D NAND Flash, enabling it to directly participate in parallel computing in the AI ​​model as system memory, greatly reducing manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 is a structural block diagram of a high-bandwidth flash memory provided by an embodiment of the present application;

[0026] Figure 2 is a simplified three-dimensional structural diagram of a high-bandwidth flash memory provided in an embodiment of the present application;

[0027] Figure 3 is an example diagram of a first latch sharing circuit provided in an embodiment of the present application;

[0028] Figure 4 is an example diagram of a second latch sharing circuit provided in an embodiment of the present application;

[0029] Figure 5 is an example diagram of a third latch sharing circuit provided in an embodiment of the present application;

[0030] Figure 6 is an example diagram of a fourth latch sharing circuit provided in an embodiment of the present application;

[0031] Figure 7 is an example diagram of a fifth latch sharing circuit provided in an embodiment of the present application;

[0032] Figure 8 It is a flow chart of a method for reading data from a high-bandwidth flash memory provided by an embodiment of the present application;

[0033] Fig. 9 is a waveform diagram of a read operation provided in an embodiment of the present application;

[0034] Fig.10 It is a structural block diagram of a storage chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0037] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0038] The following introduces relevant terms involved in the embodiments of the present application.

[0039] CMOS die: refers to a single silicon chip manufactured using CMOS technology, usually containing thousands to millions of transistors. CMOS (Complementary Metal-Oxide-Semiconductor) is a technology used to manufacture semiconductor devices, especially in digital integrated circuits. Its main features are low power consumption and high density. It is widely used in computer chips, microcontrollers and other digital electronic devices.

[0040] SeDRAM (Stacked Embedded DRAM): is an embedded DRAM solution that uses nano-level interconnection technology to vertically stack DRAM memory wafers and logic wafers and directly interconnect them. This technology can achieve ultra-large bandwidth, ultra-low power consumption, and ultra-large capacity embedded memory.

[0041] 3D NAND Flash is a non-volatile memory that increases storage capacity by vertically stacking memory particles. It has great parallelism due to its unique three-dimensional storage structure. However, at present, due to insufficient bandwidth, flash memory can only be used to store persistent data (such as model parameters) in parallel computing of AI models, while the main memory that directly interacts with the computing chip needs to have sufficient memory bandwidth. Therefore, in the existing parallel computing architecture, DDR is still used as the main memory to directly participate in computing, but DDR is relatively expensive and costly.

[0042] After research and experiments, the inventor of this application found that in the application scenario of parallel computing of AI models, the bandwidth of the existing 3D NAND Flash can be increased by modifying it, so that it can meet the bandwidth capacity required by the parallel computing tasks of the AI ​​model, and then it can replace DDR as the system main memory to directly interact with the computing chip for data and participate in the calculation, greatly reducing the cost. Based on this, the embodiment of this application provides a high-bandwidth flash memory, a data reading method and a storage chip.

[0043] Figure 1 is a structural block diagram of a high-bandwidth flash memory provided by an embodiment of the present application. Figure 1 As shown, the high bandwidth flash memory 100 includes a plurality of memory devices 10 , each of which includes a memory cell array 11 and a page buffer 12 .

[0044] The memory cell array 11 includes a plurality of memory cell strings (110a-110c), a plurality of bit lines (BL[0]-BL[m-1]) and a plurality of word lines (WL[0]-WL[n-1]), each memory cell string includes a plurality of memory cells (such as 1101c[0]-1101c[n-1] in the memory cell string 110c), and each memory cell corresponds to a bit line and a word line. In particular, the type of the memory cell in the embodiment of the present application is a single-level cell, that is, each memory cell stores only one bit of information.

[0045] Among them, the page buffer 12 includes multiple latch sharing circuits 120 (only one is shown in the figure), and the latch sharing circuit 120 only includes one latch 121. The latch 121 is connected to at least two bit lines in the memory cell array 11 via a sensing node (not shown in the figure), such as the first bit line BL[0] and the second bit line BL[1]. The latch 121 is used to latch the data of the at least two bit lines at different time points. In this way, multiple bit lines can share the same latch, reducing the number of latches in the page buffer 12, reducing the chip area requirement when manufacturing the chip, and further reducing the cost.

[0046] Among them, Figure 2 As shown, the memory cell array 11 is a three-dimensional storage structure, and each page buffer 12 is arranged corresponding to its corresponding memory cell array 11, and can be arranged below the memory cell array 11 and connected through a bit line, thereby saving silicon area. Among them, multiple page buffers 12 can be concentrated on the surface of the CMOS die, and the multiple page buffers 12 as a whole constitute the page buffer of the high-bandwidth flash memory 100.

[0047] It can be understood that the high-bandwidth flash memory 100 may also include other elements not shown in the figure, such as a string select line (SSL), a ground select line (GSL) and a row decoder, etc. The row decoder can be connected to the memory cell array 11 through the above-mentioned multiple word lines WL[0]~WL[n-1], the above-mentioned string select line SSL and the ground select line GSL to implement the read operation of the high-bandwidth flash memory.

[0048] Furthermore, in actual design, the size and number of memory cell arrays are related to the page buffer size and the technology node of NAND Flash, where the technology node of NAND Flash refers to the size of the memory cell, that is, the width of the floating gate MOS transistor. For example, assuming that the technology node is 36nm and the page buffer size is 12KB, 204 memory cell arrays are required at this time. Among them, the size of each memory cell array is 7mm wide and 41um deep, each memory cell array includes 572 memory blocks, and each memory block contains 192 pages. It should be noted that the above examples are only used as auxiliary explanations of the embodiments of the present application and do not constitute any limitation to the present application.

[0049] It can be seen that in the embodiments of the present application, the number of bit lines in the memory is increased by arranging multiple memory cell arrays, thereby improving the bandwidth of the memory so that it can meet the bandwidth requirements of parallel computing. At the same time, multiple bit lines share one latch, which greatly reduces the number of latches required, thereby reducing the number of electronic components used in the page buffer, solving the problem of requiring a large amount of chip area to arrange the page buffer due to the increase in the number of memory cell arrays and bit lines, further reducing costs, and enabling high-bandwidth flash memory to directly participate in parallel computing in the AI ​​model as system memory, thereby reducing manufacturing costs.

[0050] In a possible example, the latch sharing circuit includes a precharge circuit, which is connected to the at least two bit lines via the sensing node, and the precharge circuit is used to generate a precharge voltage in a precharge phase to charge the at least two bit lines.

[0051] like Figure 3As shown, the latch sharing circuit 120 includes a precharge circuit 122, which is connected to the first bit line BL[0] and the second bit line BL[1]. The precharge circuit 122 is used to generate a precharge voltage in the precharge stage to charge the first bit line BL[0] and the second bit line BL[1], so that the precharge voltage is loaded on the first bit line BL[0] and the second bit line BL[1], and the subsequent data exchange process is implemented based on the bit line voltage. Among them, the first bit line BL[0] is coupled to the first storage cell string 110a, and the second bit line BL[1] is coupled to the second storage cell string 110b. The two bit lines are connected to the latch 121 via the sensing node SO to latch the data of the first bit line BL[0] and the second bit line BL[1] into the latch 121 at different time points.

[0052] In a possible example, the pre-charging circuit includes only one charging control switch, the charging control switch is connected to the at least two bit lines, and the charging control switch is configured to be turned on in a pre-charging phase to charge the at least two bit lines simultaneously.

[0053] like Figure 4 As shown, the pre-charge circuit 122 includes only one charge control switch PCH, one end of the charge control switch PCH is connected to the VDD (Power Supply Voltage, positive power supply voltage) end, and the other end is connected to the first bit line BL[0] and the second bit line BL[1]. The charge control switch PCH is used to be turned on in the pre-charge stage to charge the first bit line BL[0] and the second bit line BL[1] at the same time, so that the pre-charge voltage is loaded on the first bit line BL[0] and the second bit line BL[1].

[0054] Optionally, the precharge circuit 122 may also be configured to include at least two charge control switches corresponding to at least two bit lines, each charge control switch being respectively configured to be turned on during the precharge phase to load the precharge voltage to the corresponding bit line, which is not a sole limitation herein.

[0055] In one possible example, the latch sharing circuit includes at least two control switches corresponding to the at least two bit lines; wherein the first end of each control switch is connected to the corresponding bit line, and the second end is connected to the latch via the sensing node; the at least two control switches are used to be turned on at different time points so that the latch latches the data of the at least two bit lines at different time points.

[0056] like Figure 5As shown, the latch sharing circuit 120 includes a first control switch SEL0 corresponding to the first bit line BL[0] and a second control switch SEL1 corresponding to the second bit line BL[1]. The first end of the first control switch SEL0 is connected to the first bit line BL[0], and the second end is connected to the latch 121 via the sensing node SO; the first end of the second control switch SEL1 is connected to the second bit line BL[1], and the second end is connected to the latch 121 via the sensing node SO. The first control switch SEL0 and the second control switch SEL1 are turned on at different time points, so that the latch 121 latches the data of the first bit line BL[0] and the second bit line BL[1] at different time points.

[0057] In one possible example, the latch sharing circuit includes at least two protection switches corresponding to the at least two bit lines; wherein the first end of each protection switch is connected to the corresponding bit line, and the second end is connected to the control switch on the corresponding bit line; the at least two protection switches are used to protect the low-voltage elements in the high-bandwidth flash memory when the potential of the at least two bit lines is high.

[0058] like Figure 6 As shown, the latch sharing circuit includes a first protection switch HV0 corresponding to the first bit line BL[0] and a second protection switch HV1 corresponding to the second bit line BL[1]. The first end of the first protection switch HV0 is connected to the first bit line BL[0], and the second end is connected to the first control switch SEL0; the first end of the second protection switch HV1 is connected to the second bit line BL[1], and the second end is connected to the second control switch SEL1. The first protection switch HV0 and the second protection switch HV1 are specifically implemented as high-voltage MOS tubes. The first protection switch HV0 is used to protect the low-voltage components in the high-bandwidth flash memory when the potential of the first bit line BL[0] is high, and the second protection switch HV1 is used to protect the low-voltage components in the high-bandwidth flash memory when the potential of the second bit line BL[1] is high. For example, it can reach 20V when erasing, and a voltage will be applied to make it fully conductive when reading, thereby improving the safety of the circuit.

[0059] In a possible example, the latch sharing circuit is arranged corresponding to the word line.

[0060] The correspondence setting includes a one-to-one correspondence between the number of latch sharing circuits and the number of word lines, that is, a latch sharing circuit is set for each word line, so that all bit lines corresponding to each word line share a latch, reducing the number of latches required.

[0061] Furthermore, if Figure 7 As shown, C BL[0] and C BL[1]represents the bit line capacitance of the first bit line BL[0] and the second bit line BL[1], respectively, C SO represents the sensing capacitance of the sensing node SO. In this example, the bit line capacitance C BL and the sensing capacitor C SO are key parameters that affect the sensing performance of the latch sharing circuit 120, and their ratio determines the working efficiency and speed of the latch sharing circuit 120. In a possible example, the capacitance value of the bit line capacitor of the at least two bit lines is approximately 2000 times the capacitance value of the sensing capacitor corresponding to the sensing node. For example, C BL :C SO =2pF:fF. The bit line capacitance and the sensing capacitance may specifically refer to parasitic capacitors. In some implementations, the parasitic capacitors may be replaced by other normal capacitors.

[0062] A method for reading data from a high-bandwidth flash memory provided by an embodiment of the present application is described below.

[0063] See also Figure 8 , Figure 8 FIG. 1 is a flow chart of a method for reading data from a high-bandwidth flash memory provided in an embodiment of the present application. Figure 8 As shown, the method includes:

[0064] S801, determining a target word line and a plurality of bit lines corresponding to a target read operation.

[0065] The plurality of bit lines are connected to latches in a target latch sharing circuit in a page buffer via a sensing node, and the target latch sharing circuit includes only one latch.

[0066] The read operation is performed in units of page data, that is, each read operation reads a page of data. Specifically, the information indicated by the target read operation includes address information, and the row decoder in the high-bandwidth flash memory responds to the address information to determine the storage block selected by the target read operation and the target word line selected in the storage block. The page data to be read is the data set stored in multiple selected target storage cells among the multiple storage cells corresponding to the target word line.

[0067] S802, determining at least two target bit lines from the plurality of bit lines.

[0068] The target bit line refers to a bit line corresponding to a target storage unit selected by the target read operation.

[0069] In one possible example, determining at least two target bit lines from the multiple bit lines includes: turning on a charging control switch in a pre-charging phase to load a pre-charging voltage to the multiple bit lines; turning off the charging control switch to store the pre-charging voltage in the multiple bit lines through the bit line capacitors of the multiple bit lines; and determining the at least two target bit lines based on the voltage states of the multiple bit lines.

[0070] Among them, after the precharge voltage is loaded to the bit line by turning on the charge control switch in the precharge stage, the charge control switch is turned off so that the precharge voltage is maintained by the bit line capacitor on each bit line. After a period of time, the selected memory cell, i.e., the target memory cell, is in the on state, and conducts current to discharge its corresponding bit line, i.e., the target bit line, to a predetermined voltage, while the unselected memory cell is in the off state, and its corresponding bit line is maintained at the precharge voltage because the memory cell is disconnected. Therefore, the target bit line corresponding to the target memory cell and other bit lines are in different voltage states at this time, so that the target bit line can be determined based on the voltage state of the bit line.

[0071] S803, latching the data of the at least two target bit lines into the latch at different time points.

[0072] The data of each target bit line is determined by a sensing logic circuit, and the data is binary data representing a logic value, which is expressed as "0" or "1", depending on the charge state of the target memory cell. Exemplarily, "0" represents that there is a charge in the target memory cell on the target bit line, and "1" represents that there is no charge in the target memory cell on the target bit line. In this example, the above-mentioned sensing logic circuit is specifically expressed as the latch sharing circuit. The target latch sharing circuit can specifically refer to the latch sharing circuit corresponding to the target word line.

[0073] In one possible example, latching the data of the at least two target bit lines into the latch at different time points includes: performing the following operations on the at least two target bit lines in sequence at different time points: turning on the control switch corresponding to the target bit line currently being processed so that the target bit line currently being processed is coupled to the latch; latching the data of the target bit line currently being processed into the latch; and repeating the above operations until all the at least two target bit lines are processed.

[0074] Here, taking the first bit line BL[0] as an example, the first control switch SEL0 corresponding to the first bit line BL[0] is turned on, so that the first bit line BL[0] is coupled to the latch via the sensing node SO. At this time, since the first bit line BL[0] has a much larger capacitance than the sensing node SO (for example, about 2000 times), the sensing node SO can be discharged in a very short time, thereby activating the latch signal to latch the data of the first bit line BL[0] into the latch to determine the logic value of the first bit line BL[0].

[0075] It can be seen that in the embodiment of the present application, the target word line and multiple bit lines corresponding to the target read operation are first determined, then at least two target bit lines are determined from the multiple bit lines, and then the data of the at least two target bit lines are latched into the latch at different time points. In this way, after the target word line is determined, the latch can sequentially latch the data of the target bit line corresponding to the selected target storage unit at different time points by sharing the latch with multiple bit lines, which not only reduces the number of latches required in the page buffer and reduces the cost, but also can improve the efficiency of data reading to a certain extent.

[0076] Fig. 9 is a waveform diagram of a read operation provided by an embodiment of the present application. Fig. 9As shown, in the pre-charging stage (T0 to T1 stage), the charging control switch PCH, the first control switch SEL0, and the second control switch SEL1 are all in the on state, and the pre-charging voltage is loaded to the first bit line BL[0] and the second bit line BL[1]. At time T1, the charging control switch PCH, the first control switch SEL0, and the second control switch SEL1 are turned off. At this time, if the bit line is the target bit line, that is, the storage unit on the bit line is in the on state, the bit line will be discharged to a predetermined voltage, as shown in the falling section waveform of the first bit line BL[0] and the second bit line BL[1] in the T1 to T2 stage. In this example, the predetermined voltage is, for example, 0V; if the bit line is not the target bit line, that is, the storage unit on the bit line is in the off state, the bit line will remain at the pre-charging voltage, as shown in the horizontal section waveform of the first bit line BL[0] and the second bit line BL[1] in the T1 to T2 stage. At time T2, the target bit line is discharged. At this time, the charge control switch PCH and the first control switch SEL0 are turned on, so that the first bit line BL[0] is coupled to the latch via the sensing node. At this time, the sensing node SO is discharged in a very short time, thereby activating the latch signal to latch the data of the first bit line BL[0] into the latch (LAT is high level). After the reading is completed (time T3), the charge control switch PCH and the first control switch SEL0 are turned off. At time T4, the charge control switch PCH and the second control switch SEL1 are turned on, so that the second bit line BL[1] is coupled to the latch via the sensing node. At this time, the sensing node SO is discharged in a very short time, thereby activating the latch signal to latch the data of the second bit line BL[1] into the latch (LAT is high level). After the reading is completed (time T5), the charge control switch PCH and the second control switch SEL1 are turned off. In this way, it is realized that a latch is shared by multiple bit lines to perform sensing logic, the number of latches required in the page buffer is reduced, and the chip manufacturing cost is reduced.

[0077] Fig.10 is a structural block diagram of a memory chip provided in an embodiment of the present application. Fig.10 As shown, the memory chip 1000 includes a high-bandwidth flash memory 100 and a controller 101. The controller 101 is connected to the high-bandwidth flash memory 100 and is used to execute the data reading method involved in the above embodiment.

[0078] It should be noted that the high-bandwidth flash memory involved in the embodiments of the present application is intended to replace DDR as the system main memory in the parallel computing of the AI ​​model to directly participate in the computing to reduce the manufacturing cost, but in actual design and manufacturing, DRAM is not completely eliminated. For example, in some embodiments, SeDRAM is used to store intermediate parameters generated by the data processing process, such as the context generated by a large language model, which is specifically manifested as a KV cache (key-value cache).

[0079] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions without departing from the spirit and scope of the present application, and can make various changes and modifications, including the combination of the above-mentioned different functions and implementation steps, including software and hardware implementation methods, all of which are within the scope of protection of the present application.

Claims

1. A high bandwidth flash memory, characterized in that: include: A plurality of memory devices, each of which comprises a memory cell array and a page buffer; wherein, The memory cell array comprises a plurality of memory cell strings, a plurality of bit lines and a plurality of word lines, each memory cell string comprises a plurality of memory cells, each memory cell corresponds to a bit line and a word line; and The page buffer comprises a plurality of latch sharing circuits; wherein each latch sharing circuit comprises only one latch, the latch being connected to at least two bit lines in the memory cell array via a sensing node, and the latch being used to latch data of the at least two bit lines at different time points; The capacitance value of the bit line capacitors of the at least two bit lines is 2000 times the capacitance value of the sensing capacitor corresponding to the sensing node.

2. The high bandwidth flash memory according to claim 1, characterized in that: The latch sharing circuit includes a precharge circuit, which is connected to the at least two bit lines and is used to generate a precharge voltage in a precharge phase to charge the at least two bit lines.

3. The high bandwidth flash memory according to claim 2, characterized in that: The pre-charging circuit includes only one charging control switch, which is connected to the at least two bit lines. The charging control switch is used to be turned on in the pre-charging stage to charge the at least two bit lines simultaneously.

4. The high bandwidth flash memory according to claim 3, characterized in that: The latch sharing circuit includes at least two control switches corresponding to the at least two bit lines; wherein a first end of each control switch is connected to the corresponding bit line, and a second end is connected to the latch via the sensing node; the at least two control switches are used to be turned on at different time points so that the latch latches the data of the at least two bit lines at different time points.

5. The high bandwidth flash memory according to claim 4, characterized in that: The latch sharing circuit includes at least two protection switches corresponding to the at least two bit lines; wherein the first end of each protection switch is connected to the corresponding bit line, and the second end is connected to the control switch on the corresponding bit line; the at least two protection switches are used to protect the low-voltage elements in the high-bandwidth flash memory when the potential of the at least two bit lines is high.

6. The high bandwidth flash memory according to any one of claims 1 to 5, characterized in that: The latch sharing circuit is arranged corresponding to the word line.

7. A method for reading data from a high-bandwidth flash memory, characterized in that: The method comprises: Determining a target word line and a plurality of bit lines corresponding to a target read operation, wherein the plurality of bit lines are connected to latches in a target latch sharing circuit in a page buffer via sensing nodes, wherein the target latch sharing circuit includes only one latch; Determine at least two target bit lines from the plurality of bit lines, the target bit lines being bit lines corresponding to the target memory cells selected by the target read operation; latching the data of the at least two target bit lines into the latch at different time points; The capacitance value of the bit line capacitors of the at least two target bit lines is 2000 times the capacitance value of the sensing capacitor corresponding to the sensing node.

8. The method according to claim 7, characterized in that The step of determining at least two target bit lines from the plurality of bit lines comprises: Turning on the charge control switch in the precharge phase to load the precharge voltage to the plurality of bit lines; Turning off the charge control switch to store the precharge voltage in the plurality of bit lines through the bit line capacitors of the plurality of bit lines; The at least two target bit lines are determined according to voltage states of the plurality of bit lines.

9. The method according to claim 8, characterized in that The latching the data of the at least two target bit lines into the latch at different time points comprises: The following operations are performed on the at least two target bit lines in sequence at different time points: Turning on a control switch corresponding to a target bit line currently being processed so that the target bit line currently being processed is coupled to the latch; latching the data of the currently processed target bit line into the latch; The above operations are repeatedly performed until the at least two target bit lines are completely processed.

10. A memory chip, characterized in that: include: The high bandwidth flash memory as claimed in any one of claims 1 to 6; A controller is connected to the high-bandwidth flash memory, and the controller is used to execute the method according to any one of claims 7 to 9.

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