Optimization method and device for test excitation code, equipment and medium

Abstract

The invention discloses a test excitation code optimization method and device, equipment and a medium. Relates to the technical field of chip verification, and the method comprises the following steps: obtaining constraint expressions belonging to the same action range from a test excitation code to be input into a chip verification environment, identifying target constraint expressions to be optimized according to contained constraint quantities, sorting the target constraint expressions, respectively traversing each target constraint expression according to a sorting result, and determining the target constraint expressions to be optimized according to the sorted target constraint expressions; gradually determining a target value range of a target constrained random variable in each target constraint expression, and recoding the target value range of each target constrained random variable according to the data width of each target constrained random variable and a set data width unit; and adding the recoding result into a test excitation code. The target value range of the target constrained random variable is gradually reduced in sequence and recoding is carried out, so that the scale of inputting a constraint solving problem into a solving engine is reduced, and the performance of a constraint solver is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to an optimization method, device, equipment and medium for testing stimulus codes. Background Art

[0002] Software simulation tools can be used to simulate electronic systems and circuit behavior, and simulate circuit logic behavior, including signal transmission, logical operations, and timing control, to verify whether the functions and timing constraints of chip circuits are correct.

[0003] As the scale and complexity of problems increase, the performance of constraint solvers based on SAT (Boolean Satisfiability) solver engines decreases due to the expansion of search space. In the prior art, the performance of constraint solvers based on SAT solver engines can be improved by improving the SAT algorithm. Although this can directly improve the solver's computational efficiency and ability to handle complex problems, it will increase the complexity of algorithm implementation, over-optimize specific types of problems, and reduce the risk of generalization when solving new or unforeseen problems. Summary of the invention

[0004] The present invention provides a method, device, equipment and medium for optimizing a test stimulus code to solve the problem of performance degradation of a constraint solver based on a SAT solving engine due to the excessive scale of the constraint problem in a large-scale constraint scenario.

[0005] According to one aspect of an embodiment of the present invention, a method for optimizing a test stimulus code is provided, comprising:

[0006] Obtain each constraint expression belonging to the same scope in the test stimulus code to be input into the chip verification environment; wherein each constraint expression contains a constrained random variable and a constraint quantity for constraining the value range of the constrained random variable, and the constraint quantity is a constant or other random variable; according to the constraint quantity contained in the constraint expression, identify the target constraint expression to be optimized in each constraint expression, and sort each target constraint expression; traverse each target constraint expression according to the sorting result, and gradually determine the target value range of the target constrained random variable in each target constraint expression during the traversal process, wherein the target value range only contains constants; according to the data width of each target constrained random variable, re-encode the target value range of each target constrained random variable according to the set data width unit, and add the re-encoded result to the test stimulus code.

[0007] According to another aspect of an embodiment of the present invention, there is also provided a device for optimizing a test stimulus code, comprising:

[0008] A constraint expression acquisition module is used to obtain each constraint expression belonging to the same scope in the test stimulus code to be input into the chip verification environment; a target constraint expression sorting module is used to identify the target constraint expression to be optimized in each constraint expression according to the constraint amount contained in the constraint expression, and sort the target constraint expressions; a target value range determination module is used to traverse each target constraint expression according to the sorting result, and gradually determine the target value range of the target constrained random variable in each target constraint expression during the traversal process; a target value range recoding module is used to recode the target value range of each target constrained random variable according to the data width of each target constrained random variable according to the set data width unit, and add the recoded result to the test stimulus code.

[0009] According to another aspect of an embodiment of the present invention, an electronic device is provided, the electronic device comprising:

[0010] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the test stimulus code optimization method described in any embodiment of the present invention.

[0011] According to another aspect of an embodiment of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the test stimulus code optimization method described in any embodiment of the present invention when executed.

[0012] According to another aspect of an embodiment of the present invention, a computer program product is provided, comprising computer instructions, wherein when the computer instructions are executed by a processor, the steps of the method described in any embodiment of the present invention are implemented.

[0013] The technical solution of the embodiment of the present invention obtains each constraint expression belonging to the same scope in the test stimulus code to be input into the chip verification environment, identifies the target constraint expression to be optimized according to the constraint amount contained and sorts it, traverses each target constraint expression according to the sorting result, and gradually determines the target value range of the target constrained random variable in each target constraint expression, recodes the target value range of each target constrained random variable according to the data width of each target constrained random variable and the set data width unit, and adds the recoded result to the test stimulus code. By gradually narrowing the target value range of the target constrained random variable and recoding it in sequence, the test stimulus code is optimized, the scale of the constraint solving problem input solving engine is reduced, and the performance of the constraint solver is improved.

[0014] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0016] Figure 1 is a flow chart of a method for optimizing a test stimulus code provided according to Embodiment 1 of the present invention;

[0017] Figure 2 is an example diagram of an abstract syntax tree applicable to an embodiment of the present invention;

[0018] Figure 3 is a schematic diagram of the structure of a test stimulus code optimization device provided according to Embodiment 2 of the present invention;

[0019] Figure 4 It is a structural schematic diagram of an electronic device for implementing the test stimulus code optimization method of an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0022] Embodiment 1

[0023] Figure 1 This is a flow chart of a test stimulus code optimization method provided in the first embodiment of the present invention. This embodiment can be applied to the case of reducing the scale of the constraint solving problem of the input solving engine during the chip verification stage. The method can be executed by a test stimulus code optimization device, which can be implemented in the form of hardware and / or software and can generally be configured in an electronic device. Figure 1 As shown, the method includes:

[0024] S110. Obtain each constraint expression belonging to the same scope in the test stimulus code to be input into the chip verification environment.

[0025] In the embodiment of the present invention, the test stimulus code can be specifically understood as a code for simulating the input conditions of a chip or circuit design. These codes are used to generate signals in a simulation environment to verify the correctness of the design. The test stimulus may include the generation of clock, reset, data input and control signals. The same scope can be specifically understood as the context range that a variable or function can access in a programming language. In SystemVerilog, the scope can be local (such as a variable defined inside a function or module) or global (such as a variable defined outside a module). Variables within the same scope can access each other, while variables in different scopes need to interact in a specific way (such as parameter passing or global variables). Constraint expressions can be specifically understood as being used in SystemVerilog to define the legal value range of variables, which are used to generate random variables to ensure that the generated test data meets specific conditions. Constraint expressions can be simple conditional statements or complex combinations of logical statements used to control the generation process of random variables.

[0026] S120. According to the constraint quantities included in the constraint expressions, identify the target constraint expressions to be optimized in each constraint expression, and sort the target constraint expressions.

[0027] In the embodiment of the present invention, the constraint quantity can be specifically understood as the quantity used to limit the value of the random variable in the constraint expression, which can be a constant or other random variables. The constraint expression can be specifically understood as a logical expression used to limit the value of the random variable, which can be an expression containing relational operators (such as <, <=, ==, >= or >), logical operators (such as &&, || or!), set membership operators (such as inside) and distribution operators (such as dist). Through these expressions, complex relationships and conditions between random variables can be defined.

[0028] In the embodiment of the present invention, the constraint expression to be optimized can be specifically understood as an expression involving an indefinite number of solutions of a random variable (for example, 3≤x≤5; 10≤y≤20; x≤z≤y, z has an indefinite number of solutions), and at least two expressions that limit the value range of a random variable (for example, 2≤z≤10; 3≤z≤6). The purpose of optimization is to find a solution that satisfies all constraints, and to reduce the range of values ​​of random variables by adjusting the constraint expression to reduce the scale of the constraint problem. Sorting the constraint expression can be specifically understood as defining a processing priority among multiple constraints, wherein the processing priority of the constraint can be determined according to the dependency between the constraints, the complexity of the constraints and the test coverage, that is, if it is judged from the constraint quantity that some constraints depend on the results of other constraints, then the dependent constraints should be given a higher priority; give priority to satisfying the constraints that can improve the test coverage; more complex constraints require more computing resources, so they can be given a higher priority to reduce the solution time. In SystemVerilog, the solve before constraint can be used to specify the solution order of random variables. For example, solve xbefore y means solving the random variable x before solving the random variable y. When the value range of the random variable y depends on the random variable x, this can affect the order in which the random variables are solved. By first determining the value range of the dependent random variable x, the value range of the target random variable y can be narrowed, making the variable constraints easier to meet.

[0029] S130, traversing each target constraint expression respectively according to the sorting result, and gradually determining the target value range of the target constrained random variable in each target constraint expression during the traversal process.

[0030] Specifically, after assigning a priority to each target constraint expression and sorting them, each target constraint expression is traversed from high to low according to the priority. For each random variable, its possible value range is gradually determined by applying the constraint expression. For example, if there are multiple constraint expressions for the same random variable to restrict its value range, the value range of the random variable can be streamlined by removing redundant constraints and merging similar constraints, while ensuring that there is no conflict between the constraints, thereby reducing the scale of the constraint solving problem. Among them, removing redundant constraints may include: if two constraints restrict the same variable range and these ranges overlap, then only one stricter constraint can be retained; if some constraints will never be satisfied or are irrelevant to the possible value range of the variable, these constraints should be deleted. Merging similar constraints may include: if two constraints cover the same range, or if the merged constraint can accurately cover all overlapping parts and will not introduce new and unnecessary restrictions, they can be merged into one constraint; if multiple constraints are only valid under the same conditions, they can be merged into one conditional constraint.

[0031] S140. According to the data width of each target constrained random variable, the target value range of each target constrained random variable is re-encoded according to the set data width unit, and the re-encoding result is added to the test stimulus code.

[0032] In the embodiment of the present invention, data width can be specifically understood as the number of bits used when data is stored or transmitted. In programming languages, such as SystemVerilog, data types have clear bit widths (such as int, bit and logic bit widths are 32 bits, 1 bit and 1 bit respectively). Recoding can be specifically understood as the process of converting data from one encoding format to another encoding format, mapping input data to different output data according to specific rules or algorithms, mapping the wide bit representation of original data to new narrow bit representation, and realizing compressed data by reducing the number of bits required to represent data. According to the target value range of each target constrained random variable, the coding strategy is optimized to minimize the number of bits required. For example, Huffman coding or other variable-length coding techniques can be used to assign shorter codes to random variables under satisfying constraints. After recoding, the recoding result is added to the test stimulus code to achieve optimization of the test stimulus code.

[0033] The technical solution of the embodiment of the present invention obtains each constraint expression belonging to the same scope in the test stimulus code to be input into the chip verification environment, identifies the target constraint expression to be optimized according to the constraint amount contained and sorts it, traverses each target constraint expression according to the sorting result, and gradually determines the target value range of the target constrained random variable in each target constraint expression, recodes the target value range of each target constrained random variable according to the data width of each target constrained random variable and the set data width unit, and adds the recoded result to the test stimulus code. By gradually narrowing the target value range of the target constrained random variable and recoding it in sequence, the test stimulus code is optimized, the scale of the constraint solving problem input solving engine is reduced, and the performance of the constraint solver is improved.

[0034] Optionally, in the embodiment of the present invention, according to the constraint amount included in the constraint expression, identifying the target constraint expression to be optimized in each constraint expression may include:

[0035] Initialize the first-class constraint variable list and the second-class constraint variable list; obtain a constraint expression from each constraint expression as the current constraint expression; if the constraints in the current constraint expression are all constants, determine the current constraint expression as the first-class target constraint expression belonging to the single-variable constraint, and add the constrained random variables in the current constraint expression to the first-class constraint variable list; if the constraints in the current constraint expression are constants and random variables in the first-class constraint variable list or are all any of the random variables in the first-class constraint variable list, determine the current constraint expression as the second-class target constraint expression belonging to the multi-variable association constraint, and add the constraints in the current constraint expression to the first-class constraint variable list. The constrained random variables are added to the second category constraint variable list; if the constraint in the current constraint expression is a constant and a random variable in the second category constraint variable list, a random variable in the first category constraint variable list and a random variable in the second category constraint variable list, or both are random variables in the second category constraint variable list, then the current constraint expression is determined as a second category target constraint expression belonging to a multi-variable associated constraint, and the constrained random variables in the current constraint expression are added to the second category constraint variable list; the operation of obtaining a constraint expression in each constraint expression in turn is repeated until no new first category target constraint expression or second category target constraint expression can be determined.

[0036] In the embodiments of the present invention, the first type of constrained variable list can be specifically understood as: the constrained random variables in the first type of target constraint expression, that is, the set composed of the constrained random variables in the single-variable constraint expression. Among them, the single-variable constraint means that the constraint quantities in the current constraint expression are all constants. For example, var inside{[constant1:constant2]} or var>constant1; var<constant2, where var represents a variable and constant represents a constant. In SystemVerilog, inside is a set membership operator, which is used to constrain the value range of random variables. When a random variable is constrained to be inside a specific set, it must satisfy at least one element in the set. var inside{[constant1:constant2]} represents that the value range of var is constant1≤var≤constant2.

[0037] The second type of constrained variable list can be specifically understood as: the constrained random variables in the second type of target constraint expression, that is, the set composed of the constrained random variables in the multi-variable association constraint expression. Among them, the multi-variable association constraint means that the constraint quantities in the current constraint expression are any one of constants and random variables in the first type of constrained variable list, all random variables in the first type of constrained variable list, constants and random variables in the second type of constrained variable list, random variables in the first type of constrained variable list and random variables in the second type of constrained variable list, or all random variables in the second type of constrained variable list. For example, var1 inside{[var2:var3]}; where the constraints involved in var2 and var3 are constants and single-variable constraints, all single-variable constraints, constants and multi-variable association constraints, single-variable constraints and multi-variable association constraints, or all multi-variable association constraints, and the range of var1 is jointly determined by var2 and var3. In addition, it can also include a third type of constraint, that is, the range of variables cannot be further simplified and determined by sorting or other means through other constraints, or it can be understood as a constraint other than single-variable constraints and multi-variable association constraints.

[0038] Specifically, the first-class constraint variable list and the second-class constraint variable list are initialized to empty, and a constraint expression is obtained in each constraint expression. When it is judged as a single-variable constraint expression by the constraint amount, and there is no such constrained random variable in the first-class constraint variable list, the constrained random variable in the expression is added to the first-class constraint variable list. When it is judged as a multi-variable associated constraint expression by the constraint amount, and there is no such constrained random variable in the second-class constraint variable list, the constrained random variable in the expression is added to the second-class constraint variable list. Repeat the operation of obtaining a constraint expression in each constraint expression in turn until no new first-class target constraint expression or second-class target constraint expression can be determined in this round of execution. At this time, the remaining undetermined constraint expressions are third-class target constraint expressions. Thus, the first-class target constraint expression is identified according to the constraint amount, and the second-class target constraint expression is identified in sequence, and the third-class expression can also be determined.

[0039] Optionally, in the embodiment of the present invention, sorting the target constraint expressions may include:

[0040] Randomly sort the first-category objective constraint expressions to obtain a first sorting result; sort the second-category objective constraint expressions according to the dependency relationship between the random variables in the constraint quantities to obtain a second sorting result; append the second sorting result to the first sorting result to obtain a final sorting result.

[0041] Specifically, since the first type of objective constraint expression only contains constrained random variables and the constraints are all constants, the order of the objective constraint expression does not affect the solution of other variables. Since the range of the variables in the third type of constraints cannot be determined no matter how they are sorted, the description of the gate circuit level generated in the end is the same, that is, there is no need to sort the first and third types of constraints, and only the second type of constraints need to be sorted. Therefore, the first type of objective constraint expressions are randomly sorted to obtain the first sorting result; the second type of objective constraint expressions are sorted according to the dependency relationship between the random variables in the constraint quantities, that is, according to the recognition order of the objective constraint expressions to be optimized, or according to the order of adding the constrained random variables in the expression to the second type of constraint variable list, to obtain the second sorting result; the third type of objective constraint expressions can also be randomly sorted to obtain the third sorting result; thus, the second sorting result is appended to the first sorting result, and the third sorting result is appended to the second sorting result to obtain the final sorting result.

[0042] Optionally, in the embodiment of the present invention, sorting the second-type objective constraint expressions according to the dependency relationship between the random variables in the constraint quantities to obtain the second sorting result may include:

[0043] In each sorting round, the current second-class objective constraint expressions in each second-class objective constraint expression to be sorted are obtained in turn, and the random variables in each current constraint quantity are extracted from the current second-class objective constraint expression; if the random variables in all current constraint quantities are in the dependent item set, the current second-class objective constraint expression is added to the sorting queue, and the operation of adding the current second-class objective constraint expression to the sorting queue and returning to sequentially obtain the current second-class objective constraint expression in each second-class objective constraint expression is performed; wherein, the constrained random variables in each first-class objective constraint expression are initialized and stored in the dependent item set; if at least one current constraint quantity is not in the dependent item set, the operation of sequentially obtaining the current second-class objective constraint expression in each second-class objective constraint expression is directly returned; after completing the processing of the current sorting round, the constrained random variables in each second-class objective constraint expression newly added to the sorting queue are added to the dependent item set; in the new sorting round, the operation of sequentially obtaining the current second-class objective constraint expression in each second-class objective constraint expression is re-executed until all second-class objective constraint expressions are added to the sorting queue to obtain the second sorting result.

[0044] Specifically, the dependent item set refers to the set defined by the constrained random variables used in the constraint expression depending on the value of another variable. This dependency relationship is usually reflected in the constraints of random variables, in which the legal value set of one variable is determined by the current value of another variable. In an embodiment of the present invention, the dependent item set stores the constrained random variables in the constraint expressions that have participated in the sorting. Since the constraint quantity in the first type of objective constraint expression is a constant, the order of the objective constraint expression does not affect the solution of other variables. The constrained random variables in each first type of objective constraint expression are initialized and stored in the dependent item set as dependencies of the constrained random variables in the second type of objective constraint expression.

[0045] In each round of sorting of the second-class objective constraint expression, the current second-class objective constraint expression is obtained in turn, and each current constraint quantity is extracted. If all currently processed constraint quantities are in the dependent item set, that is, the constraint quantities on which the constrained random variables depend are all derived from the sorted constraint expressions, the current second-class objective constraint expression is added to the sorting queue and the current operation is returned; if at least one current constraint quantity is not in the dependent item set, the current second-class objective constraint expression does not participate in the sorting and directly returns to the current operation; after completing the sorting operation of the second-class objective constraint expression in this round, the constrained random variables in each newly added second-class objective constraint expression in the sorting queue are added to the dependent item set, and a new sorting round is started, and the operation of obtaining the current second-class objective constraint expression in turn is re-executed in the remaining second-class objective constraint expressions that are not involved in the sorting, until all second-class objective constraint expressions are added to the sorting queue, and the second sorting result is obtained, so as to achieve the sorting of the second-class objective constraint expression according to the dependency relationship between random variables.

[0046] Optionally, in an embodiment of the present invention, traversing each target constraint expression according to the sorting result, and gradually determining the target value range of the target constrained random variable in each target constraint expression during the traversal process, may include:

[0047] Set an initial value range for each target constrained random variable; traverse each target constraint expression in turn according to the sorting result, and update the value range of each target constrained random variable according to the constraint content in each target constraint expression; after completing the traversal of all target constraint expressions, obtain the target value range of each target constrained random variable.

[0048] Specifically, in the process of gradually determining the target value range of the target constrained random variable in each target constraint expression, first set the initial value range for each target constrained random variable, such as [-inf:inf], that is, the value range of the variable is unrestricted and can extend from negative infinity to positive infinity, which can cover all possible value ranges of the random variable. In the subsequent process of traversing each target constraint expression in sequence according to the sorting result, the target value range of the target constrained random variable is determined according to the constraint content in each target constraint expression and is updated to the preset initial value range in sequence. After completing the traversal of all target constraint expressions, the final target value range of each target constrained random variable is obtained. Sorting the constraint expressions according to the dependency order of the random variables and optimizing the value range of the random variables can significantly improve the efficiency and success rate of constraint solving. This method reduces the workload of the solver in finding a solution that satisfies all constraints, avoids invalid randomization attempts, enhances the quality of testing, and improves test coverage. In addition, it also helps to improve the verifiability of the design, ensure that resources are reasonably used, and make the test data more representative, thereby covering more test scenarios.

[0049] Optionally, in an embodiment of the present invention, traversing each target constraint expression in turn according to the sorting result, and updating the value range of each target constrained random variable according to the constraint content in each target constraint expression, may include:

[0050] When traversing to the current second-class objective constraint expression, obtain the current target constrained random variable contained in the second-class objective constraint expression, and at least one target random variable used to constrain the value range of the current target constrained random variable; if the target random variable constrains the upper boundary of the current target constrained random variable, then in the value range of the updated target random variable, obtain the maximum value of the target random variable, and use the maximum value to update the upper boundary of the current target constrained random variable; if the target random variable constrains the lower boundary of the current target constrained random variable, then in the value range of the updated target random variable, obtain the minimum value of the target random variable, and use the minimum value to update the lower boundary of the current target constrained random variable.

[0051] Specifically, when traversing each target constraint expression in turn and updating the value range of the target constrained random variable, since the constraint quantity of the second type of target constraint expression contains at least one random variable (the optional combination of the constraint quantity is a constant and a first type constrained random variable, both are first type constrained random variables, a constant and a second type constrained random variable, a first type constrained random variable and a second type constrained random variable, or both are second type constrained random variables), the current target constrained random variable contained in the second type of target constraint expression and at least one target random variable used to constrain the value range of the current target constrained random variable are obtained. When the target random variable constrains the upper boundary of the current target constrained random variable, the maximum value of the target random variable is obtained in the value range of the updated target random variable, and the upper boundary of the current target constrained random variable is updated. For example, in the case of var1 inside{[3:var2]}; var2 inside{[var2_min:var2_max]}, this case can be converted to var1 inside{[3:var2_max]}. When the target random variable constrains the lower bound of the current target constrained random variable, the minimum value of the target random variable is obtained in the updated range of the target random variable, and the lower bound of the current target constrained random variable is updated. For example, var1 inside{[var2:3]}; var2 inside{[var2_min:var2_max]} can be converted to var1 inside{[var2_min:3]}, which converts the range of random variables into a form containing only constant constraints, improving the certainty and predictability of the simulation because they provide clear value boundaries, making the results easier to reproduce. This constraint method simplifies the solution process, speeds up the solution, and reduces the dependencies between random variables, thereby reducing the complexity of the problem.

[0052] Optionally, in the embodiment of the present invention, the data width unit is 1 bit, and according to the data width of each constrained random variable, the target value range of each constrained random variable is re-encoded according to the set data width unit, which may include:

[0053] According to the target value range and data width of each constrained random variable, the extreme value bit number of each constrained random variable is calculated; according to the data width range of 0 bits in the extreme value bit number of each constrained random variable, the target value range of each constrained random variable is re-encoded.

[0054] Specifically, calculating the extreme value bit number of the constrained random variable involves determining the minimum and maximum values ​​of the variable, and then calculating the bit width of these two values. The extreme value bit number refers to the minimum number of bits required to represent the maximum and minimum values ​​of the random variable. For each constraint expression that has been sorted and optimized for the value range, the target value range of each constrained random variable is limited by recoding according to the data width range of the 0 bit in the extreme value bit number of each constrained random variable. For example:

[0055] rand int rand_var;

[0056] constraint c_rand_var{

[0057] rand_var inside{4:15};}

[0058] rand_var is an int variable with 32 bits. The minimum value of rand_var is 4, which is 100 in binary and requires 3 bits to represent. The maximum value is 15, which is 1111 in binary and requires 4 bits to represent. In this example, rand_var can be recoded as:

[0059] rand_var[31:4]==28'b0; rand_var[3:0]inside{[4:15]};

[0060] By re-encoding the random variable to limit its bit number through the extreme value bit number of the constrained random variable, it is possible to optimize the allocation of storage resources, ensure that no bits are wasted, reduce the scale of the constraint solving problem, reduce power consumption and improve verification efficiency.

[0061] Specific application scenarios

[0062] Figure 2 AST (Abstract Syntax Tree) is a tree representation of source code, which shows the grammatical structure of programming language in a tree structure. In a compiler or interpreter, source code is first parsed into AST, which ignores format details (such as spaces and brackets) in the code and focuses on its grammatical structure. AST facilitates program analysis, optimization and execution.

[0063] For example, for a section of system Verilog code about random variables and constraints:

[0064] rand bit[31:0]x;

[0065] constraint c1{x<10;x! =5;x>=2;}

[0066] The code contains two key pieces of information, namely the definition of the random variable x and the set c1 of constraint expressions. These two are called expression-level constraint descriptions. At this point, the constraints are only in the form of strings, and the constraints need to be converted into an abstract syntax tree. For example, x<10, the corresponding Figure 2 As shown:

[0067] x<10 as a whole can be regarded as an expression tree, and the type of the root node is a Boolean operation, that is, if the expression is true, the value of the overall expression is true, otherwise it is false.

[0068] If the value of the expression is false, it means that the constraint cannot be satisfied, that is, the solution fails. The root node has only one child node, the type is a binary operation, and the operator is a less than operation. Since it is a binary operation, there must be two child nodes. Child node 1 is a reference to the random variable, that is, the variable itself; child node 2 is a constant node. Both nodes are leaf nodes.

[0069] By analogy, each constraint in the constraint set can be converted into a similar expression tree, and the root node of each expression tree is a Boolean operation. By combining the root nodes of each expression with a logical AND (&&) operation, we can get only one root node in the end, which is the root node of the abstract syntax tree. The type of this root node is also a Boolean operation. If the return value is 1, it means that the value of the random variable can satisfy all constraints. If the return value is 0, it means that at least one constraint cannot be satisfied. In the process of constructing the abstract syntax tree, each constraint can be based on different expression operation types.

[0070] When the test stimulus code is not optimized, it often has a large constraint solving problem scale. For example, when the test stimulus code is:

[0071] rand bit[31:0]x,y,z,u,v,w;

[0072] constraint c1{

[0073] x inside{[0:50]}; z inside{[20:40]}; y inside{[x:z]};

[0074] u inside{[y:y+20]}; v inside{[z-10:u]};

[0075] x+y>=w;}

[0076] The above code is analyzed using an abstract syntax tree. These three inputs will be converted into three abstract syntax trees. The leaf nodes of the three abstract syntax trees have the same reference variables, namely x, y, and z. The array composed of abstract syntax trees is the input of this algorithm.

[0077] If this set of constraints is directly input into the SAT engine without optimization, the number of bits to be randomized is 192, that is, there are at most 2^192 possibilities, and the amount of calculation is very large. Therefore, if the number of bits to be randomized can be reduced as much as possible when inputting into the SAT engine, the solution can be accelerated to a great extent. The specific constraint optimization process based on the abstract syntax tree can be:

[0078] 1. Constraint classification and sorting

[0079] Constraint solvers are generally used to generate random stimuli that meet specific rules. In the field of chip verification, random simulation is an indispensable part. Random stimuli are generally used to verify whether the output of the chip design circuit meets the designer's expectations under specific random inputs. In the syntax of SystemVerilog, the variables modified by the rand and randc keywords are random variables (stimuli) that need to meet specific constraints. As described above, these variables are used as inputs to the chip design circuit. According to the output of the chip design circuit or its subcircuits, it is judged whether the circuit design being verified meets expectations.

[0080] Traditional constraint solvers, in the absence of solve-before constraints, do not prioritize constraints. Each constraint has the same weight and will be solved at the same time, that is, no matter which constraint is analyzed first, the gate circuits input into the SAT engine are the same. However, the range of some variables can be deduced from the range of other variables. Therefore, the order in which constraints are analyzed is an important factor in code optimization. In constraint programming, solve-before constraints can be used to specify the order of variables when solving constraints, ensuring that dependent variables are processed and determined first to optimize the search process and adjust probability distribution. Solve-before constraints cannot be used for randc type variables (used to declare periodic random variables) because they are always solved first. Therefore, this specific application scenario only discusses random variables modified by the rand keyword and the constraints involved. Random variables modified by the randc keyword are not within the scope of this specific application scenario.

[0081] At this stage, the input is the array of abstract syntax trees obtained previously. After constraint classification, three arrays are obtained, namely three classifications: single-variable constraints, multi-variable association constraints, and other constraints. The input of the sorting stage is the array composed of the second type of abstract syntax trees, that is, multi-variable association constraints. The output result is the array composed of the sorted second type of abstract syntax trees, which is sorted according to the solution priority.

[0082] 1.1 Traverse all constraints and classify them into three categories

[0083] The first type of constraint is a single-variable constraint, which contains only one random variable (var) and the rest are all constants (constant). For example, var inside{[constant1:constant2]}; that is, constant1 ≤ var ≤ constant2 or var > constant1; var < constant2. Single-variable constraints are the most common. The second type of constraint is a multi-variable association constraint, which contains multiple random variables. Each random variable either has all the constraints it involves being the first type of constraint, or its range can be determined by other random variables. For example, var1 inside{[var2:var3]}, that is, var2 ≤ var1 ≤ var3; the constraints that var2 and var3 involve are all the first type of constraint, and the range of var1 is determined jointly by var2 and var3. The third type of constraint is other constraints. Other constraints cannot further simplify and determine the variable range through sorting or other means. For example, var1 + var2 < var3. This operation can reduce the complexity of the subsequent sorting. For the above example, the first type of constraints are: x inside{[0:50]}; z inside{[20:40]}; the second type of constraints are: y inside{[x:z]}; u inside{[y:y + 20]}; v inside{[z - 10:u]}; the third type of constraints are: x + y >= w.

[0084] 1.2 Constraint sorting

[0085] After constraint classification, it is necessary to sort the constraints belonging to different categories because the ranges of some variables are determined by the ranges of other variables, that is, there is a dependency relationship between variables. For the first type and the third type of constraints, no sorting is required. The first type of constraint contains only single variables, and the order does not affect the solution of other variables. Sorting the third type of constraint is meaningless. No matter how it is sorted, the variable ranges in it cannot be determined, resulting in the same description at the gate circuit level in the end.

[0086] Therefore, only the second type of constraints need to be sorted. The algorithm used for sorting is similar to the principle of topological sorting, which constructs a directed acyclic graph. It is worth noting that this directed acyclic graph is for random variables, not constraints. First, the random variables whose range can be determined only by the first type of constraints are put in the front, and these variables are recorded as sv0; then the random variables that require variables in sv0 to determine the range are arranged, and these random variables are recorded as sv1, and the constraints containing at least sv1, that is, containing constants and sv1, sv0 and sv1, or only containing sv1 are recorded as sc1; and so on, constraints containing at least sv2 can be obtained, recorded as sc2, until scN.

[0087] After the second category constraints are sorted, the first category, second category, and third category constraints are sorted in order to obtain the final constraint sorting. For the above example, the second category constraints are sorted as follows:

[0088] sc0:y inside{[x:z]};

[0089] sc1:u inside{[y:y+20]};

[0090] sc2:v inside{[z-10:u]};

[0091] 2. Random variable range analysis

[0092] After obtaining the order of the constraints, we analyze them according to the ordered constraints. By traversing the constraints involved in each variable, we continuously narrow the range of random variables, thereby determining the value range of each variable and obtaining a result in the form of var inside{[min:max]}.

[0093] First, set an initial range for all variables: [-inf:inf], that is, negative infinity to positive infinity. In order to obtain the final variable range, traverse all constraints, starting from the first type of constraints. In the process of traversing the constraints, the range of the variables is continuously updated. After the first type of constraints are completed, traverse the second type of constraints. In the process of traversing the second type of constraints, when encountering constraints in the form of var1inside{[var2:var3]}, it can be converted to var1 inside{[var2_min:var3_max]}, where var2_min refers to the minimum value that var2 can take, and var3_max refers to the maximum value of var3. After the second type of constraints are traversed, the random variable range analysis is completed, and there is no need to traverse the third type of constraints.

[0094] The input of this stage is the abstract syntax tree array consisting of the first type of single variable constraints and the second type of multi-variable associated constraints obtained in the previous stage. In this stage, the algorithm will first analyze the first type of constraints to obtain the range of some random variables, and then traverse and analyze the second type of constraints based on the range of these variables. Since the second type of constraint array is sorted, it is inevitable that the range of random variables only included in the first and second types of constraints can be obtained. That is, the output is an array consisting of random variables and their ranges only included in the first and second types of constraints. In other words, the original range of random variables only included in the first and second types of constraints is [-inf:inf]. After this stage, it can be narrowed to [a:b], where -inf<=a<=b<=inf. This range does not represent the final value range of the variable, but the search range of its next solution stage (logic synthesis and SAT solution). The smaller the range, the less search space and the faster the solution speed.

[0095] 3. Recoding the range of random variables

[0096] After getting the range of all variables, we can recode them to show the range in the constraints so that they can be reduced in size when converted into gate circuits in the next step. For example:

[0097] rand int a;a inside{[0:20]};

[0098] a can be re-encoded as:

[0099] a[31:5]==27'b0;a[4:0]inside{[0:20]};

[0100] That is, the 5th to 31st bits of a, a total of 27 bits, are set to zero, the value of a is in the range of 0 to 20, and only the 0th to 4th bits of a are operated. The size of the gate circuit generated by this operation will be greatly reduced.

[0101] The input of this stage is the array of random variables and their ranges obtained in the previous stage that are only included in the first and second type constraints, and the abstract syntax tree array composed of the first and second type constraints. The operation of this stage is to directly modify the abstract syntax tree of the first and second types of constraints, use the recoded random variables to form a new abstract syntax subtree, replace the nodes corresponding to the original abstract syntax tree, and obtain a new abstract syntax tree. The new abstract syntax tree array is the output of this stage.

[0102] In the next constraint solving stage, the logic synthesis stage, the abstract syntax tree will be converted into a gate-level netlist through logic synthesis, and then converted into cnf (Conjunctive Normal Form) as the input for the Sat solver. The optimized abstract syntax tree corresponds to a gate-level netlist with fewer nodes, so the number of clauses in the generated cnf will also be smaller. The Sat solver can be understood as a search algorithm. Fewer clauses means a smaller search space, which means that answers that meet all constraints can be found faster, thereby achieving the purpose of accelerating constraint solving. For example:

[0103] rand int a,b,c;

[0104] constraint c1{

[0105] a inside{[0:20]};

[0106] b inside{[0:100]};

[0107] c==a%b;}

[0108] If the above example is not optimized, c needs to perform 32x32 operations. After the above example is optimized by the excitation code optimization method provided by the present invention, it will become:

[0109] rand int a,b,c;

[0110] constraint c1{

[0111] a[31:5]==0; b[31:7]==0;

[0112] a[4:0]inside{[0:20]};

[0113] b[6:0]inside{[0:100]};

[0114] c == a[4:0] % b[6:0];}

[0115] After optimization, c only needs to perform 5x7 operations, which is about 30 times faster. Compared with the acceleration effect, the overhead of the optimization algorithm itself can be ignored.

[0116] The optimization method of the excitation code provided by the present invention can greatly reduce the scale of the constraint solving problem input into the SAT solving engine, and realize the rapid generation of random variables that meet specific constraints and are uniformly distributed, thereby improving the performance of the constraint solver.

[0117] Embodiment 2

[0118] Figure 3 This is a schematic diagram of the structure of a test stimulus code optimization device provided in the second embodiment of the present invention. Figure 3 As shown, the device includes: a constraint expression acquisition module 310, a target constraint expression sorting module 320, a target value range determination module 330 and a target value range recoding module 340.

[0119] The constraint expression acquisition module 310 is used to acquire each constraint expression belonging to the same scope in the test stimulus code to be input into the chip verification environment;

[0120] The target constraint expression sorting module 320 is used to identify the target constraint expressions to be optimized in each constraint expression according to the constraint quantities contained in the constraint expressions, and sort the target constraint expressions;

[0121] A target value range determination module 330 is used to traverse each target constraint expression according to the sorting result, and gradually determine the target value range of the target constrained random variable in each target constraint expression during the traversal process;

[0122] The target value range recoding module 340 is used to recode the target value range of each target constrained random variable according to the data width of each target constrained random variable and the set data width unit, and add the recoding result to the test stimulus code.

[0123] The technical solution of the embodiment of the present invention obtains each constraint expression belonging to the same scope in the test stimulus code to be input into the chip verification environment, identifies the target constraint expression to be optimized according to the constraint amount contained and sorts it, traverses each target constraint expression according to the sorting result, and gradually determines the target value range of the target constrained random variable in each target constraint expression, recodes the target value range of each target constrained random variable according to the data width of each target constrained random variable and the set data width unit, and adds the recoded result to the test stimulus code. By gradually narrowing the target value range of the target constrained random variable and recoding it in sequence, the test stimulus code is optimized, the scale of the constraint solving problem input solving engine is reduced, and the performance of the constraint solver is improved.

[0124] In the embodiment of the present invention, the target constraint expression sorting module 320 is specifically used for:

[0125] Initialize the first-class constraint variable list and the second-class constraint variable list; obtain a constraint expression from each constraint expression as the current constraint expression; if the constraints in the current constraint expression are all constants, determine the current constraint expression as the first-class target constraint expression belonging to the single-variable constraint, and add the constrained random variables in the current constraint expression to the first-class constraint variable list; if the constraints in the current constraint expression are constants and random variables in the first-class constraint variable list or are all any of the random variables in the first-class constraint variable list, determine the current constraint expression as the second-class target constraint expression belonging to the multi-variable association constraint, and add the constraints in the current constraint expression to the first-class constraint variable list. The constrained random variables are added to the second category constraint variable list; if the constraint in the current constraint expression is a constant and a random variable in the second category constraint variable list, a random variable in the first category constraint variable list and a random variable in the second category constraint variable list, or both are random variables in the second category constraint variable list, then the current constraint expression is determined as a second category target constraint expression belonging to a multi-variable associated constraint, and the constrained random variables in the current constraint expression are added to the second category constraint variable list; the operation of obtaining a constraint expression in each constraint expression in turn is repeated until no new first category target constraint expression or second category target constraint expression can be determined.

[0126] Optionally, the target constraint expression sorting module 320 includes:

[0127] A first sorting result obtaining submodule is used to randomly sort each first-category objective constraint expression to obtain a first sorting result;

[0128] A second sorting result obtaining submodule is used to sort the second type target constraint expressions according to the dependency relationship between the random variables in the constraint quantities to obtain a second sorting result;

[0129] The final sorting result obtaining module is used to append the second sorting result to the first sorting result to obtain the final sorting result.

[0130] Optionally, the second sorting result obtaining submodule includes:

[0131] The current second-class objective constraint expression acquisition unit is used to sequentially acquire the current second-class objective constraint expressions in each second-class objective constraint expression to be sorted in each sorting round, and extract the random variables in each current constraint quantity in the current second-class objective constraint expression;

[0132] The current second-class objective constraint expression sorting unit is used to add the current second-class objective constraint expression to the sorting queue if all the random variables in the current constraint quantities are in the dependent item set, and to add the current second-class objective constraint expression to the sorting queue and return to perform the operation of sequentially obtaining the current second-class objective constraint expression in each second-class objective constraint expression;

[0133] An operation execution return unit, used for directly returning to execute the operation of sequentially obtaining the current second-category objective constraint expression in each second-category objective constraint expression if at least one current constraint quantity is not in the dependent item set;

[0134] A dependent item set updating unit, used for adding the constrained random variables in each second type objective constraint expression newly added to the sorting queue to the dependent item set after completing the processing of the current sorting round;

[0135] The second sorting result obtaining unit is used to re-execute the operation of obtaining the current second-category target constraint expression in each second-category target constraint expression in turn under a new sorting round, until all second-category target constraint expressions are added to the sorting queue to obtain the second sorting result.

[0136] In the embodiment of the present invention, the target value range determination module 330 is specifically used to:

[0137] Set an initial value range for each target constrained random variable; traverse each target constraint expression in turn according to the sorting result, and update the value range of each target constrained random variable according to the constraint content in each target constraint expression; after completing the traversal of all target constraint expressions, obtain the target value range of each target constrained random variable.

[0138] Optionally, the target value range determination module 330 includes:

[0139] The current second-class objective constraint expression traversal submodule is used to obtain the current objective constrained random variable contained in the second-class objective constraint expression and at least one objective random variable used to constrain the value range of the current objective constrained random variable when traversing to the current second-class objective constraint expression;

[0140] An upper boundary updating submodule, for obtaining the maximum value of the target random variable in the value range of the updated target random variable if the target random variable constrains the upper boundary of the current target constrained random variable, and using the maximum value to update the upper boundary of the current target constrained random variable;

[0141] The lower bound updating submodule is used to obtain the minimum value of the target random variable within the value range of the updated target random variable if the target random variable constrains the lower bound of the current target constrained random variable, and use the minimum value to update the lower bound of the current target constrained random variable.

[0142] In the embodiment of the present invention, the target value range recoding module 340 is specifically used for:

[0143] Calculate the number of extreme value bits of each constrained random variable according to the target value range and data width of each constrained random variable;

[0144] According to the data width range of 0 bits in the extreme value bit number of each constrained random variable, the target value range of each constrained random variable is re-encoded.

[0145] The test stimulus code optimization device provided in the embodiment of the present invention can execute the test stimulus code optimization method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0146] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0147] Embodiment 3

[0148] Figure 4 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0149] like Figure 4As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0150] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0151] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the optimization method of the test stimulus code.

[0152] That is: in the test stimulus code to be input into the chip verification environment, each constraint expression belonging to the same scope is obtained; wherein each constraint expression contains a constrained random variable and a constraint quantity for constraining the value range of the constrained random variable, and the constraint quantity is a constant or other random variable; according to the constraint quantity contained in the constraint expression, the target constraint expression to be optimized is identified in each constraint expression, and each target constraint expression is sorted; according to the sorting result, each target constraint expression is traversed respectively, and in the traversal process, the target value range of the target constrained random variable in each target constraint expression is gradually determined, wherein the target value range only contains constants; according to the data width of each target constrained random variable, the target value range of each target constrained random variable is re-encoded according to the set data width unit, and the re-encoded result is added to the test stimulus code.

[0153] In some embodiments, the optimization method of the test stimulus code may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the optimization method of the test stimulus code described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the optimization method of the test stimulus code in any other appropriate manner (e.g., by means of firmware).

[0154] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0155] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0156] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0157] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0158] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0159] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0160] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0161] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for optimizing a test stimulus code, characterized in that: include: Obtaining each constraint expression belonging to the same scope in the test stimulus code to be input into the chip verification environment; wherein each constraint expression includes a constrained random variable and a constraint quantity for constraining the value range of the constrained random variable, and the constraint quantity is a constant or other random variable; According to the constraint quantities contained in the constraint expressions, target constraint expressions to be optimized are identified in each constraint expression, and each target constraint expression is sorted; Traverse each target constraint expression according to the sorting result, and gradually determine the target value range of the target constrained random variable in each target constraint expression during the traversal process, wherein the target value range only contains constants; According to the data width of each target constrained random variable, the target value range of each target constrained random variable is recoded according to the set data width unit, and the recoded result is added to the test stimulus code.

2. The method according to claim 1, characterized in that According to the constraint quantities contained in the constraint expressions, the target constraint expressions to be optimized are identified in each constraint expression, including: Initialize the first type constraint variable list and the second type constraint variable list; Get a constraint expression from each constraint expression as the current constraint expression; If the constraints in the current constraint expression are all constants, the current constraint expression is determined as a first-category target constraint expression belonging to a single-variable constraint, and the constrained random variables in the current constraint expression are added to the first-category constraint variable list; If the constraint quantity in the current constraint expression is a constant and a random variable in the first-category constraint variable list or both are any of the random variables in the first-category constraint variable list, the current constraint expression is determined as a second-category target constraint expression belonging to a multi-variable association constraint, and the constrained random variables in the current constraint expression are added to the second-category constraint variable list; If the constraint in the current constraint expression is any one of a constant and a random variable in the second constraint variable list, a random variable in the first constraint variable list and a random variable in the second constraint variable list, or both of them are random variables in the second constraint variable list, the current constraint expression is determined as a second target constraint expression belonging to a multi-variable association constraint, and the constrained random variables in the current constraint expression are added to the second constraint variable list; The operation of obtaining one constraint expression in each constraint expression is repeatedly performed until no new first-category target constraint expression or second-category target constraint expression can be determined.

3. The method according to claim 2, characterized in that Sort each objective constraint expression, including: Randomly sort the first-category objective constraint expressions to obtain a first sorting result; Sorting the second-category objective constraint expressions according to the dependency relationship between the random variables in the constraint quantities to obtain a second sorting result; The second sorting result is added to the first sorting result to obtain the final sorting result.

4. The method according to claim 3, characterized in that The second-type objective constraint expressions are sorted according to the dependency relationship between the random variables in the constraint quantities to obtain a second sorting result, including: In each sorting round, the current second-type objective constraint expressions in each second-type objective constraint expression to be sorted are obtained in turn, and the random variables in each current constraint quantity are extracted from the current second-type objective constraint expression; If all the random variables in the current constraint quantities are in the dependent item set, the current second-category objective constraint expression is added to the sorting queue, and the operation of sequentially obtaining the current second-category objective constraint expression in each second-category objective constraint expression is returned; The constrained random variables in each first-type objective constraint expression are initialized and stored in the dependent item set; If at least one current constraint quantity is not in the dependent item set, directly return to execute the operation of sequentially obtaining the current second-category objective constraint expression in each second-category objective constraint expression; After completing the processing of the current sorting round, the constrained random variables in each newly added second-type objective constraint expression in the sorting queue are added to the dependent item set; In a new sorting round, the operation of obtaining the current second-category objective constraint expression in each second-category objective constraint expression in turn is re-executed until all second-category objective constraint expressions are added to the sorting queue to obtain a second sorting result.

5. The method according to claim 1, characterized in that: Each target constraint expression is traversed according to the sorting results, and the target value range of the target constrained random variable in each target constraint expression is gradually determined during the traversal process, including: Set the initial value range for each target constrained random variable; Traverse each target constraint expression in turn according to the sorting results, and update the value range of each target constrained random variable according to the constraint content in each target constraint expression; After completing the traversal processing of all target constraint expressions, the target value range of each target constrained random variable is obtained.

6. The method according to claim 5, characterized in that Traverse each target constraint expression in turn according to the sorting results, and update the value range of each target constrained random variable according to the constraint content in each target constraint expression, including: When traversing to the current second-type objective constraint expression, obtaining the current objective constrained random variable contained in the second-type objective constraint expression and at least one objective random variable used to constrain the value range of the current objective constrained random variable; If the target random variable constrains the upper bound of the current target constrained random variable, then in the value range of the updated target random variable, the maximum value of the target random variable is obtained, and the upper bound of the current target constrained random variable is updated using the maximum value; If the target random variable constrains the lower bound of the current target constrained random variable, then the minimum value of the target random variable is obtained within the value range of the updated target random variable, and the lower bound of the current target constrained random variable is updated using the minimum value.

7. The method according to claim 1, characterized in that The data width unit is 1 bit; According to the data width of each constrained random variable, the target value range of each constrained random variable is recoded according to the set data width unit, including: Calculate the number of extreme value bits of each constrained random variable according to the target value range and data width of each constrained random variable; According to the data width range of 0 bits in the extreme value bit number of each constrained random variable, the target value range of each constrained random variable is re-encoded.

8. An optimization device for test stimulus code, characterized in that: include: A constraint expression acquisition module, used to acquire each constraint expression belonging to the same scope in the test stimulus code to be input into the chip verification environment; A target constraint expression sorting module is used to identify target constraint expressions to be optimized in each constraint expression according to the constraint quantities contained in the constraint expressions, and sort the target constraint expressions; A target value range determination module is used to traverse each target constraint expression according to the sorting result, and gradually determine the target value range of the target constrained random variable in each target constraint expression during the traversal process; The target value range recoding module is used to recode the target value range of each target constrained random variable according to the data width of each target constrained random variable and the set data width unit, and add the recoding result to the test stimulus code.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory in communication with the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the test stimulus code optimization method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the test stimulus code optimization method according to any one of claims 1 to 7 when executed.

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