Address mapping method and device of storage equipment, electronic equipment and storage medium

Abstract

The embodiment of the invention provides an address mapping method and device of a storage device, electronic equipment and a storage medium, and the method comprises the steps: writing target data carried by a target write instruction into the storage device based on a target physical address indicated by the target write instruction; the number of address bits of the target physical address is the same as the number of address bits corresponding to the maximum memory capacity of the storage device; based on the physical addresses corresponding to the data reading addresses indicated by the at least two target reading instructions, respectively reading at least two pieces of first data from the storage device; the values corresponding to the at least two physical addresses only on the same at least two row address bits are different, and the at least two row address bits comprise the highest bit in the physical addresses and the adjacent row address bits; determining the actual memory capacity of the storage device based on the at least two pieces of first data and the target data; and reconfiguring the memory address mapping relationship of the storage device based on the target mapping relationship corresponding to the actual memory capacity.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an address mapping method and device for a storage device, an electronic device and a storage medium. Background Art

[0002] Double Data Rate (DDR) has become an indispensable component in the design of Application Specific Integrated Circuit (ASIC) due to its advantages such as fast access speed, small size and relatively low price.

[0003] In the related art, during the actual use of the application-specific integrated circuit, the memory management system in the ASIC can dynamically adjust the capacity of the DDR according to the needs of the application program to meet different storage capacity requirements. After adjusting the DDR capacity, it is necessary to manually rewrite the address mapping relationship code suitable for the new capacity and compile and generate the firmware. However, since each capacity corresponds to an address mapping relationship code and a firmware version, whenever the DDR capacity needs to be changed, the code and firmware need to be regenerated, resulting in poor code portability and a large number of versions that are not conducive to version management. Summary of the invention

[0004] In order to overcome the problems existing in the related art, the present invention provides a

[0005] In a first aspect, the present invention provides an address mapping method for a storage device, the method comprising:

[0006] Based on the target physical address indicated by the target write instruction, writing the target data carried by the target write instruction into the storage device; the number of address bits of the target physical address is the same as the number of address bits corresponding to the maximum memory capacity of the storage device;

[0007] Based on the physical addresses corresponding to the data read addresses indicated by at least two target read instructions, at least two first data are read from the storage device respectively; the physical addresses corresponding to the data read addresses indicated by the at least two target read instructions have different values ​​corresponding to the same at least two row address bits, and the at least two row address bits include the highest bit in the physical address and adjacent row address bits;

[0008] Determining an actual memory capacity of the storage device based on the at least two first data and the target data;

[0009] Based on the target mapping relationship corresponding to the actual memory capacity, the memory address mapping relationship of the storage device is reconfigured.

[0010] Optionally, before writing the target data carried by the target write instruction to the target address indicated by the target write instruction in the storage device based on the target write instruction, the method includes:

[0011] Pre-configuring memory mapping relationships corresponding to different memory capacities corresponding to the storage device;

[0012] Determine the maximum memory capacity corresponding to the storage device;

[0013] Based on a first memory mapping relationship corresponding to the maximum memory capacity, memory address mapping is performed on the storage device.

[0014] Optionally, the at least two target read instructions include a first read instruction; and the reading at least two first data from the storage device based on the physical addresses corresponding to the data read addresses indicated by the at least two target read instructions respectively includes:

[0015] Based on the first physical address corresponding to the first address indicated by the first read instruction, the first data corresponding to the first read instruction is read from the storage device; the first physical address is the same as the target physical address, and the highest bit and the second highest bit of the row address corresponding to the first physical address and the target physical address have values ​​of 1.

[0016] Optionally, the at least two target read instructions further include a second read instruction; and the reading at least two first data from the storage device based on the physical addresses corresponding to the data read addresses indicated by the at least two target read instructions respectively includes:

[0017] Based on the second physical address corresponding to the second address indicated by the second read instruction, the first data corresponding to the second read instruction is read from the storage device; the value of the highest bit of the row address in the second physical address is 0, and the second physical address and the first physical address have the same numerical value of other row address bits except the highest bit of the row address.

[0018] Optionally, the at least two target read instructions further include a third read instruction; and the reading at least two first data from the storage device based on the physical addresses corresponding to the data read addresses indicated by the at least two target read instructions respectively includes:

[0019] Based on the third physical address corresponding to the third address indicated by the third read instruction, the first data corresponding to the third read instruction is read from the storage device; the highest bit and the second highest bit of the row address in the third physical address are 0, and the third physical address is the same as the first physical address in terms of the values ​​of the other row address bits except the highest bit and the second highest bit of the row address.

[0020] Optionally, determining the actual memory capacity of the storage device based on the at least two first data and the target data includes:

[0021] When the first data corresponding to the first read instruction is equal to the target data, the first data corresponding to the second read instruction, and the first data corresponding to the third read instruction are equal, determining that the actual memory capacity of the storage device is the first capacity;

[0022] When the first data corresponding to the first read instruction is equal to the target data and the first data corresponding to the second read instruction and is not equal to the first data corresponding to the third read instruction, determining that the actual memory capacity of the storage device is the second capacity;

[0023] When the first data corresponding to the first read instruction is the same as the target data and the first data corresponding to the second read instruction and the first data corresponding to the third read instruction are not equal, determining that the actual memory capacity of the storage device is the third capacity;

[0024] The first capacity is smaller than the second capacity, and the second capacity is smaller than the third capacity.

[0025] Optionally, the first capacity is 512 MB, the second capacity is 1 GB, and the first capacity is 2 GB.

[0026] In a second aspect, the present invention provides an address mapping device for a storage device, the device comprising:

[0027] A first writing module, configured to write target data carried by the target write instruction into a storage device based on a target physical address indicated by the target write instruction; the number of address bits of the target physical address is the same as the number of address bits corresponding to the maximum memory capacity of the storage device;

[0028] A first reading module comprises reading at least two first data from the storage device respectively based on physical addresses corresponding to data reading addresses indicated by at least two target read instructions; the physical addresses corresponding to the data reading addresses indicated by the at least two target read instructions have different values ​​corresponding to at least two same row address bits, and the at least two row address bits include the highest bit in the physical address and adjacent row address bits;

[0029] A first determining module, configured to determine an actual memory capacity of the storage device based on the at least two first data and the target data;

[0030] The first configuration module is used to reconfigure the memory address mapping relationship of the storage device based on the target mapping relationship corresponding to the actual memory capacity.

[0031] Optionally, the device further comprises:

[0032] A second configuration module is used to pre-configure a memory mapping relationship corresponding to each memory capacity according to different memory capacities corresponding to the storage device;

[0033] A second determination module, used to determine the maximum memory capacity corresponding to the storage device;

[0034] The first mapping module is used to perform memory address mapping on the storage device based on a first memory mapping relationship corresponding to the maximum memory capacity.

[0035] Optionally, the at least two target read instructions include a first read instruction; and the first read module includes:

[0036] A first read submodule is used to read the first data corresponding to the first read instruction from the storage device based on the first physical address corresponding to the first address indicated by the first read instruction; the first physical address is the same as the target physical address, and the highest bit and the second highest bit of the row address corresponding to the first physical address and the target physical address have values ​​of 1.

[0037] Optionally, the at least two target read instructions further include a second read instruction; and the first reading module further includes:

[0038] A second reading submodule is used to read the first data corresponding to the second read instruction from the storage device based on the second physical address corresponding to the second address indicated by the second read instruction; the value of the highest bit of the row address in the second physical address is 0, and the second physical address and the first physical address have the same numerical value of other row address bits except the highest bit of the row address.

[0039] Optionally, the at least two target read instructions further include a third read instruction; and the first read module further includes:

[0040] A third reading submodule is used to read the first data corresponding to the third read instruction from the storage device based on the third physical address corresponding to the third address indicated by the third read instruction; the highest bit and the second highest bit of the row address in the third physical address are 0, and the third physical address is the same as the first physical address in terms of the values ​​of the other row address bits except the highest bit and the second highest bit of the row address.

[0041] Optionally, the first determining module includes:

[0042] A first determination submodule, configured to determine that the actual memory capacity of the storage device is a first capacity when the first data corresponding to the first read instruction is equal to the target data, the first data corresponding to the second read instruction, and the first data corresponding to the third read instruction are equal;

[0043] A second determination submodule is used to determine that the actual memory capacity of the storage device is a second capacity when the first data corresponding to the first read instruction is equal to the target data and the first data corresponding to the second read instruction and is not equal to the first data corresponding to the third read instruction;

[0044] A third determination submodule, configured to determine that the actual memory capacity of the storage device is a third capacity when the first data corresponding to the first read instruction is the same as the target data and the first data corresponding to the second read instruction and the first data corresponding to the third read instruction are not equal;

[0045] The fourth determining submodule is used to determine that the first capacity is smaller than the second capacity, and the second capacity is smaller than the third capacity.

[0046] In a third aspect, the present invention provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the address mapping method for the storage device described in any one of the first aspects when executing the program.

[0047] In a fourth aspect, the present invention provides a readable storage medium, which, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform the steps in the address mapping method of a storage device in any one of the embodiments of the first aspect above.

[0048] In an embodiment of the present invention, based on the target physical address indicated by the target write instruction, the target data carried by the target write instruction is written to the storage device; the number of address bits of the target physical address is the same as the number of address bits corresponding to the maximum memory capacity of the storage device; based on the physical addresses corresponding to the data read addresses indicated by at least two target read instructions, at least two first data are read from the storage device respectively; the physical addresses corresponding to the data read addresses indicated by at least two target read instructions have different values ​​only in the same at least two row address bits and at least two row address bits contain the highest bit in the physical address and adjacent row address bits; based on the at least two first data and the target data, the actual memory capacity of the storage device is determined; based on the target mapping relationship corresponding to the actual memory capacity, the memory address mapping relationship of the storage device is reconfigured. In this way, the target data is first written into the storage device based on the target physical address with the same number of address bits as the maximum memory capacity, and then the characteristic that different memory capacities of the storage device correspond to different numbers of identifiable row address bits is utilized, and at least two first data are read from the storage device by adjusting at least two row address bits of at least two target read instructions, and finally the actual memory capacity of the storage device is determined by comparing at least two first data and the pre-written target data, and then the memory address mapping relationship of the storage device can be reconfigured based on the target mapping relationship corresponding to the actual memory capacity, so that the memory address mapping relationship matches the actual memory capacity, and the accuracy of the data read and write operation for the storage device is ensured. In addition, the address mapping method provided by the embodiment of the present invention does not need to rewrite the address mapping relationship code or compile and generate firmware when the storage device is applied to different applications of the same chip or ASIC and the memory capacity needs to be adjusted. The actual memory capacity of the storage device can be identified through write instructions and read instructions, and then the correct memory address mapping relationship can be reconfigured based on the target mapping relationship, thereby improving the address mapping efficiency and reducing the complexity of version management. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 It is a flowchart of the steps of an address mapping method for a storage device provided by an embodiment of the present invention;

[0051] Figure 2 It is a schematic diagram of row address line configuration of a 2GB storage device provided by an embodiment of the present invention;

[0052] Figure 3It is a schematic diagram of row address line configuration of a 1GB storage device provided by an embodiment of the present invention;

[0053] Figure 4 It is a schematic diagram of row address line configuration of a 512MB storage device provided by an embodiment of the present invention;

[0054] Figure 5 It is a schematic diagram of specific steps of an address mapping method for a storage device provided by an embodiment of the present invention;

[0055] Figure 6 is a data interaction diagram of a storage device provided by an embodiment of the present invention;

[0056] Figure 7 It is a structural diagram of an address mapping device of a storage device provided by an embodiment of the present invention;

[0057] Figure 8 It is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] Figure 1 is a flowchart of a method for address mapping of a storage device provided by an embodiment of the present invention. Figure 1 As shown, the method may include:

[0060] Step 101: write target data carried by the target write instruction into a storage device based on a target physical address indicated by the target write instruction; the number of address bits of the target physical address is the same as the number of address bits corresponding to the maximum memory capacity of the storage device.

[0061] In an embodiment of the present invention, the storage device may be a double data rate synchronous dynamic random access memory (Double Data Rate, DDR), and the storage device is arranged in an application specific integrated circuit (Application Specific Integrated Circuit, ASIC). The address line of the DDR particle of the storage device is composed of Bank Group (a logical grouping in the memory of the storage device), Bank (a storage unit in the logic of the storage device), Row (row), and Column (column). When the bit widths of Bank Group, Bank, Column, etc. are the same and the bit width of the data bus (DQ, Data Bus) is the same, the DDR memory capacity is determined by the Row address bit width, that is, by utilizing the difference in address line bit width caused by different capacities of DDR particles, the memory capacity of the storage device can be adjusted by configuring the Row address bit width of the storage device. For example, a DDR particle has a data bus (DQ, Data Bus) bit width of 16, and particles of different capacities have the same bit widths of Bank Group, Bank, Column, etc. The Row address of a 512MB DDR particle is A0-A14, the Row address of a 1GB DDR particle is A0-A15, and the Row address of a 2GB DDR particle is A0-A16.

[0062] When designing ASIC, since DDR can provide different memory capacities, the DDR physical interface needs to be compatible with different memory capacities and reserve address lines with the bit width corresponding to the maximum memory capacity, i.e. A0-A16. Then, memory address mapping can be performed based on different row address bit widths, so that the storage device can provide different memory capacities. For example, Figure 2 , 3 , 4, when the bit widths of the Bank Group, Bank, Column, etc. of the storage device are the same and the bit width of the data bus (DQ, DataBus) is the same, when according to Figure 2 When the row address lines are configured in the manner shown, the memory capacity of the storage device is 2GB; when the row address lines are configured in the manner shown, the memory capacity of the storage device is 2GB. Figure 3 When the row address lines are configured in the manner shown, the memory capacity of the storage device is 1 GB; when the row address lines are configured in the manner shown, the memory capacity of the storage device is 1 GB. Figure 4 When the row address lines are configured in the manner shown, the memory capacity of the storage device is 512MB.

[0063] In response to the target write instruction, the write operation indicated by the target write instruction is executed. The target write instruction carries the target data to be written to the storage device and the data storage address. The data storage address can be a user address (or logical address, virtual address). According to the pre-configured memory address mapping relationship between the user address and the memory address (physical address), the data storage address can be converted into a physical address, that is, the target physical address indicated by the target write instruction.

[0064] In an embodiment of the present invention, the storage device can provide different memory capacities, for example, the storage device can provide 512MB, 1GB or 2GB of memory capacity. Therefore, in the case where the actual memory capacity of the storage device is unclear, it can be assumed that the memory capacity of the storage device is the maximum memory capacity, and then in the scenario where the actual memory capacity of the storage device is any memory capacity, the valid information in the target physical address can be identified to write the target data to the corresponding address. Based on this, the number of address bits of the target physical address is set to be the same as the number of address bits corresponding to the maximum memory capacity supported by the storage device. In this way, since the number of row address bits of the memory capacity is proportional to the memory capacity, the smaller the memory capacity, the smaller the corresponding number of row address bits, and the number of row address bits that can be effectively identified by storage devices corresponding to different memory capacities is different. In the case where the actual memory capacity of the storage device is less than the maximum memory capacity, the storage device will only recognize the row address corresponding to the number of row address bits corresponding to the actual memory capacity in the target physical address (less than the number of address bits corresponding to the maximum memory capacity), that is, at least one address bit of the row address in the target physical address will not be recognized, and then the target data will be written into the identifiable physical address corresponding to the actual memory capacity, wherein the difference between the number of row address bits of the identifiable physical address corresponding to the actual memory capacity and the number of row address bits of the target physical address is at least 1. It can be understood that, since the number of identifiable row address bits of storage devices corresponding to different memory capacities is different, when storage devices with different memory capacities perform a write operation in response to a target write instruction, the target data will be actually written into 3 different physical addresses.

[0065] For example, assuming that the maximum memory capacity of the storage device is 2GB, since the row address of the storage device corresponding to the 2GB memory capacity is A0-A16, the row address of the target physical address is A0-A16. When the actual memory capacity of the storage device is 1GB, the storage device can effectively identify the A0-A15 row address of the target physical address, that is, the highest bit of the row address in the target physical address cannot be effectively identified. Therefore, when the storage device writes the target data, it will write data based on the A0-A15 row address in the target physical address. Correspondingly, when the actual memory capacity of the storage device is 512MB, the storage device can effectively identify the A0-A14 row address of the target physical address, that is, the highest bit and the second highest bit of the row address in the target physical address cannot be effectively identified. Therefore, when the storage device writes the target data, it will write data based on the A0-A14 row address in the target physical address.

[0066] Step 102: Based on the physical addresses corresponding to the data read addresses indicated by at least two target read instructions, read at least two first data from the storage device respectively; the physical addresses corresponding to the data read addresses indicated by the at least two target read instructions have different values ​​only in the same at least two row address bits and the at least two row address bits include the highest bit in the physical address and adjacent row address bits.

[0067] In an embodiment of the present invention, after the target data is written into the storage device, a read operation can be performed through at least two target read instructions. For any target read instruction, based on the physical address corresponding to the data read address indicated by the target read instruction, data is read from the storage device as the first data corresponding to the target read instruction. Wherein, the number of address bits of the physical address corresponding to the data read address indicated by at least two target read instructions is the same as the number of address bits of the target physical address, and the physical addresses corresponding to the data read addresses indicated by at least two target read instructions are different from each other. Specifically, each physical address has different values ​​corresponding to only the same at least two row address bits (the values ​​corresponding to the other address bits except at least two row address bits in each physical address are exactly the same), and at least two row address bits include the highest bit and adjacent address bits in the physical address. Wherein, the number of at least two row address bits depends on the number of identifiable row address bits corresponding to each memory capacity that the storage device can provide. Assuming that the number of identifiable row address bits corresponding to different memory capacities of the storage device is n, n-1, and n-2, respectively, the number of at least two row address bits can include two row address bits, namely the highest bit and the second highest bit of the row address. Exemplarily, when the storage device can provide a memory capacity of 512MB, 1GB or 2GB, and the corresponding number of identifiable row address bits is 14, 15, or 16, the number of at least two row address bits may include two row address bits, namely, the highest bit and the second highest bit of the row address. When the storage device can provide a memory capacity of 512MB, 1GB, 2GB or 4GB, and the corresponding number of identifiable row address bits is 14, 15, 16, or 17, the number of at least two row address bits may include three row address bits, namely, the highest bit of the row address and two row address bits adjacent to the highest bit. Similarly, since storage devices corresponding to different memory capacities can effectively identify different numbers of row address bits, the first data read out by at least two target read instructions may be the same or different depending on the actual memory capacity of the storage device.

[0068] Step 103: Determine the actual memory capacity of the storage device based on the at least two first data and the target data.

[0069] In an embodiment of the present invention, by controlling the different values ​​of at least two row address bits in the physical address, the actual memory capacity of the storage device can be determined based on the characteristics of different numbers of identifiable row address bits corresponding to different memory capacities of the storage device, based on the target data and at least two first data read in response to at least two target read instructions.

[0070] Step 104: reconfigure the memory address mapping relationship of the storage device based on the target mapping relationship corresponding to the actual memory capacity.

[0071] In an embodiment of the present invention, based on the target mapping relationship corresponding to the predefined actual memory capacity, the memory address mapping relationship of the storage device is reconfigured so that the storage device enters a normal working state. Specifically, the values ​​of the declaration parameters (ddr_cap) corresponding to different memory capacities can be preconfigured, and different values ​​represent configurations based on different memory address mapping relationships. After determining the actual memory capacity, the declaration parameters are configured in the address mapping register based on the values ​​corresponding to the actual memory capacity, so that the memory address mapping relationship of the storage device is the target mapping relationship. Exemplarily, assuming that the storage device can provide 512MB, 1GB or 2GB of memory capacity, it can be set that when the declaration parameter (ddr_cap) = 2, the memory address mapping relationship corresponding to the 2GB memory capacity is selected as the target mapping relationship for configuration, when the declaration parameter (ddr_cap) = 1, the memory address mapping relationship corresponding to the 1GB memory capacity is selected as the target mapping relationship for configuration, and when the declaration parameter (ddr_cap) = 0, the memory address mapping relationship corresponding to the 512MB memory capacity is selected as the target mapping relationship for configuration.

[0072] To summarize, in an embodiment of the present invention, based on the target physical address indicated by the target write instruction, the target data carried by the target write instruction is written to the storage device; the number of address bits of the target physical address is the same as the number of address bits corresponding to the maximum memory capacity of the storage device; based on the physical addresses corresponding to the data read addresses indicated by at least two target read instructions, at least two first data are read from the storage device respectively; the physical addresses corresponding to the data read addresses indicated by at least two target read instructions have different values ​​only in the same at least two row address bits and at least two row address bits contain the highest bit in the physical address and adjacent row address bits; based on the at least two first data and the target data, the actual memory capacity of the storage device is determined; based on the target mapping relationship corresponding to the actual memory capacity, the memory address mapping relationship of the storage device is reconfigured. In this way, the target data is first written into the storage device based on the target physical address with the same number of address bits as the maximum memory capacity, and then the characteristic that different memory capacities of the storage device correspond to different numbers of identifiable row address bits is utilized, and at least two first data are read from the storage device by adjusting at least two row address bits of at least two target read instructions, and finally the actual memory capacity of the storage device is determined by comparing at least two first data and the pre-written target data, and then the memory address mapping relationship of the storage device can be reconfigured based on the target mapping relationship corresponding to the actual memory capacity, so that the memory address mapping relationship matches the actual memory capacity, and the accuracy of the data read and write operation for the storage device is ensured. In addition, the address mapping method provided by the embodiment of the present invention does not need to rewrite the address mapping relationship code or compile and generate firmware when the storage device is applied to different applications of the same chip or ASIC and the memory capacity needs to be adjusted. The actual memory capacity of the storage device can be identified through write instructions and read instructions, and then the correct memory address mapping relationship can be reconfigured based on the target mapping relationship, thereby improving the address mapping efficiency and reducing the complexity of version management.

[0073] Optionally, before step 101, the embodiment of the present invention may include the following steps:

[0074] Step 201: Pre-configure memory mapping relationships corresponding to different memory capacities corresponding to the storage device.

[0075] In the embodiment of the present invention, memory mapping relationships corresponding to different memory capacities are configured in advance. Specifically, the values ​​of declaration parameters (ddr_cap) corresponding to different memory capacities can be configured in advance, and different values ​​represent configurations based on different memory address mapping relationships.

[0076] Step 202: Determine the maximum memory capacity corresponding to the storage device.

[0077] Step 203: Based on the first memory mapping relationship corresponding to the maximum memory capacity, perform memory address mapping on the storage device.

[0078] In an embodiment of the present invention, the maximum memory capacity that a storage device can provide is determined, and based on the first memory mapping relationship corresponding to the maximum memory capacity, the memory address of the storage device is mapped. Specifically, the value of the declaration parameter corresponding to the maximum memory capacity can be determined, and the declaration parameter is configured in the address mapping register based on the value corresponding to the maximum memory capacity. The configuration of the memory address mapping relationship is actually implemented based on the controller of the storage device. After the declaration parameter is configured in the address mapping register, the controller will complete the memory address mapping configuration of the storage device based on the corresponding memory mapping relationship. As is customary, the user address corresponding to the 2GB memory capacity is 31 bits in total (bit30~bit0). The user address bit30 can be mapped to the 16th bit of the row address (the highest bit of the row address), and the user address bit29 can be mapped to the 15th bit of the row address (the second highest bit of the row address). The other address bits can be mapped one-to-one to other row addresses, column addresses, Bank addresses, and BG addresses.

[0079] Optionally, it is assumed that the storage device can provide 3 memory capacities (first capacity, second capacity and third capacity), wherein the first capacity is less than the second capacity, the second capacity is less than the third capacity (maximum memory capacity), and the number of identifiable row address bits corresponding to each memory capacity can form an arithmetic progression with a difference of 1. For example, the storage device can provide a memory capacity of 512MB, 1GB or 2GB, and the number of identifiable row address bits corresponding to each memory capacity is 14, 15, and 16, respectively. Then at least two target instructions may include a first read instruction, a second read instruction and a third read instruction. The first read instruction, the second read instruction and the third read instruction have different corresponding values ​​on the highest bit and the second highest bit of the row address. Exemplarily, the highest bit of the row address of the first read instruction is different from the highest bit of the row address of the second read instruction, the second highest bit of the row address of the first read instruction is the same as the second highest bit of the row address of the second read instruction, and the highest bit of the row address and the second highest bit of the row address of the first read instruction are different from the highest bit of the row address and the second highest bit of the row address of the third read instruction.

[0080] Step 301, based on the first physical address corresponding to the first address indicated by the first read instruction, read the first data corresponding to the first read instruction from the storage device; the first physical address is the same as the target physical address, and the highest bit and the second highest bit of the row address corresponding to the first physical address and the target physical address are 1.

[0081] In an embodiment of the present invention, a read operation is initiated based on a first read instruction, and data is read from a storage device based on a first physical address corresponding to a first address indicated by the first read instruction as the first data corresponding to the first read instruction, and the first data corresponding to the first read instruction is written into a cache register. The first physical address corresponding to the first address is the same as the target physical address, and the values ​​of the highest bit and the second highest bit of the row address corresponding to the first physical address and the target physical address can be 1. By keeping the first physical address consistent with the target physical address, the first data read by the first read instruction can be completely consistent with the target data written by the target write instruction regardless of the actual memory capacity of the storage device. Then, by adjusting the values ​​of the highest bit and the second highest bit of the row address of the second read instruction and the third read instruction, and taking the first data read by the first read instruction as the standard, it is possible to determine whether the read data is consistent with the first data read by the first read instruction, and thus the actual memory capacity of the storage device can be determined.

[0082] Step 302: based on the second physical address corresponding to the second address indicated by the second read instruction, read the first data corresponding to the second read instruction from the storage device; the value of the highest bit of the row address in the second physical address is 0, and the second physical address is the same as the first physical address in terms of the values ​​of the other row address bits except the highest bit of the row address.

[0083] In an embodiment of the present invention, a read operation is initiated again based on the second read instruction, and data is read from the storage device based on the second physical address corresponding to the second address indicated by the second read instruction as the first data corresponding to the second read instruction, and the first data corresponding to the second read instruction is written into the cache register. Among them, the value of the highest bit of the row address in the second physical address is 0, and the values ​​of the other address bits except the highest bit of the row address are the same as the values ​​of the other address bits except the highest bit of the row address of the first physical address. In other words, the second physical address and the first physical address differ only in the value of the highest bit of the row address, and the values ​​of the other address bits are exactly the same.

[0084] By setting the highest bit of the row address of the second physical address to 0, the other address bits are the same as the first physical address. In this way, when the actual memory capacity of the storage device is the first capacity, the storage device cannot identify the highest bit and the second highest bit of the row address. Therefore, regardless of the value of the highest bit and the second highest bit of the row address, the first data read by the storage device based on the first read instruction and the first data read based on the second read instruction are the same. When the actual memory capacity of the storage device is the second capacity, the storage device cannot identify the highest bit of the row address. At this time, since the second physical address and the first physical address are different only in the value of the highest bit of the row address, the values ​​of the other address bits are exactly the same, then the first data read by the storage device based on the first read instruction and the first data read based on the second read instruction are also the same. When the actual memory capacity of the storage device is the third capacity, the storage device can identify all the row address bits in the physical address, but due to the difference in the value of the highest bit of the row address, the first data read by the storage device based on the first read instruction and the first data read based on the second read instruction are different.

[0085] Step 303: Based on the third physical address corresponding to the third address indicated by the third read instruction, read the first data corresponding to the third read instruction from the storage device; the highest bit and the second highest bit of the row address in the third physical address are 0, and the third physical address is the same as the first physical address in terms of the values ​​of the other row address bits except the highest bit and the second highest bit of the row address.

[0086] In an embodiment of the present invention, a read operation is performed based on a third read instruction, and data is read from a storage device based on a third physical address corresponding to the bottom order address indicated by the third read instruction as the first data corresponding to the third read instruction, and the first data corresponding to the third read instruction is written into a cache register. Among them, the values ​​of the highest bit and the second highest bit of the row address of the third physical address are 0, and the third physical address and the first physical address have the same values ​​of the other row address bits except for the highest bit and the second highest bit of the row address. In other words, the third physical address and the first physical address differ only in the values ​​of the highest bit and the second highest bit of the row address, and the values ​​of the other address bits are exactly the same.

[0087] It can be understood that the number of address bits of the first physical address, the second physical address and the third physical address is the same as the number of address bits of the target physical address, that is, the number of address bits of the first physical address, the second physical address, the third physical address and the target physical address depends on the number of address bits corresponding to the maximum memory capacity of the storage device.

[0088] By setting the highest bit and the second highest bit of the row address of the third physical address to 0, the first data read by the third read instruction is the same regardless of whether the actual memory capacity of the storage device is the first capacity, the second capacity or the third capacity. However, when the actual memory capacity of the storage device is the first capacity, assuming that the first data read by the third read instruction is a, since the storage device cannot identify the highest bit and the second highest bit of the row address in the physical address, the first data read based on the first read instruction and the first data read based on the second read instruction are also a. When the actual memory capacity of the storage device is the second capacity, since the storage device cannot identify the highest bit of the row address in the physical address, the first data read based on the third read instruction is a, and the first data read based on the first read instruction and the first data read based on the second read instruction are b. When the actual memory capacity of the storage device is the third capacity, since the storage device can identify all the row address bits in the physical address, the first data read based on the third read instruction is a, the first data read based on the second read instruction is b, and the first data read based on the first read instruction is c. It can be understood that based on the description of the data read by the read instructions under the above different memory capacities, the actual memory capacity of the storage device can be inferred based on the first data read by the first read instruction, the second read instruction and the third read instruction.

[0089] Optionally, step 103 may include the following steps:

[0090] Step 401: When the first data corresponding to the first read instruction is equal to the target data, the first data corresponding to the second read instruction and the first data corresponding to the third read instruction are equal, determine that the actual memory capacity of the storage device is the first capacity.

[0091] Step 402: When the first data corresponding to the first read instruction is equal to the target data and the first data corresponding to the second read instruction and is not equal to the first data corresponding to the third read instruction, determine that the actual memory capacity of the storage device is the second capacity.

[0092] Step 403: When the first data corresponding to the first read instruction is the same as the target data and the first data corresponding to the second read instruction and the first data corresponding to the third read instruction are not equal, determine that the actual memory capacity of the storage device is the third capacity; the first capacity is smaller than the second capacity, and the second capacity is smaller than the third capacity.

[0093] In an embodiment of the present invention, when the first data corresponding to the first read instruction is equal to the target data, the first data corresponding to the second read instruction, and the first data corresponding to the third read instruction are all equal, the actual memory capacity of the storage device is determined to be the first capacity (minimum capacity); when the first data corresponding to the first read instruction is equal to the target data and the first data corresponding to the second read instruction is equal to the first data corresponding to the third read instruction, the actual memory capacity of the storage device is determined to be the second capacity; when the first data corresponding to the first read instruction is the same as the target data and the first data corresponding to the second read instruction and the first data corresponding to the third read instruction are all unequal, the actual memory capacity of the storage device is determined to be the third capacity.

[0094] For example, Figure 5 A schematic diagram of specific steps of an address mapping method for a storage device is shown. Figure 5 As shown, it is assumed that the ASIC chip can support a single DDR4 particle (i.e., storage device) of DQ16, whose Row address width is 17 bits, Column address width is 10 bits, Bank Group address width is 2 bits, and Bank address width is 2 bits. The memory capacity that this specification of DDR4 particles can provide is: 2GB, 1GB, 512MB. The method for memory capacity detection and address mapping for this DDR includes the following steps:

[0095] S001, pre-write the memory address mapping relationships corresponding to three memory capacities in the firmware, corresponding to 2GB, 1GB, and 512MB respectively. The steps are as follows: configure the declaration parameter ddr_cap, and set its initial value to 2. Among them, when ddr_cap=2, select the memory address mapping relationship corresponding to the 2GB memory capacity, when ddr_cap=1, select the memory address mapping relationship corresponding to the 1GB memory capacity, and when ddr_cap=0, select the memory address mapping relationship corresponding to the 512MB memory capacity. Among them, the 2GB memory address mapping relationship may include: the 27th bit of the AXI address is mapped to the 16th bit of the DDR Row address, the 23rd bit of the AXI address is mapped to the 15th bit of the DDR Row address, etc.;

[0096] S002, during the DDR initialization process, first configure according to the 2GB address mapping relationship, wait for the DDR initialization to be completed, and enter the DDR readable and writable state;

[0097] S003, entering the DDR capacity detection process, first, the algorithm initiates an AXI write operation, and its main signals are: waddr = 0x08800000, wdata = 0xA5A55A5A, wsize = 0x2, wlen = 0x0;

[0098] S004, after waiting for S003 to complete, the algorithm initiates the first AXI read operation, whose main signals are: raddr = 0x08800000, rsize = 0x2, rlen = 0x0, waits for the read operation to complete, records the read data as data0, and caches it;

[0099] S005, after waiting for S004 to complete, the algorithm initiates the second AXI read operation, whose main signals are: raddr = 0x00800000, rsize = 0x2, rlen = 0x0, waits for the read operation to complete, records the read data as data1, and caches it;

[0100] S006, after waiting for S005 to complete, the algorithm initiates the third AXI read operation, whose main signals are: raddr = 0x00000000, rsize = 0x2, rlen = 0x0, waits for the read operation to complete, records the read data as data2, and caches it;

[0101] S007, data interpretation, compare data1, data2 and data0;

[0102] S008, if data0=data1, and data0=data2, and data0=0xA5A55A5A, then the capacity recognition result is 512MB, the parameter ddr_cap is set to 0, the algorithm ends, and jumps to S012;

[0103] S009, if S008 is not true, and data0 = data1, and data0 ≠ data2, and data0 = 0xA5A55A5A, then the capacity recognition result is 1GB, the parameter ddr_cap is set to 1, the algorithm ends, and jumps to S012;

[0104] S010, if S008 and S009 are not true, and data0 = 0xA5A55A5A, then the capacity recognition result is 2GB, the parameter ddr_cap is set to 2, the algorithm ends, and jumps to S012;

[0105] S011, if S008, S009, and S010 are all not true, the algorithm ends, and the DDR read and write functions are checked, or DDR is initialized again;

[0106] S012, according to the value of parameter ddr_cap, select the appropriate memory address mapping for configuration;

[0107] S013, DDR enters normal working state.

[0108] For example, Figure 6A schematic diagram of data interaction of a storage device is shown. Figure 6 In the figure, APB BUS is the register configuration interface, and the address mapping relationship can be configured through this interface; AXI BUS is the interface for users to access storage devices (i.e., DDR particles), and it is connected to the storage devices (i.e., DDR particles) through the DDR PHY of the DDR controller; CTRL BUS is the DDR control bus, and the initialization, read, write, refresh and other operations of the storage device (i.e., DDR particles) are sent to the storage device (i.e., DDR particles) through this interface; ADDR BUS is the DDR address bus, and the memory address of the read and write operations is sent to the storage device (i.e., DDR particles) through this bus; DQ BUS is the DDR data bus, and read and write data are transmitted through this bus.

[0109] Figure 7 is a schematic diagram of the structure of an address mapping device for a storage device provided by an embodiment of the present invention, such as Figure 7 As shown, the device may specifically include:

[0110] A first writing module 501 is used to write the target data carried by the target write instruction into the storage device based on the target physical address indicated by the target write instruction; the number of address bits of the target physical address is the same as the number of address bits corresponding to the maximum memory capacity of the storage device;

[0111] The first reading module 502 comprises reading at least two first data from the storage device respectively based on the physical addresses corresponding to the data reading addresses indicated by at least two target read instructions; the physical addresses corresponding to the data reading addresses indicated by the at least two target read instructions have different values ​​only in the same at least two row address bits, and the at least two row address bits include the highest bit in the physical address and adjacent row address bits;

[0112] A first determining module 503, configured to determine an actual memory capacity of the storage device based on the at least two first data and the target data;

[0113] The first configuration module 504 is used to reconfigure the memory address mapping relationship of the storage device based on the target mapping relationship corresponding to the actual memory capacity.

[0114] An embodiment of the present invention provides an address mapping device for a storage device, which writes target data carried by a target write instruction into the storage device based on a target physical address indicated by a target write instruction; the number of address bits of the target physical address is the same as the number of address bits corresponding to the maximum memory capacity of the storage device; based on the physical addresses corresponding to the data read addresses indicated by at least two target read instructions, at least two first data are read from the storage device respectively; the physical addresses corresponding to the data read addresses indicated by at least two target read instructions have different values ​​only on the same at least two row address bits and at least two row address bits contain the highest bit in the physical address and adjacent row address bits; based on the at least two first data and the target data, the actual memory capacity of the storage device is determined; based on the target mapping relationship corresponding to the actual memory capacity, the memory address mapping relationship of the storage device is reconfigured. In this way, the target data is first written into the storage device based on the target physical address with the same number of address bits as the maximum memory capacity, and then the characteristic that different memory capacities of the storage device correspond to different numbers of identifiable row address bits is utilized, and at least two first data are read from the storage device by adjusting at least two row address bits of at least two target read instructions, and finally the actual memory capacity of the storage device is determined by comparing at least two first data and the pre-written target data, and then the memory address mapping relationship of the storage device can be reconfigured based on the target mapping relationship corresponding to the actual memory capacity, so that the memory address mapping relationship matches the actual memory capacity, and the accuracy of the data read and write operation for the storage device is ensured. In addition, the address mapping method provided by the embodiment of the present invention does not need to rewrite the address mapping relationship code or compile and generate firmware when the storage device is applied to different applications of the same chip or ASIC and the memory capacity needs to be adjusted. The actual memory capacity of the storage device can be identified through write instructions and read instructions, and then the correct memory address mapping relationship can be reconfigured based on the target mapping relationship, thereby improving the address mapping efficiency and reducing the complexity of version management.

[0115] Optionally, the device may further include:

[0116] A second configuration module is used to pre-configure a memory mapping relationship corresponding to each memory capacity according to different memory capacities corresponding to the storage device;

[0117] A second determination module, used to determine the maximum memory capacity corresponding to the storage device;

[0118] The first mapping module is used to perform memory address mapping on the storage device based on a first memory mapping relationship corresponding to the maximum memory capacity.

[0119] Optionally, the at least two target read instructions include a first read instruction; and the first read module 502 includes:

[0120] A first read submodule is used to read the first data corresponding to the first read instruction from the storage device based on the first physical address corresponding to the first address indicated by the first read instruction; the first physical address is the same as the target physical address, and the highest bit and the second highest bit of the row address corresponding to the first physical address and the target physical address have values ​​of 1.

[0121] Optionally, the at least two target read instructions further include a second read instruction; and the first read module 502 further includes:

[0122] A second reading submodule is used to read the first data corresponding to the second read instruction from the storage device based on the second physical address corresponding to the second address indicated by the second read instruction; the value of the highest bit of the row address in the second physical address is 0, and the second physical address and the first physical address have the same numerical value of other row address bits except the highest bit of the row address.

[0123] Optionally, the at least two target read instructions further include a third read instruction; and the first read module 502 further includes:

[0124] A third reading submodule is used to read the first data corresponding to the third read instruction from the storage device based on the third physical address corresponding to the third address indicated by the third read instruction; the highest bit and the second highest bit of the row address in the third physical address are 0, and the third physical address is the same as the first physical address in terms of the values ​​of the other row address bits except the highest bit and the second highest bit of the row address.

[0125] Optionally, the first determining module 503 includes:

[0126] A first determination submodule, configured to determine that the actual memory capacity of the storage device is a first capacity when the first data corresponding to the first read instruction is equal to the target data, the first data corresponding to the second read instruction, and the first data corresponding to the third read instruction are equal;

[0127] A second determination submodule, configured to determine that the actual memory capacity of the storage device is a second capacity when the first data corresponding to the first read instruction is equal to the target data and the first data corresponding to the second read instruction and is not equal to the first data corresponding to the third read instruction;

[0128] A third determination submodule, configured to determine that the actual memory capacity of the storage device is a third capacity when the first data corresponding to the first read instruction is the same as the target data and the first data corresponding to the second read instruction and the first data corresponding to the third read instruction are not equal;

[0129] The fourth determining submodule is used to determine that the first capacity is smaller than the second capacity, and the second capacity is smaller than the third capacity.

[0130] The present invention also provides an electronic device, see Figure 8 , including: a processor 601, a memory 602, and a computer program 6021 stored in the memory and executable on the processor, wherein when the processor executes the program, the address mapping method of the storage device of the foregoing embodiment is implemented.

[0131] The present invention also provides a readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the address mapping method of the storage device of the foregoing embodiment.

[0132] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0133] The algorithm and display provided herein are not inherently related to any particular computer, virtual system or other device. Various general purpose systems can also be used together with the teachings based on this. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the present invention is not directed to any specific programming language either. It should be understood that various programming languages ​​can be utilized to realize the content of the present invention described herein, and the description of the above specific languages ​​is for disclosing the best mode of the present invention.

[0134] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0135] Similarly, it should be understood that in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: that the claimed invention requires more features than the features explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0136] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0137] The various component embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or digital signal processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention may also be implemented as a device or apparatus program for executing part or all of the methods described herein. Such a program for implementing the present invention may be stored on a computer-readable medium, or may be in the form of one or more signals. Such a signal may be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0138] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0139] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0140] It should be noted that all actions of acquiring signals, information or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where they are located and with the authorization given by the owner of the corresponding device.

[0141] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

[0142] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for address mapping of a storage device, characterized in that: The method comprises: Based on the target physical address indicated by the target write instruction, writing the target data carried by the target write instruction into the storage device; the number of address bits of the target physical address is the same as the number of address bits corresponding to the maximum memory capacity of the storage device; Based on the physical addresses corresponding to the data read addresses indicated by at least two target read instructions, at least two first data are read from the storage device respectively; the physical addresses corresponding to the data read addresses indicated by the at least two target read instructions have different values ​​corresponding to the same at least two row address bits, and the at least two row address bits include the highest bit in the physical address and adjacent row address bits; Determining an actual memory capacity of the storage device based on the at least two first data and the target data; Based on the target mapping relationship corresponding to the actual memory capacity, the memory address mapping relationship of the storage device is reconfigured.

2. The method according to claim 1, characterized in that Before writing the target data carried by the target write instruction into the target address indicated by the target write instruction in the storage device based on the target write instruction, the method includes: Pre-configuring memory mapping relationships corresponding to different memory capacities corresponding to the storage device; Determine the maximum memory capacity corresponding to the storage device; Based on a first memory mapping relationship corresponding to the maximum memory capacity, memory address mapping is performed on the storage device.

3. The method according to claim 1, characterized in that The at least two target read instructions include a first read instruction; and the at least two first data are read from the storage device based on the physical addresses corresponding to the data read addresses indicated by the at least two target read instructions, respectively, including: Based on the first physical address corresponding to the first address indicated by the first read instruction, the first data corresponding to the first read instruction is read from the storage device; the first physical address is the same as the target physical address, and the highest bit and the second highest bit of the row address corresponding to the first physical address and the target physical address have values ​​of 1.

4. The method according to claim 3, characterized in that The at least two target read instructions further include a second read instruction; and the at least two first data are read from the storage device based on the physical addresses corresponding to the data read addresses indicated by the at least two target read instructions, respectively, and further include: Based on the second physical address corresponding to the second address indicated by the second read instruction, the first data corresponding to the second read instruction is read from the storage device; the value of the highest bit of the row address in the second physical address is 0, and the second physical address and the first physical address have the same numerical value of other row address bits except the highest bit of the row address.

5. The method according to claim 4, characterized in that The at least two target read instructions further include a third read instruction; and the at least two first data are read from the storage device based on the physical addresses corresponding to the data read addresses indicated by the at least two target read instructions, respectively, and further include: Based on the third physical address corresponding to the third address indicated by the third read instruction, the first data corresponding to the third read instruction is read from the storage device; the highest bit and the second highest bit of the row address in the third physical address are 0, and the third physical address is the same as the first physical address in terms of the values ​​of the other row address bits except the highest bit and the second highest bit of the row address.

6. The method according to claim 5, characterized in that The determining the actual memory capacity of the storage device based on the at least two first data and the target data includes: When the first data corresponding to the first read instruction is equal to the target data, the first data corresponding to the second read instruction, and the first data corresponding to the third read instruction are equal, determining that the actual memory capacity of the storage device is the first capacity; When the first data corresponding to the first read instruction is equal to the target data and the first data corresponding to the second read instruction and is not equal to the first data corresponding to the third read instruction, determining that the actual memory capacity of the storage device is the second capacity; When the first data corresponding to the first read instruction is the same as the target data and the first data corresponding to the second read instruction and the first data corresponding to the third read instruction are not equal, determining that the actual memory capacity of the storage device is the third capacity; The first capacity is smaller than the second capacity, and the second capacity is smaller than the third capacity.

7. The method according to claim 6, characterized in that The first capacity is 512 MB, the second capacity is 1 GB, and the first capacity is 2 GB.

8. An address mapping device for a storage device, characterized in that: The device comprises: A first writing module, configured to write target data carried by the target write instruction into a storage device based on a target physical address indicated by the target write instruction; the number of address bits of the target physical address is the same as the number of address bits corresponding to the maximum memory capacity of the storage device; A first reading module comprises reading at least two first data from the storage device respectively based on physical addresses corresponding to data reading addresses indicated by at least two target read instructions; the physical addresses corresponding to the data reading addresses indicated by the at least two target read instructions have different values ​​corresponding to at least two same row address bits, and the at least two row address bits include the highest bit in the physical address and adjacent row address bits; A first determining module, configured to determine an actual memory capacity of the storage device based on the at least two first data and the target data; The first configuration module is used to reconfigure the memory address mapping relationship of the storage device based on the target mapping relationship corresponding to the actual memory capacity.

9. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the address mapping method for a storage device as claimed in any one of claims 1 to 7 when executing the program.

10. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the address mapping method for a storage device as described in any one of claims 1 to 7.

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