Memory management method, device and equipment and readable storage medium

Abstract

The embodiment of the invention provides a memory management method and device, equipment and a readable storage medium, and the method comprises the steps: obtaining a to-be-applied first memory capacity, and determining a first offset sequence corresponding to the first memory capacity; a positive correlation exists between the first memory capacity and the number of offsets in the first offset sequence; starting from a first offset in the first offset sequence, according to the first offset, offsetting a bit of a preset register, and based on the register value before offset and the register value after offset, obtaining a register update value; each bit is used for representing that the corresponding memory area is in an idle state or an occupied state; on the basis of the register update value, continuing the next offset until the first offset sequence is traversed, and determining a final first register value; and encoding the first register value to obtain a first memory address corresponding to the first register value. The memory management efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory management method, device, electronic device and readable storage medium. Background Art

[0002] Dynamic memory management is a technology that allocates and releases memory while a program is running. Dynamic memory management can handle memory requirements of different sizes and life cycles, avoiding the rigidity of static memory allocation, improving program performance, and having a significant impact on system stability and performance.

[0003] In the related technology, the dynamic memory allocation mechanism is implemented based on the software module, and various existing dynamic memory management algorithms, such as the malloc and free functions of the C language, are implemented at the software level. These functions will apply for memory from the operating system, allocate memory, and perform other dynamic memory management operations.

[0004] However, in the related art, dynamic memory management is performed by software. Compared with hardware implementation, the dynamic memory allocation mechanism implemented by these software is still slower in processing speed and lower in efficiency. Summary of the invention

[0005] The embodiments of the present invention provide a memory management method, device, electronic device and readable storage medium, which can solve the problem of low efficiency of dynamic memory allocation mechanism implemented by software in related technologies.

[0006] In order to solve the above problems, an embodiment of the present invention discloses a memory management method, which includes: Acquire a first memory capacity to be applied for, and determine a first offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the first offset sequence; there is an increasing relationship between the offsets in the first offset sequence; Starting from the first offset in the first offset sequence, the bits of the preset register are offset according to the first offset, and a register update value is obtained based on the register value before the offset and the register value after the offset; the register value is determined by multiple bits of the register; each bit is used to indicate that the corresponding memory area is in an idle state or an occupied state; Based on the register update value, continue the next offset until the first offset sequence is traversed and a final first register value is determined; The first register value is encoded to obtain a first memory address corresponding to the first register value; the first memory address is a starting address to be allocated.

[0007] On the other hand, an embodiment of the present invention further discloses a memory management device, the device comprising: an application sequence module, configured to obtain a first memory capacity to be applied for, and determine a first offset sequence corresponding to the first memory capacity; a positive correlation exists between the first memory capacity and the number of offsets in the first offset sequence; and an increasing relationship exists between the offsets in the first offset sequence; An iterative offset module, configured to start from a first offset in the first offset sequence, offset the bits of a preset register according to the first offset, and obtain a register update value based on the register value before the offset and the register value after the offset; the register value is determined by a plurality of bits of the register; each bit is used to indicate that the corresponding memory area is in an idle state or an occupied state; An iteration result module, configured to update the register value, continue the next offset until the first offset sequence is traversed and completed, and determine a final first register value; The address allocation module is used to encode the first register value to obtain a first memory address corresponding to the first register value; the first memory address is a starting address to be allocated.

[0008] An embodiment of the present invention also discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned memory management method.

[0009] An embodiment of the present invention further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned memory management method.

[0010] The embodiment of the present invention includes the following advantages: obtaining the first memory capacity to be applied, determining the first offset sequence corresponding to the first memory capacity, starting from the first offset in the first offset sequence, offsetting the bits of the preset register according to the first offset, and obtaining the register update value based on the register value before the offset and the register value after the offset, continuing the next offset based on the register update value until the first offset sequence is traversed, and determining the final first register value, encoding the first register value, and obtaining the starting address to be allocated corresponding to the first register value. Based on the bit offset update of the register, the free memory corresponding to the first memory capacity and the starting address of the free memory can be calculated and determined, and the memory application processing at the hardware level can be realized. Since the hardware processing speed is fast, the efficiency of memory management is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0012] Figure 1 It is a step diagram of a memory management method of the present invention; Figure 2 is a step diagram of another memory management method of the present invention; Figure 3 is a structural block diagram of a memory management device of the present invention; Figure 4 It is a structural block diagram of an electronic device for memory management of the present invention. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0015] Dynamic memory refers to a mechanism that dynamically allocates and reclaims memory based on requests during operation. Generally, an application makes a memory request, and the application specifies the required memory size. The dynamic memory management system finds a memory size not less than this size in the free memory, returns the starting address to the application layer, and also needs to set the memory to an occupied state. When the application needs to release the specified memory interval, the dynamic memory management system should set this interval to an idle state to complete the release, so that it can be used for subsequent applications.

[0016] Method Embodiment Figure 1 It is a step diagram of a memory management method of the present invention, the method comprising: Step 101, obtaining a first memory capacity to be applied for, and determining a first offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the first offset sequence.

[0017] In an embodiment of the present invention, the steps of the memory management method may be performed by other controllers other than the processor. The memory may be requested by an application or a software module of an operating system. For example, a file system requests memory to cache file contents and index nodes; a device driver may request memory to temporarily store data received from a hardware device or sent to a hardware device; and a network driver needs to request memory to store network data packets when receiving the data packets.

[0018] According to the memory application of the application program or the software module of the operating system, the memory application may carry the required memory size, so that the first memory capacity to be applied is determined based on the memory application.

[0019] Based on the first memory capacity of different sizes, a corresponding first offset sequence can be determined, and the first offset sequence includes at least one or more offsets. The first offset sequence can be determined by performing calculations based on the size of the first memory capacity, and can be calculated by the following formula: k = log2N In the above formula, k represents the number of offsets, N represents the size of the first memory capacity, and log2 represents the logarithm operation with base 2.

[0020] In addition, the offsets in the first offset sequence may be increasing in size, for example, they may be increasing based on a power of two. For example, when the number of offsets in the first offset sequence is 5, the 5 offsets in the first offset sequence are 1, 2, 4, 8, and 16, respectively, and so on. When the first memory capacity is larger, the number of offsets in the first offset sequence is, for example, 7, and the 7 offsets are 1, 2, 4, 8, 16, 32, and 64, respectively. The size of the first memory capacity and the first offset sequence are not specifically limited herein.

[0021] Step 102, starting from the first offset in the first offset sequence, according to the first offset, offset the bit of the preset register, and obtain the register update value based on the register value before the offset and the register value after the offset; the register value is determined by multiple bits of the register; each bit is used to indicate that the corresponding memory area is in an idle state or an occupied state.

[0022] In the embodiment of the present invention, the first offset sequence may include one or more offsets, and starting from the first offset in the first offset sequence, the bits of the preset register are offset based on the first offset.

[0023] The preset register may have multiple bits, each bit representing the state of a memory area of ​​a certain size, including an idle state and an occupied state. Thus, according to the multiple bits of the register, the state of each memory area in a larger memory is represented. Among them, a bit of 1 can represent an idle state, a bit of 0 can represent an occupied state, or other representations can be used. This is only an example and is not limited.

[0024] When the bits of a register are shifted according to the offset, all the bits of the register are shifted left or right as a whole. The shift will cause some changes in the register value. For example, the register value represented by the bits of the register is "001001110". If the offset is 2 and it is a left shift, the register value after the shift is "100111000". It should be noted that due to the left shift, the first two bits "00" are shifted out, and two bits "00" can be shifted in on the right as a supplement.

[0025] After completing a shift, a specific operation such as an AND operation can be performed based on the register value before the shift and the register value after the shift to obtain a register update value. For example, if the register value before the shift is "001001110" and the register value after the shift is "100111000", then after the AND operation, the register update value obtained is "000001000".

[0026] Step 103: Based on the register update value, continue the next offset until the first offset sequence is traversed and completed, and determine the final first register value.

[0027] In the embodiment of the present invention, if there is only one offset 2 in the first offset sequence, the obtained register update value is "000001000", which is the final first register value.

[0028] If there are multiple offsets in the first offset sequence, the next offset is continued based on the register update value. The offset process is similar, based on the bit represented by the register update value, the offset is performed based on the next offset, and the register value before the offset (i.e., the previous register update value) and the register value after the offset are obtained to obtain the next register update value. The specific process is not repeated here.

[0029] The traversal of the first offset sequence is completed, indicating that the corresponding bit shifts are completed based on each offset, and the final first register value can be determined.

[0030] When performing successive shifts based on each offset in the first offset sequence, each shift may be controlled based on a clock. For example, one shift is calculated at a rising edge of the clock, i.e., one step of iteration. When there are 7 offsets, the overall process may be as follows: First clock: F = F&(F<<1) Second clock: F = F&(F<<2) The third clock: F = F&(F<<4) 4th clock: F = F&(F<<8) The fifth clock: F = F&(F<<16) The sixth clock: F = F&(F<<32) 7th clock: F = F&(F<<64) In the above process, F is the preset register. The first clock indicates that the bit of register F is shifted left by 1 bit (<<1). The register value after the shift (F<<1) is obtained and the register value before the shift (F) is ANDed to obtain the register update value and assign it to register F. Then the shift process from the second clock to the seventh clock is continued.

[0031] Step 104: encode the first register value to obtain a first memory address corresponding to the first register value; the first memory address is a starting address to be allocated.

[0032] In an embodiment of the present invention, before performing an iterative offset, each bit of the register indicates that the corresponding memory area is in an idle state or an occupied state. After completing the iterative offset, each bit 1 in the first register value (if 1 indicates an idle state) can represent free memory of the first memory capacity at different locations. The first register value may include multiple 1s, that is, the memory includes multiple free memories of the first memory capacity.

[0033] The first register value may be encoded by inputting the first register value into an encoder circuit, encoding the first register value of the register into an address, and thereby obtaining a first memory address, where the first memory address is the starting address of a memory of the first memory capacity required by an application or other memory requester.

[0034] Thereby, the starting address of the memory to be allocated can be returned to the application so that the application can use the memory space to store data.

[0035] It should be noted that the starting address is the starting address of the memory of the first memory capacity size that is in an idle state, that is, starting from the starting address, the continuous memory of the first memory capacity size is idle and can be used by the memory applicant. This is because the register update value is obtained by performing an AND operation based on the register value before the offset and the register value after the offset. This process is essentially a checking or screening process, the purpose of which is to screen out the continuous free memory of the first memory capacity size.

[0036] For example, since each bit is used to indicate that the corresponding memory area is in an idle state or an occupied state, if the first bit is 1, it means that the memory area of ​​the first byte in the memory is idle, and the second bit is 0, it means that the memory area of ​​the second byte in the memory is occupied. Since the first bit is 1 and the second bit is 0, after shifting left by 1 bit, the new first bit is 0, and the AND operation with the original first bit 1 is performed, and the updated first bit is 0. Therefore, this 0 can be reversed to indicate that the original second bit or the original first bit is 0, so the memory corresponding to the original first bit and the second bit is not two consecutive idle areas, and therefore cannot be used as memory to be allocated to the memory applicant.

[0037] When applying for 128 bytes of memory, the offsets are 1, 2, 4, 8, 16, 32 and 64. After 7 offsets, in the final first register value, each bit that is 1 can represent a continuous 128 bytes of free memory. Then the memory address encoded based on this first register value is the memory address that can be used for allocation, and starting from this memory address, there are 128 bytes of free memory.

[0038] In addition, it can be understood that the preset register F or temporary register based on the above iterative offset can only bear the calculation function, and a special memory management register R can also be set up, and the bits of the memory management register R directly represent the idle state or occupied state of the corresponding memory. Before starting the offset, the temporary register F=R is set, so that the temporary register is assigned a value first, and then the iterative offset and calculation are completed based on the bits of the assigned temporary register.

[0039] In summary, the embodiment of the present invention is implemented to obtain the first memory capacity to be applied, determine the first offset sequence corresponding to the first memory capacity, start from the first offset in the first offset sequence, according to the first offset, offset the bit of the preset register, and based on the register value before the offset and the register value after the offset, obtain the register update value, based on the register update value, continue the next offset until the first offset sequence is traversed, and determine the final first register value, encode the first register value, and obtain the starting address to be allocated corresponding to the first register value. Based on the bit offset update of the register, the free memory corresponding to the first memory capacity and the starting address of the free memory can be calculated and determined, and the memory application at the hardware level can be realized. Since the hardware processing speed is fast, the efficiency of memory management is improved.

[0040] Figure 2 is a step diagram of another memory management method provided by an embodiment of the present invention, the method comprising: Step 201, obtaining a first memory capacity to be applied for, and determining a first offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the first offset sequence; there is an increasing relationship between the offsets in the first offset sequence; Step 202, starting from the first offset in the first offset sequence, offset the bits of the preset register according to the first offset, and obtain a register update value based on the register value before the offset and the register value after the offset; the register value is determined by multiple bits of the register; each bit is used to indicate that the corresponding memory area is in an idle state or an occupied state; Step 203, based on the register update value, continue the next offset until the first offset sequence is traversed and completed, and determine the final first register value; Step 204: encode the first register value to obtain a first memory address corresponding to the first register value; the first memory address is a starting address to be allocated.

[0041] For details of steps 201 to 204, please refer to the Figure 1 The embodiments are not described in detail here.

[0042] Optionally, after step 204 of encoding the first register value to obtain a first memory address corresponding to the first register value, the method further includes: Step 205, decoding the first memory address to obtain a second register value corresponding to the first memory address, and setting the bit of the register based on the second register value; Step 206, determining a second offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the second offset sequence; there is a decreasing relationship between the offsets in the second offset sequence; Step 207, starting from the first offset of the second offset sequence, shifting the bits of the register according to the first offset, and obtaining a register update value based on the register value before the shift and the register value after the shift; Step 208, based on the register update value, continue the next offset until the second offset sequence is traversed, and determine the final third register value to set the memory area indicated by the first memory address and the first memory capacity to an occupied state.

[0043] In an embodiment of the present invention, when dynamic memory management is performed, if the memory of a specific area has been applied for and allocated, the corresponding memory area needs to be marked to accurately track the status of the memory. In dynamic memory management, the memory may be in different states, such as occupied, idle, etc. By marking, it is possible to know which memory blocks are being used and which can be reallocated. Marking memory can help determine the appropriate location for the next memory allocation. In addition, if the memory is not marked correctly, it may cause the program to write data to the wrong location or access the memory that has been released. For example, if a piece of allocated memory is not marked, the program may accidentally allocate the memory block again, causing the data originally stored therein to be lost or overwritten.

[0044] A first memory address for allocation to a memory requester has been determined, and therefore a memory of a first memory capacity corresponding to the first memory address needs to be marked.

[0045] Since the present invention uses the bits of the register to indicate the idle state or occupied state of the memory, the bits of the register can be set to set the specific memory to the occupied state to complete the memory marking.

[0046] The first memory address is decoded to obtain a second register value corresponding to the first memory address. For example, the first memory address may be 5, and the decoded second register value may be "0b11111011111111...", where 0b represents a binary number, and the ellipsis indicates that the specific number of bits of the second register value is not limited. The 0 in the second register value represents an occupied state, and the 1 represents an idle state. It should be noted that if the first memory address is 5, the first 5 bits of the second register value are 1, and the 6th bit is 0, indicating an occupied state (that is, the memory is allocated).

[0047] The first memory capacity corresponds to a first offset sequence, and the first offset sequence is used to find a memory of the first memory capacity that is in an idle state. Similarly, a second offset sequence is determined based on the first memory capacity, and the second offset sequence is used to mark the memory of the first memory capacity as occupied.

[0048] There is also a positive correlation between the first memory capacity and the number of offsets in the second offset sequence, and the number of offsets in the second offset sequence can be calculated based on the same formula used to calculate the first offset sequence. However, the offsets in the second offset sequence can be decreasing, or can be decreasing based on a power of two. For example, if there are also seven offsets in the second offset sequence, they can be 64, 32, 16, 8, 4, 2, and 1.

[0049] Similarly, starting from the first offset of the second offset sequence, the bits of the offset register are shifted according to the first offset, and an AND operation is performed based on the register value before the shift and the register value after the shift to obtain the register update value.

[0050] The difference between the memory marking stage and the memory application stage is that the offset is decremented, not incremented. Decrement means that the initial offset is based on a larger offset, which can avoid duplication when setting the bit to 0 and improve the efficiency of memory marking. In addition, the shift bit in the memory marking stage can be right shifted, and the value shifted in from the left can be 1. The process of each shift in the memory marking stage will not be repeated here.

[0051] After traversing the second offset sequence, the memory of the first memory capacity corresponding to the first memory address can be marked as occupied, thereby completing the memory marking. Similarly, since the preset register F can be used only for iterative offset and operation, after traversing the second offset sequence, for the preset register F and the memory management register R. Through R = R&F, the register value of the preset register F and the register value of the memory management register R are ANDed. After traversing the second offset sequence, the register value of the preset register F, the bit corresponding to the allocated memory is 0, and after the AND operation, the corresponding bit of the memory management register R will also be set to 0, thereby completing the marking.

[0052] For example, the first memory address is A, and the first memory capacity to be marked is, for example, 128 bytes. The following iterative process needs to be completed in sequence under 7 clock pulses: 1st clock: F = F&(F>>64) Second clock: F = F&(F>>32) The third clock: F = F&(F>>16) 4th clock: F = F&(F>>8) 5th clock: F = F&(F>>4) 6th clock: F = F&(F>>2) 7th clock: F = F&(F>>1) In the above process, corresponding to the first clock, “>>64” indicates a right shift of 64 bits, (F>>64) is the register value after the right shift, and “F&(F>>64)” indicates an AND operation between the register value after the shift and the register value before the shift.

[0053] After the 7th clock, all 128 bits of register F starting from position A are set to 0. Finally, R= R&F is set to complete the memory marking and set the corresponding memory bit to occupied status.

[0054] In an embodiment of the present invention, the first memory address is decoded to obtain a second register value, and the bits of the register are set based on the second register value to determine a second offset sequence. Starting from the first offset of the second offset sequence, the bits of the register are offset until the second offset sequence is traversed, and a final third register value is determined to set the memory area indicated by the first memory address and the first memory capacity to an occupied state. Based on the iterative offset and operation of the bits of the register, fast memory marking at the hardware level can be achieved, thereby improving memory management efficiency.

[0055] Optionally, the method further includes: Step 209, obtaining a second memory address and a second memory capacity to be released, and determining a third offset sequence corresponding to the second memory capacity; there is a positive correlation between the second memory capacity and the number of offsets in the third offset sequence; there is a decreasing relationship between the offsets in the third offset sequence; Step 210, decoding the second memory address to obtain a fourth register value corresponding to the second memory address, and setting the bit of the register based on the fourth register value; Step 211, starting from the first offset of the third offset sequence, shifting the bits of the register according to the first offset, and obtaining a register update value based on the register value before the shift and the register value after the shift; Step 212, based on the register update value, continue the next offset until the third offset sequence is traversed, and determine the final fourth register value to set the memory area jointly indicated by the second memory address and the second memory capacity to an idle state.

[0056] In the embodiment of the present invention, when the application or its operating system software module has completed the use of a piece of memory and no longer needs to access the data stored in the memory, it is necessary to release the memory, that is, set the memory to an idle state. Releasing memory can avoid memory leaks and ensure the effective use of system resources. If it is not released in time, the program will occupy the memory throughout the entire running period.

[0057] A memory release request generated by an application or other memory user can be obtained, including a second memory address and a second memory capacity to be released. The second memory address indicates the starting address of the memory to be released, and the second memory capacity indicates the size of the memory to be released starting from the starting address.

[0058] Similarly, a third offset sequence corresponding to the second memory capacity is determined. The process of determining the third offset sequence may be similar to that of the second offset sequence. The offsets in the third offset sequence may be decreasing, and other details are not repeated here.

[0059] Based on the second memory address that needs to be released, the second memory address is decoded to obtain a fourth register value corresponding to the second memory address.

[0060] Among them, there are some differences between the decoding of the second memory address and the decoding of the first memory address. Since the decoding based on the first memory address is for memory marking, the first memory address is 5, for example, then the register value obtained by decoding can be, for example, "0b1111101111...", where bit 0 serves to mark the memory as occupied (if 0 means occupied, 1 means idle). However, the second memory address is used for memory release. Therefore, if the second memory address is 5, the register value obtained by decoding can be, for example, "0b000001000...", where bit 1 serves to release the memory, that is, to set the memory to an idle state.

[0061] For example, if the capacity of the second memory to be released is 128 bytes, the following calculations need to be completed in sequence under 7 clock pulses: 1st clock: F = F | (F>>64) Second clock: F = F | (F>>32) 3rd clock: F = F | (F>>16) 4th clock: F = F | (F>>8) 5th clock: F = F | (F>>4) 6th clock: F = F | (F>>2) 7th clock: F = F&(F>>1) In the above process, the second memory address is A. After the 7th clock, all 128 bits of register F starting from position A are set to 1. Finally, register R = R | F is set to complete the free mark to release the memory for the next memory request. Among them, "|" is a bitwise OR operator, which is a bit operation operator used to perform a logical OR operation on each bit of two operands.

[0062] In an embodiment of the present invention, a second memory address and a second memory capacity to be released are obtained, a third offset sequence is determined, the second memory address is decoded, a fourth register value corresponding to the second memory address is obtained, and the bits of the register are set based on the fourth register value. Starting from the first offset of the third offset sequence, the bits of the register are offset until the third offset sequence is traversed, and the final fourth register value is determined to set the memory area indicated by the second memory address and the second memory capacity to an idle state, thereby completing the memory release. Based on the iterative offset and operation of the bits of the register, fast memory release at the hardware level can be achieved, thereby improving the efficiency of memory management.

[0063] The bit operation process in the above-mentioned memory application stage, memory marking stage and memory release stage actually corresponds to the gradual aggregation and expansion of a binary tree of a specific structure, which has the advantages of simple structure and high efficiency. Therefore, it can improve the processing speed of memory application, memory marking and memory release, thereby improving the overall memory management efficiency.

[0064] Optionally, the step 201 of obtaining a first memory capacity to be applied for and determining a first offset sequence corresponding to the first memory capacity includes: Sub-step 2011, determining the mapping memory capacity corresponding to each bit of the register; the mapping memory capacity indicates the memory size corresponding to each bit; Sub-step 2012, determining the memory application quantity according to the first memory capacity and the mapped memory capacity; Sub-step 2013, determining a target offset number corresponding to the memory application number, and determining a first offset sequence including the target offset number of offsets.

[0065] In an embodiment of the present invention, the memory capacity corresponding to each bit is consistent, and they are all equal mapped memory capacities. For example, each bit corresponds to one byte or multiple bytes. The larger the mapped memory capacity corresponding to each bit, the larger the memory capacity that can be managed. The smaller the mapped memory capacity corresponding to each bit, the smaller the memory capacity that can be managed, but the management precision is higher.

[0066] The memory application quantity can be determined based on the first memory capacity and the mapped memory capacity corresponding to each bit. The memory application quantity is the corresponding bit quantity, which indicates how many consecutive bits are required to be 1 (if the bit is 1, it indicates an idle state). For example, if the first memory capacity is 128 bytes and the mapped memory capacity is 1 byte, the memory application quantity is 128, and it is necessary to filter out 128 consecutive bits that are 1.

[0067] Therefore, by determining the target offset number corresponding to the memory application number, the first offset sequence including the target offset number offsets can be determined. For example, if the first memory capacity is 128 bytes, the first offset sequence including 7 offsets is finally determined, including 1, 2, 4, 8, 16, 32 and 64.

[0068] The embodiment of the present invention is implemented by determining the mapped memory capacity corresponding to each bit of the register, determining the memory application quantity according to the first memory capacity and the mapped memory capacity, determining the corresponding target offset quantity, and determining the first offset sequence including the target offset quantity offsets. The memory application quantity and the first offset sequence can be flexibly determined according to the mapped memory capacity corresponding to the bit. The larger the mapped memory capacity, the larger the memory capacity that can be managed. The smaller the mapped memory capacity, the higher the precision of the memory management, thereby improving the flexibility of memory management.

[0069] Since the offsets in the offset sequence are all obtained based on powers of two, when applying for memory, searching or filtering for free memory, the free memory also needs to be determined based on powers of two. However, the memory required by the memory applicant does not necessarily fully conform to the power of two. For example, if the application is for 100 bytes, but when determining the available free memory, in order to meet the demand for 100 bytes, at least 128 bytes of free memory need to be determined, which easily leads to the problem of wasted memory space.

[0070] Optionally, the step 201 of obtaining a first memory capacity to be applied for and determining a first offset sequence corresponding to the first memory capacity includes: Sub-step 2014, obtaining a first memory capacity to be applied for, splitting the first memory capacity into at least two sub-memory capacities, and respectively determining a sub-offset sequence corresponding to each sub-capacity; Sub-step 2015, the step of encoding the first register value to obtain a first memory address to be allocated corresponding to the first register value, includes: Sub-step 2016, encoding the sub-register value corresponding to each sub-offset sequence to obtain a sub-memory address corresponding to each sub-register value; each sub-memory address is a starting address to be allocated.

[0071] In the embodiment of the present invention, after obtaining the first memory capacity, it is possible to additionally determine whether the first memory capacity meets the power of two, so as to perform the next step of capacity splitting. For example, if the first memory capacity is 100 bytes, it does not meet the power of two, and the 100 bytes can be split into 64 bytes, 32 bytes, and 4 bytes, that is, 4 sub-memory capacities, each of which meets the power of two, so that no waste of memory space is generated.

[0072] Similarly, based on each sub-memory capacity, the corresponding sub-offset sequence is determined, and based on the sub-offset sequence, the offset is performed, and the respective sub-register values ​​are also obtained and encoded to obtain the sub-memory address corresponding to each sub-memory capacity. Each sub-memory address is the starting address to be allocated. Based on each sub-memory address and the corresponding value memory capacity, different sizes of memory to be allocated can be determined.

[0073] In implementing the embodiments of the present invention, by acquiring the first memory capacity to be applied for, splitting the first memory capacity into at least two sub-memory capacities, and respectively determining the sub-offset sequence of each sub-capacity, encoding the sub-register value corresponding to each sub-offset sequence to obtain the sub-memory address corresponding to each sub-register value, the applied first memory capacity can be split, and different memories to be allocated can be respectively determined, which can avoid or reduce the waste of memory space and improve the accuracy of memory management.

[0074] Optionally, the step 204 of encoding the first register value to obtain a first memory address to be allocated corresponding to the first register value includes: Sub-step 2041, determining the number of leading zeros of the first register value; the number of leading zeros represents the number of bits that are consecutively zero starting from the most significant bit of the first register value; Sub-step 2042: determining a first memory address to be allocated corresponding to the first register value based on the number of leading zeros.

[0075] In an embodiment of the present invention, encoding the first register value may be inputting the first register value into an encoder circuit, and the encoder circuit may be configured to calculate the number of leading zeros of the first register value, where the number of leading zeros represents the number of bits that are consecutively zero starting from the highest bit of the first register value. For example, if the first register value is "00001010010", the number of leading zeros is 4.

[0076] Since each bit in the first register value that is 1 can indicate free memory of the first memory capacity, the first memory address can be the number of leading zeros plus 1. For example, if the first register value is "00001010010", the number of leading zeros is 4, and the fifth bit is 1, indicating that there is free memory of the first memory capacity, then the first memory address can be 5.

[0077] Optionally, the step 205 of decoding the first memory address to obtain a second register value corresponding to the first memory address includes: Sub-step 2051, based on the first memory address, determining a target bit in the register, and setting the target bit to a first preset value; the target bit being the first preset value indicates that the corresponding memory area is in an occupied state; Sub-step 2052, setting the other bits except the target bit to a second preset value to determine the second register value after all the bits of the register are set; the other bits being the second preset value indicates that the corresponding memory area is in an idle state.

[0078] In an embodiment of the present invention, when decoding the first memory address, a bit position can be obtained according to the first memory address, and then a target bit in the register is determined, and the target bit is set to a first preset value. Among them, since the decoding process of the first memory address is to mark the memory as occupied, the first preset value can be 0 (a bit of 0 indicates that the memory is occupied).

[0079] The other bits except the target bit are set to a second preset value, for example, 1 (a bit of 1 indicates that the memory is in an idle state). After all the bits in the register are set, the second register value can be obtained.

[0080] The first memory address may be input into a decoder circuit to obtain a second register value output by the decoder circuit. In addition, when decoding based on the second memory address, it may be similar to the process of decoding the second memory address, except that the second memory address is an address for releasing memory, so based on the second memory address, a target bit of a second preset value (e.g., 1, indicating an idle state) is determined, and other bits other than the target bit are set to a first preset value (e.g., 0, indicating an occupied state). The specific process is not repeated here.

[0081] The memory management method of the present invention can perform binary tree aggregation and expansion iteration through a specially designed bit operation structure and process, efficiently complete the search, allocation and release of free memory, realize dynamic memory management, and can be used to realize complex circuit IP (Intellectual Property).

[0082] In the fields of automobiles, robots, etc., due to the high requirements for real-time performance, high-performance processors and software protocol stacks are usually used to complete communication protocol processing, which increases hardware costs. Based on the memory management method of the present invention, a high-performance dedicated communication IP can be realized, and with a low-cost and low-speed processor, the system cost can be reduced as a whole. A controller area network bus (CAN) IP can also be developed, which can support dynamic data unpacking and unpacking through the memory management method of the present invention, and can also realize an Ethernet-based fieldbus system (etherCAT, Ethernet for Control Automation Technology) with hardware-enhanced functions, supporting hardware-implemented variable-length data packet grouping and parsing.

[0083] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0084] Device Embodiment Figure 3 is a structural block diagram of a memory management device of the present invention, wherein the device 30 comprises: The application sequence module 301 is used to obtain a first memory capacity to be applied for, and determine a first offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the first offset sequence; there is an increasing relationship between the offsets in the first offset sequence; An iterative offset module 302 is used to start from the first offset in the first offset sequence, offset the bits of the preset register according to the first offset, and obtain a register update value based on the register value before the offset and the register value after the offset; the register value is determined by multiple bits of the register; each bit is used to indicate that the corresponding memory area is in an idle state or an occupied state; An iteration result module 303, configured to continue the next offset based on the register update value until the first offset sequence is traversed and a final first register value is determined; The address allocation module 304 is used to encode the first register value to obtain a first memory address corresponding to the first register value; the first memory address is a starting address to be allocated.

[0085] Optionally, the device further comprises: a memory marking module, configured to decode the first memory address to obtain a second register value corresponding to the first memory address, and set a bit of the register based on the second register value; a marking sequence module, configured to determine a second offset sequence corresponding to the first memory capacity; a positive correlation exists between the first memory capacity and the number of offsets in the second offset sequence; and a decreasing relationship exists between the offsets in the second offset sequence; A first offset module, configured to start from a first offset of the second offset sequence, offset the bit of the register according to the first offset, and obtain a register update value based on the register value before the offset and the register value after the offset; A marking completion module is used to continue the next offset based on the register update value until the second offset sequence is traversed and completed, and determine the final third register value to set the memory area jointly indicated by the first memory address and the first memory capacity to an occupied state.

[0086] Optionally, the device further comprises: a release application module, configured to obtain a second memory address and a second memory capacity to be released, and determine a third offset sequence corresponding to the second memory capacity; a positive correlation exists between the second memory capacity and the number of offsets in the third offset sequence; and a decreasing relationship exists between the offsets in the third offset sequence; a decoding processing module, configured to decode the second memory address to obtain a fourth register value corresponding to the second memory address, and set a bit of the register based on the fourth register value; A second offset module, configured to start from a first offset of the third offset sequence, offset the bit of the register according to the first offset, and obtain a register update value based on the register value before the offset and the register value after the offset; A memory release module is used to continue the next offset based on the register update value until the third offset sequence is traversed, and determine a final fourth register value to set the memory area jointly indicated by the second memory address and the second memory capacity to an idle state.

[0087] Optional, application sequence modules, including: A mapping memory submodule, used to determine the mapping memory capacity corresponding to each bit of the register; the mapping memory capacity indicates the memory size corresponding to each bit; An application quantity submodule, used to determine the memory application quantity according to the first memory capacity and the mapped memory capacity; The quantity sequence submodule is used to determine a target offset quantity corresponding to the memory application quantity, and to determine a first offset sequence including the target offset quantity offsets.

[0088] Optional, application sequence modules, including: an application splitting submodule, configured to obtain a first memory capacity to be applied for, split the first memory capacity into at least two sub-memory capacities, and respectively determine a sub-offset sequence corresponding to each sub-capacity; The address allocation module includes: The address distinguishing submodule is used to encode the subregister value corresponding to each sub-offset sequence to obtain the sub-memory address corresponding to each subregister value; each sub-memory address is the starting address to be allocated.

[0089] Optional, address allocation module, including: A leading zero calculation submodule, used to determine the number of leading zeros of the first register value; the number of leading zeros represents the number of bits that are consecutively zero starting from the most significant bit of the first register value; The leading address submodule is used to determine a first memory address to be allocated corresponding to the first register value based on the number of leading zeros.

[0090] Optional, memory tagging module, including: A target bit submodule, used to determine a target bit in the register based on the first memory address, and set the target bit to a first preset value; the target bit being the first preset value indicates that the corresponding memory area is in an occupied state; The other bit submodule is used to set other bits except the target bit to a second preset value to determine the second register value after all the bits of the register are set; the other bits being the second preset value indicate that the corresponding memory area is in an idle state.

[0091] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0092] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0093] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0094] Reference Figure 4 , is a structural block diagram of an electronic device for memory management provided by an embodiment of the present invention. Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the memory management method of the aforementioned embodiment.

[0095] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor.

[0096] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The communication bus may be divided into an address bus, a data bus, and a control bus. For ease of representation, Figure 4 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0097] The memory can be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it can be an EEPROM (Electrically ErasableProgrammable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, and an optical data storage device.

[0098] The embodiment of the present invention further provides a non-temporary readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor is enabled to execute Figure 2 The memory management method shown.

[0099] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0100] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (which may include disk storage, CD-ROM, optical storage) containing computer-usable program code.

[0101] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable memory management terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable memory management terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0102] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable memory management terminal device to operate in a predictive manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, the instruction device being implemented in the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0103] These computer program instructions can also be loaded into a computer or other programmable memory management terminal device so that a series of operation steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable terminal device provide for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 Functional steps of one or more boxes.

[0104] Although the preferred embodiments of the present invention are described, those skilled in the art will recognize the basic creative concept and may make other changes and modifications to these embodiments. The appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0105] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0106] The above is a detailed introduction to a memory management method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A memory management method, characterized in that: The method comprises: Acquire a first memory capacity to be applied for, and determine a first offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the first offset sequence; there is an increasing relationship between the offsets in the first offset sequence; Starting from the first offset in the first offset sequence, the bits of the preset register are offset according to the first offset, and a register update value is obtained based on the register value before the offset and the register value after the offset; the register value is determined by multiple bits of the register; each bit is used to indicate that the corresponding memory area is in an idle state or an occupied state; Based on the register update value, continue the next offset until the first offset sequence is traversed and a final first register value is determined; The first register value is encoded to obtain a first memory address corresponding to the first register value; the first memory address is a starting address to be allocated.

2. The method according to claim 1, characterized in that After the step of encoding the first register value to obtain a first memory address corresponding to the first register value, the method further includes: Decoding the first memory address to obtain a second register value corresponding to the first memory address, and setting a bit of the register based on the second register value; Determine a second offset sequence corresponding to the first memory capacity; there is a positive correlation between the first memory capacity and the number of offsets in the second offset sequence; there is a decreasing relationship between the offsets in the second offset sequence; Starting from a first offset of the second offset sequence, shifting the bits of the register according to the first offset, and obtaining a register update value based on a register value before the shift and a register value after the shift; Based on the register update value, the next offset is continued until the second offset sequence is traversed and completed, and a final third register value is determined to set the memory area indicated by the first memory address and the first memory capacity to an occupied state.

3. The method according to claim 1, characterized in that The method further comprises: Acquire a second memory address and a second memory capacity to be released, and determine a third offset sequence corresponding to the second memory capacity; there is a positive correlation between the second memory capacity and the number of offsets in the third offset sequence; there is a decreasing relationship between the offsets in the third offset sequence; Decoding the second memory address to obtain a fourth register value corresponding to the second memory address, and setting a bit of the register based on the fourth register value; Starting from a first offset of the third offset sequence, shifting the bits of the register according to the first offset, and obtaining a register update value based on a register value before the shift and a register value after the shift; Based on the register update value, the next offset is continued until the third offset sequence is traversed and completed, and a final fourth register value is determined to set the memory area indicated by the second memory address and the second memory capacity to an idle state.

4. The method according to claim 1, characterized in that The step of obtaining the first memory capacity to be applied for and determining a first offset sequence corresponding to the first memory capacity includes: Determine a mapped memory capacity corresponding to each bit of the register; the mapped memory capacity indicates a memory size corresponding to each bit; Determining a memory application quantity according to the first memory capacity and the mapped memory capacity; A target offset number corresponding to the memory application number is determined, and a first offset sequence including the target offset number of offsets is determined.

5. The method according to claim 1, characterized in that The step of obtaining the first memory capacity to be applied for and determining a first offset sequence corresponding to the first memory capacity includes: Acquire a first memory capacity to be applied for, split the first memory capacity into at least two sub-memory capacities, and respectively determine a sub-offset sequence corresponding to each sub-capacity; The step of encoding the first register value to obtain a first memory address to be allocated corresponding to the first register value includes: The sub-register value corresponding to each sub-offset sequence is encoded to obtain a sub-memory address corresponding to each sub-register value; each sub-memory address is a starting address to be allocated.

6. The method according to claim 1, characterized in that The step of encoding the first register value to obtain a first memory address to be allocated corresponding to the first register value includes: Determine the number of leading zeros of the first register value; the number of leading zeros represents the number of bits that are consecutively zero starting from the most significant bit of the first register value; Based on the number of leading zeros, a first memory address to be allocated corresponding to the first register value is determined.

7. The method according to claim 2, characterized in that The step of decoding the first memory address to obtain a second register value corresponding to the first memory address includes: Based on the first memory address, determine a target bit in the register, and set the target bit to a first preset value; the target bit being the first preset value indicates that the corresponding memory area is in an occupied state; The other bits except the target bit are set to a second preset value to determine a second register value after all the bits of the register are set; the other bits being the second preset value indicates that the corresponding memory area is in an idle state.

8. A memory management device, characterized in that: The device comprises: an application sequence module, configured to obtain a first memory capacity to be applied for, and determine a first offset sequence corresponding to the first memory capacity; a positive correlation exists between the first memory capacity and the number of offsets in the first offset sequence; and an increasing relationship exists between the offsets in the first offset sequence; An iterative offset module, configured to start from a first offset in the first offset sequence, offset the bits of a preset register according to the first offset, and obtain a register update value based on the register value before the offset and the register value after the offset; the register value is determined by a plurality of bits of the register; each bit is used to indicate that the corresponding memory area is in an idle state or an occupied state; An iteration result module, configured to update the register value, continue the next offset until the first offset sequence is traversed and completed, and determine a final first register value; The address allocation module is used to encode the first register value to obtain a first memory address corresponding to the first register value; the first memory address is a starting address to be allocated.

9. An electronic device, characterized in that: The electronic device comprises a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the memory management method according to any one of claims 1 to 7.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the memory management method as described in any one of claims 1 to 7.

Images