Memory access method, memory access device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a memory access method, a memory access device, electronic equipment and a storage medium. The memory access method comprises the steps that address processing operation is executed on a first address field of a system memory address, a first memory address comprising a channel selection address field is obtained, and a plurality of memory channels correspond to a plurality of values of the channel selection address field in a one-to-one mode; and accessing the corresponding memory channel according to the plurality of values of the channel selection address field. According to the memory access method, different numbers of memory channel configurations can be flexibly coped with, the load balancing problem of the memory system under the condition of multiple memory channels is improved, and the bandwidth loss caused by memory access imbalance is reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a memory access method, a memory access device, an electronic device, and a storage medium. Background Art

[0002] With the widespread adoption of technologies like artificial intelligence (AI), the computing power of processors and chips continues to increase, driving higher requirements for memory access bandwidth. In systems on a chip (SoC), multi-channel memory control technology can be used for memory access, effectively increasing total memory bandwidth to accommodate the data transfer and processing needs of high-speed processors. To fully utilize the combined bandwidth of multiple channels, the SoC master must interleave address accesses to each memory channel. This access method is known as memory interleaving. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a memory access method, wherein the memory corresponds to multiple memory channels. The memory access method includes: performing an address processing operation on a first address segment of a system memory address to obtain a first memory address including a channel selection address segment, wherein the multiple memory channels correspond one-to-one to multiple values ​​of the channel selection address segment; and accessing the corresponding memory channels according to the multiple values ​​of the channel selection address segment.

[0004] At least one embodiment of the present disclosure provides a memory access device, wherein the memory corresponds to multiple memory channels, and the memory access device includes: an address processing module, configured to perform an address processing operation on a first address segment of a system memory address to obtain a first memory address including a channel selection address segment, wherein the multiple memory channels correspond one-to-one to multiple values ​​of the channel selection address segment; and an allocation module, configured to access the corresponding memory channels according to the multiple values ​​of the channel selection address segment.

[0005] At least one embodiment of the present disclosure provides an electronic device, comprising: at least one processor; a memory comprising one or more computer program modules; wherein the one or more computer program modules are stored in the memory and configured to be executed by the at least one processor, and the one or more computer program modules are used to implement the memory access method described in at least one embodiment above.

[0006] At least one embodiment of the present disclosure provides a non-transitory readable storage medium having computer instructions stored thereon, wherein the computer instructions, when executed by at least one processor, implement the memory access method described in at least one embodiment above. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0008] Figure 1 A schematic diagram of an unbalanced memory channel load;

[0009] Figure 2A A schematic diagram of memory interleaving;

[0010] Figure 2B A schematic diagram of memory interleaving with an odd number of memory channels;

[0011] Figure 2C A schematic diagram of another memory interleaving method with an odd number of memory channels;

[0012] Figure 3A A flowchart of a memory access method provided by at least one embodiment of the present disclosure;

[0013] Figure 3B A schematic diagram of an address processing operation provided by at least one embodiment of the present disclosure;

[0014] Figure 3C A schematic diagram of a second XOR hash operation provided by at least one embodiment of the present disclosure;

[0015] Figure 3D A schematic diagram of an example of a memory access method provided by at least one embodiment of the present disclosure;

[0016] Figure 3E A schematic diagram of another example of a memory access method provided by at least one embodiment of the present disclosure; Figure 4 A schematic block diagram of a memory access device provided in at least one embodiment of the present disclosure;

[0017] Figure 5 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure;

[0018] Figure 6 A schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure; and

[0019] Figure 7 A schematic block diagram of a non-transitory readable storage medium provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0021] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0022] With advancements in chip technology and growing demand for high-performance computing, the need for memory bandwidth is becoming increasingly urgent, driving a continuous increase in the number of memory channels in system-on-chip (SoC) designs. However, this increase in memory channels increases costs in terms of chip area, power consumption, and other factors. Therefore, it is necessary to control the number of memory channels to just meet bandwidth requirements.

[0023] To meet these requirements, introducing non-power-of-two memory interleaving is an ideal choice. However, the locality of address distribution probability can lead to memory load imbalance in memory interleaving, which in turn reduces bandwidth utilization. The load imbalance problem is particularly prominent for non-power-of-two memory interleaving methods due to address mapping. The specific reasons are analyzed as follows:

[0024] Reason 1: The locality of address distribution probability can cause memory interleaving to cause memory load imbalance.

[0025] Burst Transfer is a mechanism used by memory controllers in modern computer systems to efficiently read and write data. It allows the CPU or memory controller to send a starting address and burst size information at once, and then continuously read and write multiple consecutive storage cells in a short period of time. This reduces the command and address information required for each data exchange, greatly improving memory bandwidth and system performance.

[0026] Host-initiated read and write accesses are generally aligned and continuous in address. The channel selection address segment used for memory channel selection is more likely to contain small values. This means that memory channels corresponding to small values ​​are more heavily loaded than those corresponding to large values, resulting in uneven loads across memory channels. For short periods of time, some memory channels may be fully loaded while others are relatively idle, resulting in wasted available bandwidth. The ratio of actual available bandwidth to theoretically available bandwidth is called bandwidth utilization. Unbalanced memory load leads to low bandwidth utilization, which in turn limits system performance.

[0027] Figure 1 A schematic diagram of memory channel load imbalance.

[0028] For example, Figure 1 As shown in the figure, taking a four-channel double data rate synchronous dynamic random access memory (DDR) as an example, when the address segment addr[9:8] is selected as the channel selection address segment for four-channel selection, the address segment values ​​2'b00 to 2'b11 correspond to memory DDR0 to DDR3 in sequence. During continuous access, the address addr[9:8] generally starts from 2'b00 and increases in sequence, but does not necessarily end at 2'b11. Figure 1 As shown, solid boxes represent addresses that transactions need to access, while dashed boxes represent addresses that transactions do not need to access. In the case of misaligned burst lengths, for example, when the burst length is not an integer multiple of the minimum granularity (e.g., 1024KB) for data prefetching or processing within the storage device, the memory channel corresponding to addr[9:8] = 2'b00 will obviously need to bear more data transmission tasks, resulting in unbalanced memory channel load and affecting overall performance.

[0029] Reason 2: For the memory interleaving method with a number that is not a power of 2, the load imbalance problem is particularly prominent due to address mapping.

[0030] Depending on the number of memory channels, memory interleaving methods can be categorized as either power-of-2 or non-power-of-2 interleaving. In power-of-2 interleaving, all values ​​in the channel select address segment can be mapped to a single memory channel. For example, if the channel select address segment is 2 bits, corresponding to four memory channels, then the values ​​2'b00 to 2'b11 can correspond to memory channels DDR0 to DDR3, respectively. When the access addresses are continuous and complete, each address can be assigned to a different memory channel, resulting in relatively balanced load. However, in non-power-of-2 interleaving, the number of channel select address values ​​exceeds the number of memory channels, making it inevitable that different values ​​will be mapped to the same memory channel. For example, if the channel select address segment is 2 bits, corresponding to three memory channels, two address values ​​will inevitably be mapped to the same memory channel. Even if the access addresses are continuous and complete, the load on a particular memory channel will be heavier.

[0031] Figure 2A A schematic diagram of memory interleaving.

[0032] For example, Figure 2A As shown in the figure, when the number of memory channels is 4, addr[9:8] is selected as the channel selection address segment. In this case, the number of channel selection address segment values ​​is 4, and the addr[9:8] values ​​2'b00 to 2'b11 are mapped to DDR0 to DDR3, respectively. When the number of memory channels is a power of 2, each channel selection address segment value corresponds to a specific memory channel.

[0033] Figure 2B A schematic diagram of memory interleaving with an odd number of memory channels.

[0034] For example, Figure 2B As shown in the figure, when the number of memory channels is 3, addr[9:8] is selected as the channel selection address segment. At this time, the number of channel selection address segments is 4. When the number of memory channels is an odd number, the number of memory channels is not equal to the number of channel selection address segments. In this case, memory interleaving will cause repeated mapping, resulting in uneven channel load distribution. Figure 2B As shown, the values ​​of addr[9:8] 2'b00~2'b11 are mapped to DDR0~DDR2 respectively. Taking the host access granularity of 2KB and the memory interleaving granularity of 512B as an example, in every 2KB access, both memory DDR1 and memory DDR2 will be idle, wasting 1KB of bandwidth. Therefore, the theoretical bandwidth loss is 1KB ÷ (2+1)KB = 33%, and the load of memory DDR0 is much higher than that of memory DDR1 and memory DDR2.

[0035] Figure 2C Schematic diagram of another memory interleaving with an odd number of memory channels.

[0036] By increasing the number of bits in the channel selection address segment, load balancing can be improved and bandwidth loss can be reduced. Figure 2C As shown, addr[10:8] is selected as the channel select address segment, increasing the number of bits in the channel select address segment from 2 to 3. The addr[10:8] values ​​3'b000 to 3'b111 are mapped to DDR0 to DDR2, respectively. Therefore, for every 4KB access, only memory DDR2 is idle, wasting 512B of bandwidth. Therefore, the theoretical bandwidth loss is reduced to 0.5KB ÷ (4 + 0.5)KB = 11%. Although increasing the number of bits in the channel select address segment can reduce bandwidth loss, achieving uniform access requires increasing the host's access granularity, which also limits access balance.

[0037] Based on the above analysis, the inventors of the present disclosure noticed that the load balancing of the memory interleaving method with a number that is not a power of 2 is limited by the address mapping method and the access granularity.

[0038] At least one embodiment of the present disclosure provides a memory access method, wherein a memory corresponds to multiple memory channels. The memory access method comprises: performing an address processing operation on a first address segment of a system memory address to obtain a first memory address including a channel selection address segment, wherein the multiple memory channels correspond one-to-one to multiple values ​​of the channel selection address segment; and accessing the corresponding memory channels according to the multiple values ​​of the channel selection address segment.

[0039] At least one embodiment of the present disclosure provides a memory access method that performs address processing on a first address segment of a memory address to obtain a channel selection address segment whose values ​​correspond one-to-one with multiple memory channels. The corresponding memory channels are then accessed based on the multiple values ​​of the channel selection address segment. This memory access method can flexibly accommodate configurations with varying numbers of memory channels, improving load balancing in memory systems with multiple memory channels and reducing bandwidth loss caused by uneven memory access.

[0040] Furthermore, the memory access method provided by at least one embodiment of the present disclosure provides a non-power-of-2 XOR hashing method to scatter the addresses, thereby enhancing the uniform distribution of addresses among various channels, thereby further improving the load balancing effect of the non-power-of-2 memory channel interleaving method, ensuring that memory resources are optimized to the greatest extent, and improving the performance of the overall system.

[0041] In at least one embodiment of the present disclosure, a memory corresponds to multiple memory channels. For example, the memory may be DDR, and the memory channels may be DDR channels (DDRC). Other types of memory units and memory channels may also be selected based on actual needs, and the embodiments of the present disclosure are not limited thereto.

[0042] Figure 3A A flowchart of a memory access method provided in at least one embodiment of the present disclosure, wherein the memory corresponds to multiple memory channels.

[0043] For example, Figure 3A As shown, the memory access method provided by at least one embodiment of the present disclosure includes the following steps S101 to S102.

[0044] Step S101: performing an address processing operation on a first address segment of a system memory address to obtain a first memory address including a channel selection address segment, wherein a plurality of memory channels correspond one to one with a plurality of values ​​of the channel selection address segment.

[0045] Step S102: accessing corresponding memory channels according to multiple values ​​of the channel selection address segment.

[0046] For example, in step S101, the system memory address is used to access multiple memory channels, and the first address segment can be any address segment in the system memory address. For example, the address processing operation may include an address mapping operation, an address scattering operation, an address decoding operation, a logical operation operation, a shift operation, etc., the purpose of which is to extract the part used to select the memory channel from the system memory address, that is, the channel selection address segment. The embodiments of the present disclosure are not limited to this. For example, the number of memory channels does not necessarily meet the nth power of 2. By performing the address processing operation on the first address segment, the number of values ​​of the channel selection address segment obtained is the same as the number of memory channels, that is, multiple memory channels correspond one-to-one to multiple values ​​of the channel selection address segment.

[0047] For example, in step S102, since multiple memory channels correspond one-to-one to multiple values ​​of the channel selection address segment, different memory channels can be accessed based on different values ​​of the channel selection address segment. When the host needs to perform a read or write operation on the memory, it sends the first memory address to the memory controller, which then distributes the access request to the corresponding memory channel based on the channel selection address segment in the first memory address.

[0048] In at least one embodiment of the present disclosure, the system memory address includes m1+1 address bits, and the first address segment includes the m1th address bit to the m3th address bit of the system memory address, where m1 is an integer greater than 1, and m3 is an integer greater than 1 and less than m1.

[0049] For example, the first address segment is also called the high-order portion of the system memory address. The bit width of the first address segment can be selected according to actual needs, and the embodiments of the present disclosure do not limit this.

[0050] In at least one embodiment of the present disclosure, the system memory address further includes a second address segment, and the second address segment includes the m3-1th address bit to the 0th address bit of the system memory address.

[0051] For example, the second address segment is also called the low-order part of the system memory address, which is used for transparent transmission. This means that when the host sends an address request to the memory controller, the memory controller does not convert or recalculate the second address segment, but directly includes it in the memory access command and sends it to the memory. The bit width of the second address segment depends on the interleaving granularity, which refers to the minimum data block size that can be accessed continuously during read and write operations. For example, when the interleaving granularity is 256 bytes, 8-bit binary numbers are required to represent 256 different addresses to ensure that the data in the memory can be accessed continuously and accurately. At this time, the bit width of the second address segment corresponds to 8 bits, m3=8. It should be noted that the size of the interleaving granularity can be adjusted according to actual needs, and the embodiments of the present disclosure do not limit this. By setting the transparent transmission address segment (second address segment), the principle of locality can be maintained during data transmission, which is conducive to improving data access speed and bandwidth utilization.

[0052] For example, in some examples, the memory access method proposed in at least one embodiment of the present disclosure may further include the following step S103.

[0053] Step S103: Delete the channel selection address segment in the first memory address to obtain a second memory address.

[0054] For example, the first memory address contains information for selecting a memory channel (i.e., the channel selection address segment) and information for locating the address of a specific storage unit. When continuous access to the memory is required, the first memory address can be processed, the channel selection address segment can be removed, and the remaining address bits can be reassembled into a continuous address, i.e., the second memory address. The second memory address only contains the actual address information for locating each storage unit in the memory, and no longer contains the channel selection part. Therefore, it can continuously point to the entire addressable space of the memory, ensuring that when continuous read and write operations are performed on a single channel, every storage unit in the memory can be accurately addressed.

[0055] In at least one embodiment of the present disclosure, Figure 3A Step S101 may include the following steps S201 to S202.

[0056] Step S201: performing a mapping operation on a first address segment of a system memory address to obtain a mapping address segment.

[0057] For example, in step S201, a mapping operation can be performed by address calculation, such as performing a modulo transformation on the first address segment, in order to divide the system address into N parts evenly to achieve load balancing, where N is the number of memory channels, and the embodiments of the present disclosure do not limit this.

[0058] In at least one embodiment of the present disclosure, the mapped address segment includes a first mapped address segment addr_cal[m1:m2] and a second mapped address segment addr_cal[m2-1:m3]. An example of step S201 may be:

[0059] addr_cal[m1:m2]=addr_in[m1:m3] / N;

[0060] addr_cal[m2-1:m3]=addr_in[m1:m3]%N,

[0061] Where addr_in[m1:m3] is the first address segment of the system memory address, N is the number of memory channels, m2 is an integer less than m1, and m2-m3>log2N, and % represents the remainder operation. After this remainder operation, the second mapped address segment addr_cal[m2-1:m3] has only N possible values, dividing the system address into N equal parts.

[0062] It should be noted that since the low-order portion of the system memory address (the second address segment) is used for transparent transmission, the mapping operation is performed only on the high-order portion of the system memory address (the first address segment), and the low-order portion remains unchanged, that is, addr_cal[m3-1:0] = addr_in[m3-1:0]. For convenience of description, addr_cal[m1:0] will be referred to as the mapped memory address below.

[0063] Step S202: performing a random scattering operation on the mapped address segment to obtain a first memory address.

[0064] For example, in step S202, a random scattering operation can be performed by using XOR hash processing or other address rearrangement algorithms. The purpose is to evenly distribute the highly localized memory access requests to each memory channel according to the channel selection address segment in the first memory address when the host needs to read or write the memory, so as to avoid the phenomenon that some channels are overly busy and other channels are idle due to address continuity.

[0065] Figure 3B A schematic diagram of an XOR hash process provided in at least one embodiment of the present disclosure.

[0066] To alleviate the load imbalance problem of memory interleaving, a common optimization method is to perform XOR hash processing on the memory access address. The purpose of this approach is to disperse the continuous address access requests that may be concentrated on certain specific channels, so that the addresses are transformed to present a relatively random and uniform distribution state on the channel selection address segment corresponding to each channel. XOR hash processing is generally performed by XORing a specific address segment with a channel selection address segment to obtain a new channel selection address segment, which is randomly and uniformly distributed in all values. For example, a number of bits can be selected from the address to perform XOR operation, and a new address segment is generated as the basis for channel selection. For example, as shown in Figure 3B compared with Figure 1 , the values of the channel selection address segment are no longer concentrated on 2'b00, but a relatively balanced access allocation is achieved among the various memory channels.

[0067] In at least one embodiment of the present disclosure, step S202 can include steps S301-S303.

[0068] Step S301: performing a first XOR hash operation on a plurality of address bits in the first mapping address segment to obtain a first intermediate result.

[0069] Step S302: performing a second XOR hash operation on the first intermediate result and a second mapping address segment to obtain a channel selection address segment.

[0070] Step S303: replacing the second mapping address segment with the channel selection address segment to obtain a first memory address.

[0071] For example, in step S301, any number of address bits in the first mapping address segment can be selected and a first XOR hash operation is performed thereon, the purpose being to break the original address locality feature, that is, to disperse continuous address access requests to different address spaces. For example, the first XOR hash operation can be implemented based on a conventional XOR hash algorithm or other algorithms that can achieve the above purpose, and the embodiments of the present disclosure do not limit this.

[0072] For example, in step S302, the number of memory channels does not necessarily satisfy 2 raised to the power of n, and by performing a second XOR hash operation on the first intermediate result and the second mapping address segment, the number of values of the channel selection address segment obtained is the same as the number of memory channels, that is, the plurality of memory channels correspond one-to-one to the plurality of values of the channel selection address segment.

[0073] For example, in step S303, for the mapped memory address addr_cal[m1:0], the second mapped address segment addr_cal[m2-1:m3] is replaced with the channel selection address segment to obtain the first memory address addr_hash[m1:0]. That is, the first memory address includes the first mapped address segment, the channel selection address segment, and the second address segment. The specific calculation method for the channel selection address segment will be described later.

[0074] In at least one embodiment of the present disclosure, step S301 may include the following steps S401 to S403.

[0075] Step S401: Divide a plurality of address bits in a first mapped address segment into M groups of address bits, where each group of the M groups of address bits includes at least two address bits.

[0076] Step S402: Select at least two address bits in each group of address bits to perform a first XOR operation to obtain a corresponding XOR result.

[0077] Step S403: Combine the obtained M groups of XOR results to obtain a first intermediate result. The number of bits of the first intermediate result is M, and the number of bits of the first intermediate result is the same as the number of bits of the second mapping address segment.

[0078] For example, in step S401, grouping can be performed in any manner, and the number of address bit groups M can also be any value addr_cal. The present disclosure does not limit the value of the number of address bit groups M and the grouping method, as long as each of the M groups of address bits includes at least two address bits.

[0079] For example, in step S402, for each group of address bits, more address bits may be selected to perform the first XOR operation, such as three or four. The embodiment of the present disclosure does not limit the number of selected address bits. The more address bits selected, the better the address scattering effect.

[0080] For example, in step S403, M groups of address bits correspond to M XOR results (for example, 0 or 1), and they can be assigned to M bits of the first intermediate result in any order, thereby obtaining an M-bit first intermediate result, and the number of bits of the second mapping address segment is also M bits.

[0081] Step S501: performing a second XOR operation on the first intermediate result and the second mapping address segment to obtain a second intermediate result.

[0082] Step S502: In response to the value of the second intermediate result being a valid value, the second intermediate result is used as a channel selection address segment.

[0083] Step S503: In response to the value of the second intermediate result being an invalid value, a remapping operation is performed on the second intermediate result according to the first intermediate result and the second mapping address segment to obtain a channel selection address segment.

[0084] For example, in step S501, the first intermediate result and the second mapping address segment have the same number of bits, and an XOR operation can be performed on the value of the first intermediate result and the value of the second mapping address segment, and the result of the XOR operation is the value of the second intermediate result.

[0085] For example, in step S502 , when the value of the second intermediate result is less than the number of memory channels, the value of the second intermediate result has a corresponding memory channel, and the value of the second intermediate result is a valid value.

[0086] For example, in step S503, when the value of the second intermediate result is greater than or equal to the number of memory channels (for example, when the number of memory channels is not a power of 2), the value of the second intermediate result has no corresponding memory channel, and the value of the second intermediate result is an invalid value.

[0087] For example, when the value of the second intermediate result is an invalid value, a remapping operation may be performed on the second intermediate result through the mapping table, and the remapping result is the channel selection address segment.

[0088] In at least one embodiment of the present disclosure, before step S503, the memory access method proposed in at least one embodiment of the present disclosure further includes: establishing a mapping table of multiple values ​​of the first intermediate result and multiple values ​​of the second mapping address segment and multiple values ​​of the channel selection address segment.

[0089] In at least one embodiment of the present disclosure, an example of step S503 is: in response to the value of the second intermediate result being greater than or equal to the number of memory channels, mapping the second intermediate result to a corresponding value among multiple values ​​of the channel selection address segment according to a mapping table.

[0090] For example, the following is an example of a first XOR hash operation provided by at least one embodiment of the present disclosure, that is, a specific example of the above steps S401 to S403.

[0091] For example, for the first mapping address segment addr_cal[m1:m2] and the second mapping address segment addr_cal[m2-1:m3], assuming m1=31, m2=10, m3=8, execute step S401, the first mapping address segment interval can be divided into two groups, that is, the even address bits are divided into the first group, and the odd address bits are divided into the second group.

[0092] For example, step S402 is executed to select four address bits from each of the two groups of address bits to perform a first exclusive-OR operation. The first group of exclusive-OR results, X1, = addr_cal

[10] ⊕addr_cal

[12] ⊕addr_cal

[14] ⊕addr_cal

[16] , and the second group of exclusive-OR results, X2, = addr_cal

[11] ⊕addr_cal

[13] ⊕addr_cal

[15] ⊕addr_cal

[17] , where ⊕ represents an exclusive-OR operation. It should be noted that the selection of four address bits is merely an example, and more or fewer address bits may be selected. The present disclosure does not limit the number of selected address bits.

[0093] For example, executing step S403, combining the first group of XOR results X1 and the second group of XOR results X2, can obtain the first intermediate result R1[1:0]. Corresponding to the two groups of XOR results, the number of bits of the first intermediate result R1 is 2, where R1[0]=X1 and R1[1]=X2. It should be noted that the order of combination can also be reversed, that is, R1[0]=X2 and R1[1]=X1, and this is not limited in the embodiment of the present disclosure. According to the above example, the number of bits of the second mapping address segment addr_cal[9:8] is 2, and the number of bits of the first intermediate result R1[1:0] is 2, and the number of bits of the first intermediate result is the same as the number of bits of the second mapping address segment. In at least one embodiment of the present disclosure, step S302 may include the following steps S501 to S503.

[0094] Figure 3C A schematic diagram of a second XOR hash operation provided by at least one embodiment of the present disclosure. For example, Figure 3C This is a specific example of steps S501 to S503 provided in at least one embodiment above.

[0095] For example, Figure 3C As shown, the first intermediate result R1[1:0] and the second mapping address segment have a number of 2 bits as an example. For example, the first intermediate result R1[1:0] comes from the specific example of the first XOR hash operation described above. For example, for the second mapping address segment addr_cal[m2-1:m3], assuming m2 = 10 and m3 = 8, the value of the first intermediate result R1[1:0] can be 2'b00 to 2'b11, and the value of the second mapping address segment addr_cal[9:8] can be 2'b00 to 2'b11.

[0096] For example, in step S501, Figure 3CAs shown, an XOR operation is performed on the value of the first intermediate result and the value of the second mapped address segment, and the result of the XOR operation is the value of the second intermediate result. For example, assuming that the value of the first intermediate result is R1 = 2'b10 and the value of the second mapped address segment is Y2 = 2'b00, then the value of the second intermediate result is R2 = R1⊕Y2 = 2'b10⊕2'b00 = 2'b10, where ⊕ represents an XOR operation. Figure 3C 2 shows the first intermediate result and the second intermediate result corresponding to different values ​​of the second mapping address segment, and the values ​​of the second intermediate result are 2'b00 to 2'b11.

[0097] For example, in step S502, if Figure 3C As shown, taking the number of memory channels as 3 as an example (memory channels DDRC0 to DDRC2), when the value of the second intermediate result is 2'b00, 2'b01 or 2'b10, which is less than the number of memory channels 3, the value of the second intermediate result is a valid value, and the multiple values ​​2'b00-2'b10 of the second intermediate result correspond to the memory channels DDRC0 to DDRC2 respectively.

[0098] For example, in step S503, if Figure 3C As shown, taking the number of memory channels as 3 as an example, when the value of the second intermediate result is 2'b11, it is equal to the number of memory channels 3. There is no memory channel corresponding to the value of the second intermediate result 2'b11, so the value of the second intermediate result 2'b11 is an invalid value.

[0099] For example, in another example, assuming the number of bits in the second mapped address segment is 3 and the number of memory channels is 3, the multiple values ​​3'b000-3'b010 of the second intermediate result correspond to memory channels DDRC0-DDRC2, respectively. When the value of the second intermediate result is 3'b100, which is greater than the number of memory channels 3 and no memory channel corresponds to it, the value 3'b100 of the second intermediate result is invalid.

[0100] For example, Figure 3C As shown, taking the number of bits of the first intermediate result and the second mapping address segment as 2 and the number of memory channels as 3 as an example, a mapping table can be established as shown in Table 1.

[0101] Table 1 Mapping table

[0102] First intermediate result Second mapping address segment Channel selection address segment 2'b01 2'b10 2'b10 2'b10 2'b01 2'b01 2'b11 2'b00 2'b00

[0103] For example, Figure 3CAs shown, when the value of the first intermediate result is 2'b01 and the value of the second mapping address segment is 2'b10, the second intermediate result obtained by performing the second XOR operation on the two according to step S501 is 2'b11. At this time, the value of the second intermediate result 2'b11 is equal to the number of memory channels 3. Therefore, according to the first row of Table 1, the second intermediate result 2'b11 is mapped to 2'b10, that is, the value of the channel selection address segment is 2'b10. Similarly, the above remapping operation is performed on all second intermediate results with invalid values ​​to obtain the corresponding channel selection address segment, as shown in FIG. Figure 3C shown.

[0104] The remapping operation in the above embodiment can be described as:

[0105] if ({first intermediate result, second mapping address segment} == 4'b0110): channel selection address segment

[0106] =2'b10;

[0107] else if ({first intermediate result, second mapping address segment} == 4'b1001): channel selection address

[0108] segment = 2'b11;

[0109] else if ({first intermediate result, second mapping address segment} == 4'b1100): channel selection address

[0110] segment = 2'b00;

[0111] else: channel selection address segment = second intermediate result.

[0112] It should be noted that the above mapping table is only an example. When the number of bits of the first intermediate result and the second mapping address segment is other values, or when the number of memory channels is other values, the content of the mapping table is also different.

[0113] The memory access method provided by at least one embodiment of the present disclosure, based on the first XOR operation and the second XOR operation, can be applied to the case where the number of memory channels is not a power of 2, thereby overcoming the problem that the traditional XOR hash algorithm is only applicable to the scattering of bit values ​​of the power of 2 and is difficult to apply to bit values ​​of the power of 2.

[0114] In at least one embodiment of the present disclosure, it is possible to handle both situations where the number of memory channels is a power of 2 and situations where the number of memory channels is not a power of 2. Based on actual measurements, the memory access method provided in at least one embodiment of the present disclosure shows that, compared to a power of 2 memory interleaving scheme, a non-power of 2 memory interleaving scheme only reduces bandwidth utilization by less than 2%.

[0115] In at least one embodiment of the present disclosure, the first memory address not only retains the original information for locating specific storage unit addresses in the system memory address, but also optimizes its channel selection. This ensures that even when the number of memory channels is not a power of 2, the access load across different channels is relatively balanced, thereby effectively improving overall system performance and bandwidth utilization.

[0116] Figure 3D A schematic diagram of an example of a memory access method provided by at least one embodiment of the present disclosure; Figure 3E A schematic diagram of another example of a memory access method provided by at least one embodiment of the present disclosure.

[0117] For example, Figure 3D This is a specific example of steps S101 to S103 provided in at least one embodiment of the present disclosure. For example, Figure 3E for Figure 3D A specific example of the system memory address, mapped memory address, first memory address and second memory address.

[0118] For example, Figure 3D As shown, the host (Master) in the chip (e.g., SoC) initiates read and write access requests and interleaves access to multiple memory channels according to a specific interleaving granularity. For example, the number of memory channels (DDRC0 to DDRC2) is 3 (i.e., N=3), where N is not a power of 2. For example, refer to Figure 3D and Figure 3E , the system memory address addr_in[31:0] used for memory access includes 32 address bits, the first address segment addr_in[31:8] includes the 31st address bit to the 10th address bit of the system memory address, and the second address segment addr_in[7:0] includes the 7th address bit to the 0th address bit of the system memory address.

[0119] For example, executing step S101 of Figure 2, performing an address processing operation on the first address segment of the system memory address. For example, specifically executing step S201: performing a mapping operation on the first address segment of the system memory address to obtain a mapped address segment.

[0120] For example, Figure 3E As shown, the mapping address segment addr_cal[31:8] includes the first mapping address segment addr_cal[31:10] and the second mapping address segment addr_cal[9:8]. The mapping address segment is obtained according to the following formula:

[0121] addr_cal[31:10]=addr_in[31:8] / 3

[0122] addr_cal[9:8]=addr_in[31:8]%3

[0123] For example, Figure 3E As shown, the second address segment addr_in[7:0] is directly transparently transmitted, addr_cal[7:0]=addr_in[7:0].

[0124] For example, other relevant descriptions about step S201 can refer to the relevant content described above and will not be repeated here.

[0125] For example, specifically, step S202 is executed to perform a random scattering operation on the mapped address segment to obtain a first memory address.

[0126] For example, the mapping address segment addr_cal[31:8] is sequentially subjected to steps S301 and S302 in at least one embodiment described above to obtain the channel selection address segment s_channel[1:0]. Figure 3E As shown, for the mapped memory address addr_cal[31:0], the second mapped address segment addr_cal[9:8] is replaced with the channel selection address segment channel[1:0], and addr_cal[7:0] is still directly transparently transmitted, then the first memory address addr_hash[31:0] can be obtained, that is:

[0127] addr_hash[31:10]=addr_cal[31:10]

[0128] addr_hash[9:8]=s_channel[1:0]

[0129] addr_hash[7:0]=addr_cal[7:0]=addr_in[7:0]

[0130] For example, other relevant descriptions about step S202 can refer to the relevant content described above and will not be repeated here.

[0131] For example, further, step S102 of FIG. 2 is executed to access the corresponding memory channel according to multiple values ​​of the channel selection address segment.

[0132] For example, refer to Figure 3D and 3EWhen the host needs to read or write memory, it sends the first memory address addr_hash[31:0] to the memory controller. The memory controller then distributes the access request to the corresponding memory channel based on the channel selection address segment addr_hash[9:8] in the first memory address addr_hash[31:0]. For example, when the channel selection address segment addr_hash[9:8] is 2'b00 to 2'b10, the request is distributed to memory channels DDRC0 to DDRC2 respectively.

[0133] For example, other relevant descriptions about step S102 can refer to the relevant content described above and will not be repeated here.

[0134] For example, further, step S103 in at least one of the above embodiments is executed to delete the channel selection address segment in the first memory address to obtain the second memory address.

[0135] For example, Figure 3E As shown, the first memory address addr_hash[31:0] is processed, the channel selection address segment addr_hash[9:8] is removed, and the remaining address bits addr_hash[31:10] and addr_hash[7:0] are re-joined into a continuous second memory address addr_cut[29:0], that is,

[0136] addr_cut[29:8]=addr_hash[31:10]

[0137] addr_cut[7:0]=addr_hash[7:0]

[0138] For example, other relevant descriptions about step S103 can refer to the relevant content described above, which will not be repeated here.

[0139] It should be noted that Figure 3D and Figure 3E The memory addresses, operation modes, and memory channels are merely exemplary. The specific number, form, and operation mode of each address and memory channel are not limited to the above examples. They can be selected according to actual needs, and the embodiments of the present disclosure do not impose any restrictions on this.

[0140] In at least one embodiment of the present disclosure, the order of the scattering operation and the mapping operation may be swapped, that is, another example of step S101 may include the following steps S601 to S602.

[0141] Step S601: performing a random scattering operation on the first address segment of the system memory address to obtain a scattering address segment.

[0142] Step S602: performing a mapping operation on the scattered address segment to obtain a first memory address.

[0143] For the relevant description of the scattering operation and the mapping operation, please refer to the relevant content of at least one embodiment of the present disclosure above, which will not be repeated here.

[0144] It should also be noted that, in various embodiments of the present disclosure, the execution order of the various steps of the memory access method is not limited. Although the execution process of each step is described above in a specific order, this does not constitute a limitation on the embodiments of the present disclosure. The various steps in the memory access method can be executed serially or in parallel, which can be determined according to actual needs.

[0145] For example, compared with the above description, the memory access method provided by at least one embodiment of the present disclosure may further include more or fewer steps, and the embodiments of the present disclosure are not limited thereto.

[0146] At least one embodiment of the present disclosure also provides a memory access device that can flexibly handle configurations with varying numbers of memory channels, thereby improving the load balancing problem of the memory system in the case of multiple memory channels and reducing bandwidth loss due to uneven memory access. Furthermore, the memory access device provided by at least one embodiment of the present disclosure utilizes a non-power-of-two XOR hashing method to break up addresses, thereby enhancing the uniform distribution of addresses across channels, thereby further improving the load balancing effect of the non-power-of-two memory channel interleaving method, ensuring that memory resources are optimally utilized to the greatest extent possible and improving overall system performance.

[0147] Figure 4 This is a schematic block diagram of a memory access device provided by at least one embodiment of the present disclosure, wherein the memory corresponds to multiple memory channels.

[0148] For example, Figure 4 As shown, the memory access device 400 includes an address processing module 401 and an allocation module 402 .

[0149] For example, in at least one embodiment of the present disclosure, the address processing module 401 is configured to perform an address processing operation on the first address segment of the system memory address to obtain a first memory address including a channel selection address segment, wherein the plurality of memory channels correspond one-to-one with the plurality of values ​​of the channel selection address segment. For example, the address processing module 401 may implement step S101. The specific implementation method thereof may be referred to the relevant description of step S101 and will not be repeated here.

[0150] For example, in at least one embodiment of the present disclosure, the distribution module 402 is configured to access the corresponding memory channel according to the multiple values of the channel selection address segment of the system memory address. For example, the distribution module 402 can implement step S102, and the specific implementation method can refer to the related description of step S102, which will not be repeated here.

[0151] For example, in at least one embodiment of the present disclosure, the system memory address includes m1+1 address bits, and the first address segment includes the m1th address bit to the m3th address bit of the system memory address, where m1 is an integer greater than 1, and m3 is an integer greater than 1 and less than m1.

[0152] For example, in at least one embodiment of the present disclosure, the system memory address further includes a second address segment, and the second address segment includes the m3-1th address bit to the 0th address bit of the system memory address.

[0153] For example, in at least one embodiment of the present disclosure, the memory access device 400 further includes a deletion module configured to delete the channel selection address segment in the first memory address to obtain the second memory address. For example, the deletion module can implement step S103, and the specific implementation method can refer to the related description of step S103.

[0154] For example, in at least one embodiment of the present disclosure, the address processing module 401 includes a first mapping module and a first scattering module. The first mapping module is configured to perform a mapping operation on the first address segment of the system memory address to obtain a mapping address segment; and the first scattering module is configured to perform a random scattering operation on the mapping address segment to obtain the first memory address. For example, the first mapping module can implement step S201, and the specific implementation method can refer to the related description of step S201; and the first scattering module can implement step S202, and the specific implementation method can refer to the related description of step S202, which will not be repeated here.

[0155] For example, in at least one embodiment of the present disclosure, the mapping address segment includes a first mapping address segment addr_cal[m1:m2] and a second mapping address segment addr_cal[m2-1:m3], and the first mapping module is further configured to:

[0156] addr_cal[m1:m2]=addr[m1:m3] / N;

[0157] addr_cal[m2-1:m3]=addr[m1:m3]%N,

[0158] addr[m1:m3] is the first address segment of the system memory address, N is the number of memory channels, m2 is an integer less than m1, and m2-m3>log2N, and % represents the remainder operation.

[0159] For example, in at least one embodiment of the present disclosure, the mapping address segment includes a first mapping address segment and a second mapping address segment, and the first scattering module includes a first XOR hash unit, a second XOR hash unit and a replacement unit. The first XOR hash unit is configured to perform a first XOR hash operation on multiple address bits in the first mapping address segment to obtain a first intermediate result; the second XOR hash unit is configured to perform a second XOR hash operation on the first intermediate result and the second mapping address segment to obtain a channel selection address segment; the replacement unit is configured to replace the second mapping address segment of the mapping address segment with the channel selection address segment to obtain a first memory address, and the first memory address includes the first mapping address segment and the channel selection address segment. For example, the first XOR hash unit can implement step S301, and its specific implementation method can refer to the relevant description of step S301; the second XOR hash unit can implement step S302, and its specific implementation method can refer to the relevant description of step S302; the replacement unit can implement step S303, and its specific implementation method can refer to the relevant description of step S303, which will not be repeated here.

[0160] For example, in at least one embodiment of the present disclosure, the first XOR hash unit includes a splitting unit, a first XOR unit, and a combining unit. The splitting unit is configured to split the plurality of address bits in the first mapping address segment into M groups of address bits, each group of the M groups of address bits including at least two address bits; the first XOR unit is configured to select at least two address bits in each group of address bits to perform a first XOR operation to obtain a corresponding XOR result; and the combining unit is configured to combine the obtained M groups of XOR results to obtain a first intermediate result, the number of bits of the first intermediate result being M, and the number of bits of the first intermediate result being the same as the number of bits of the second mapping address segment.

[0161] For example, the segmentation unit can implement step S401, and its specific implementation method can refer to the relevant description of step S401; the first XOR unit can implement step S402, and its specific implementation method can refer to the relevant description of step S402; the combination unit can implement step S403, and its specific implementation method can refer to the relevant description of step S403, which will not be repeated here.

[0162] For example, in at least one embodiment of the present disclosure, the second XOR hash unit includes a second XOR unit, a selection unit, and a remapping unit. The second XOR unit is configured to perform a second XOR operation on the first intermediate result and the second mapping address segment to obtain a second intermediate result; the selection unit is configured to use the second intermediate result as a channel selection address segment in response to the value of the second intermediate result being a valid value; the remapping unit is configured to perform a remapping operation on the second intermediate result according to the first intermediate result and the second mapping address segment in response to the value of the second intermediate result being an invalid value to obtain a channel selection address segment. For example, the second XOR unit can implement step S501, and its specific implementation method can refer to the relevant description of step S501; the selection unit can implement step S502, and its specific implementation method can refer to the relevant description of step S502; the remapping unit can implement step S503, and its specific implementation method can refer to the relevant description of step S503, which will not be repeated here.

[0163] For example, in at least one embodiment of the present disclosure, the second XOR hash unit also includes an establishment unit, which is configured to establish a mapping table of multiple values ​​of the first intermediate result and multiple values ​​of the second mapping address segment and multiple values ​​of the channel selection address segment.

[0164] For example, in at least one embodiment of the present disclosure, the remapping unit is further configured to map the second intermediate result to a corresponding value among multiple values ​​of the channel selection address segment according to a mapping table in response to the value of the second intermediate result being greater than or equal to the number of memory channels.

[0165] For example, in at least one embodiment of the present disclosure, the address processing module 401 includes a second scattering module and a second mapping module. The second scattering module is configured to perform a random scattering operation on the first address segment of the system memory address to obtain a scattering address segment; the second mapping module is configured to perform a mapping operation on the scattering address segment to obtain a first memory address. For example, the second scattering module can implement step S601, and its specific implementation method can refer to the relevant description of step S601; the second mapping module can implement step S602, and its specific implementation method can refer to the relevant description of step S602, which will not be repeated here.

[0166] For example, in at least one embodiment of the present disclosure, the number of memory channels is not a power of 2.

[0167] It should be noted that the above-mentioned address processing module 401 and allocation module 402 can be implemented by software, hardware, firmware or any combination thereof. For example, they can be implemented as an acquisition circuit, a determination circuit and a fitting circuit respectively. The embodiments of this disclosure do not limit their specific implementation methods.

[0168] It should be understood that the memory access device 400 provided in at least one embodiment of the present disclosure can be used to implement the aforementioned visual memory access method, and can also achieve technical effects similar to the aforementioned memory access method, which will not be elaborated here.

[0169] It should be noted that in the embodiments of the present disclosure, the memory access device 400 may include more or fewer modules or units, and the connection relationship between the modules or units is not limited and can be determined according to actual needs. The specific configuration of each module is not limited and can be composed of analog devices according to circuit principles, or can be composed of digital chips, or can be constructed in other applicable ways.

[0170] Figure 5 A schematic block diagram of an electronic device provided in accordance with at least one embodiment of the present disclosure.

[0171] For example, Figure 5 As shown, the electronic device 500 includes at least one processor 501 and a memory 502. The memory 502 includes one or more computer program modules. The one or more computer program modules are stored in the memory 502 and are configured to be executed by the at least one processor 501. The one or more computer program modules include instructions for executing the above-mentioned memory access method. When executed by the at least one processor 501, one or more steps in the memory access method provided in at least one embodiment of the present disclosure can be executed. The memory 502 and the processor 501 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0172] For example, the processor 501 may be a central processing unit (CPU), a digital signal processor (DSP), or other processing units with data processing capabilities and / or program execution capabilities, such as a field programmable gate array (FPGA). For example, the central processing unit (CPU) may be an X86, ARM, or RISC-V architecture. The processor 501 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 500 to perform desired functions.

[0173] For example, the memory 502 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc.

[0174] Figure 6 A schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0175] The electronic devices in at least one embodiment of the present disclosure may include but are not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), wearable electronic devices, etc., as well as fixed terminals such as digital TVs, desktop computers, etc. Figure 6 The electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0176] The electronic device includes at least one processor and a memory. The processor here can be referred to as the processing device 601 described below, and the memory can include at least one of the read-only memory (ROM) 602, the random access memory (RAM) 603, and the storage device 608 described below. The memory is used to store programs for executing the methods described in the above-mentioned various method embodiments; the processor is configured to execute the programs stored in the memory. The processor can be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and can control other components in the electronic device to perform desired functions.

[0177] like Figure 6 As shown, the electronic device 600 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage device 608 into a random access memory (RAM) 603. Various programs and data required for the operation of the electronic device 600 are also stored in the RAM 603. The processing device 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0178] Typically, the following devices may be connected to the I / O interface 605: an input device 606 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 607 including, for example, a display (e.g., a liquid crystal display (LCD) or an organic light emitting diode display (OLED)), a speaker, a vibrator, etc.; a storage device 608 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 609. The communication device 609 may allow the electronic device 600 to communicate with other devices wirelessly or by wire to exchange data. Although Figure 6The electronic device 600 is shown with various devices, but it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed instead.

[0179] In particular, according to at least one embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, at least one embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 609, or installed from the storage device 608, or installed from the ROM 602. When the computer program is executed by the processing device 601, the above-mentioned functions defined in the method of at least one embodiment of the present disclosure are performed.

[0180] It should be noted that the computer-readable medium described above in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. Computer-readable storage media may be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or components, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In at least one embodiment of the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device, or component. Furthermore, in at least one embodiment of the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wires, optical cables, RF (radio frequency), etc., or any suitable combination thereof.

[0181] The computer-readable medium may be included in the electronic device 600 , or may exist independently without being incorporated into the electronic device 600 .

[0182] Figure 7 A schematic block diagram of a non-transitory readable storage medium provided for at least one embodiment of the present disclosure.

[0183] For example, Figure 7 As shown, a non-transitory readable storage medium 700 stores computer instructions 701 , which, when executed by at least one processor, perform one or more steps of the above-mentioned memory access method.

[0184] For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above storage media, or other suitable storage media. For example, the readable storage medium may also be Figure 5 For the memory 502 in the embodiment, the related description can be referred to the aforementioned content and will not be repeated here.

[0185] Although the present disclosure has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made based on the embodiments of the present disclosure. Therefore, such modifications or improvements, as long as they do not depart from the spirit of the present disclosure, are within the scope of protection claimed by the present disclosure.

[0186] Regarding this disclosure, the following points need to be explained:

[0187] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0188] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale.

[0189] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0190] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A memory access method, wherein: The memory corresponds to multiple memory channels, The memory access method includes: performing an address processing operation on a first address segment of the system memory address to obtain a first memory address including a channel selection address segment, wherein the plurality of memory channels correspond one-to-one to a plurality of values ​​of the channel selection address segment; The corresponding memory channel is accessed according to multiple values ​​of the channel selection address segment.

2. The memory access method according to claim 1, wherein: The system memory address includes m1+1 address bits, The first address segment includes the m1th address bit to the m3th address bit of the system memory address, wherein m1 is an integer greater than 1, and m3 is an integer greater than 1 and less than m1.

3. The memory access method according to claim 2, wherein: The system memory address further includes a second address segment, and the second address segment includes the m3-1th address bit to the 0th address bit of the system memory address.

4. The memory access method according to claim 1, wherein: The memory access method further includes: The channel selection address segment in the first memory address is deleted to obtain a second memory address.

5. The memory access method according to claim 1, wherein: The performing of an address processing operation on the first address segment of the system memory address to obtain a first memory address including a channel selection address segment includes: Performing a mapping operation on the first address segment of the system memory address to obtain a mapped address segment; A random scattering operation is performed on the mapped address segment to obtain the first memory address.

6. The memory access method according to claim 5, wherein: The mapping address segment includes a first mapping address segment addr_cal[m1:m2] and a second mapping address segment addr_cal[m2-1:m3], The performing a mapping operation on the first address segment of the system memory address to obtain a mapped address segment includes: addr_cal[m1:m2]=addr_in[m1:m3] / N; addr_cal[m2-1:m3]=addr_in[m1:m3]%N, Wherein, addr_in[m1:m3] is the first address segment of the system memory address, N is the number of the memory channels, m2 is an integer smaller than m1, and m2-m3>log2N, and % represents a modulo operation.

7. The memory access method according to claim 5, wherein: The mapping address segment includes a first mapping address segment and a second mapping address segment, The performing a random scattering operation on the mapped address segment to obtain the first memory address includes: Performing a first XOR hash operation on a plurality of address bits in the first mapped address segment to obtain a first intermediate result; Performing a second XOR hash operation on the first intermediate result and the second mapping address segment to obtain the channel selection address segment; The second mapping address segment is replaced with the channel selection address segment to obtain the first memory address, wherein the first memory address includes the first mapping address segment and the channel selection address segment.

8. The memory access method according to claim 7, wherein: The performing a first XOR hash operation on a plurality of address bits in the first mapping address segment to obtain a first intermediate result includes: Dividing the plurality of address bits in the first mapped address segment into M groups of address bits, each group of the M groups of address bits including at least two address bits; Select at least two address bits in each group of address bits to perform a first exclusive-OR operation to obtain a corresponding exclusive-OR result; Combine the obtained M groups of XOR results to obtain the first intermediate result, The number of bits of the first intermediate result is M, and the number of bits of the first intermediate result is the same as the number of bits of the second mapping address segment.

9. The memory access method according to claim 7, wherein: The performing a second XOR hash operation on the first intermediate result and the second mapping address segment to obtain the channel selection address segment includes: Performing a second XOR operation on the first intermediate result and the second mapping address segment to obtain a second intermediate result; In response to the value of the second intermediate result being a valid value, using the second intermediate result as the channel selection address segment; In response to the value of the second intermediate result being an invalid value, a remapping operation is performed on the second intermediate result according to the first intermediate result and the second mapping address segment to obtain the channel selection address segment.

10. The memory access method according to claim 9, wherein: Before, in response to the value of the second intermediate result being an invalid value, performing a remapping operation on the second intermediate result according to the first intermediate result and the second mapping address segment, the method further includes: Establishing a mapping table of multiple values ​​of the first intermediate result, multiple values ​​of the second mapping address segment, and multiple values ​​of the channel selection address segment; In response to the value of the second intermediate result being an invalid value, performing a remapping operation on the second intermediate result according to the first intermediate result and the second mapping address segment, including: In response to a value of the second intermediate result being greater than or equal to the number of the memory channels, the second intermediate result is mapped to a corresponding value among multiple values ​​of the channel selection address segment according to the mapping table.

11. The memory access method according to claim 1, wherein: The performing of an address processing operation on the first address segment of the system memory address to obtain a first memory address including a channel selection address segment further includes: Performing a random scattering operation on the first address segment of the system memory address to obtain a scattering address segment; A mapping operation is performed on the scattered address segment to obtain the first memory address.

12. The memory access method according to any one of claims 1 to 11, wherein: The number of the memory channels is not a power of 2.

13. A memory access device, wherein the memory corresponds to a plurality of memory channels. The memory access device comprises: an address processing module configured to perform an address processing operation on a first address segment of a system memory address to obtain a first memory address including a channel selection address segment, wherein a plurality of memory channels correspond one-to-one to a plurality of values ​​of the channel selection address segment; The allocation module is configured to access the corresponding memory channel according to multiple values ​​of the channel selection address segment.

14. The memory access device according to claim 13, wherein: The memory access device further includes: The deletion module is configured to delete the channel selection address segment in the first memory address to obtain a second memory address.

15. The memory access device according to claim 13, wherein: The address processing module includes: A first mapping module is configured to perform a mapping operation on a first address segment of the system memory address to obtain a mapped address segment; The first scattering module is configured to perform a random scattering operation on the mapping address segment to obtain the first memory address.

16. The memory access device according to claim 15, wherein: The mapping address segment includes a first mapping address segment addr_cal[m1:m2] and a second mapping address segment addr_cal[m2-1:m3], The performing a mapping operation on the first address segment of the system memory address to obtain a mapped address segment includes: addr_cal[m1:m2]=addr_in[m1:m3] / N; addr_cal[m2-1:m3]=addr_in[m1:m3]%N, Wherein, addr_in[m1:m3] is the first address segment of the system memory address, N is the number of the memory channels, m2 is an integer smaller than m1, and m2-m3>log2N, and % represents a modulo operation.

17. The memory access device according to claim 15, wherein: The mapping address segment includes a first mapping address segment and a second mapping address segment, The first breaking up module includes: a first XOR hash unit, configured to perform a first XOR hash operation on a plurality of address bits in the first mapping address segment to obtain a first intermediate result; a second XOR hash unit, configured to perform a second XOR hash operation on the first intermediate result and the second mapping address segment to obtain the channel selection address segment; A replacement unit is configured to replace the second mapping address segment with the channel selection address segment to obtain the first memory address, wherein the first memory address includes the first mapping address segment and the channel selection address segment.

18. The memory access device according to claim 17, wherein: The first XOR hash unit includes: a segmentation unit configured to divide a plurality of address bits in the first mapped address segment into M groups of address bits, each group of address bits in the M groups of address bits including at least two address bits; a first XOR unit configured to select at least two address bits in each group of address bits to perform a first XOR operation to obtain a corresponding XOR result; A combining unit is configured to combine the obtained M groups of XOR results to obtain the first intermediate result, The number of bits of the first intermediate result is M, and the number of bits of the first intermediate result is the same as the number of bits of the second mapping address segment.

19. An electronic device comprising: at least one processor; a memory comprising one or more computer program modules; The one or more computer program modules are stored in the memory and configured to be executed by the at least one processor, and the one or more computer program modules are used to implement the memory access method according to any one of claims 1 to 12.

20. A non-transitory readable storage medium having computer instructions stored thereon, wherein: When the computer instructions are executed by at least one processor, the memory access method according to any one of claims 1 to 12 is implemented.

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