Excitation generation method and device and medium

Abstract

The invention relates to the technical field of computers, in particular to an incentive generation method and device and a medium, and the incentive generation method comprises the following steps: distributing a first number of multiple physical addresses, and distributing a second number of multiple page table entry addresses; for each virtual address in a third number of virtual addresses needing to be generated, selecting a corresponding target physical address from the plurality of physical addresses and selecting at least one target page table entry address for the target physical address from the plurality of page table entry addresses, determining page table item data and storing the page table item data in a target page table item to generate a corresponding virtual address; and generating excitation for verifying the memory management unit. According to the excitation generation method and device disclosed by the embodiment of the invention, the medium can realize dynamic simulation of flexible allocation of the memory address, strengthen randomized verification of the address and improve the verification coverage rate of the mapping relationship between the page table entries at all levels.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to an incentive generation method, device, and medium. Background Art

[0002] The main function of the memory management unit (MMU) is to map the virtual address (VA) in the request to access the main memory (Memory, or "memory") to the actual physical address (PA) of the main memory according to a certain mapping relationship. This mapping relationship is generated by the software running on the computer system and performing dynamic simulation address allocation and recorded in the page table (PT). The mapping relationship reflects the software's address management of the entire system. Different data requests may be mapped to physical spaces of different page sizes. By reasonably and flexibly adjusting the page size of the page table, the efficiency of the software's use of main memory will be improved. The software generates a page table and flexibly allocates actual storage addresses for storage. This process can be regarded as incentive generation.

[0003] At present, related technologies usually generate page table entries (PTE) according to the unit of page table, and the generated PTE is in the same page. This cannot truly simulate the flexible allocation of main memory addresses by software in actual situations, and may even cause simulation failure due to unreasonable allocation. Summary of the invention

[0004] In view of this, the present disclosure proposes an incentive generation method, device, and medium, which can realize dynamic simulation of flexible allocation of memory addresses, strengthen randomized verification of addresses, and improve the verification coverage of mapping relationships between page table entries at all levels.

[0005] According to one aspect of the present disclosure, a stimulus generation method is provided, including: allocating a first number of multiple physical addresses, and allocating a second number of multiple page table entry addresses; for each virtual address of a third number of virtual addresses that need to be generated, selecting a corresponding target physical address from the multiple physical addresses, and selecting at least one target page table entry address for the target physical address from the multiple page table entry addresses, determining page table entry data according to the target physical address and each of the target page table entry addresses, and storing the page table entry data in a target page table entry corresponding to each of the target page table entry addresses, generating a corresponding virtual address according to a first identifier of the target physical address and a second identifier of each of the target page table entry addresses; generating a stimulus for verifying a memory management unit according to the target physical address, the virtual address, and the target page table entry corresponding to each of the target page table entry addresses; wherein the target page table entries corresponding to each of the target page table entry addresses are in page tables of different levels.

[0006] In this way, by allocating a first number of multiple physical addresses and a second number of multiple page table entry addresses, as many PAs and addresses required by each level of PTE are generated as possible to strengthen the randomization verification of the address. By flexibly selecting the target physical address and each target page table entry address from the numerous allocated addresses and generating the corresponding virtual address, dynamic simulation of the flexible allocation of memory addresses can be achieved, and the verification coverage of the mapping relationship between page table entries at all levels can be improved. Based on the generated target physical address, virtual address, and each target page table entry, incentives are further generated to perform the verification process of the MMU UT, so as to improve the reliability and stability of the system and reduce MMU-related problems that may occur in actual use.

[0007] In a possible implementation, the page table includes at least one level, and the page table of each level includes a preset number of multiple page table entries; wherein the selecting of the corresponding target physical address from the multiple physical addresses and the selecting of at least one target page table entry address for the target physical address from the multiple page table entry addresses include: selecting the target physical address from the multiple physical addresses according to a preset selection method, wherein the preset selection method includes a random selection method; when the target physical address is not used, selecting the page table entry addresses corresponding to the page tables of each level in order from low to high levels of the page table, respectively A target page table entry address for the target physical address is selected; if the target physical address has been used, the target page table entry addresses for the target physical address previously selected are used as the target page table entry addresses for the virtual address to be generated this time; wherein, the page table entry data stored in the target page table entry in the lowest-level page table is data determined according to the target physical address; among the target page table entries of the remaining levels, the page table entry data stored in the target page table entry in the higher-level page table of the two target page table entries in the adjacent-level page tables is data determined according to the target page table entry address of the target page table entry in the lower-level page table.

[0008] In this way, reusing the content of the previously generated mapping relationship can increase the speed of generating the third number of mapping relationships, that is, the virtual address, and can simulate the application scenario of multiple virtual addresses accessing the same physical address. At the same time, it strengthens the randomization verification of the address and avoids the potential risk of address trampling. Randomness in the entire address space can increase the verification coverage of the correspondence between page table entries at all levels.

[0009] In a possible implementation, the target page table entry address for the target physical address is selected from the page table entry addresses corresponding to the page tables at each level in order from low to high, including: for each level of the page table, the target page table entry address is selected from the page table entry address corresponding to the current page table according to the preset selection method; when the target page table entry address is not used, continue to randomly select the target page table entry address corresponding to the higher-level page table; when the target page table entry address has been used, the target page table entry address corresponding to the higher-level page table corresponding to the target page table entry address previously selected is used as the remaining target page table entry addresses that have not been selected for the virtual address to be generated this time.

[0010] In this way, reusing the content of the previously generated mapping relationship can increase the speed of generating the third number of mapping relationships, that is, the virtual address, while strengthening the randomization verification of the address and avoiding the potential risk of address trampling. Randomness in the entire address space can increase the verification coverage of the correspondence between page table entries at all levels.

[0011] In one possible implementation, when the storage spaces respectively indicated by the multiple physical addresses are located in a continuous first storage space, the first identifier indicates the offset address of the corresponding target physical address relative to the base address of the first storage space; and / or, when the storage spaces respectively indicated by the multiple page table entry addresses are located in a continuous second storage space, the second identifier indicates the offset address of the corresponding target page table entry address relative to the base address of the second storage space.

[0012] In this way, the target physical address or the target page table entry address is represented by a base address plus an offset address, which simplifies the logic of address conversion, not only reduces the complexity of hardware design, but also reduces the possibility of errors.

[0013] In a possible implementation, the method further includes: setting the first quantity, the second quantity, and the third quantity according to a configuration parameter; wherein the configuration parameter is set based on verifying an application scenario of the memory management unit.

[0014] In this way, verifying the application scenario configuration parameters of the memory management unit helps to achieve randomness and controllability of later test cases, and facilitates the simultaneous development of directed test cases and random test cases.

[0015] In a possible implementation, the method further includes: randomly generating the configuration parameters based on verifying the constraint conditions corresponding to the application scenario of the memory management unit; and / or, in the case of a detected user input operation, determining the configuration parameters based on the user input operation.

[0016] In this way, by randomly generating configuration parameters according to the constraints corresponding to the application scenario of verifying the memory management unit, it can be ensured that the configuration parameters not only meet the requirements of specific application scenarios, but also have a certain degree of randomness, thereby enhancing the flexibility and adaptability of the system. Different application scenarios may have different performance requirements, resource limitations or specific workloads. The randomly generated configuration parameters can better adapt to these changes and enhance the randomness of the subsequent MMU UT verification process; allowing users to set configuration parameters through input operations, so that users can customize the number of VA, PA, and PTE at each level according to their own needs or preferences. This user-participated configuration method not only improves the user experience, but also makes the verification process closer to the actual needs of users.

[0017] According to another aspect of the present disclosure, a stimulus generation device is provided, comprising: an address allocation module, the address allocation module being configured to allocate a first number of multiple physical addresses, and a second number of multiple page table entry addresses; a first generation module, the first generation module being configured to select, for each virtual address of a third number of virtual addresses that need to be generated, a corresponding target physical address from the multiple physical addresses, and to select at least one target page table entry address for the target physical address from the multiple page table entry addresses, determine page table entry data according to the target physical address and each of the target page table entry addresses, store the page table entry data in a target page table entry corresponding to each of the target page table entry addresses, and generate a corresponding virtual address according to a first identifier of the target physical address and a second identifier of each of the target page table entry addresses; and a second generation module, the second generation module being configured to generate a stimulus for verifying a memory management unit according to the target physical address, the virtual address, and a target page table entry corresponding to each of the target page table entry addresses; wherein the target page table entries corresponding to each of the target page table entry addresses are in page tables of different levels.

[0018] In this way, a first number of multiple physical addresses and a second number of multiple page table entry addresses are allocated through the address allocation module, and enough PAs and addresses required by each level of PTE are generated as much as possible to strengthen the randomization verification of the address. The first generation module flexibly selects the target physical address and each target page table entry address from the numerous allocated addresses to generate the corresponding virtual address, which can realize dynamic simulation of flexible allocation of memory addresses and improve the verification coverage of the mapping relationship between page table entries at all levels. The second generation module is used to further generate incentives based on the generated target physical address, virtual address, and each target page table entry, so as to perform the verification process of the MMU UT, so as to improve the reliability and stability of the system and reduce MMU-related problems that may occur in actual use.

[0019] In a possible implementation, the page table includes at least one level, and the page table of each level includes a preset number of multiple page table entries; wherein the selecting of the corresponding target physical address from the multiple physical addresses and the selecting of at least one target page table entry address for the target physical address from the multiple page table entry addresses include: selecting the target physical address from the multiple physical addresses according to a preset selection method, wherein the preset selection method includes a random selection method; when the target physical address is not used, selecting the page table entry addresses corresponding to the page tables of each level in order from low to high levels of the page table, respectively A target page table entry address for the target physical address is selected; if the target physical address has been used, the target page table entry addresses for the target physical address previously selected are used as the target page table entry addresses for the virtual address to be generated this time; wherein, the page table entry data stored in the target page table entry in the lowest-level page table is data determined according to the target physical address; among the target page table entries of the remaining levels, the page table entry data stored in the target page table entry in the higher-level page table of the two target page table entries in the adjacent-level page tables is data determined according to the target page table entry address of the target page table entry in the lower-level page table.

[0020] In this way, reusing the content of the previously generated mapping relationship can increase the speed of generating the third number of mapping relationships, that is, the virtual address, and can simulate the application scenario of multiple virtual addresses accessing the same physical address. At the same time, it strengthens the randomization verification of the address and avoids the potential risk of address trampling. Randomness in the entire address space can increase the verification coverage of the correspondence between page table entries at all levels.

[0021] In a possible implementation, the target page table entry address for the target physical address is selected from the page table entry addresses corresponding to the page tables at each level in order from low to high, including: for each level of the page table, the target page table entry address is selected from the page table entry address corresponding to the current page table according to the preset selection method; when the target page table entry address is not used, continue to randomly select the target page table entry address corresponding to the higher-level page table; when the target page table entry address has been used, the target page table entry address corresponding to the higher-level page table corresponding to the target page table entry address previously selected is used as the remaining target page table entry addresses that have not been selected for the virtual address to be generated this time.

[0022] In this way, reusing the content of the previously generated mapping relationship can increase the speed of generating the third number of mapping relationships, that is, the virtual address, while strengthening the randomization verification of the address and avoiding the potential risk of address trampling. Randomness in the entire address space can increase the verification coverage of the correspondence between page table entries at all levels.

[0023] In one possible implementation, when the storage spaces respectively indicated by the multiple physical addresses are located in a continuous first storage space, the first identifier indicates the offset address of the corresponding target physical address relative to the base address of the first storage space; and / or, when the storage spaces respectively indicated by the multiple page table entry addresses are located in a continuous second storage space, the second identifier indicates the offset address of the corresponding target page table entry address relative to the base address of the second storage space.

[0024] In this way, the target physical address or the target page table entry address is represented by a base address plus an offset address, which simplifies the logic of address conversion, not only reduces the complexity of hardware design, but also reduces the possibility of errors.

[0025] In a possible implementation, the device also includes a setting module, which is configured to set the first quantity, the second quantity, and the third quantity according to configuration parameters; wherein the configuration parameters are set based on verifying an application scenario of the memory management unit.

[0026] In this way, verifying the application scenario configuration parameters of the memory management unit helps to achieve randomness and controllability of later test cases, and facilitates the simultaneous development of directed test cases and random test cases.

[0027] In one possible implementation, the device also includes a determination module, which is configured to: randomly generate the configuration parameters based on verifying the constraint conditions corresponding to the application scenario of the memory management unit; and / or, in the case of a detected user input operation, determine the configuration parameters based on the user input operation.

[0028] In this way, by randomly generating configuration parameters according to the constraints corresponding to the application scenario of verifying the memory management unit, it can be ensured that the configuration parameters not only meet the requirements of specific application scenarios, but also have a certain degree of randomness, thereby enhancing the flexibility and adaptability of the system. Different application scenarios may have different performance requirements, resource limitations or specific workloads. The randomly generated configuration parameters can better adapt to these changes and enhance the randomness of the subsequent MMU UT verification process; allowing users to set configuration parameters through input operations, so that users can customize the number of VA, PA, and PTE at each level according to their own needs or preferences. This user-participated configuration method not only improves the user experience, but also makes the verification process closer to the actual needs of users.

[0029] According to another aspect of the present disclosure, there is provided a stimulus generation device, comprising: a processor; a memory for storing processor executable instructions; wherein the processor is configured to implement the above-mentioned stimulus generation method when executing the instructions stored in the memory.

[0030] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, wherein the computer program instructions implement the above-mentioned stimulus generation method when executed by a processor.

[0031] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0033] Figure 1 A flowchart of a method for generating incentives according to an embodiment of the present disclosure is shown.

[0034] Figure 2 A schematic diagram showing a method for generating incentives according to an embodiment of the present disclosure is shown.

[0035] Figures 3 to 6 A schematic diagram of the process of generating a virtual address in the stimulus generation method provided according to an embodiment of the present disclosure is shown.

[0036] Figure 7 A block diagram of an incentive generating device provided according to an embodiment of the present disclosure is shown.

[0037] Figure 8 A block diagram of an incentive generating device provided according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0038] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0039] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0040] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0041] In order to facilitate those skilled in the art to understand the technical solution provided by the embodiments of the present disclosure, the technical environment in which the technical solution is implemented is described below.

[0042] In the related art, page table entries are usually generated according to the unit of the page table, and the generated PTEs are in the same page. From the perspective of memory, PTEs with adjacent addresses are in the same page. This adjacent address is relative to the real storage memory, and is the address where the PTE is actually placed in the storage memory. In addition, the relevant scheme usually sets the page table size in the early stage, so that the generated PTEs are not only in the same page, but also have the same page table size. In addition, when simulating the address management of the entire system by the software, the stimulus is generally generated in the order of VA→PTE at all levels→PA. Furthermore, several address intervals are generally fixedly divided for PA and page table entries (Page Table Entry, PTE) at all levels. However, since the address space is relatively fixed, it is impossible to truly simulate the flexible allocation of the main memory address by the software in the actual situation, and even unreasonable allocation may occur, resulting in insufficient address space allocated to a certain level of PTE resources, and ultimately the simulation fails. In addition, when a PTE generates an error, it is necessary to use a waveform to assist debugging, which has low overall efficiency and is difficult to quickly locate the error information. Therefore, it is of great significance to study the stimulus generation method.

[0043] In order to solve the above technical problems, the embodiment of the present disclosure provides an incentive generation method, which generates as many PAs and addresses required by PTEs at all levels as possible by allocating a first number of multiple physical addresses and a second number of multiple page table entry addresses, and then for each virtual address of the third number of virtual addresses to be generated, selects a corresponding target physical address from the multiple physical addresses, and selects at least one target page table entry address for the target physical address from the multiple page table entry addresses, determines page table entry data according to the target physical address and each target page table entry address, and stores the page table entry data in each target page table entry. The page table entry data in the target page table entry corresponding to the address generates a corresponding virtual address according to the first identifier of the target physical address and the second identifier of each target page table entry address, so as to generate a physical address, each target page table entry address, and a virtual address in sequence, thereby generating a stimulus for verifying the memory management unit according to the target physical address, the virtual address, and the target page table entries corresponding to each target page table entry address, wherein the target page table entries corresponding to each target page table entry address are in page tables of different levels. In this way, dynamic simulation of flexible allocation of memory addresses can be achieved, random verification of addresses can be strengthened, and verification coverage of mapping relationships between page table entries at all levels can be improved.

[0044] Figure 1 A flowchart of a method for generating incentives according to an embodiment of the present disclosure is shown. Figure 2 A schematic diagram showing a method for generating incentives according to an embodiment of the present disclosure is shown. Figures 3 to 6 A schematic diagram showing a virtual address generated by the stimulus generation method provided in an embodiment of the present disclosure is shown. Figures 1 to 6 The incentive generation method provided in the embodiment of the present disclosure is schematically illustrated.

[0045] The stimulus generation method provided in the embodiment of the present disclosure can be applied to the verification process of the MMU UT to generate the required stimulus, so that the verification process of the MMU UT can be performed according to the generated stimulus. Figure 1 As shown, the incentive generation method may include the following steps S101 to S103.

[0046] Step S101: Allocate a first number of multiple physical addresses, and allocate a second number of multiple page table entry addresses.

[0047] Among them, the physical address can be the PA that the MMU needs to manage, and the page table entry address is also the actual physical address. The first quantity and the second quantity can be set according to actual needs, and the embodiments of the present disclosure are not specifically limited. The first quantity and the second quantity can be determined based on the configuration parameters used when generating the required stimulus. The configuration parameters can be set based on the application scenario of verifying the memory management unit, wherein the application scenario can be the scenario expected to be simulated, such as the scenario where the MMU bypass translation buffer (Translation Lookaside Buffer, TLB) is hit. The configuration parameters can be set randomly, can be manually specified, or can be manually modified after random generation. This helps to achieve randomness and controllability of later test cases, and facilitates the simultaneous development of directed test cases and random test cases. The process of setting the first quantity and the second quantity is detailed later.

[0048] The address allocation method may be random allocation, and the physical address and the page table entry address may be any unused address in the current memory space that is sufficient to accommodate the current page table content in the current application scenario. Through step S101, sufficient addresses required by the PA and sufficient addresses required by each level of PTE may be allocated, and these addresses may all be randomly scattered to strengthen the randomization verification of the address.

[0049] Before explaining the process of allocating addresses, the page table item address, page table item, page table, and page table item data in the embodiment of the present disclosure are now explained to better explain the incentive generation method provided by the embodiment of the present disclosure. The page table PT is a data structure for managing the mapping relationship between virtual memory and physical memory. The page table may include at least one level. In other words, the page table may include a first-level page table, a second-level page table, a third-level page table...N-level page tables with decreasing levels. The number of page tables in each level of the page table can be set to the same number or different numbers according to actual conditions. In the multi-level page table, each level of the page table can be set with a different page table size. In this way, through the present incentive generation method, it can be realized that the PTEs on adjacent addresses are from different page tables and have different page table sizes (different page table sizes and different page tables have different PTEs), so as to achieve complete address isolation, wherein the adjacent address is relative to the real storage memory and is the address where the PTE is actually placed in the storage memory. The page table entry PTE is an entry in the page table. According to the different levels of the page table where the page table entry is located, the page table entry can also be divided into the first-level page table entry, the second-level page table entry, the third-level page table entry...N-level page table entry. The number of page table entries in each level of page table entry (that is, the number of all page table entries in each level of the page table) can be set to the same number or different numbers according to the actual situation. The page table entry address refers to the location of the corresponding page table entry in the memory. Through the page table entry address, a storage space can be determined and the data stored in the corresponding page table entry can be obtained from the storage space. This data is the page table entry data. The page table entry address, page table entry, and page table entry data are one-to-one corresponding. Similarly, according to the different levels of the page table where the page table entry is located, the page table entry address can also be divided into the first-level page table entry address, the second-level page table entry address, the third-level page table entry address...N-level page table entry address, among which the first-level page table entry address corresponds to the first-level page table entry, and the first-level page table entry is in the first-level page table. The page table entry addresses of other levels are similar to this. For the sake of brevity, this article will not repeat them. It should be noted that the description of the page table entry in this article is also applicable to the target page table entry.

[0050] During the verification process of the MMU UT, a block of memory can be instantiated in the verification environment to maintain the usage status of different addresses to simulate real memory usage. In some embodiments, a virtual memory block can be created in the verification environment. This memory block can be represented by an array, a list, or a special memory simulation structure. This memory block can be a fixed size or configurable. The specific size of the memory block can be flexibly set according to the actual application scenario. Each memory location or address in the memory block can store certain data, which can be of any data type, depending on the requirements of the verification environment. A status flag can be assigned to each address to indicate that the current address is in a usage state such as free, allocated, read-only, or writable. In this way, the traceability of the usage status of the memory address in the real operating system can be simulated, thereby ensuring the accuracy of the verification.

[0051] After instantiating the memory, you can use the first number of physical addresses (i.e. x p ) and the second number of page table entry addresses (i.e., x1, x2, ... x n The sum of the two random addresses is randomly assigned to any unused address in the current memory space that is large enough to hold the current page table content in the current application scenario. Among them, i represents the corresponding page table level, n is the level of the lowest level page table, i∈[1,n], x i is the preset number of page table entries in the i-level page table LVi, and can also be called the preset number of optional page table entry addresses in the i-level page table. The second number of page table entry addresses can also be called the second number of page table entries.

[0052] In the process of random address allocation, x p PA allocation x p addresses, such as PA_addr_1, PA_addr_2, ... PA_addr_x p x1 first-level page table entry addresses can be allocated to x1 page table entries of the highest level first-level page table LV1, such as LV1_addr_1, LV1_addr_2, ... LV1_addr_x1, and x2 second-level page table entry addresses can be allocated to x2 page table entries of the second-level page table LV2, such as LV2_addr_1, LV2_addr_2, ... LV2_addr_x2, and the same can be applied to x2 page table entries of the lowest level N-level page table LVn. n Page table entries are allocated x n N-level page table entry addresses, such as LVn_addr_1, LVn_addr_2, ... LVn_addr_x n Among them, users can set PA_addr_1, PA_addr_2...PA_addr_x according to actual needs. p This p Whether there is an identical address in the addresses, the same applies to the page table entry addresses of page table entries at all levels, and the embodiments of the present disclosure do not limit this.

[0053] Step S102: for each virtual address of the third number of virtual addresses that need to be generated, select a corresponding target physical address from multiple physical addresses, and select at least one target page table entry address for the target physical address from multiple page table entry addresses, determine page table entry data according to the target physical address and each target page table entry address, and store the page table entry data in the target page table entry corresponding to each target page table entry address, and generate a corresponding virtual address according to a first identifier of the target physical address and a second identifier of each target page table entry address.

[0054] The third number can be set according to actual needs, and the embodiment of the present disclosure does not specifically limit it. The third number can be determined and set based on the configuration parameters used when generating the required incentive.

[0055] The process of setting the first quantity, the second quantity and the third quantity is schematically described below.

[0056] In this embodiment, the first number, the second number, and the third number may be determined based on the configuration parameters used to generate the required stimulus. The configuration parameters may be used to indicate the following: p , the preset number of page table entry addresses at each level is x i , the third quantity x of VA v . Where i∈[1,n], x1, x2, … x n The sum is the second quantity. The meanings of i and n have been explained above and will not be repeated here.

[0057] In a possible implementation, configuration parameters may be randomly generated according to the constraints corresponding to the application scenario of the memory management unit for verification. The application scenario may be a scenario that is desired to be simulated. Different application scenarios have different corresponding constraints. Under the action of the constraints, the number of VA, PTEs at all levels, and PAs may be randomly generated to form configuration parameters. In this way, by randomly generating configuration parameters according to the constraints corresponding to the application scenario of the memory management unit for verification, it is possible to ensure that the configuration parameters not only meet the requirements of specific application scenarios, but also have a certain degree of randomness, thereby enhancing the flexibility and adaptability of the system. Different application scenarios may have different performance requirements, resource constraints, or specific workloads. The randomly generated configuration parameters can better adapt to these changes and enhance the randomness of the subsequent MMU UT verification process.

[0058] In the case of randomly generating configuration parameters, the third number of VAs can be determined first. In some embodiments, the application scenario expected to be simulated for the test cases generated subsequently is to simulate the scenario of TLB being hit, and it is necessary to constrain the third number of VAs to be greater than the first number of PAs, so that some VAs corresponding to the same PA can be generated. It should be noted that although the third number of VAs is introduced using the scenario of TLB being hit as an example, those skilled in the art can understand that the embodiments of the present disclosure should not be limited thereto. In fact, the user can flexibly set the number of VAs according to the actual application scenario.

[0059] The preset number of PTEs at each level depends on the situation. For example, when the number of levels included in the page table is three, that is, the page table includes a first-level page table LV1, a second-level page table LV2, and a third-level page table LV3, the preset number of PTEs of the lowest level LV3 can be more than the first number of PAs, so that each PA can be guaranteed to have a corresponding LV3 PTE; the preset number of PTEs of LV2 can be half to one times the first number of PAs, so that some of the PTEs of LV2 can be reused, so that the same application scenario of LV2 PTE can be simulated, that is, multiple mapping relationships formed subsequently use the same PTE in LV2; the preset number of PTEs of the highest level LV1 can be one-fifth to half of the first number of PAs, so that some of the PTEs of LV1 can be reused, so that the same application scenario of LV1 PTE can be simulated, that is, multiple mapping relationships formed subsequently use the same PTE in LV1. It should be noted that although the three-level page table is used as an example, those skilled in the art can understand that the embodiments of the present disclosure should not be limited to this. In fact, the user can flexibly set the number of levels according to the actual application scenario, the size of the address space, etc. In addition, the above constraints (the third number is greater than the first number, the preset number of PTEs of LV3 is greater than the first number, the preset number of PTEs of LV2 is half to one times the first number, and the preset number of PTEs of the highest level LV1 is one-fifth to one-half of the first number) are only used as examples to introduce how to set constraints according to application scenarios. The embodiments of the present disclosure are not limited to this. Users can flexibly set constraints according to actual application scenarios.

[0060] In a possible implementation, when a user input operation is detected, the configuration parameters can be determined according to the user input operation. The user can configure the number of VA, PA, and PTE at each level in the interface for inputting configuration parameters according to the specific use case, and then the configuration parameters can be generated according to the user's settings. In this way, the user is allowed to set the configuration parameters through input operations, so that the user can customize the number of VA, PA, and PTE at each level according to his or her needs or preferences. This user-involved configuration method not only improves the user experience, but also makes the verification process closer to the actual needs of the user.

[0061] In a possible implementation, configuration parameters may be randomly generated according to the constraint conditions corresponding to the application scenario of the verification memory management unit, and then, when a user modification operation on the randomly generated configuration parameters is detected, the configuration parameters modified by the user are used as the final configuration parameters.

[0062] After determining the first number, the second number, and the third number, any unused address in the current memory space that is large enough to accommodate the current page table content in the current application scenario can be randomly assigned to the first number of physical addresses and the second number of page table entries at all levels. After completing the address assignment, step S102 can be executed.

[0063] Each of the third number of virtual addresses required to be generated in step S102 includes at least a first identifier and a second identifier. Whether other information is included can be set according to actual needs, and the embodiment of the present disclosure does not limit this.

[0064] The first identifier corresponds to the target physical address. The target physical address can be distinguished from other physical addresses based on the first identifier, and the number of first identifiers in the virtual address is one. The second identifier corresponds to each target page table entry address. The target page table entry address can be distinguished from other page table entry addresses based on the second identifier. The number of second identifiers in the virtual address is the same as the number of target page table entry addresses corresponding to the virtual address. Among them, since the target page table entry address, the target page table entry, and the page table entry data stored in the target page table entry are in a one-to-one correspondence, the number of second identifiers in the virtual address is the same as the number of target page table entries corresponding to the virtual address and the number of page table entry data stored in the target page table entry corresponding to the virtual address.

[0065] The target page table entries corresponding to the target page table entry addresses corresponding to the virtual address are in page tables of different levels. The number of target page table entry addresses corresponding to the virtual address depends on the number of levels of the current page table. For example, assuming that the number of levels included in the current page table is three, the page table may include a first-level page table, a second-level page table, and a third-level page table. The target page table entry addresses used to generate each virtual address include a first-level target page table entry address, a second-level target page table entry address, and a third-level target page table entry address. The number of second identifiers in the generated virtual address is three, and these three second identifiers are determined according to the determined first-level target page table entry address, the second-level target page table entry address, and the third-level target page table entry address.

[0066] Each physical address can be determined by the corresponding base address and offset address, wherein the base address can represent the starting address of the storage space indicated by the physical address, and the offset address can represent the offset of the physical address relative to the base address, and the physical address can be determined by the base address and the offset address. The page table entry address is similar to the physical address, and for the sake of brevity, it will not be repeated. In some embodiments, when the storage spaces indicated by multiple physical addresses are located in a continuous first storage space, the first identifier can indicate the offset address of the corresponding target physical address relative to the base address of the first storage space; and / or, when the storage spaces indicated by multiple page table entry addresses are located in a continuous second storage space, the second identifier can indicate the offset address of the corresponding target page table entry address relative to the base address of the second storage space. The base address corresponding to the target physical address and the base address corresponding to the page table entry address can be used as a basis for determining the page table entry data. In this way, the target physical address or the target page table entry address is represented by the base address plus the offset address, which simplifies the logic of address conversion, not only reduces the complexity of hardware design, but also reduces the possibility of errors.

[0067] It should be noted that the target physical address is determined from multiple physical addresses, and the target page table entry address is determined from multiple page table entry addresses. The description of the physical address in this article also applies to the target physical address, and the description of the page table entry address also applies to the target page table entry address.

[0068] In a possible implementation, the step S102 of selecting a corresponding target physical address from a plurality of physical addresses and selecting at least one target page table entry address for the target physical address from a plurality of page table entry addresses may include: selecting the target physical address from a plurality of physical addresses according to a preset selection method, and the preset selection method may include other selection methods such as a random selection method; when the target physical address is not used, selecting the target page table entry address for the target physical address from the page table entry addresses corresponding to each level of the page table in order from low to high levels; when the target physical address has been used, using the previously selected target page table entry addresses for the target physical address as the target page table entry addresses used for the virtual address to be generated this time. In this way, reusing the content of the mapping relationship that has been generated before can increase the speed of generating the third number of mapping relationships, i.e., virtual addresses, and can simulate the application scenario of multiple virtual addresses accessing the same physical address, while strengthening the randomization verification of the address, and avoiding the potential risk of address trampling, and randomly increasing the verification coverage of the corresponding relationship between page table entries at all levels in the full address space.

[0069] In a possible implementation, the step S102 selects the target page table entry address for the target physical address from the page table entry addresses corresponding to the page tables at each level in order from low to high levels, which may include: for each level of page table, selecting the target page table entry address from the page table entry address corresponding to the current page table according to a preset selection method; when the target page table entry address is not used, continue to randomly select the target page table entry address corresponding to the higher level page table; when the target page table entry address has been used, use the target page table entry address corresponding to the higher level page table previously selected corresponding to the target page table entry address as the remaining target page table entry addresses not yet selected for the virtual address to be generated this time. In this way, reusing the content of the mapping relationship that has been generated before can increase the speed of generating the third number of mapping relationships, that is, virtual addresses, while strengthening the random verification of addresses, and avoiding potential address trampling risks. Randomly in the full address space can increase the verification coverage of the corresponding relationship between page table entries at all levels.

[0070] In step S102, in the process of selecting the target physical address and each target page table item address and determining each page table item data, the order relationship of determining the address and the page table item data can be set according to actual needs. For example, the address can be determined as a whole first and then the data can be determined as a whole, that is, the target physical address and each target page table item address are determined first, and then the page table item data is determined according to the target physical address and each target page table item address. Alternatively, the address and data can be determined alternately, that is, the target physical address is determined first, the lowest level page table item data is determined according to the target physical address, and then the lowest level page table item address is determined, and the page table item data of a higher level relative to the lowest level is determined according to the lowest level page table item address, and so on.

[0071] In order to better illustrate the execution process of step S102, a generated virtual address, a target physical address used to generate the virtual address, and target page table item addresses at all levels are now simplified as a mapping relationship. Therefore, step S102 can be regarded as a process of generating a third number of mapping relationships. In step S102, each mapping relationship is generated in the manner of first determining the target physical address, then determining the target page table items at all levels, and finally generating the virtual address. Among them, in the same mapping relationship, the page table item data stored in the target page table item in the lowest level page table is data determined according to the target physical address, and in the target page table items of the remaining level page tables, the page table item data stored in the target page table item in the higher level page table of the two target page table items in the adjacent level page tables is data determined according to the target page table item address corresponding to the target page table item in the lower level page table; the virtual address can be spliced ​​from the target physical address and the offset address of each address in each target page table item address, that is, at least including the first identifier and each second identifier.

[0072] The process of generating the mapping relationship in step S102 is now described by taking the method of alternately determining the address and data and the number of levels of the page table including three as an example. In this example, the first-level page table, the second-level page table, and the third-level page table, the page table with the lowest level is the third-level page table, the page table with the highest level is the first-level page table, and the level of the second-level page table is higher than the third-level page table but lower than the first-level page table.

[0073] like Figure 2 As shown, from multiple optional physical addresses PA_addr_1, PA_addr_2...PA_addr_x p One of the physical addresses PA_addr_1 is randomly selected as the target physical address (PA_addr). Then the following process can be performed according to the usage of the target physical address: When the target physical address PA_addr_1 is used, it means that before the mapping relationship is generated this time, the subsequent steps of generating the mapping relationship have been performed based on PA_addr_1. Then, the target page table entry addresses for PA_addr_1 in the previously generated mapping relationship (i.e., the third-level target page table entry address, the second-level target page table entry address, and the first-level target page table entry address) can be used as the target page table entry addresses used for the virtual address in the mapping relationship to be generated this time, and the page table entry data determined according to PA_addr_1 and the target page table entry addresses are stored in the target page table entries, and the root page table entry in the previously generated mapping relationship is stored in the target page table entries. The first identifier generated according to PA_addr_1 is used as the first identifier for the virtual address in the mapping relationship to be generated this time, and the three second identifiers generated by the page table item data generated according to PA_addr_1 and the target page table item addresses in the previously generated mapping relationship are used as the three second identifiers for the virtual address in the mapping relationship to be generated this time. In this way, reusing the content of the previously generated mapping relationship can increase the speed of generating the third number of mapping relationships, that is, the virtual addresses, and can simulate the application scenario of multiple virtual addresses accessing the same physical address. At the same time, it strengthens the randomization verification of the address and avoids the potential risk of address trampling. Randomness in the entire address space can increase the verification coverage of the correspondence between page table items at all levels.

[0074] In the case where the target physical address PA_addr_1 is not used, the page table entry data (LV3_data) can be determined according to PA_addr_1, and the page table entry data can be the base address of PA_addr_1, and the page table entry data is stored at the third-level target page table entry in the third-level page table, and the first identifier can be determined according to PA_addr_1, and the first identifier can be the offset address of PA_addr_1, and Figure 3 As shown, the first identifier is placed in bits 0 to 11 of the virtual address.

[0075] Next, for the lowest level three page table, such as Figure 2 As shown, one of the third-level page table entry addresses LV3_addr_3 is randomly selected from multiple optional third-level page table entry addresses LV3_addr_1, LV3_addr_2, LV3_addr_3...LV3_addr_x3 as the third-level target page table entry address (LV3_addr), and the following process can be continued according to the usage of the third-level target page table entry address: In the case where the third-level target page table entry address LV3_addr_3 is used, it means that before the mapping relationship is generated this time, the subsequent steps of generating the mapping relationship have been performed based on LV3_addr_3, then the target page table entry address corresponding to the higher-level page table corresponding to LV3_addr_3 in the previously generated mapping relationship (i.e., the secondary target The page table entry address, the first-level target page table entry address) are used as the remaining target page table entry addresses that have not been selected for the virtual address in the mapping relationship to be generated this time, and the remaining page table entry data determined according to LV3_addr_3 are stored in the remaining target page table entries, and the three second identifiers generated according to LV3_addr_3 in the previously generated mapping relationship are used as the three second identifiers for the virtual address in the mapping relationship to be generated this time. In this way, reusing the content of the previously generated mapping relationship can increase the speed of generating the third number of mapping relationships, that is, the virtual addresses, and at the same time strengthen the random verification of the addresses, avoid potential address trampling risks, and randomly increase the verification coverage of the corresponding relationships between page table entries at all levels in the entire address space.

[0076] When the third-level target page table entry address LV3_addr_3 is not used, the page table entry data (LV2_data) can be determined according to LV3_addr_3, and the page table entry data can be the base address of LV3_addr_3, and the page table entry data is stored at the second-level target page table entry in the second-level page table, and the first second identifier can be determined according to LV3_addr_3, and the first second identifier can be the offset address of LV3_addr_3, and as shown in FIG. Figure 4 As shown, the first second identifier is placed in bits 12 to 20 of the virtual address.

[0077] Next, for the secondary page table, such as Figure 2As shown, one of the secondary page table entry addresses LV2_addr_2 is randomly selected from multiple optional secondary page table entry addresses LV2_addr_1, LV2_addr_2...LV2_addr_x2 as the secondary target page table entry address (LV2_addr), and the page table entry data (LV1_data) can be further determined according to the usage of the secondary target page table entry address and stored in the target page table entry in the primary page table. The page table entry data can be the base address of LV2_addr_2, and a second second identifier can be determined according to LV2_addr_2, and the second second identifier can be the offset address of LV2_addr_2, and as shown Figure 5 As shown, the second second identifier is placed in the 21st to 29th bits of the virtual address. The process of continuing to determine the page table entry data (LV1_data) and the second second identifier according to the usage of the secondary target page table entry address can be similar to the process performed according to the usage of the tertiary target page table entry address. For the sake of brevity, the text will not be repeated.

[0078] Next, for the first-level page table, such as Figure 2 As shown, one of the first-level page table entry addresses LV1_addr_1 is randomly selected from multiple optional first-level page table entry addresses LV1_addr_1, LV1_addr_2, ... LV1_addr_x1 as the first-level target page table entry address (LV1_addr). When the first-level target page table entry address LV1_addr_1 is not used, the third second identifier can be determined according to LV1_addr_1. The third second identifier can be the offset address of LV1_addr_1, and as shown in FIG. Figure 6 As shown, the third second identifier is placed in the 30th to 38th bits of the virtual address to obtain a complete virtual address. When the first-level target page table entry address LV1_addr_1 is used, the third second identifier generated according to LV1_addr_1 in the previously generated mapping relationship can be used as the third second identifier used for the virtual address in the mapping relationship to be generated this time.

[0079] After the mapping relationships satisfying the third quantity are generated, these mapping relationships may be printed into a unified file for auxiliary verification, so that the user can easily see the corresponding relationships and error messages.

[0080] In general, the process of determining the virtual address, physical address, and page table entries at all levels corresponding to the addresses of each target page table entry in step S102 is performed by first determining the physical address, then determining the addresses corresponding to the page table entries at all levels, and finally generating the virtual address. Among them, the incentive generation method is to sequentially determine the PTEs corresponding to the N-level page table, the N-1-level page table... the first-level page table, and then write the page table in units of PTE, and then write the page table information into the memory. This is different from the current related scheme of writing to the memory in units of page tables, and the incentive generation method is more in line with actual application scenarios.

[0081] Through step S102, the target physical address and each target page table entry address can be flexibly selected from the numerous addresses allocated in step S101 to generate the corresponding virtual address, thereby realizing dynamic simulation of flexible allocation of memory addresses and improving the verification coverage of the mapping relationship between page table entries at all levels.

[0082] Step S103: Generate multiple stimuli for verifying the memory management unit according to the target physical address, the virtual address, and the target page table entries corresponding to the target page table entry addresses.

[0083] Among them, the stimulus can be understood as the input signal (which may include input instructions and input data) used in the verification process of the MMU UT, and its specific content can be set according to the actual test requirements. In some embodiments, the stimulus can be adjusted, including the target physical address, target page table entries at all levels, and virtual addresses under the same mapping relationship, to comprehensively test the conversion logic, error handling mechanism, and performance of the MMU, so as to ensure the correctness and reliability of the MMU in the actual operating environment. Since the general MMU first determines the corresponding PTEs at all levels according to the virtual address, and then determines the corresponding physical address, in some embodiments, the stimulus can be set to include only the generated virtual address. Similarly, in this case, the stimulus can generate all physical addresses and all required PTEs except the virtual address. It should be noted that the stimulus composition shown in the above embodiment is only an example, and those skilled in the art can understand that the embodiments of the present disclosure should not be limited to this. In fact, the user can flexibly set the stimulus composition according to the actual test requirements.

[0084] Step S103 can further generate stimulus according to the target physical address, virtual address, and target page table entries generated in step S102, thereby performing the verification process of the MMU UT to improve the reliability and stability of the system and reduce MMU-related problems that may occur in actual use.

[0085] The disclosed embodiment also provides an incentive generating device. Figure 7 FIG. 2 is a block diagram of an incentive generating device provided according to an embodiment of the present disclosure. Figure 7As shown, the stimulus generating device 700 may include: an address allocation module 700, the address allocation module 700 is configured to allocate a first number of multiple physical addresses, and allocate a second number of multiple page table entry addresses; a first generating module 701, the first generating module 701 is configured to select a corresponding target physical address from the multiple physical addresses for each virtual address of the third number of virtual addresses to be generated, and select at least one target page table entry address for the target physical address from the multiple page table entry addresses, determine page table entry data according to the target physical address and each of the target page table entry addresses, and store the page table entry data in a target page table entry corresponding to each of the target page table entry addresses, and generate a corresponding virtual address according to a first identifier of the target physical address and a second identifier of each of the target page table entry addresses; a second generating module 702, the second generating module 702 is configured to generate a stimulus for verifying a memory management unit according to the target physical address, the virtual address, and the target page table entry corresponding to each of the target page table entry addresses; wherein the target page table entries corresponding to each of the target page table entry addresses are in page tables of different levels.

[0086] In this way, a first number of multiple physical addresses and a second number of multiple page table entry addresses are allocated through the address allocation module, and enough PAs and addresses required by each level of PTE are generated as much as possible to strengthen the randomization verification of the address. The first generation module flexibly selects the target physical address and each target page table entry address from the numerous allocated addresses to generate the corresponding virtual address, which can realize dynamic simulation of flexible allocation of memory addresses and improve the verification coverage of the mapping relationship between page table entries at all levels. The second generation module is used to further generate incentives based on the generated target physical address, virtual address, and each target page table entry, so as to perform the verification process of the MMU UT, so as to improve the reliability and stability of the system and reduce MMU-related problems that may occur in actual use.

[0087] In a possible implementation, the page table includes at least one level, and the page table of each level includes a preset number of multiple page table entries; wherein the selecting of the corresponding target physical address from the multiple physical addresses and the selecting of at least one target page table entry address for the target physical address from the multiple page table entry addresses include: selecting the target physical address from the multiple physical addresses according to a preset selection method, wherein the preset selection method includes a random selection method; when the target physical address is not used, selecting the page table entry addresses corresponding to the page tables of each level in order from low to high levels of the page table, respectively A target page table entry address for the target physical address is selected; if the target physical address has been used, the target page table entry addresses for the target physical address previously selected are used as the target page table entry addresses for the virtual address to be generated this time; wherein, the page table entry data stored in the target page table entry in the lowest-level page table is data determined according to the target physical address; among the target page table entries of the remaining levels, the page table entry data stored in the target page table entry in the higher-level page table of the two target page table entries in the adjacent-level page tables is data determined according to the target page table entry address of the target page table entry in the lower-level page table.

[0088] In this way, reusing the content of the previously generated mapping relationship can increase the speed of generating the third number of mapping relationships, that is, the virtual address, and can simulate the application scenario of multiple virtual addresses accessing the same physical address. At the same time, it strengthens the randomization verification of the address and avoids the potential risk of address trampling. Randomness in the entire address space can increase the verification coverage of the correspondence between page table entries at all levels.

[0089] In a possible implementation, the target page table entry address for the target physical address is selected from the page table entry addresses corresponding to the page tables at each level in order from low to high, including: for each level of the page table, the target page table entry address is selected from the page table entry address corresponding to the current page table according to the preset selection method; when the target page table entry address is not used, continue to randomly select the target page table entry address corresponding to the higher-level page table; when the target page table entry address has been used, the target page table entry address corresponding to the higher-level page table corresponding to the target page table entry address previously selected is used as the remaining target page table entry addresses that have not been selected for the virtual address to be generated this time.

[0090] In this way, reusing the content of the previously generated mapping relationship can increase the speed of generating the third number of mapping relationships, that is, the virtual address, while strengthening the randomization verification of the address and avoiding the potential risk of address trampling. Randomness in the entire address space can increase the verification coverage of the correspondence between page table entries at all levels.

[0091] In one possible implementation, when the storage spaces respectively indicated by the multiple physical addresses are located in a continuous first storage space, the first identifier indicates the offset address of the corresponding target physical address relative to the base address of the first storage space; and / or, when the storage spaces respectively indicated by the multiple page table entry addresses are located in a continuous second storage space, the second identifier indicates the offset address of the corresponding target page table entry address relative to the base address of the second storage space.

[0092] In this way, the target physical address or the target page table entry address is represented by a base address plus an offset address, which simplifies the logic of address conversion, not only reduces the complexity of hardware design, but also reduces the possibility of errors.

[0093] In a possible implementation, the device also includes a setting module, which is configured to set the first quantity, the second quantity, and the third quantity according to configuration parameters; wherein the configuration parameters are set based on verifying an application scenario of the memory management unit.

[0094] In this way, verifying the application scenario configuration parameters of the memory management unit helps to achieve randomness and controllability of later test cases, and facilitates the simultaneous development of directed test cases and random test cases.

[0095] In one possible implementation, the device also includes a determination module, which is configured to: randomly generate the configuration parameters based on verifying the constraint conditions corresponding to the application scenario of the memory management unit; and / or, in the case of a detected user input operation, determine the configuration parameters based on the user input operation.

[0096] In this way, by randomly generating configuration parameters according to the constraints corresponding to the application scenario of verifying the memory management unit, it can be ensured that the configuration parameters not only meet the requirements of specific application scenarios, but also have a certain degree of randomness, thereby enhancing the flexibility and adaptability of the system. Different application scenarios may have different performance requirements, resource limitations or specific workloads. The randomly generated configuration parameters can better adapt to these changes and enhance the randomness of the subsequent MMU UT verification process; allowing users to set configuration parameters through input operations, so that users can customize the number of VA, PA, and PTE at each level according to their own needs or preferences. This user-participated configuration method not only improves the user experience, but also makes the verification process closer to the actual needs of users.

[0097] In some embodiments, the functions or modules included in the incentive generation device provided in the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above incentive generation method embodiments. For the sake of brevity, it will not be repeated here.

[0098] The present disclosure embodiment also proposes a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the above-mentioned incentive generation method when executed by a processor. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium. In some embodiments, the functions or modules included in the computer-readable storage medium provided by the present disclosure embodiment can be used to execute the method described in the above method embodiment, and its specific implementation can refer to the description of the above incentive generation method embodiment, and for the sake of brevity, it will not be repeated here.

[0099] The present disclosure also provides an incentive generation device, comprising: a processor; a memory for storing processor executable instructions; wherein the processor is configured to implement the above incentive generation method when executing the instructions stored in the memory. In some embodiments, the functions or modules included in the incentive generation device provided by the present disclosure can be used to execute the method described in the above method embodiment, and its specific implementation can refer to the description of the incentive generation method embodiment above, and for the sake of brevity, it will not be repeated here.

[0100] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code, and when the computer-readable code is executed in a processor of an electronic device, the processor in the electronic device executes the above-mentioned incentive generation method. In some embodiments, the functions or modules included in the computer program product provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiment, and its specific implementation can refer to the description of the above incentive generation method embodiment, and for the sake of brevity, it will not be repeated here.

[0101] Figure 8 The block diagram of the stimulus generation device provided according to the embodiment of the present disclosure is shown. The electronic device in at least one embodiment of the present disclosure may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (such as vehicle navigation terminals), wearable electronic devices, etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 8The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure. The electronic device includes at least one processor and a memory. The processor here can be referred to as the processing device 801 described below, and the memory can include at least one of the read-only memory (ROM) 802, the random access memory (RAM) 803 and the storage device 808 described below. The memory is used to store programs for executing the methods described in the above-mentioned various method embodiments; the processor is configured to execute the programs stored in the memory. The processor can be a processing unit including a central processing unit (CPU) or other forms of processing units with data processing capabilities and / or instruction execution capabilities, and can control other components in the electronic device to perform the desired functions.

[0102] like Figure 8 As shown, the electronic device 800 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 801, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 802 or a program loaded from a storage device 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 are also stored. The processing device 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0103] Typically, the following devices may be connected to the I / O interface 805: input devices 806 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 807 including, for example, a display (e.g., a liquid crystal display (LCD) or an organic light emitting diode display (OLED)), a speaker, a vibrator, etc.; storage devices 808 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 809. The communication device 809 may allow the electronic device 800 to communicate with other devices wirelessly or by wire to exchange data. Although Figure 8An electronic device 800 with various devices is shown, but it should be understood that it is not required to implement or have all the devices shown. More or fewer devices may be implemented or provided alternatively. In particular, according to at least one embodiment of the present disclosure, the process described with reference to the flowchart above may be implemented as a computer software program. For example, at least one embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transient computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through a communication device 809, or installed from a storage device 808, or installed from a ROM 802. When the computer program is executed by the processing device 801, the above-mentioned functions defined in the method of at least one embodiment of the present disclosure are executed. It should be noted that the above-mentioned computer-readable medium of the present disclosure may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection with one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In at least one embodiment of the present disclosure, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device, or device. And in at least one embodiment of the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in combination with an instruction execution system, device, or device. The program code contained in the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above. The above-mentioned computer-readable medium may be included in the above-mentioned electronic device 800; or it may exist independently without being assembled into the electronic device 800.

[0104] Although the disclosure has been described in detail above with general descriptions and specific implementation methods, it is obvious to those skilled in the art that some modifications or improvements may be made to the embodiments of the disclosure. Therefore, these modifications or improvements made without departing from the spirit of the disclosure are within the scope of protection claimed by the disclosure.

[0105] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A method for generating an incentive, characterized in that: include: Allocating a first number of multiple physical addresses, and allocating a second number of multiple page table entry addresses; For each virtual address of the third number of virtual addresses that need to be generated, a corresponding target physical address is selected from the multiple physical addresses, and at least one target page table entry address for the target physical address is selected from the multiple page table entry addresses, page table entry data is determined according to the target physical address and each of the target page table entry addresses, and the page table entry data is stored in a target page table entry corresponding to each of the target page table entry addresses, and a corresponding virtual address is generated according to a first identifier of the target physical address and a second identifier of each of the target page table entry addresses; Generate a stimulus for verifying a memory management unit according to the target physical address, the virtual address, and the target page table entry corresponding to each of the target page table entry addresses; The target page table entries corresponding to the target page table entry addresses are in page tables of different levels.

2. The method according to claim 1, characterized in that: The page table includes at least one level, and the page table of each level includes a preset number of page table entries; The step of selecting a corresponding target physical address from the multiple physical addresses and selecting at least one target page table entry address for the target physical address from the multiple page table entry addresses includes: Selecting a target physical address from the multiple physical addresses according to a preset selection method, wherein the preset selection method includes a random selection method; When the target physical address is not used, the target page table entry address for the target physical address is selected from the page table entry addresses corresponding to each level of the page table in order from low to high levels of the page table; In the case where the target physical address has been used, using the target page table entry addresses previously selected for the target physical address as the target page table entry addresses used for the virtual address to be generated this time; Among them, the page table entry data stored in the target page table entry in the lowest level page table is data determined according to the target physical address; among the target page table entries of other levels, the page table entry data stored in the target page table entry in the higher level page table among the two target page table entries in the adjacent level page tables is data determined according to the target page table entry address of the target page table entry in the lower level page table.

3. The method according to claim 2, characterized in that The step of selecting the target page table entry address for the target physical address from the page table entry addresses corresponding to each level of the page table in order from low to high levels of the page table includes: For each level of page table, select a target page table entry address from the page table entry addresses corresponding to the current page table according to the preset selection method; When the target page table entry address is not used, continue to randomly select the target page table entry address corresponding to the higher-level page table; When the target page table entry address has been used, the target page table entry address corresponding to the higher-level page table previously selected and corresponding to the target page table entry address is used as the remaining target page table entry addresses that have not been selected and used for the virtual address to be generated this time.

4. The method according to claim 1, characterized in that In a case where the storage spaces respectively indicated by the multiple physical addresses are located in a continuous first storage space, the first identifier indicates an offset address of the corresponding target physical address relative to a base address of the first storage space; and / or, In a case where the storage spaces respectively indicated by the multiple page table entry addresses are located in a continuous second storage space, the second identifier indicates an offset address of the corresponding target page table entry address relative to a base address of the second storage space.

5. The method according to claim 1, characterized in that: The method further comprises: Setting the first quantity, the second quantity, and the third quantity according to configuration parameters; The configuration parameters are set based on verifying an application scenario of the memory management unit.

6. The method according to claim 5, characterized in that The method further comprises: Randomly generating the configuration parameters according to the constraint conditions corresponding to the application scenario of the memory management unit; and / or, In case of a detected user input operation, the configuration parameter is determined according to the user input operation.

7. An incentive generating device, characterized in that: include: an address allocation module, the address allocation module being configured to allocate a first number of multiple physical addresses and a second number of multiple page table entry addresses; A first generating module, wherein the first generating module is configured to, for each virtual address of a third number of virtual addresses to be generated, select a corresponding target physical address from the multiple physical addresses, and select at least one target page table entry address for the target physical address from the multiple page table entry addresses, determine page table entry data according to the target physical address and each of the target page table entry addresses, store the page table entry data in a target page table entry corresponding to each of the target page table entry addresses, and generate a corresponding virtual address according to a first identifier of the target physical address and a second identifier of each of the target page table entry addresses; A second generation module, wherein the second generation module is configured to generate a stimulus for verifying a memory management unit according to the target physical address, the virtual address, and a target page table entry corresponding to each of the target page table entry addresses; The target page table entries corresponding to the target page table entry addresses are in page tables of different levels.

8. An incentive generating device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to implement the method described in any one of claims 1 to 6 when executing the instructions stored in the memory.

9. A non-volatile computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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