Method and system for direct memory access

Abstract

A method and apparatus for a computing system are described herein. The method comprises the steps that a data packet and address data are received, the data packet comprises data to be written into a computing system, and the address data comprises addresses in an address set of a first address space of the computing system; determining an address of a second address space of the computing system identified by an address of the data packet; the data is written to the computing system in accordance with the determination. A first subset and a second subset of the set are identified, the first subset of addresses of the second address space being associated with a memory region of the computing system, and the second subset of addresses of the second address space being associated with a data store region.

Description

[0001] This application is a divisional application. The application number of the original application is 202080018121.2, and the original application date is May 28, 2020. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to a system and method for a computing system. In particular, the present disclosure relates to a system and method for performing direct memory access operations on a computing system. Background Art

[0003] Direct memory access (DMA) enables devices or subsystems in a computing system to read data directly from and write data to the computing system. DMA can be implemented in a computing system through devices such as a graphics processing unit or sound card, or other processor cores in a multi-core system. DMA frees up computing resources in the computing system. In particular, when a program is running on the main processor, DMA operations can be performed simultaneously.

[0004] Remote direct memory access (RDMA) enables a computing system to read data from or write data to the memory of another computing system over a network. RDMA can improve network performance, resulting in higher throughput and lower network latency on systems that do not implement RDMA. Summary of the invention

[0005] The present disclosure is directed to a method for a computing system, such as may be used to perform direct memory access operations on a computing system.

[0006] The above-mentioned objects and other objects are achieved by the features of the independent claims. Further implementation forms are evident from the dependent claims, the description and the drawings.

[0007] According to a first aspect, a method for a computing system is provided. The method comprises receiving a data packet and address data, the data packet comprising data to be written into the computing system, the address data comprising an address in an address set of a first address space of the computing system; determining an address of a second address space of the computing system identified by the address of the data packet; and writing the data into the computing system according to the determination. A first subset of the set is identified by a first address subset of the second address space, a second subset of the set is identified by a second address subset of the second address space, the first address subset of the second address space is associated with a memory area of ​​the computing system, and the second address subset of the second address space is associated with a data storage area.

[0008] The method according to the first aspect provides a method for writing data to a computing system based on determining an address in a second address space of the computing system from an address in a first address space. The second address space is divided into subsets, the subsets including a subset of addresses associated with a memory and a subset associated with a data storage area. If the determined address is in one of the subsets, the data is written to the memory or the data storage area.

[0009] According to a second aspect, there is provided an apparatus for a computing system. The apparatus is arranged to: identify an address in a set of addresses in a first address space of a computing system in a data packet and address data, the data packet comprising data to be written to the computing system, the address data comprising the address, determine an address in a second address space of the computing system identified by the address of the data packet, and write the data to the computing system according to the determination. A first subset of the set is identified by a first subset of addresses in the second address space, a second subset of the set is identified by a second subset of addresses in the second address space, the first subset of addresses in the second address space is associated with a memory area of ​​the computing system, and the second subset of addresses in the second address space is associated with a data storage area.

[0010] In one implementation, determining the address of the second address space includes accessing an address translation table and determining the address according to the address translation table.

[0011] In another implementation, the method includes: when the address of the data packet is not identified by the address of the first or second subset of the second address space, determining an address from the third address subset in the second address space associated with the data storage area, and writing the data to the data storage area associated with the determined address.

[0012] The implementation of the method provides a method for selecting an address from an address pool of a data storage area to map an unmapped address in a first address space.

[0013] In another implementation, the method includes updating the address translation table to identify addresses in the data packet based on addresses determined in the third subset.

[0014] The implementation provides a method for performing direct memory accesses to addresses in the third subset at previously unmapped addresses in an uninterrupted manner.

[0015] In another implementation, the second address space is a physical address space of the computing system.

[0016] In another implementation, the first address space is a virtual address space.

[0017] In another implementation, determining an address in a third subset of the second address space includes accessing stored address data to obtain at least one address in the third subset, and determining an address in the third subset from the stored address data.

[0018] The implementation provides a method for selecting an address from an address pool to map an unmapped address in a first address space to the address.

[0019] In another implementation of the method, determining addresses in a third subset of the second address space includes sending a request to the computing system to identify addresses of the third subset, and receiving a response from the computing system, the response including addresses of data in the third address subset.

[0020] This implementation provides an alternative method for determining an address from a pool of available addresses to map an unmapped address into.

[0021] In one implementation, the method includes removing the determined address from the third subset.

[0022] The method according to this implementation provides a method to remove previously unmapped addresses in the pool that have been allocated to the first address space.

[0023] In another implementation, the method includes determining the number of addresses of the second address space in the third subset, and when the number of addresses is lower than a threshold number, replenishing the third subset.

[0024] This implementation replenishes the address pool to ensure that there are enough addresses to sustain a large number of requests from unmapped addresses.

[0025] In another implementation, supplementing the third subset includes determining availability of addresses in the second address space according to a criterion, and including the addresses in the third subset according to the determination.

[0026] In another implementation, the criteria include criteria for use of the address by the computing system.

[0027] The implementation provides a criterion for determining the availability of addresses to replenish the address pool based on the usage of the addresses. This implementation of the method ensures that addresses that are not fully used by the computing system are recycled and used to map unmapped addresses in the available address pool.

[0028] In another implementation, the address of the data packet is a destination address of a direct memory access (DMA) request.

[0029] In another implementation, the address of the data packet is a destination address of a remote direct memory access (RDMA) request.

[0030] In another implementation, the method includes accessing at least one other address translation table, each table including an entry for each address in the set, and updating the entry of the at least one other address translation table corresponding to the address of the data packet to use the determined address to identify the address of the data packet.

[0031] In another implementation, the address translation table is stored in the computing system.

[0032] In another implementation, the address translation table is stored in a device that performs a direct memory access or remote direct memory access request on the computing system.

[0033] The above aspects and other aspects of the present application will be apparent from the embodiments described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0035] Figure 1 A computing system according to an example is shown.

[0036] Figure 2A is a schematic diagram of a remote direct memory access request according to an example.

[0037] Figure 2B is a schematic diagram of a remote direct memory access request according to an example.

[0038] Figure 3 A flow chart of a method for a computing system according to an example is shown. DETAILED DESCRIPTION

[0039] The following will describe the exemplary embodiments in sufficient detail to enable those skilled in the art to embody and implement the systems and processes described herein. It should be understood that the embodiments may be embodied in many different forms and should not be construed to be limited to the examples described herein.

[0040] Therefore, the embodiments may be modified in various ways and in various alternative forms, specific embodiments of which are shown in the drawings and described in detail below in an exemplary form. It is not intended to limit the specific forms disclosed herein. On the contrary, all modifications, equivalents and alternative forms falling within the scope of the appended claims should be included. In the drawings and appropriate detailed descriptions, the elements of the exemplary embodiments are always represented by the same reference numerals.

[0041] The terms used herein to describe the embodiments are not intended to limit the scope. The articles "a", "an" and "the" are singular and therefore have a single reference, but the use of the singular in this article should not exclude the presence of multiple references. In other words, unless the context clearly indicates otherwise, elements represented in the singular may be numbered as one or more. It should be further understood that when used in this specification, the terms "comprises", "includes" and / or "comprises" specify the presence of the described features, items, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, items, steps, operations, elements, parts and / or combinations thereof.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used in this article should be interpreted according to the conventions of the art. It should be further understood that, unless explicitly defined herein, commonly used terms should also be interpreted as customary terms in the relevant field, rather than idealized or overly formalized meanings.

[0043] Figure 1 1 is a block diagram of an apparatus 100. The apparatus 100 includes a computing system 110. The apparatus 100 may be used with the methods and systems described herein. The computing system 110 includes a central processing unit (CPU) 120. The CPU 120 includes logic for reading or writing data to memory and executing processes on the computing system 110. The CPU 120 is connected to other components of the computing system 110 via a bus 130. The bus 130 enables data transfer between interconnected components of the computing system 110.

[0044] The computing system 110 includes a storage device 140. The storage device 140 may include any type of non-transitory storage device for storing data, programs, and other information and making them accessible via the bus 130. The storage device 140 may include at least one such as a solid state drive, a hard disk drive, a magnetic disk drive, or an optical disk drive. The storage device 140 is connected to other components of the computing system 110 via the bus 130.

[0045] The computing system 110 includes physical memory 150. The memory 150 may include any type of non-temporary system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), or a combination thereof. The memory 150 includes a plurality of memory cells. Each memory cell has an address for identifying the location of the memory cell in the memory 150. The discrete address range of the memory 150 is called a physical address space.

[0046] In the examples described herein, storage device 140 may also be referred to as a switching device. Figure 1 In the example, storage device 140 is a physically separate entity from physical memory 150. In other examples, the function of storage device 140 as a switching device may be performed by a cache or similar device in physical memory 150 of computing system 110. In other examples, a remote storage device that is physically separate from computing system 110 may perform equivalent functions to storage device 140 as a switching device.

[0047] Typically, only system software such as BIOS and the operating system in the boot state directly access physical memory 150. For other processes, the computing system 110 maintains a virtual address space. The virtual address space is similar to the physical address space, but the addresses do not correspond to locations in physical memory 150. The virtual address space provides a continuous address space appearance to the process. The mapping of virtual addresses to physical addresses is stored in a data structure called a page table. Each entry in the page table can be called a page table entry. A page, memory page, or virtual page is a fixed-length continuous block of virtual memory, represented by a single page table entry. A frame is a fixed-length continuous block of a page mapped to physical memory.

[0048] In addition to providing the appearance of a continuous address space, virtual addressing can also create a virtual partition of memory 150 in two non-contiguous areas. The first area, called kernel space, is reserved for protected processes, such as the BIOS and operating system. The second area, called user space, is allocated to other processes. The computing system 110 maintains the separation of kernel space and user space by preventing processes executing in user space from addressing kernel space.

[0049] Figure 1The CPU 120 is shown including a memory management unit (MMU) 160. The MMU 160 performs address translation to map virtual addresses of pages addressed by a process to physical addresses of corresponding frames in the memory 150. The MMU 160 also performs virtual memory management for processes running on the computing system 110. When pages are moved between different physical memory locations, the MMU 160 manages the corresponding page table entries, updating the page table as necessary.

[0050] Data stored at virtual addresses is moved between physical memory 150 and other storage, such as storage device 140, using a virtual memory management process called paging. When a process requests a page in the virtual address space, MMU 160 determines whether the requested page is available in memory 150 by performing an address translation. When the page is available, a physical address is returned, and a calculation is performed on CPU 120. When the page is not available in memory 150, MMU 160 returns a page fault. Software running on the operating system, called a page manager, accesses storage device 140, restores the frame corresponding to the virtual address of the page that caused the page fault, and updates the page table in MMU 160 with the new mapping between the virtual address and the physical address, where the page has been restored to memory 150.

[0051] Paging allows a computing system to allocate a continuous virtual address range to a process that exceeds the available space in physical memory 150 by extending the virtual address space into a secondary storage device such as storage device 140. However, when all frames are used in physical memory 150, the operating system must select a frame to reuse as a page required by the process. The paging manager can use a page replacement algorithm such as Least Recently Used (LRU) or First In First Out (FIFO) to determine which memory location in memory 150 to release the requested page. The paging manager can page out or "swap" pages from memory 150 to storage device 140 according to the page replacement algorithm. The paging manager updates the page table so that the page requested by the process points to the released location in memory. The area of ​​storage device 140 reserved for this purpose is called swap space. In some cases, a page can be locked or "pinned" in memory 150 to prevent the page from being swapped out to storage device 140.

[0052] The computing system 110 also includes a direct memory access (DMA) device 170. The DMA device 170 may be a disk drive, a graphics card, a sound card, or other hardware device. In other examples, the DMA device 170 may be another processing core similar to the CPU 120. The DMA device 170 is connected to the bus 130 and may interact with other components of the computing system 110 through the bus 130. The DMA device 170 may perform DMA requests to the memory 150. A DMA request from the device 170 to the memory 150 is an operation such as a data write operation that is independent of the CPU 120 and is performed directly to a location in the memory 150. Without DMA, when the CPU 120 uses programmed input / output, the CPU 120 will be completely occupied during the entire process of the read or write operation and cannot perform other work. DMA allows the CPU 120 to perform other operations while processing DMA requests from the device 170. DMA is useful for performing large data transfers such as between the device 170 and the memory 150. Once the DMA operation to memory 150 is completed, device 170 sends an interrupt request back to CPU 120 so that CPU 120 can process the data from device 170 that was written to memory 150 after the DMA operation.

[0053] Similar to processes running on computing system 110, DMA requests from DMA device 170 may specify addresses in a virtual address space. In some examples, DMA device 170 is arranged to perform address translation of addresses specified in DMA requests. For example, in some cases, DMA device 170 and / or computing system 110 include an input-output memory management unit (IOMMU) ( Figure 1 1 ), the input-output memory management unit performs address translation for I / O devices in the computing system 110 in a manner similar to the manner in which the MMU 160 performs address translation for the CPU 120. In other examples, the DMA device 170 uses a remote procedure call to the operating system to track or query page table entries.

[0054] The computing system 110 further includes a network interface controller (NIC) 180 that connects the computing system 110 to a network 190. The NIC 180 may include a wired or wireless link to the network 190, such as Ethernet or a wireless transmitter and receiver. In some examples, the network 190 may be a local area network (LAN). In other examples, the network 190 is a wide area network. The network 190 may enable communication between the computing system 110 and remote devices, such as other computing systems, network servers, and remote storage and data processing devices.

[0055] exist Figure 1 1, computing system 110 communicates with remote computing device 195 across network 190. According to an example, NIC 180 supports remote direct memory access (RDMA) requests from remote device 195 to memory 150. Similar to DMA requests from DMA device 170, RDMA requests from remote device 195 are requests to perform operations directly on locations in memory 150, bypassing the operating system of computing system 110. RDMA enables high throughput, low latency networking between computing system 110 and remote device 195 by using zero copy of data to memory 150 without requiring CPU 120 to copy data to other memory locations.

[0056] Similar to processes running on computing system 110 and DMA requests from DMA device 170, RDMA requests received at NIC 180 may include addresses of a virtual address space. In some examples, NIC 180 is arranged to perform address translation of addresses specified in RDMA requests. In other examples, NIC 180 uses, for example, an onboard IOMMU to track or query page table entries. Once the physical address is determined, NIC 180 may write the data in the RDMA request directly to memory 150.

[0057] The methods and systems described herein may be used to perform DMA (or RDMA) to storage device 140 because DMA requests sent to unmapped virtual addresses do not have corresponding physical addresses in memory 150 .

[0058] One approach to addressing the problem of (R)DMA requests to unmapped virtual addresses is to pin a subset of virtual addresses that can be used by the DMA device 170 or NIC 180 to physical addresses in the memory 150. This ensures that (R)DMA operations never encounter unmapped memory. However, there is a significant cost in that the pinned memory is not available for use by other processes or devices in the computing system 120. In addition, the memory consumption in this case can hurt performance because other memory must be swapped from the memory 150 to the storage device 140 more frequently to accommodate the required space.

[0059] Another approach to using pinning to permanently allocate memory for DMA operations is to provide temporary pinned buffers in memory 150 for the purpose of DMA operations. Each buffer can be reused once the last DMA request is completed. For example, input data for an RDMA request from device 195 can first be placed in a pinned buffer in memory 150 and then copied to another buffer in the virtual address space subspace addressed by the process. The original pinned buffer can then be reused in further DMA requests.

[0060] Unfortunately, this approach also has many disadvantages. First, the latency is significantly reduced due to the extra copy operation of the fixed buffer. However, this operation is necessary, otherwise the buffer will not be available for other DMA requests. In addition, a dedicated fixed buffer pool needs to be allocated, which results in management overhead in the computing system 110, similar to the fixed approach described previously. Other similar approaches also have latency penalties or cause large memory usage due to the excessive number of fixed areas in the memory 150 area.

[0061] In the methods and systems described herein, (R)DMA operations to unmapped virtual addresses are not stalled and are not transferred to locations in memory 150. Instead, (R)DMA operations are handled by the swap space in the storage device 140. If the virtual address has a corresponding swap slot in the swap space of the storage device 140, the data is written directly to the slot, overwriting any previous data in the slot. Otherwise, the request is handled by the buffer pool with the address in the swap space. The address pool handles (R)DMA requests that are sent to unmapped memory that does not have a corresponding swap slot. Processing the request does not require the CPU 120 to perform any operations, nor does it require the data to pass through the memory 150.

[0062] Figure 2A is a simplified diagram of an example 200 of an RDMA request according to the methods described herein. Figure 2A The example 200 shown is composed of Figure 1 NIC 180 is shown processing RDMA requests. Figure 1 DMA requests for the DMA device 170 shown are processed in a similar manner, and Figure 2A The examples shown are not intended to limit other methods and examples described herein to RDMA requests.

[0063] In the example 200 shown in FIG2A , Figure 1 NIC 180 is shown receiving RDMA request 210. RDMA request 210 may be received by, for example, Figure 1 Received by remote device 195 as shown. RDMA request 210 includes destination (virtual) address 211, such as an address in the virtual address space of a target process running on computing system 110, and data 212 to be written to computing system 110. In some cases, data 212 may be divided into one or more packets, where the virtual address of each packet is determined by an offset from the virtual address of the first packet, which is represented by virtual address 211 of RDMA request 210. When NIC 180 receives RDMA request 210, NIC 180 performs address translation (by itself, or using, for example, an onboard IOMMU as described above) to identify the address in memory 150 for destination virtual address 211.

[0064] An example of converting the destination address 211 is shown in box 220. Three examples are shown in this article. When the virtual address 211 of the RDMA request has been mapped to the memory 150, the NIC 180 only needs to perform the address conversion and write the data 212 to the corresponding location in the memory 150. For example, in Figure 2A , if virtual address 211 maps to physical address 221, NIC 180 writes data 212 to location 221 in memory 150. If NIC 180 determines that the page for destination address 211 does not exist in memory 150, but a swap slot has been allocated at address 222 in swap space of storage device 140, NIC 180 writes data 212 to slot 222. If NIC 180 determines that address 211 is not mapped to any address in physical memory 150 or in swap space in storage device 140, NIC 180 writes data 212 to temporary swap space buffer 230, pointing to address 223 in swap space selected from a pool of available addresses of storage device 140, and interrupts CPU 120 to remap to swap space buffer 230.

[0065] Figure 2B Shown with Figure 2A The same example 200 is shown. Figure 2B , a virtual address space 240 and a process 241 addressing an address range in the virtual address space 240 are shown. If the virtual address targeted by the RDMA request is not mapped, once the NIC 180 determines that the data 212 of the RDMA request 210 is to be written to the swap slot address 223, the NIC 180 notifies the CPU 120 to update the address translation table 250 for the process 241 so that the address translation table entry 251 points to the swap buffer 223. The CPU 120 (re)maps the virtual address in the address translation table 250 of the process 241 to point to the buffer 230.

[0066] Figure 3 is a block diagram of a method 300 shown according to an example. Figure 3 The method 300 shown can be used in conjunction with other methods and systems described herein. In particular, the method 300 can be used in conjunction with Figure 1 The illustrated computing system 110 is implemented to handle DMA and RDMA requests to the memory 150 .

[0067] At block 310, a data packet includes data to be written to a computing system, and the address data includes an address in a set of addresses in a first address space of the receiving computing system. According to an example, the data packet may be a data packet for a DMA request or an RDMA request. The computing system may be Figure 1The computing system 110 is shown. According to an example, the first address space is a virtual address space of the computing system.

[0068] At block 320, an address of a second address space of the computing system identified by the address of the data packet is determined. In some examples described herein, the determination is made based on an address translation table that identifies a first subset of the set using a first subset of addresses of the second address space and identifies a second subset of the set using a second subset of addresses of the second address space. The first subset of addresses of the second address space is associated with a memory region of the computing system, and the second subset of addresses of the second address space is associated with a data storage region. In an example, the memory and data storage regions may be Figure 1 Memory 150 and storage device 140 are shown.

[0069] At block 330, data is written to the computing system based on the determination. In an example, when the data packet address is not identified using an address in the first or second subset of the second address space, the method 300 includes determining an address from a third subset of addresses in the second address space associated with an area of ​​the data storage area, and writing the data to the data storage area associated with the determined address. In an example, the method 300 includes updating the address translation table to identify the address in the data packet using the determined address.

[0070] Determining an address in the third subset of addresses includes accessing the stored address data to obtain at least one address in the third subset, and determining the address in the third subset from the stored address data. Figure 1 When implemented on the computing system 110 shown in , the NIC 180 can store a pool of addresses that is used as a "swap buffer" for data of RDMA requests to contain unmapped virtual addresses in the case of such requests.

[0071] In some cases, determining an address in the third subset of addresses includes sending a query including a request to identify an address in the third subset of addresses, and receiving a response from the computing system including address data in the third subset of addresses. For example, NIC 180 may determine an address of an IOMMU swap buffer without storing a local address.

[0072] In some examples, method 300 also includes removing the determined address from the third address subset. Method 300 may also include determining the number of addresses in the second address space in the third subset, and when the number of addresses is below a threshold number, supplementing the third subset. Supplementing the third subset may include: determining the availability of addresses in the second address space according to a standard, and including the addresses in another subset according to the determination. According to an example, the standard may include a standard for the computing system to use the address. These examples enable the computing system to maintain a supply of swap buffers and write data in DMA requests to the system on demand in a non-pause manner without copying the data to other buffers.

[0073] The methods and examples described herein use DMA operations for unmapped memory without causing delays due to paging requests. The DMA operation causes data to be stored directly to a swap slot in the storage device 140, or to a location in a swap buffer. Regardless of whether the swap slot is mapped to a target virtual address, the DMA to the storage device is completed by the (R)DMA device without any action by the host computing system. This further eliminates redundant swap operations in the storage device. And the DMA operation triggered by an independent device does not need to stop or pause. Therefore, due to the limitations of the receiver, the triggering device does not need to support data pause or stop. The redundancy of the stop and adjustment commands caused by the pause of the receiving end reduces the control data packets with RDMA function on the network. Since the DMA operation does not require physical memory, the methods and systems described herein do not need to allocate new pages for the DMA operation. Since there is no need to allocate new pages and the number of free pages in the system has not decreased, the operating system does not need to perform page frame recovery operations.

[0074] It should be understood that one or more steps of the embodiment methods provided herein can be performed by corresponding units or modules. Each unit or module can be hardware, software, or a combination thereof. For example, one or more of these units or modules can be an integrated circuit, such as a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).

[0075] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

[0076] The present application may be embodied in other specific devices and / or methods. The described embodiments should be considered to be illustrative and not restrictive in all respects. In particular, the scope of the present application is specified by the attached claims rather than the description and drawings herein. Any changes within the meaning and equivalent range of the claims should be included within their scope.

Claims

1. A memory access method, characterized in that: include: receiving a data packet and address data, the data packet including data to be written into a computing system, the address data including an address in a set of addresses in a first address space of the computing system; determining an address of a second address space of the computing system identified by the address of the data packet; as well as writing the data into the computing system according to the determined address of the second address space; wherein the first subset of the set is identified by a first subset of addresses in the second address space, and the second subset of the set is identified by a second subset of addresses in the second address space; and The first address subset of the second address space is associated with a memory area of ​​the computing system, and the second address subset of the second address space is associated with a data storage area.

2. The method according to claim 1, characterized in that Determining the address of the second address space includes accessing an address translation table and determining the address according to the address translation table.

3. The method according to claim 1, characterized in that include: determining an address from the third subset of addresses in the second address space associated with the data storage area when the address of the data packet is not identified by an address of the first or second subset of the second address space; as well as The data is written to the data storage area associated with the determined address.

4. The method according to claim 2, characterized in that: The method also includes updating the address translation table to use the determined address to identify the address in the data packet.

5. The method according to claim 1, characterized in that The second address space is a physical address space.

6. The method according to claim 1, characterized in that The first address space is a virtual address space.

7. The method according to claim 3, characterized in that Determining an address in the third address subset includes: accessing the stored address data to obtain at least one address in the third subset; and Addresses in the third subset are determined from the stored address data.

8. The method according to claim 3, characterized in that Determining an address in the third address subset includes: sending a request to identify an address of the third subset; A response including address data is received to obtain addresses of a third subset of the computing systems.

9. The method according to claim 3, characterized in that: Also included is removing the determined address from the third subset.

10. The method according to claim 3, characterized in that: Also includes: determining the number of addresses in the second address space in the third subset; and When the number of addresses is lower than a threshold number, the third subset is supplemented.

11. The method according to claim 10, characterized in that Supplement the third subset, including: determining availability of addresses in the second address space based on criteria; and The address is included in the third subset based on the determination.

12. The method according to claim 11, characterized in that The criteria include criteria for use of the address by the computing system.

13. The method according to claim 1, characterized in that The address of the data packet is a destination address of a direct memory access (DMA) request.

14. The method according to claim 1, characterized in that The address of the data packet is a destination address of a remote direct memory access (RDMA) request.

15. The method according to claim 2, characterized in that include: accessing at least one other address translation table, each table comprising an entry for each address in the set; as well as An entry of the at least one other address translation table corresponding to the address of the data packet is updated to identify the address of the data packet using the determined address.

16. The method according to claim 2, characterized in that The address translation table is stored in the computing system.

17. The method according to claim 2, characterized in that The address translation table is stored in a device that performs a direct memory access or remote direct memory access request on the computing system.

18. An apparatus for a computing system, characterized in that: The device is used for: identifying an address in a set of addresses in a first address space of a computing system in a data packet and address data, the data packet including data to be written to the computing system, the address data including the address; determining an address of a second address space of the computing system identified by the address of the data packet; as well as writing the data into the computing system according to the determined address of the second address space; wherein the first subset of the set is identified by a first subset of addresses in the second address space, and the second subset of the set is identified by a second subset of addresses in the second address space; and The first address subset of the second address space is associated with a memory area of ​​the computing system, and the second address subset of the second address space is associated with a data storage area.

19. The device according to claim 18, characterized in that To determine the address of the second address space, the apparatus is arranged to access an address translation table and to determine the address from the address translation table.

20. The device according to claim 18, characterized in that The device is used for: determining an address from the third subset of addresses in the second address space associated with the data storage area when the address of the data packet is not identified by an address of the first or second subset of the second address space; as well as The data is written to the data storage area associated with the determined address.

21. The device according to claim 20, characterized in that The device is arranged to: storing address data in at least one address of the third subset; and Addresses in the third subset are determined from the stored address data.

22. The device according to claim 19, characterized in that The device is arranged to: accessing at least one other address translation table, each table comprising an entry for each address in the set; and An entry of the at least one other address translation table corresponding to the address of the data packet is updated to identify the address of the data packet using the determined address.

Images